1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD , VT, Legal);
407 setOperationAction(ISD::SUB , VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::STORE, VT, Promote);
435 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
437 // No other operations are legal.
438 setOperationAction(ISD::MUL , VT, Expand);
439 setOperationAction(ISD::SDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UDIV, VT, Expand);
442 setOperationAction(ISD::UREM, VT, Expand);
443 setOperationAction(ISD::FDIV, VT, Expand);
444 setOperationAction(ISD::FREM, VT, Expand);
445 setOperationAction(ISD::FNEG, VT, Expand);
446 setOperationAction(ISD::FSQRT, VT, Expand);
447 setOperationAction(ISD::FLOG, VT, Expand);
448 setOperationAction(ISD::FLOG10, VT, Expand);
449 setOperationAction(ISD::FLOG2, VT, Expand);
450 setOperationAction(ISD::FEXP, VT, Expand);
451 setOperationAction(ISD::FEXP2, VT, Expand);
452 setOperationAction(ISD::FSIN, VT, Expand);
453 setOperationAction(ISD::FCOS, VT, Expand);
454 setOperationAction(ISD::FABS, VT, Expand);
455 setOperationAction(ISD::FPOWI, VT, Expand);
456 setOperationAction(ISD::FFLOOR, VT, Expand);
457 setOperationAction(ISD::FCEIL, VT, Expand);
458 setOperationAction(ISD::FTRUNC, VT, Expand);
459 setOperationAction(ISD::FRINT, VT, Expand);
460 setOperationAction(ISD::FNEARBYINT, VT, Expand);
461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
463 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
464 setOperationAction(ISD::MULHU, VT, Expand);
465 setOperationAction(ISD::MULHS, VT, Expand);
466 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
468 setOperationAction(ISD::UDIVREM, VT, Expand);
469 setOperationAction(ISD::SDIVREM, VT, Expand);
470 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
471 setOperationAction(ISD::FPOW, VT, Expand);
472 setOperationAction(ISD::BSWAP, VT, Expand);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::CTTZ, VT, Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::VSELECT, VT, Expand);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
479 for (MVT InnerVT : MVT::vector_valuetypes()) {
480 setTruncStoreAction(VT, InnerVT, Expand);
481 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
483 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
521 if (Subtarget.hasP8Altivec())
522 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
524 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
526 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
527 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
537 // Altivec does not contain unordered floating-point compare instructions
538 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
539 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
543 if (Subtarget.hasVSX()) {
544 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
545 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
548 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
549 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
550 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
551 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
553 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
555 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
556 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
558 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
559 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
561 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
562 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
563 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
564 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
565 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
567 // Share the Altivec comparison restrictions.
568 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
571 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
573 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
574 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
576 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
578 if (Subtarget.hasP8Vector())
579 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
581 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
583 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
584 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
586 if (Subtarget.hasP8Altivec()) {
587 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
588 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
589 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
591 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
594 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
595 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
596 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
598 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
600 // VSX v2i64 only supports non-arithmetic operations.
601 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
602 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
605 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
606 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
607 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
608 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
610 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
612 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
613 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
614 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
615 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
617 // Vector operation legalization checks the result type of
618 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
619 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
621 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
622 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
624 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
627 if (Subtarget.hasP8Altivec()) {
628 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
629 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
633 if (Subtarget.hasQPX()) {
634 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
635 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
636 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
637 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
640 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
642 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
643 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
645 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
646 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
648 if (!Subtarget.useCRBits())
649 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
650 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
652 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
653 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
654 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
655 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
656 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
657 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
660 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
661 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
663 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
664 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
665 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
667 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
668 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
669 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
671 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
672 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
673 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
674 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
675 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
676 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
677 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
679 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
680 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
682 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
683 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
685 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
687 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
688 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
689 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
690 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
692 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
693 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
695 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
696 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
698 if (!Subtarget.useCRBits())
699 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
700 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
703 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
704 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
705 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
706 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
708 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
711 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
713 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
714 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
715 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
717 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
718 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
719 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
720 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
721 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
722 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
723 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
725 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
726 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
728 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
729 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
731 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
733 setOperationAction(ISD::AND , MVT::v4i1, Legal);
734 setOperationAction(ISD::OR , MVT::v4i1, Legal);
735 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
737 if (!Subtarget.useCRBits())
738 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
739 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
741 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
742 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
745 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
746 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
748 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
750 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
752 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
753 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
755 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
757 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
758 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
759 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
760 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
762 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
763 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
764 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
765 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
767 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
768 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
770 // These need to set FE_INEXACT, and so cannot be vectorized here.
771 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
772 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
774 if (TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
776 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
782 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
784 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
785 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
789 if (Subtarget.has64BitSupport())
790 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
792 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
795 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
796 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
799 setBooleanContents(ZeroOrOneBooleanContent);
801 if (Subtarget.hasAltivec()) {
802 // Altivec instructions set fields to all zeros or all ones.
803 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
807 // These libcalls are not available in 32-bit.
808 setLibcallName(RTLIB::SHL_I128, nullptr);
809 setLibcallName(RTLIB::SRL_I128, nullptr);
810 setLibcallName(RTLIB::SRA_I128, nullptr);
814 setStackPointerRegisterToSaveRestore(PPC::X1);
815 setExceptionPointerRegister(PPC::X3);
816 setExceptionSelectorRegister(PPC::X4);
818 setStackPointerRegisterToSaveRestore(PPC::R1);
819 setExceptionPointerRegister(PPC::R3);
820 setExceptionSelectorRegister(PPC::R4);
823 // We have target-specific dag combine patterns for the following nodes:
824 setTargetDAGCombine(ISD::SINT_TO_FP);
825 if (Subtarget.hasFPCVT())
826 setTargetDAGCombine(ISD::UINT_TO_FP);
827 setTargetDAGCombine(ISD::LOAD);
828 setTargetDAGCombine(ISD::STORE);
829 setTargetDAGCombine(ISD::BR_CC);
830 if (Subtarget.useCRBits())
831 setTargetDAGCombine(ISD::BRCOND);
832 setTargetDAGCombine(ISD::BSWAP);
833 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
834 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
835 setTargetDAGCombine(ISD::INTRINSIC_VOID);
837 setTargetDAGCombine(ISD::SIGN_EXTEND);
838 setTargetDAGCombine(ISD::ZERO_EXTEND);
839 setTargetDAGCombine(ISD::ANY_EXTEND);
841 if (Subtarget.useCRBits()) {
842 setTargetDAGCombine(ISD::TRUNCATE);
843 setTargetDAGCombine(ISD::SETCC);
844 setTargetDAGCombine(ISD::SELECT_CC);
847 // Use reciprocal estimates.
848 if (TM.Options.UnsafeFPMath) {
849 setTargetDAGCombine(ISD::FDIV);
850 setTargetDAGCombine(ISD::FSQRT);
853 // Darwin long double math library functions have $LDBL128 appended.
854 if (Subtarget.isDarwin()) {
855 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
856 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
857 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
858 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
859 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
860 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
861 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
862 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
863 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
864 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
867 // With 32 condition bits, we don't need to sink (and duplicate) compares
868 // aggressively in CodeGenPrep.
869 if (Subtarget.useCRBits()) {
870 setHasMultipleConditionRegisters();
871 setJumpIsExpensive();
874 setMinFunctionAlignment(2);
875 if (Subtarget.isDarwin())
876 setPrefFunctionAlignment(4);
878 switch (Subtarget.getDarwinDirective()) {
882 case PPC::DIR_E500mc:
891 setPrefFunctionAlignment(4);
892 setPrefLoopAlignment(4);
896 setInsertFencesForAtomic(true);
898 if (Subtarget.enableMachineScheduler())
899 setSchedulingPreference(Sched::Source);
901 setSchedulingPreference(Sched::Hybrid);
903 computeRegisterProperties(STI.getRegisterInfo());
905 // The Freescale cores do better with aggressive inlining of memcpy and
906 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
907 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
908 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
909 MaxStoresPerMemset = 32;
910 MaxStoresPerMemsetOptSize = 16;
911 MaxStoresPerMemcpy = 32;
912 MaxStoresPerMemcpyOptSize = 8;
913 MaxStoresPerMemmove = 32;
914 MaxStoresPerMemmoveOptSize = 8;
915 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
916 // The A2 also benefits from (very) aggressive inlining of memcpy and
917 // friends. The overhead of a the function call, even when warm, can be
918 // over one hundred cycles.
919 MaxStoresPerMemset = 128;
920 MaxStoresPerMemcpy = 128;
921 MaxStoresPerMemmove = 128;
925 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
926 /// the desired ByVal argument alignment.
927 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
928 unsigned MaxMaxAlign) {
929 if (MaxAlign == MaxMaxAlign)
931 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
932 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
934 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
936 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
937 unsigned EltAlign = 0;
938 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
939 if (EltAlign > MaxAlign)
941 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
942 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
943 unsigned EltAlign = 0;
944 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
945 if (EltAlign > MaxAlign)
947 if (MaxAlign == MaxMaxAlign)
953 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
954 /// function arguments in the caller parameter area.
955 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
956 // Darwin passes everything on 4 byte boundary.
957 if (Subtarget.isDarwin())
960 // 16byte and wider vectors are passed on 16byte boundary.
961 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
962 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
963 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
964 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
968 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
969 switch ((PPCISD::NodeType)Opcode) {
970 case PPCISD::FIRST_NUMBER: break;
971 case PPCISD::FSEL: return "PPCISD::FSEL";
972 case PPCISD::FCFID: return "PPCISD::FCFID";
973 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
974 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
975 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
976 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
977 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
978 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
979 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
980 case PPCISD::FRE: return "PPCISD::FRE";
981 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
982 case PPCISD::STFIWX: return "PPCISD::STFIWX";
983 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
984 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
985 case PPCISD::VPERM: return "PPCISD::VPERM";
986 case PPCISD::CMPB: return "PPCISD::CMPB";
987 case PPCISD::Hi: return "PPCISD::Hi";
988 case PPCISD::Lo: return "PPCISD::Lo";
989 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
990 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
991 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
992 case PPCISD::SRL: return "PPCISD::SRL";
993 case PPCISD::SRA: return "PPCISD::SRA";
994 case PPCISD::SHL: return "PPCISD::SHL";
995 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
996 case PPCISD::CALL: return "PPCISD::CALL";
997 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
998 case PPCISD::MTCTR: return "PPCISD::MTCTR";
999 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1000 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1001 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1002 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1003 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1004 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1005 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1006 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1007 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1008 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1009 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1010 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1011 case PPCISD::VCMP: return "PPCISD::VCMP";
1012 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1013 case PPCISD::LBRX: return "PPCISD::LBRX";
1014 case PPCISD::STBRX: return "PPCISD::STBRX";
1015 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1016 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1017 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1018 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1019 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1020 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1021 case PPCISD::BDZ: return "PPCISD::BDZ";
1022 case PPCISD::MFFS: return "PPCISD::MFFS";
1023 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1024 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1025 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1026 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1027 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1028 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1029 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1030 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1031 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1032 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1033 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1034 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1035 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1036 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1037 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1038 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1039 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1040 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1041 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1042 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1043 case PPCISD::SC: return "PPCISD::SC";
1044 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1045 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1046 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1047 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1048 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1049 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1050 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1051 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1052 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1053 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1058 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &C, EVT VT) const {
1060 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1062 if (Subtarget.hasQPX())
1063 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1065 return VT.changeVectorElementTypeToInteger();
1068 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1069 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1073 //===----------------------------------------------------------------------===//
1074 // Node matching predicates, for use by the tblgen matching code.
1075 //===----------------------------------------------------------------------===//
1077 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1078 static bool isFloatingPointZero(SDValue Op) {
1079 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1080 return CFP->getValueAPF().isZero();
1081 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1082 // Maybe this has already been legalized into the constant pool?
1083 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1084 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1085 return CFP->getValueAPF().isZero();
1090 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1091 /// true if Op is undef or if it matches the specified value.
1092 static bool isConstantOrUndef(int Op, int Val) {
1093 return Op < 0 || Op == Val;
1096 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1097 /// VPKUHUM instruction.
1098 /// The ShuffleKind distinguishes between big-endian operations with
1099 /// two different inputs (0), either-endian operations with two identical
1100 /// inputs (1), and little-endian operations with two different inputs (2).
1101 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1102 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1103 SelectionDAG &DAG) {
1104 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1105 if (ShuffleKind == 0) {
1108 for (unsigned i = 0; i != 16; ++i)
1109 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1111 } else if (ShuffleKind == 2) {
1114 for (unsigned i = 0; i != 16; ++i)
1115 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1117 } else if (ShuffleKind == 1) {
1118 unsigned j = IsLE ? 0 : 1;
1119 for (unsigned i = 0; i != 8; ++i)
1120 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1121 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1127 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1128 /// VPKUWUM instruction.
1129 /// The ShuffleKind distinguishes between big-endian operations with
1130 /// two different inputs (0), either-endian operations with two identical
1131 /// inputs (1), and little-endian operations with two different inputs (2).
1132 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1133 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1134 SelectionDAG &DAG) {
1135 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1136 if (ShuffleKind == 0) {
1139 for (unsigned i = 0; i != 16; i += 2)
1140 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1141 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1143 } else if (ShuffleKind == 2) {
1146 for (unsigned i = 0; i != 16; i += 2)
1147 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1148 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1150 } else if (ShuffleKind == 1) {
1151 unsigned j = IsLE ? 0 : 2;
1152 for (unsigned i = 0; i != 8; i += 2)
1153 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1154 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1155 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1156 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1162 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1163 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1164 /// current subtarget.
1166 /// The ShuffleKind distinguishes between big-endian operations with
1167 /// two different inputs (0), either-endian operations with two identical
1168 /// inputs (1), and little-endian operations with two different inputs (2).
1169 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1170 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1171 SelectionDAG &DAG) {
1172 const PPCSubtarget& Subtarget =
1173 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1174 if (!Subtarget.hasP8Vector())
1177 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1178 if (ShuffleKind == 0) {
1181 for (unsigned i = 0; i != 16; i += 4)
1182 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1183 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1184 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1185 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1187 } else if (ShuffleKind == 2) {
1190 for (unsigned i = 0; i != 16; i += 4)
1191 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1192 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1193 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1194 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1196 } else if (ShuffleKind == 1) {
1197 unsigned j = IsLE ? 0 : 4;
1198 for (unsigned i = 0; i != 8; i += 4)
1199 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1200 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1201 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1202 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1203 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1204 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1205 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1206 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1212 /// isVMerge - Common function, used to match vmrg* shuffles.
1214 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1215 unsigned LHSStart, unsigned RHSStart) {
1216 if (N->getValueType(0) != MVT::v16i8)
1218 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1219 "Unsupported merge size!");
1221 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1222 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1223 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1224 LHSStart+j+i*UnitSize) ||
1225 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1226 RHSStart+j+i*UnitSize))
1232 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1233 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1234 /// The ShuffleKind distinguishes between big-endian merges with two
1235 /// different inputs (0), either-endian merges with two identical inputs (1),
1236 /// and little-endian merges with two different inputs (2). For the latter,
1237 /// the input operands are swapped (see PPCInstrAltivec.td).
1238 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1239 unsigned ShuffleKind, SelectionDAG &DAG) {
1240 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1241 if (ShuffleKind == 1) // unary
1242 return isVMerge(N, UnitSize, 0, 0);
1243 else if (ShuffleKind == 2) // swapped
1244 return isVMerge(N, UnitSize, 0, 16);
1248 if (ShuffleKind == 1) // unary
1249 return isVMerge(N, UnitSize, 8, 8);
1250 else if (ShuffleKind == 0) // normal
1251 return isVMerge(N, UnitSize, 8, 24);
1257 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1258 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1259 /// The ShuffleKind distinguishes between big-endian merges with two
1260 /// different inputs (0), either-endian merges with two identical inputs (1),
1261 /// and little-endian merges with two different inputs (2). For the latter,
1262 /// the input operands are swapped (see PPCInstrAltivec.td).
1263 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1264 unsigned ShuffleKind, SelectionDAG &DAG) {
1265 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1266 if (ShuffleKind == 1) // unary
1267 return isVMerge(N, UnitSize, 8, 8);
1268 else if (ShuffleKind == 2) // swapped
1269 return isVMerge(N, UnitSize, 8, 24);
1273 if (ShuffleKind == 1) // unary
1274 return isVMerge(N, UnitSize, 0, 0);
1275 else if (ShuffleKind == 0) // normal
1276 return isVMerge(N, UnitSize, 0, 16);
1283 * \brief Common function used to match vmrgew and vmrgow shuffles
1285 * The indexOffset determines whether to look for even or odd words in
1286 * the shuffle mask. This is based on the of the endianness of the target
1289 * - Use offset of 0 to check for odd elements
1290 * - Use offset of 4 to check for even elements
1292 * - Use offset of 0 to check for even elements
1293 * - Use offset of 4 to check for odd elements
1294 * A detailed description of the vector element ordering for little endian and
1295 * big endian can be found at
1296 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1297 * Targeting your applications - what little endian and big endian IBM XL C/C++
1298 * compiler differences mean to you
1300 * The mask to the shuffle vector instruction specifies the indices of the
1301 * elements from the two input vectors to place in the result. The elements are
1302 * numbered in array-access order, starting with the first vector. These vectors
1303 * are always of type v16i8, thus each vector will contain 16 elements of size
1304 * 8. More info on the shuffle vector can be found in the
1305 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1306 * Language Reference.
1308 * The RHSStartValue indicates whether the same input vectors are used (unary)
1309 * or two different input vectors are used, based on the following:
1310 * - If the instruction uses the same vector for both inputs, the range of the
1311 * indices will be 0 to 15. In this case, the RHSStart value passed should
1313 * - If the instruction has two different vectors then the range of the
1314 * indices will be 0 to 31. In this case, the RHSStart value passed should
1315 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1316 * to 31 specify elements in the second vector).
1318 * \param[in] N The shuffle vector SD Node to analyze
1319 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1320 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1321 * vector to the shuffle_vector instruction
1322 * \return true iff this shuffle vector represents an even or odd word merge
1324 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1325 unsigned RHSStartValue) {
1326 if (N->getValueType(0) != MVT::v16i8)
1329 for (unsigned i = 0; i < 2; ++i)
1330 for (unsigned j = 0; j < 4; ++j)
1331 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1332 i*RHSStartValue+j+IndexOffset) ||
1333 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1334 i*RHSStartValue+j+IndexOffset+8))
1340 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1341 * vmrgow instructions.
1343 * \param[in] N The shuffle vector SD Node to analyze
1344 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1345 * \param[in] ShuffleKind Identify the type of merge:
1346 * - 0 = big-endian merge with two different inputs;
1347 * - 1 = either-endian merge with two identical inputs;
1348 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1349 * little-endian merges).
1350 * \param[in] DAG The current SelectionDAG
1351 * \return true iff this shuffle mask
1353 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1354 unsigned ShuffleKind, SelectionDAG &DAG) {
1355 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1356 unsigned indexOffset = CheckEven ? 4 : 0;
1357 if (ShuffleKind == 1) // Unary
1358 return isVMerge(N, indexOffset, 0);
1359 else if (ShuffleKind == 2) // swapped
1360 return isVMerge(N, indexOffset, 16);
1365 unsigned indexOffset = CheckEven ? 0 : 4;
1366 if (ShuffleKind == 1) // Unary
1367 return isVMerge(N, indexOffset, 0);
1368 else if (ShuffleKind == 0) // Normal
1369 return isVMerge(N, indexOffset, 16);
1376 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1377 /// amount, otherwise return -1.
1378 /// The ShuffleKind distinguishes between big-endian operations with two
1379 /// different inputs (0), either-endian operations with two identical inputs
1380 /// (1), and little-endian operations with two different inputs (2). For the
1381 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1382 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1383 SelectionDAG &DAG) {
1384 if (N->getValueType(0) != MVT::v16i8)
1387 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1389 // Find the first non-undef value in the shuffle mask.
1391 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1394 if (i == 16) return -1; // all undef.
1396 // Otherwise, check to see if the rest of the elements are consecutively
1397 // numbered from this value.
1398 unsigned ShiftAmt = SVOp->getMaskElt(i);
1399 if (ShiftAmt < i) return -1;
1402 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1404 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1405 // Check the rest of the elements to see if they are consecutive.
1406 for (++i; i != 16; ++i)
1407 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1409 } else if (ShuffleKind == 1) {
1410 // Check the rest of the elements to see if they are consecutive.
1411 for (++i; i != 16; ++i)
1412 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1417 if (ShuffleKind == 2 && isLE)
1418 ShiftAmt = 16 - ShiftAmt;
1423 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1424 /// specifies a splat of a single element that is suitable for input to
1425 /// VSPLTB/VSPLTH/VSPLTW.
1426 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1427 assert(N->getValueType(0) == MVT::v16i8 &&
1428 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1430 // This is a splat operation if each element of the permute is the same, and
1431 // if the value doesn't reference the second vector.
1432 unsigned ElementBase = N->getMaskElt(0);
1434 // FIXME: Handle UNDEF elements too!
1435 if (ElementBase >= 16)
1438 // Check that the indices are consecutive, in the case of a multi-byte element
1439 // splatted with a v16i8 mask.
1440 for (unsigned i = 1; i != EltSize; ++i)
1441 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1444 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1445 if (N->getMaskElt(i) < 0) continue;
1446 for (unsigned j = 0; j != EltSize; ++j)
1447 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1453 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1454 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1455 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1456 SelectionDAG &DAG) {
1457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1458 assert(isSplatShuffleMask(SVOp, EltSize));
1459 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1460 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1462 return SVOp->getMaskElt(0) / EltSize;
1465 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1466 /// by using a vspltis[bhw] instruction of the specified element size, return
1467 /// the constant being splatted. The ByteSize field indicates the number of
1468 /// bytes of each element [124] -> [bhw].
1469 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1470 SDValue OpVal(nullptr, 0);
1472 // If ByteSize of the splat is bigger than the element size of the
1473 // build_vector, then we have a case where we are checking for a splat where
1474 // multiple elements of the buildvector are folded together into a single
1475 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1476 unsigned EltSize = 16/N->getNumOperands();
1477 if (EltSize < ByteSize) {
1478 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1479 SDValue UniquedVals[4];
1480 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1482 // See if all of the elements in the buildvector agree across.
1483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1484 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1485 // If the element isn't a constant, bail fully out.
1486 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1489 if (!UniquedVals[i&(Multiple-1)].getNode())
1490 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1491 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1492 return SDValue(); // no match.
1495 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1496 // either constant or undef values that are identical for each chunk. See
1497 // if these chunks can form into a larger vspltis*.
1499 // Check to see if all of the leading entries are either 0 or -1. If
1500 // neither, then this won't fit into the immediate field.
1501 bool LeadingZero = true;
1502 bool LeadingOnes = true;
1503 for (unsigned i = 0; i != Multiple-1; ++i) {
1504 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1506 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1507 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1509 // Finally, check the least significant entry.
1511 if (!UniquedVals[Multiple-1].getNode())
1512 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1513 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1514 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1515 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1518 if (!UniquedVals[Multiple-1].getNode())
1519 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1520 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1521 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1522 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1528 // Check to see if this buildvec has a single non-undef value in its elements.
1529 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1530 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1531 if (!OpVal.getNode())
1532 OpVal = N->getOperand(i);
1533 else if (OpVal != N->getOperand(i))
1537 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1539 unsigned ValSizeInBytes = EltSize;
1541 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1542 Value = CN->getZExtValue();
1543 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1544 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1545 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1548 // If the splat value is larger than the element value, then we can never do
1549 // this splat. The only case that we could fit the replicated bits into our
1550 // immediate field for would be zero, and we prefer to use vxor for it.
1551 if (ValSizeInBytes < ByteSize) return SDValue();
1553 // If the element value is larger than the splat value, check if it consists
1554 // of a repeated bit pattern of size ByteSize.
1555 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1558 // Properly sign extend the value.
1559 int MaskVal = SignExtend32(Value, ByteSize * 8);
1561 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1562 if (MaskVal == 0) return SDValue();
1564 // Finally, if this value fits in a 5 bit sext field, return it
1565 if (SignExtend32<5>(MaskVal) == MaskVal)
1566 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1570 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1571 /// amount, otherwise return -1.
1572 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1573 EVT VT = N->getValueType(0);
1574 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1577 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1579 // Find the first non-undef value in the shuffle mask.
1581 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1584 if (i == 4) return -1; // all undef.
1586 // Otherwise, check to see if the rest of the elements are consecutively
1587 // numbered from this value.
1588 unsigned ShiftAmt = SVOp->getMaskElt(i);
1589 if (ShiftAmt < i) return -1;
1592 // Check the rest of the elements to see if they are consecutive.
1593 for (++i; i != 4; ++i)
1594 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1600 //===----------------------------------------------------------------------===//
1601 // Addressing Mode Selection
1602 //===----------------------------------------------------------------------===//
1604 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1605 /// or 64-bit immediate, and if the value can be accurately represented as a
1606 /// sign extension from a 16-bit value. If so, this returns true and the
1608 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1609 if (!isa<ConstantSDNode>(N))
1612 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1613 if (N->getValueType(0) == MVT::i32)
1614 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1616 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1618 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1619 return isIntS16Immediate(Op.getNode(), Imm);
1623 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1624 /// can be represented as an indexed [r+r] operation. Returns false if it
1625 /// can be more efficiently represented with [r+imm].
1626 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1628 SelectionDAG &DAG) const {
1630 if (N.getOpcode() == ISD::ADD) {
1631 if (isIntS16Immediate(N.getOperand(1), imm))
1632 return false; // r+i
1633 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1634 return false; // r+i
1636 Base = N.getOperand(0);
1637 Index = N.getOperand(1);
1639 } else if (N.getOpcode() == ISD::OR) {
1640 if (isIntS16Immediate(N.getOperand(1), imm))
1641 return false; // r+i can fold it if we can.
1643 // If this is an or of disjoint bitfields, we can codegen this as an add
1644 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1646 APInt LHSKnownZero, LHSKnownOne;
1647 APInt RHSKnownZero, RHSKnownOne;
1648 DAG.computeKnownBits(N.getOperand(0),
1649 LHSKnownZero, LHSKnownOne);
1651 if (LHSKnownZero.getBoolValue()) {
1652 DAG.computeKnownBits(N.getOperand(1),
1653 RHSKnownZero, RHSKnownOne);
1654 // If all of the bits are known zero on the LHS or RHS, the add won't
1656 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1657 Base = N.getOperand(0);
1658 Index = N.getOperand(1);
1667 // If we happen to be doing an i64 load or store into a stack slot that has
1668 // less than a 4-byte alignment, then the frame-index elimination may need to
1669 // use an indexed load or store instruction (because the offset may not be a
1670 // multiple of 4). The extra register needed to hold the offset comes from the
1671 // register scavenger, and it is possible that the scavenger will need to use
1672 // an emergency spill slot. As a result, we need to make sure that a spill slot
1673 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1675 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1676 // FIXME: This does not handle the LWA case.
1680 // NOTE: We'll exclude negative FIs here, which come from argument
1681 // lowering, because there are no known test cases triggering this problem
1682 // using packed structures (or similar). We can remove this exclusion if
1683 // we find such a test case. The reason why this is so test-case driven is
1684 // because this entire 'fixup' is only to prevent crashes (from the
1685 // register scavenger) on not-really-valid inputs. For example, if we have:
1687 // %b = bitcast i1* %a to i64*
1688 // store i64* a, i64 b
1689 // then the store should really be marked as 'align 1', but is not. If it
1690 // were marked as 'align 1' then the indexed form would have been
1691 // instruction-selected initially, and the problem this 'fixup' is preventing
1692 // won't happen regardless.
1696 MachineFunction &MF = DAG.getMachineFunction();
1697 MachineFrameInfo *MFI = MF.getFrameInfo();
1699 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1703 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1704 FuncInfo->setHasNonRISpills();
1707 /// Returns true if the address N can be represented by a base register plus
1708 /// a signed 16-bit displacement [r+imm], and if it is not better
1709 /// represented as reg+reg. If Aligned is true, only accept displacements
1710 /// suitable for STD and friends, i.e. multiples of 4.
1711 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1714 bool Aligned) const {
1715 // FIXME dl should come from parent load or store, not from address
1717 // If this can be more profitably realized as r+r, fail.
1718 if (SelectAddressRegReg(N, Disp, Base, DAG))
1721 if (N.getOpcode() == ISD::ADD) {
1723 if (isIntS16Immediate(N.getOperand(1), imm) &&
1724 (!Aligned || (imm & 3) == 0)) {
1725 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1726 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1727 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1728 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1730 Base = N.getOperand(0);
1732 return true; // [r+i]
1733 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1734 // Match LOAD (ADD (X, Lo(G))).
1735 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1736 && "Cannot handle constant offsets yet!");
1737 Disp = N.getOperand(1).getOperand(0); // The global address.
1738 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1739 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1740 Disp.getOpcode() == ISD::TargetConstantPool ||
1741 Disp.getOpcode() == ISD::TargetJumpTable);
1742 Base = N.getOperand(0);
1743 return true; // [&g+r]
1745 } else if (N.getOpcode() == ISD::OR) {
1747 if (isIntS16Immediate(N.getOperand(1), imm) &&
1748 (!Aligned || (imm & 3) == 0)) {
1749 // If this is an or of disjoint bitfields, we can codegen this as an add
1750 // (for better address arithmetic) if the LHS and RHS of the OR are
1751 // provably disjoint.
1752 APInt LHSKnownZero, LHSKnownOne;
1753 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1755 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1756 // If all of the bits are known zero on the LHS or RHS, the add won't
1758 if (FrameIndexSDNode *FI =
1759 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1760 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1761 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1763 Base = N.getOperand(0);
1765 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1769 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1770 // Loading from a constant address.
1772 // If this address fits entirely in a 16-bit sext immediate field, codegen
1775 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1776 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1777 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1778 CN->getValueType(0));
1782 // Handle 32-bit sext immediates with LIS + addr mode.
1783 if ((CN->getValueType(0) == MVT::i32 ||
1784 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1785 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1786 int Addr = (int)CN->getZExtValue();
1788 // Otherwise, break this down into an LIS + disp.
1789 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1791 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1793 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1794 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1799 Disp = DAG.getTargetConstant(0, dl, getPointerTy());
1800 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1801 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1802 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1805 return true; // [r+0]
1808 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1809 /// represented as an indexed [r+r] operation.
1810 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1812 SelectionDAG &DAG) const {
1813 // Check to see if we can easily represent this as an [r+r] address. This
1814 // will fail if it thinks that the address is more profitably represented as
1815 // reg+imm, e.g. where imm = 0.
1816 if (SelectAddressRegReg(N, Base, Index, DAG))
1819 // If the operand is an addition, always emit this as [r+r], since this is
1820 // better (for code size, and execution, as the memop does the add for free)
1821 // than emitting an explicit add.
1822 if (N.getOpcode() == ISD::ADD) {
1823 Base = N.getOperand(0);
1824 Index = N.getOperand(1);
1828 // Otherwise, do it the hard way, using R0 as the base register.
1829 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1835 /// getPreIndexedAddressParts - returns true by value, base pointer and
1836 /// offset pointer and addressing mode by reference if the node's address
1837 /// can be legally represented as pre-indexed load / store address.
1838 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1840 ISD::MemIndexedMode &AM,
1841 SelectionDAG &DAG) const {
1842 if (DisablePPCPreinc) return false;
1848 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1849 Ptr = LD->getBasePtr();
1850 VT = LD->getMemoryVT();
1851 Alignment = LD->getAlignment();
1852 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1853 Ptr = ST->getBasePtr();
1854 VT = ST->getMemoryVT();
1855 Alignment = ST->getAlignment();
1860 // PowerPC doesn't have preinc load/store instructions for vectors (except
1861 // for QPX, which does have preinc r+r forms).
1862 if (VT.isVector()) {
1863 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1865 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1871 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1873 // Common code will reject creating a pre-inc form if the base pointer
1874 // is a frame index, or if N is a store and the base pointer is either
1875 // the same as or a predecessor of the value being stored. Check for
1876 // those situations here, and try with swapped Base/Offset instead.
1879 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1882 SDValue Val = cast<StoreSDNode>(N)->getValue();
1883 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1888 std::swap(Base, Offset);
1894 // LDU/STU can only handle immediates that are a multiple of 4.
1895 if (VT != MVT::i64) {
1896 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1899 // LDU/STU need an address with at least 4-byte alignment.
1903 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1907 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1908 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1909 // sext i32 to i64 when addr mode is r+i.
1910 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1911 LD->getExtensionType() == ISD::SEXTLOAD &&
1912 isa<ConstantSDNode>(Offset))
1920 //===----------------------------------------------------------------------===//
1921 // LowerOperation implementation
1922 //===----------------------------------------------------------------------===//
1924 /// GetLabelAccessInfo - Return true if we should reference labels using a
1925 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1926 static bool GetLabelAccessInfo(const TargetMachine &TM,
1927 const PPCSubtarget &Subtarget,
1928 unsigned &HiOpFlags, unsigned &LoOpFlags,
1929 const GlobalValue *GV = nullptr) {
1930 HiOpFlags = PPCII::MO_HA;
1931 LoOpFlags = PPCII::MO_LO;
1933 // Don't use the pic base if not in PIC relocation model.
1934 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1937 HiOpFlags |= PPCII::MO_PIC_FLAG;
1938 LoOpFlags |= PPCII::MO_PIC_FLAG;
1941 // If this is a reference to a global value that requires a non-lazy-ptr, make
1942 // sure that instruction lowering adds it.
1943 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1944 HiOpFlags |= PPCII::MO_NLP_FLAG;
1945 LoOpFlags |= PPCII::MO_NLP_FLAG;
1947 if (GV->hasHiddenVisibility()) {
1948 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1949 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1956 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1957 SelectionDAG &DAG) {
1959 EVT PtrVT = HiPart.getValueType();
1960 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1962 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1963 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1965 // With PIC, the first instruction is actually "GR+hi(&G)".
1967 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1968 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1970 // Generate non-pic code that has direct accesses to the constant pool.
1971 // The address of the global is just (hi(&g)+lo(&g)).
1972 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1975 static void setUsesTOCBasePtr(MachineFunction &MF) {
1976 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1977 FuncInfo->setUsesTOCBasePtr();
1980 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1981 setUsesTOCBasePtr(DAG.getMachineFunction());
1984 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
1986 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1987 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
1988 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
1990 SDValue Ops[] = { GA, Reg };
1991 return DAG.getMemIntrinsicNode(PPCISD::TOC_ENTRY, dl,
1992 DAG.getVTList(VT, MVT::Other), Ops, VT,
1993 MachinePointerInfo::getGOT(), 0, false, true,
1997 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1998 SelectionDAG &DAG) const {
1999 EVT PtrVT = Op.getValueType();
2000 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2001 const Constant *C = CP->getConstVal();
2003 // 64-bit SVR4 ABI code is always position-independent.
2004 // The actual address of the GlobalValue is stored in the TOC.
2005 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2006 setUsesTOCBasePtr(DAG);
2007 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2008 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2011 unsigned MOHiFlag, MOLoFlag;
2013 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2015 if (isPIC && Subtarget.isSVR4ABI()) {
2016 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2017 PPCII::MO_PIC_FLAG);
2018 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2022 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2024 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2025 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2028 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2029 EVT PtrVT = Op.getValueType();
2030 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2032 // 64-bit SVR4 ABI code is always position-independent.
2033 // The actual address of the GlobalValue is stored in the TOC.
2034 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2035 setUsesTOCBasePtr(DAG);
2036 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2037 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2040 unsigned MOHiFlag, MOLoFlag;
2042 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2044 if (isPIC && Subtarget.isSVR4ABI()) {
2045 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2046 PPCII::MO_PIC_FLAG);
2047 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2050 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2051 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2052 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2055 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2056 SelectionDAG &DAG) const {
2057 EVT PtrVT = Op.getValueType();
2058 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2059 const BlockAddress *BA = BASDN->getBlockAddress();
2061 // 64-bit SVR4 ABI code is always position-independent.
2062 // The actual BlockAddress is stored in the TOC.
2063 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2064 setUsesTOCBasePtr(DAG);
2065 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2066 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2069 unsigned MOHiFlag, MOLoFlag;
2071 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2072 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2073 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2074 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2077 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2078 SelectionDAG &DAG) const {
2080 // FIXME: TLS addresses currently use medium model code sequences,
2081 // which is the most useful form. Eventually support for small and
2082 // large models could be added if users need it, at the cost of
2083 // additional complexity.
2084 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2086 const GlobalValue *GV = GA->getGlobal();
2087 EVT PtrVT = getPointerTy();
2088 bool is64bit = Subtarget.isPPC64();
2089 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2090 PICLevel::Level picLevel = M->getPICLevel();
2092 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2094 if (Model == TLSModel::LocalExec) {
2095 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2096 PPCII::MO_TPREL_HA);
2097 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2098 PPCII::MO_TPREL_LO);
2099 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2100 is64bit ? MVT::i64 : MVT::i32);
2101 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2102 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2105 if (Model == TLSModel::InitialExec) {
2106 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2107 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2111 setUsesTOCBasePtr(DAG);
2112 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2113 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2114 PtrVT, GOTReg, TGA);
2116 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2117 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2118 PtrVT, TGA, GOTPtr);
2119 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2122 if (Model == TLSModel::GeneralDynamic) {
2123 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2126 setUsesTOCBasePtr(DAG);
2127 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2128 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2131 if (picLevel == PICLevel::Small)
2132 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2134 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2136 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2140 if (Model == TLSModel::LocalDynamic) {
2141 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2144 setUsesTOCBasePtr(DAG);
2145 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2146 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2149 if (picLevel == PICLevel::Small)
2150 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2152 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2154 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2155 PtrVT, GOTPtr, TGA, TGA);
2156 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2157 PtrVT, TLSAddr, TGA);
2158 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2161 llvm_unreachable("Unknown TLS model!");
2164 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2165 SelectionDAG &DAG) const {
2166 EVT PtrVT = Op.getValueType();
2167 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2169 const GlobalValue *GV = GSDN->getGlobal();
2171 // 64-bit SVR4 ABI code is always position-independent.
2172 // The actual address of the GlobalValue is stored in the TOC.
2173 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2174 setUsesTOCBasePtr(DAG);
2175 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2176 return getTOCEntry(DAG, DL, true, GA);
2179 unsigned MOHiFlag, MOLoFlag;
2181 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2183 if (isPIC && Subtarget.isSVR4ABI()) {
2184 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2186 PPCII::MO_PIC_FLAG);
2187 return getTOCEntry(DAG, DL, false, GA);
2191 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2193 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2195 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2197 // If the global reference is actually to a non-lazy-pointer, we have to do an
2198 // extra load to get the address of the global.
2199 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2200 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2201 false, false, false, 0);
2205 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2206 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2209 if (Op.getValueType() == MVT::v2i64) {
2210 // When the operands themselves are v2i64 values, we need to do something
2211 // special because VSX has no underlying comparison operations for these.
2212 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2213 // Equality can be handled by casting to the legal type for Altivec
2214 // comparisons, everything else needs to be expanded.
2215 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2216 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2217 DAG.getSetCC(dl, MVT::v4i32,
2218 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2219 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2226 // We handle most of these in the usual way.
2230 // If we're comparing for equality to zero, expose the fact that this is
2231 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2232 // fold the new nodes.
2233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2234 if (C->isNullValue() && CC == ISD::SETEQ) {
2235 EVT VT = Op.getOperand(0).getValueType();
2236 SDValue Zext = Op.getOperand(0);
2237 if (VT.bitsLT(MVT::i32)) {
2239 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2241 unsigned Log2b = Log2_32(VT.getSizeInBits());
2242 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2243 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2244 DAG.getConstant(Log2b, dl, MVT::i32));
2245 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2247 // Leave comparisons against 0 and -1 alone for now, since they're usually
2248 // optimized. FIXME: revisit this when we can custom lower all setcc
2250 if (C->isAllOnesValue() || C->isNullValue())
2254 // If we have an integer seteq/setne, turn it into a compare against zero
2255 // by xor'ing the rhs with the lhs, which is faster than setting a
2256 // condition register, reading it back out, and masking the correct bit. The
2257 // normal approach here uses sub to do this instead of xor. Using xor exposes
2258 // the result to other bit-twiddling opportunities.
2259 EVT LHSVT = Op.getOperand(0).getValueType();
2260 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2261 EVT VT = Op.getValueType();
2262 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2264 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2269 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2270 const PPCSubtarget &Subtarget) const {
2271 SDNode *Node = Op.getNode();
2272 EVT VT = Node->getValueType(0);
2273 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2274 SDValue InChain = Node->getOperand(0);
2275 SDValue VAListPtr = Node->getOperand(1);
2276 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2279 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2282 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2283 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2284 false, false, false, 0);
2285 InChain = GprIndex.getValue(1);
2287 if (VT == MVT::i64) {
2288 // Check if GprIndex is even
2289 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2290 DAG.getConstant(1, dl, MVT::i32));
2291 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2292 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2293 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2294 DAG.getConstant(1, dl, MVT::i32));
2295 // Align GprIndex to be even if it isn't
2296 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2300 // fpr index is 1 byte after gpr
2301 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2302 DAG.getConstant(1, dl, MVT::i32));
2305 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2306 FprPtr, MachinePointerInfo(SV), MVT::i8,
2307 false, false, false, 0);
2308 InChain = FprIndex.getValue(1);
2310 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2311 DAG.getConstant(8, dl, MVT::i32));
2313 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2314 DAG.getConstant(4, dl, MVT::i32));
2317 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2318 MachinePointerInfo(), false, false,
2320 InChain = OverflowArea.getValue(1);
2322 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2323 MachinePointerInfo(), false, false,
2325 InChain = RegSaveArea.getValue(1);
2327 // select overflow_area if index > 8
2328 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2329 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2331 // adjustment constant gpr_index * 4/8
2332 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2333 VT.isInteger() ? GprIndex : FprIndex,
2334 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2337 // OurReg = RegSaveArea + RegConstant
2338 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2341 // Floating types are 32 bytes into RegSaveArea
2342 if (VT.isFloatingPoint())
2343 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2344 DAG.getConstant(32, dl, MVT::i32));
2346 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2347 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2348 VT.isInteger() ? GprIndex : FprIndex,
2349 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2352 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2353 VT.isInteger() ? VAListPtr : FprPtr,
2354 MachinePointerInfo(SV),
2355 MVT::i8, false, false, 0);
2357 // determine if we should load from reg_save_area or overflow_area
2358 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2360 // increase overflow_area by 4/8 if gpr/fpr > 8
2361 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2362 DAG.getConstant(VT.isInteger() ? 4 : 8,
2365 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2368 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2370 MachinePointerInfo(),
2371 MVT::i32, false, false, 0);
2373 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2374 false, false, false, 0);
2377 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2378 const PPCSubtarget &Subtarget) const {
2379 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2381 // We have to copy the entire va_list struct:
2382 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2383 return DAG.getMemcpy(Op.getOperand(0), Op,
2384 Op.getOperand(1), Op.getOperand(2),
2385 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2386 false, MachinePointerInfo(), MachinePointerInfo());
2389 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2390 SelectionDAG &DAG) const {
2391 return Op.getOperand(0);
2394 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2395 SelectionDAG &DAG) const {
2396 SDValue Chain = Op.getOperand(0);
2397 SDValue Trmp = Op.getOperand(1); // trampoline
2398 SDValue FPtr = Op.getOperand(2); // nested function
2399 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2402 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2403 bool isPPC64 = (PtrVT == MVT::i64);
2405 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2408 TargetLowering::ArgListTy Args;
2409 TargetLowering::ArgListEntry Entry;
2411 Entry.Ty = IntPtrTy;
2412 Entry.Node = Trmp; Args.push_back(Entry);
2414 // TrampSize == (isPPC64 ? 48 : 40);
2415 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2416 isPPC64 ? MVT::i64 : MVT::i32);
2417 Args.push_back(Entry);
2419 Entry.Node = FPtr; Args.push_back(Entry);
2420 Entry.Node = Nest; Args.push_back(Entry);
2422 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2423 TargetLowering::CallLoweringInfo CLI(DAG);
2424 CLI.setDebugLoc(dl).setChain(Chain)
2425 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2426 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2427 std::move(Args), 0);
2429 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2430 return CallResult.second;
2433 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2434 const PPCSubtarget &Subtarget) const {
2435 MachineFunction &MF = DAG.getMachineFunction();
2436 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2440 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2441 // vastart just stores the address of the VarArgsFrameIndex slot into the
2442 // memory location argument.
2443 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2444 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2445 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2446 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2447 MachinePointerInfo(SV),
2451 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2452 // We suppose the given va_list is already allocated.
2455 // char gpr; /* index into the array of 8 GPRs
2456 // * stored in the register save area
2457 // * gpr=0 corresponds to r3,
2458 // * gpr=1 to r4, etc.
2460 // char fpr; /* index into the array of 8 FPRs
2461 // * stored in the register save area
2462 // * fpr=0 corresponds to f1,
2463 // * fpr=1 to f2, etc.
2465 // char *overflow_arg_area;
2466 // /* location on stack that holds
2467 // * the next overflow argument
2469 // char *reg_save_area;
2470 // /* where r3:r10 and f1:f8 (if saved)
2476 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2477 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2480 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2482 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2484 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2487 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2488 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2490 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2491 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2493 uint64_t FPROffset = 1;
2494 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2496 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2498 // Store first byte : number of int regs
2499 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2501 MachinePointerInfo(SV),
2502 MVT::i8, false, false, 0);
2503 uint64_t nextOffset = FPROffset;
2504 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2507 // Store second byte : number of float regs
2508 SDValue secondStore =
2509 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2510 MachinePointerInfo(SV, nextOffset), MVT::i8,
2512 nextOffset += StackOffset;
2513 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2515 // Store second word : arguments given on stack
2516 SDValue thirdStore =
2517 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2518 MachinePointerInfo(SV, nextOffset),
2520 nextOffset += FrameOffset;
2521 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2523 // Store third word : arguments given in registers
2524 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2525 MachinePointerInfo(SV, nextOffset),
2530 #include "PPCGenCallingConv.inc"
2532 // Function whose sole purpose is to kill compiler warnings
2533 // stemming from unused functions included from PPCGenCallingConv.inc.
2534 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2535 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2538 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2539 CCValAssign::LocInfo &LocInfo,
2540 ISD::ArgFlagsTy &ArgFlags,
2545 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2547 CCValAssign::LocInfo &LocInfo,
2548 ISD::ArgFlagsTy &ArgFlags,
2550 static const MCPhysReg ArgRegs[] = {
2551 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2552 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2554 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2556 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2558 // Skip one register if the first unallocated register has an even register
2559 // number and there are still argument registers available which have not been
2560 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2561 // need to skip a register if RegNum is odd.
2562 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2563 State.AllocateReg(ArgRegs[RegNum]);
2566 // Always return false here, as this function only makes sure that the first
2567 // unallocated register has an odd register number and does not actually
2568 // allocate a register for the current argument.
2572 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2574 CCValAssign::LocInfo &LocInfo,
2575 ISD::ArgFlagsTy &ArgFlags,
2577 static const MCPhysReg ArgRegs[] = {
2578 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2582 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2584 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2586 // If there is only one Floating-point register left we need to put both f64
2587 // values of a split ppc_fp128 value on the stack.
2588 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2589 State.AllocateReg(ArgRegs[RegNum]);
2592 // Always return false here, as this function only makes sure that the two f64
2593 // values a ppc_fp128 value is split into are both passed in registers or both
2594 // passed on the stack and does not actually allocate a register for the
2595 // current argument.
2599 /// FPR - The set of FP registers that should be allocated for arguments,
2601 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2602 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2603 PPC::F11, PPC::F12, PPC::F13};
2605 /// QFPR - The set of QPX registers that should be allocated for arguments.
2606 static const MCPhysReg QFPR[] = {
2607 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2608 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2610 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2612 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2613 unsigned PtrByteSize) {
2614 unsigned ArgSize = ArgVT.getStoreSize();
2615 if (Flags.isByVal())
2616 ArgSize = Flags.getByValSize();
2618 // Round up to multiples of the pointer size, except for array members,
2619 // which are always packed.
2620 if (!Flags.isInConsecutiveRegs())
2621 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2626 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2628 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2629 ISD::ArgFlagsTy Flags,
2630 unsigned PtrByteSize) {
2631 unsigned Align = PtrByteSize;
2633 // Altivec parameters are padded to a 16 byte boundary.
2634 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2635 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2636 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2637 ArgVT == MVT::v1i128)
2639 // QPX vector types stored in double-precision are padded to a 32 byte
2641 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2644 // ByVal parameters are aligned as requested.
2645 if (Flags.isByVal()) {
2646 unsigned BVAlign = Flags.getByValAlign();
2647 if (BVAlign > PtrByteSize) {
2648 if (BVAlign % PtrByteSize != 0)
2650 "ByVal alignment is not a multiple of the pointer size");
2656 // Array members are always packed to their original alignment.
2657 if (Flags.isInConsecutiveRegs()) {
2658 // If the array member was split into multiple registers, the first
2659 // needs to be aligned to the size of the full type. (Except for
2660 // ppcf128, which is only aligned as its f64 components.)
2661 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2662 Align = OrigVT.getStoreSize();
2664 Align = ArgVT.getStoreSize();
2670 /// CalculateStackSlotUsed - Return whether this argument will use its
2671 /// stack slot (instead of being passed in registers). ArgOffset,
2672 /// AvailableFPRs, and AvailableVRs must hold the current argument
2673 /// position, and will be updated to account for this argument.
2674 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2675 ISD::ArgFlagsTy Flags,
2676 unsigned PtrByteSize,
2677 unsigned LinkageSize,
2678 unsigned ParamAreaSize,
2679 unsigned &ArgOffset,
2680 unsigned &AvailableFPRs,
2681 unsigned &AvailableVRs, bool HasQPX) {
2682 bool UseMemory = false;
2684 // Respect alignment of argument on the stack.
2686 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2687 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2688 // If there's no space left in the argument save area, we must
2689 // use memory (this check also catches zero-sized arguments).
2690 if (ArgOffset >= LinkageSize + ParamAreaSize)
2693 // Allocate argument on the stack.
2694 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2695 if (Flags.isInConsecutiveRegsLast())
2696 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2697 // If we overran the argument save area, we must use memory
2698 // (this check catches arguments passed partially in memory)
2699 if (ArgOffset > LinkageSize + ParamAreaSize)
2702 // However, if the argument is actually passed in an FPR or a VR,
2703 // we don't use memory after all.
2704 if (!Flags.isByVal()) {
2705 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2706 // QPX registers overlap with the scalar FP registers.
2707 (HasQPX && (ArgVT == MVT::v4f32 ||
2708 ArgVT == MVT::v4f64 ||
2709 ArgVT == MVT::v4i1)))
2710 if (AvailableFPRs > 0) {
2714 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2715 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2716 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2717 ArgVT == MVT::v1i128)
2718 if (AvailableVRs > 0) {
2727 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2728 /// ensure minimum alignment required for target.
2729 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2730 unsigned NumBytes) {
2731 unsigned TargetAlign = Lowering->getStackAlignment();
2732 unsigned AlignMask = TargetAlign - 1;
2733 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2738 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2739 CallingConv::ID CallConv, bool isVarArg,
2740 const SmallVectorImpl<ISD::InputArg>
2742 SDLoc dl, SelectionDAG &DAG,
2743 SmallVectorImpl<SDValue> &InVals)
2745 if (Subtarget.isSVR4ABI()) {
2746 if (Subtarget.isPPC64())
2747 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2750 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2753 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2759 PPCTargetLowering::LowerFormalArguments_32SVR4(
2761 CallingConv::ID CallConv, bool isVarArg,
2762 const SmallVectorImpl<ISD::InputArg>
2764 SDLoc dl, SelectionDAG &DAG,
2765 SmallVectorImpl<SDValue> &InVals) const {
2767 // 32-bit SVR4 ABI Stack Frame Layout:
2768 // +-----------------------------------+
2769 // +--> | Back chain |
2770 // | +-----------------------------------+
2771 // | | Floating-point register save area |
2772 // | +-----------------------------------+
2773 // | | General register save area |
2774 // | +-----------------------------------+
2775 // | | CR save word |
2776 // | +-----------------------------------+
2777 // | | VRSAVE save word |
2778 // | +-----------------------------------+
2779 // | | Alignment padding |
2780 // | +-----------------------------------+
2781 // | | Vector register save area |
2782 // | +-----------------------------------+
2783 // | | Local variable space |
2784 // | +-----------------------------------+
2785 // | | Parameter list area |
2786 // | +-----------------------------------+
2787 // | | LR save word |
2788 // | +-----------------------------------+
2789 // SP--> +--- | Back chain |
2790 // +-----------------------------------+
2793 // System V Application Binary Interface PowerPC Processor Supplement
2794 // AltiVec Technology Programming Interface Manual
2796 MachineFunction &MF = DAG.getMachineFunction();
2797 MachineFrameInfo *MFI = MF.getFrameInfo();
2798 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2800 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2801 // Potential tail calls could cause overwriting of argument stack slots.
2802 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2803 (CallConv == CallingConv::Fast));
2804 unsigned PtrByteSize = 4;
2806 // Assign locations to all of the incoming arguments.
2807 SmallVector<CCValAssign, 16> ArgLocs;
2808 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2811 // Reserve space for the linkage area on the stack.
2812 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2813 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2815 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2817 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2818 CCValAssign &VA = ArgLocs[i];
2820 // Arguments stored in registers.
2821 if (VA.isRegLoc()) {
2822 const TargetRegisterClass *RC;
2823 EVT ValVT = VA.getValVT();
2825 switch (ValVT.getSimpleVT().SimpleTy) {
2827 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2830 RC = &PPC::GPRCRegClass;
2833 if (Subtarget.hasP8Vector())
2834 RC = &PPC::VSSRCRegClass;
2836 RC = &PPC::F4RCRegClass;
2839 if (Subtarget.hasVSX())
2840 RC = &PPC::VSFRCRegClass;
2842 RC = &PPC::F8RCRegClass;
2847 RC = &PPC::VRRCRegClass;
2850 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2854 RC = &PPC::VSHRCRegClass;
2857 RC = &PPC::QFRCRegClass;
2860 RC = &PPC::QBRCRegClass;
2864 // Transform the arguments stored in physical registers into virtual ones.
2865 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2866 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2867 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2869 if (ValVT == MVT::i1)
2870 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2872 InVals.push_back(ArgValue);
2874 // Argument stored in memory.
2875 assert(VA.isMemLoc());
2877 unsigned ArgSize = VA.getLocVT().getStoreSize();
2878 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2881 // Create load nodes to retrieve arguments from the stack.
2882 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2883 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2884 MachinePointerInfo(),
2885 false, false, false, 0));
2889 // Assign locations to all of the incoming aggregate by value arguments.
2890 // Aggregates passed by value are stored in the local variable space of the
2891 // caller's stack frame, right above the parameter list area.
2892 SmallVector<CCValAssign, 16> ByValArgLocs;
2893 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2894 ByValArgLocs, *DAG.getContext());
2896 // Reserve stack space for the allocations in CCInfo.
2897 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2899 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2901 // Area that is at least reserved in the caller of this function.
2902 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2903 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2905 // Set the size that is at least reserved in caller of this function. Tail
2906 // call optimized function's reserved stack space needs to be aligned so that
2907 // taking the difference between two stack areas will result in an aligned
2910 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2911 FuncInfo->setMinReservedArea(MinReservedArea);
2913 SmallVector<SDValue, 8> MemOps;
2915 // If the function takes variable number of arguments, make a frame index for
2916 // the start of the first vararg value... for expansion of llvm.va_start.
2918 static const MCPhysReg GPArgRegs[] = {
2919 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2920 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2922 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2924 static const MCPhysReg FPArgRegs[] = {
2925 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2928 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2929 if (DisablePPCFloatInVariadic)
2932 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2933 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2935 // Make room for NumGPArgRegs and NumFPArgRegs.
2936 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2937 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2939 FuncInfo->setVarArgsStackOffset(
2940 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2941 CCInfo.getNextStackOffset(), true));
2943 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2944 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2946 // The fixed integer arguments of a variadic function are stored to the
2947 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2948 // the result of va_next.
2949 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2950 // Get an existing live-in vreg, or add a new one.
2951 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2953 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2955 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2956 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2957 MachinePointerInfo(), false, false, 0);
2958 MemOps.push_back(Store);
2959 // Increment the address by four for the next argument to store
2960 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2961 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2964 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2966 // The double arguments are stored to the VarArgsFrameIndex
2968 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2969 // Get an existing live-in vreg, or add a new one.
2970 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2972 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2975 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2976 MachinePointerInfo(), false, false, 0);
2977 MemOps.push_back(Store);
2978 // Increment the address by eight for the next argument to store
2979 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2981 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2985 if (!MemOps.empty())
2986 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2991 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2992 // value to MVT::i64 and then truncate to the correct register size.
2994 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2995 SelectionDAG &DAG, SDValue ArgVal,
2998 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2999 DAG.getValueType(ObjectVT));
3000 else if (Flags.isZExt())
3001 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3002 DAG.getValueType(ObjectVT));
3004 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3008 PPCTargetLowering::LowerFormalArguments_64SVR4(
3010 CallingConv::ID CallConv, bool isVarArg,
3011 const SmallVectorImpl<ISD::InputArg>
3013 SDLoc dl, SelectionDAG &DAG,
3014 SmallVectorImpl<SDValue> &InVals) const {
3015 // TODO: add description of PPC stack frame format, or at least some docs.
3017 bool isELFv2ABI = Subtarget.isELFv2ABI();
3018 bool isLittleEndian = Subtarget.isLittleEndian();
3019 MachineFunction &MF = DAG.getMachineFunction();
3020 MachineFrameInfo *MFI = MF.getFrameInfo();
3021 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3023 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3024 "fastcc not supported on varargs functions");
3026 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3027 // Potential tail calls could cause overwriting of argument stack slots.
3028 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3029 (CallConv == CallingConv::Fast));
3030 unsigned PtrByteSize = 8;
3031 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3033 static const MCPhysReg GPR[] = {
3034 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3035 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3037 static const MCPhysReg VR[] = {
3038 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3039 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3041 static const MCPhysReg VSRH[] = {
3042 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3043 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3046 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3047 const unsigned Num_FPR_Regs = 13;
3048 const unsigned Num_VR_Regs = array_lengthof(VR);
3049 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3051 // Do a first pass over the arguments to determine whether the ABI
3052 // guarantees that our caller has allocated the parameter save area
3053 // on its stack frame. In the ELFv1 ABI, this is always the case;
3054 // in the ELFv2 ABI, it is true if this is a vararg function or if
3055 // any parameter is located in a stack slot.
3057 bool HasParameterArea = !isELFv2ABI || isVarArg;
3058 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3059 unsigned NumBytes = LinkageSize;
3060 unsigned AvailableFPRs = Num_FPR_Regs;
3061 unsigned AvailableVRs = Num_VR_Regs;
3062 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
3063 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3064 PtrByteSize, LinkageSize, ParamAreaSize,
3065 NumBytes, AvailableFPRs, AvailableVRs,
3066 Subtarget.hasQPX()))
3067 HasParameterArea = true;
3069 // Add DAG nodes to load the arguments or copy them out of registers. On
3070 // entry to a function on PPC, the arguments start after the linkage area,
3071 // although the first ones are often in registers.
3073 unsigned ArgOffset = LinkageSize;
3074 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3075 unsigned &QFPR_idx = FPR_idx;
3076 SmallVector<SDValue, 8> MemOps;
3077 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3078 unsigned CurArgIdx = 0;
3079 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3081 bool needsLoad = false;
3082 EVT ObjectVT = Ins[ArgNo].VT;
3083 EVT OrigVT = Ins[ArgNo].ArgVT;
3084 unsigned ObjSize = ObjectVT.getStoreSize();
3085 unsigned ArgSize = ObjSize;
3086 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3087 if (Ins[ArgNo].isOrigArg()) {
3088 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3089 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3091 // We re-align the argument offset for each argument, except when using the
3092 // fast calling convention, when we need to make sure we do that only when
3093 // we'll actually use a stack slot.
3094 unsigned CurArgOffset, Align;
3095 auto ComputeArgOffset = [&]() {
3096 /* Respect alignment of argument on the stack. */
3097 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3098 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3099 CurArgOffset = ArgOffset;
3102 if (CallConv != CallingConv::Fast) {
3105 /* Compute GPR index associated with argument offset. */
3106 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3107 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3110 // FIXME the codegen can be much improved in some cases.
3111 // We do not have to keep everything in memory.
3112 if (Flags.isByVal()) {
3113 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3115 if (CallConv == CallingConv::Fast)
3118 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3119 ObjSize = Flags.getByValSize();
3120 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3121 // Empty aggregate parameters do not take up registers. Examples:
3125 // etc. However, we have to provide a place-holder in InVals, so
3126 // pretend we have an 8-byte item at the current address for that
3129 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3130 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3131 InVals.push_back(FIN);
3135 // Create a stack object covering all stack doublewords occupied
3136 // by the argument. If the argument is (fully or partially) on
3137 // the stack, or if the argument is fully in registers but the
3138 // caller has allocated the parameter save anyway, we can refer
3139 // directly to the caller's stack frame. Otherwise, create a
3140 // local copy in our own frame.
3142 if (HasParameterArea ||
3143 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3144 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3146 FI = MFI->CreateStackObject(ArgSize, Align, false);
3147 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3149 // Handle aggregates smaller than 8 bytes.
3150 if (ObjSize < PtrByteSize) {
3151 // The value of the object is its address, which differs from the
3152 // address of the enclosing doubleword on big-endian systems.
3154 if (!isLittleEndian) {
3155 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3156 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3158 InVals.push_back(Arg);
3160 if (GPR_idx != Num_GPR_Regs) {
3161 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3162 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3165 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3166 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3167 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3168 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3169 MachinePointerInfo(FuncArg),
3170 ObjType, false, false, 0);
3172 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3173 // store the whole register as-is to the parameter save area
3175 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3176 MachinePointerInfo(FuncArg),
3180 MemOps.push_back(Store);
3182 // Whether we copied from a register or not, advance the offset
3183 // into the parameter save area by a full doubleword.
3184 ArgOffset += PtrByteSize;
3188 // The value of the object is its address, which is the address of
3189 // its first stack doubleword.
3190 InVals.push_back(FIN);
3192 // Store whatever pieces of the object are in registers to memory.
3193 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3194 if (GPR_idx == Num_GPR_Regs)
3197 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3198 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3201 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3202 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3204 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3205 MachinePointerInfo(FuncArg, j),
3207 MemOps.push_back(Store);
3210 ArgOffset += ArgSize;
3214 switch (ObjectVT.getSimpleVT().SimpleTy) {
3215 default: llvm_unreachable("Unhandled argument type!");
3219 // These can be scalar arguments or elements of an integer array type
3220 // passed directly. Clang may use those instead of "byval" aggregate
3221 // types to avoid forcing arguments to memory unnecessarily.
3222 if (GPR_idx != Num_GPR_Regs) {
3223 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3224 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3226 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3227 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3228 // value to MVT::i64 and then truncate to the correct register size.
3229 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3231 if (CallConv == CallingConv::Fast)
3235 ArgSize = PtrByteSize;
3237 if (CallConv != CallingConv::Fast || needsLoad)
3243 // These can be scalar arguments or elements of a float array type
3244 // passed directly. The latter are used to implement ELFv2 homogenous
3245 // float aggregates.
3246 if (FPR_idx != Num_FPR_Regs) {
3249 if (ObjectVT == MVT::f32)
3250 VReg = MF.addLiveIn(FPR[FPR_idx],
3251 Subtarget.hasP8Vector()
3252 ? &PPC::VSSRCRegClass
3253 : &PPC::F4RCRegClass);
3255 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3256 ? &PPC::VSFRCRegClass
3257 : &PPC::F8RCRegClass);
3259 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3261 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3262 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3263 // once we support fp <-> gpr moves.
3265 // This can only ever happen in the presence of f32 array types,
3266 // since otherwise we never run out of FPRs before running out
3268 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3269 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3271 if (ObjectVT == MVT::f32) {
3272 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3273 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3274 DAG.getConstant(32, dl, MVT::i32));
3275 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3278 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3280 if (CallConv == CallingConv::Fast)
3286 // When passing an array of floats, the array occupies consecutive
3287 // space in the argument area; only round up to the next doubleword
3288 // at the end of the array. Otherwise, each float takes 8 bytes.
3289 if (CallConv != CallingConv::Fast || needsLoad) {
3290 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3291 ArgOffset += ArgSize;
3292 if (Flags.isInConsecutiveRegsLast())
3293 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3303 if (!Subtarget.hasQPX()) {
3304 // These can be scalar arguments or elements of a vector array type
3305 // passed directly. The latter are used to implement ELFv2 homogenous
3306 // vector aggregates.
3307 if (VR_idx != Num_VR_Regs) {
3308 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3309 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3310 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3311 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3314 if (CallConv == CallingConv::Fast)
3319 if (CallConv != CallingConv::Fast || needsLoad)
3324 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3325 "Invalid QPX parameter type");
3330 // QPX vectors are treated like their scalar floating-point subregisters
3331 // (except that they're larger).
3332 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3333 if (QFPR_idx != Num_QFPR_Regs) {
3334 const TargetRegisterClass *RC;
3335 switch (ObjectVT.getSimpleVT().SimpleTy) {
3336 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3337 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3338 default: RC = &PPC::QBRCRegClass; break;
3341 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3342 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3345 if (CallConv == CallingConv::Fast)
3349 if (CallConv != CallingConv::Fast || needsLoad)
3354 // We need to load the argument to a virtual register if we determined
3355 // above that we ran out of physical registers of the appropriate type.
3357 if (ObjSize < ArgSize && !isLittleEndian)
3358 CurArgOffset += ArgSize - ObjSize;
3359 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3360 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3361 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3362 false, false, false, 0);
3365 InVals.push_back(ArgVal);
3368 // Area that is at least reserved in the caller of this function.
3369 unsigned MinReservedArea;
3370 if (HasParameterArea)
3371 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3373 MinReservedArea = LinkageSize;
3375 // Set the size that is at least reserved in caller of this function. Tail
3376 // call optimized functions' reserved stack space needs to be aligned so that
3377 // taking the difference between two stack areas will result in an aligned
3380 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3381 FuncInfo->setMinReservedArea(MinReservedArea);
3383 // If the function takes variable number of arguments, make a frame index for
3384 // the start of the first vararg value... for expansion of llvm.va_start.
3386 int Depth = ArgOffset;
3388 FuncInfo->setVarArgsFrameIndex(
3389 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3390 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3392 // If this function is vararg, store any remaining integer argument regs
3393 // to their spots on the stack so that they may be loaded by deferencing the
3394 // result of va_next.
3395 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3396 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3397 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3398 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3399 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3400 MachinePointerInfo(), false, false, 0);
3401 MemOps.push_back(Store);
3402 // Increment the address by four for the next argument to store
3403 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3404 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3408 if (!MemOps.empty())
3409 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3415 PPCTargetLowering::LowerFormalArguments_Darwin(
3417 CallingConv::ID CallConv, bool isVarArg,
3418 const SmallVectorImpl<ISD::InputArg>
3420 SDLoc dl, SelectionDAG &DAG,
3421 SmallVectorImpl<SDValue> &InVals) const {
3422 // TODO: add description of PPC stack frame format, or at least some docs.
3424 MachineFunction &MF = DAG.getMachineFunction();
3425 MachineFrameInfo *MFI = MF.getFrameInfo();
3426 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3428 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3429 bool isPPC64 = PtrVT == MVT::i64;
3430 // Potential tail calls could cause overwriting of argument stack slots.
3431 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3432 (CallConv == CallingConv::Fast));
3433 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3434 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3435 unsigned ArgOffset = LinkageSize;
3436 // Area that is at least reserved in caller of this function.
3437 unsigned MinReservedArea = ArgOffset;
3439 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3440 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3441 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3443 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3444 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3445 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3447 static const MCPhysReg VR[] = {
3448 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3449 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3452 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3453 const unsigned Num_FPR_Regs = 13;
3454 const unsigned Num_VR_Regs = array_lengthof( VR);
3456 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3458 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3460 // In 32-bit non-varargs functions, the stack space for vectors is after the
3461 // stack space for non-vectors. We do not use this space unless we have
3462 // too many vectors to fit in registers, something that only occurs in
3463 // constructed examples:), but we have to walk the arglist to figure
3464 // that out...for the pathological case, compute VecArgOffset as the
3465 // start of the vector parameter area. Computing VecArgOffset is the
3466 // entire point of the following loop.
3467 unsigned VecArgOffset = ArgOffset;
3468 if (!isVarArg && !isPPC64) {
3469 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3471 EVT ObjectVT = Ins[ArgNo].VT;
3472 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3474 if (Flags.isByVal()) {
3475 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3476 unsigned ObjSize = Flags.getByValSize();
3478 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3479 VecArgOffset += ArgSize;
3483 switch(ObjectVT.getSimpleVT().SimpleTy) {
3484 default: llvm_unreachable("Unhandled argument type!");
3490 case MVT::i64: // PPC64
3492 // FIXME: We are guaranteed to be !isPPC64 at this point.
3493 // Does MVT::i64 apply?
3500 // Nothing to do, we're only looking at Nonvector args here.
3505 // We've found where the vector parameter area in memory is. Skip the
3506 // first 12 parameters; these don't use that memory.
3507 VecArgOffset = ((VecArgOffset+15)/16)*16;
3508 VecArgOffset += 12*16;
3510 // Add DAG nodes to load the arguments or copy them out of registers. On
3511 // entry to a function on PPC, the arguments start after the linkage area,
3512 // although the first ones are often in registers.
3514 SmallVector<SDValue, 8> MemOps;
3515 unsigned nAltivecParamsAtEnd = 0;
3516 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3517 unsigned CurArgIdx = 0;
3518 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3520 bool needsLoad = false;
3521 EVT ObjectVT = Ins[ArgNo].VT;
3522 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3523 unsigned ArgSize = ObjSize;
3524 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3525 if (Ins[ArgNo].isOrigArg()) {
3526 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3527 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3529 unsigned CurArgOffset = ArgOffset;
3531 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3532 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3533 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3534 if (isVarArg || isPPC64) {
3535 MinReservedArea = ((MinReservedArea+15)/16)*16;
3536 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3539 } else nAltivecParamsAtEnd++;
3541 // Calculate min reserved area.
3542 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3546 // FIXME the codegen can be much improved in some cases.
3547 // We do not have to keep everything in memory.
3548 if (Flags.isByVal()) {
3549 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3551 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3552 ObjSize = Flags.getByValSize();
3553 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3554 // Objects of size 1 and 2 are right justified, everything else is
3555 // left justified. This means the memory address is adjusted forwards.
3556 if (ObjSize==1 || ObjSize==2) {
3557 CurArgOffset = CurArgOffset + (4 - ObjSize);
3559 // The value of the object is its address.
3560 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3561 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3562 InVals.push_back(FIN);
3563 if (ObjSize==1 || ObjSize==2) {
3564 if (GPR_idx != Num_GPR_Regs) {
3567 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3569 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3570 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3571 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3572 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3573 MachinePointerInfo(FuncArg),
3574 ObjType, false, false, 0);
3575 MemOps.push_back(Store);
3579 ArgOffset += PtrByteSize;
3583 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3584 // Store whatever pieces of the object are in registers
3585 // to memory. ArgOffset will be the address of the beginning
3587 if (GPR_idx != Num_GPR_Regs) {
3590 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3592 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3593 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3594 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3595 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3596 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3597 MachinePointerInfo(FuncArg, j),
3599 MemOps.push_back(Store);
3601 ArgOffset += PtrByteSize;
3603 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3610 switch (ObjectVT.getSimpleVT().SimpleTy) {
3611 default: llvm_unreachable("Unhandled argument type!");
3615 if (GPR_idx != Num_GPR_Regs) {
3616 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3617 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3619 if (ObjectVT == MVT::i1)
3620 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3625 ArgSize = PtrByteSize;
3627 // All int arguments reserve stack space in the Darwin ABI.
3628 ArgOffset += PtrByteSize;
3632 case MVT::i64: // PPC64
3633 if (GPR_idx != Num_GPR_Regs) {
3634 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3635 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3637 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3638 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3639 // value to MVT::i64 and then truncate to the correct register size.
3640 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3645 ArgSize = PtrByteSize;
3647 // All int arguments reserve stack space in the Darwin ABI.
3653 // Every 4 bytes of argument space consumes one of the GPRs available for
3654 // argument passing.
3655 if (GPR_idx != Num_GPR_Regs) {
3657 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3660 if (FPR_idx != Num_FPR_Regs) {
3663 if (ObjectVT == MVT::f32)
3664 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3666 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3668 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3674 // All FP arguments reserve stack space in the Darwin ABI.
3675 ArgOffset += isPPC64 ? 8 : ObjSize;
3681 // Note that vector arguments in registers don't reserve stack space,
3682 // except in varargs functions.
3683 if (VR_idx != Num_VR_Regs) {
3684 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3685 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3687 while ((ArgOffset % 16) != 0) {
3688 ArgOffset += PtrByteSize;
3689 if (GPR_idx != Num_GPR_Regs)
3693 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3697 if (!isVarArg && !isPPC64) {
3698 // Vectors go after all the nonvectors.
3699 CurArgOffset = VecArgOffset;
3702 // Vectors are aligned.
3703 ArgOffset = ((ArgOffset+15)/16)*16;
3704 CurArgOffset = ArgOffset;
3712 // We need to load the argument to a virtual register if we determined above
3713 // that we ran out of physical registers of the appropriate type.
3715 int FI = MFI->CreateFixedObject(ObjSize,
3716 CurArgOffset + (ArgSize - ObjSize),
3718 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3719 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3720 false, false, false, 0);
3723 InVals.push_back(ArgVal);
3726 // Allow for Altivec parameters at the end, if needed.
3727 if (nAltivecParamsAtEnd) {
3728 MinReservedArea = ((MinReservedArea+15)/16)*16;
3729 MinReservedArea += 16*nAltivecParamsAtEnd;
3732 // Area that is at least reserved in the caller of this function.
3733 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3735 // Set the size that is at least reserved in caller of this function. Tail
3736 // call optimized functions' reserved stack space needs to be aligned so that
3737 // taking the difference between two stack areas will result in an aligned
3740 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3741 FuncInfo->setMinReservedArea(MinReservedArea);
3743 // If the function takes variable number of arguments, make a frame index for
3744 // the start of the first vararg value... for expansion of llvm.va_start.
3746 int Depth = ArgOffset;
3748 FuncInfo->setVarArgsFrameIndex(
3749 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3751 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3753 // If this function is vararg, store any remaining integer argument regs
3754 // to their spots on the stack so that they may be loaded by deferencing the
3755 // result of va_next.
3756 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3760 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3762 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3765 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3766 MachinePointerInfo(), false, false, 0);
3767 MemOps.push_back(Store);
3768 // Increment the address by four for the next argument to store
3769 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3770 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3774 if (!MemOps.empty())
3775 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3780 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3781 /// adjusted to accommodate the arguments for the tailcall.
3782 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3783 unsigned ParamSize) {
3785 if (!isTailCall) return 0;
3787 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3788 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3789 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3790 // Remember only if the new adjustement is bigger.
3791 if (SPDiff < FI->getTailCallSPDelta())
3792 FI->setTailCallSPDelta(SPDiff);
3797 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3798 /// for tail call optimization. Targets which want to do tail call
3799 /// optimization should implement this function.
3801 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3802 CallingConv::ID CalleeCC,
3804 const SmallVectorImpl<ISD::InputArg> &Ins,
3805 SelectionDAG& DAG) const {
3806 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3809 // Variable argument functions are not supported.
3813 MachineFunction &MF = DAG.getMachineFunction();
3814 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3815 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3816 // Functions containing by val parameters are not supported.
3817 for (unsigned i = 0; i != Ins.size(); i++) {
3818 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3819 if (Flags.isByVal()) return false;
3822 // Non-PIC/GOT tail calls are supported.
3823 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3826 // At the moment we can only do local tail calls (in same module, hidden
3827 // or protected) if we are generating PIC.
3828 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3829 return G->getGlobal()->hasHiddenVisibility()
3830 || G->getGlobal()->hasProtectedVisibility();
3836 /// isCallCompatibleAddress - Return the immediate to use if the specified
3837 /// 32-bit value is representable in the immediate field of a BxA instruction.
3838 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3839 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3840 if (!C) return nullptr;
3842 int Addr = C->getZExtValue();
3843 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3844 SignExtend32<26>(Addr) != Addr)
3845 return nullptr; // Top 6 bits have to be sext of immediate.
3847 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3848 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3853 struct TailCallArgumentInfo {
3858 TailCallArgumentInfo() : FrameIdx(0) {}
3863 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3865 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3867 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3868 SmallVectorImpl<SDValue> &MemOpChains,
3870 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3871 SDValue Arg = TailCallArgs[i].Arg;
3872 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3873 int FI = TailCallArgs[i].FrameIdx;
3874 // Store relative to framepointer.
3875 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3876 MachinePointerInfo::getFixedStack(FI),
3881 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3882 /// the appropriate stack slot for the tail call optimized function call.
3883 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3884 MachineFunction &MF,
3893 // Calculate the new stack slot for the return address.
3894 int SlotSize = isPPC64 ? 8 : 4;
3895 const PPCFrameLowering *FL =
3896 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3897 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3898 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3899 NewRetAddrLoc, true);
3900 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3901 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3902 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3903 MachinePointerInfo::getFixedStack(NewRetAddr),
3906 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3907 // slot as the FP is never overwritten.
3909 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3910 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3912 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3913 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3914 MachinePointerInfo::getFixedStack(NewFPIdx),
3921 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3922 /// the position of the argument.
3924 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3925 SDValue Arg, int SPDiff, unsigned ArgOffset,
3926 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3927 int Offset = ArgOffset + SPDiff;
3928 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3929 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3930 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3931 SDValue FIN = DAG.getFrameIndex(FI, VT);
3932 TailCallArgumentInfo Info;
3934 Info.FrameIdxOp = FIN;
3936 TailCallArguments.push_back(Info);
3939 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3940 /// stack slot. Returns the chain as result and the loaded frame pointers in
3941 /// LROpOut/FPOpout. Used when tail calling.
3942 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3950 // Load the LR and FP stack slot for later adjusting.
3951 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3952 LROpOut = getReturnAddrFrameIndex(DAG);
3953 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3954 false, false, false, 0);
3955 Chain = SDValue(LROpOut.getNode(), 1);
3957 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3958 // slot as the FP is never overwritten.
3960 FPOpOut = getFramePointerFrameIndex(DAG);
3961 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3962 false, false, false, 0);
3963 Chain = SDValue(FPOpOut.getNode(), 1);
3969 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3970 /// by "Src" to address "Dst" of size "Size". Alignment information is
3971 /// specified by the specific parameter attribute. The copy will be passed as
3972 /// a byval function parameter.
3973 /// Sometimes what we are copying is the end of a larger object, the part that
3974 /// does not fit in registers.
3976 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3977 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3979 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
3980 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3981 false, false, false, MachinePointerInfo(),
3982 MachinePointerInfo());
3985 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3988 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3989 SDValue Arg, SDValue PtrOff, int SPDiff,
3990 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3991 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3992 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3994 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3999 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4001 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4002 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4003 DAG.getConstant(ArgOffset, dl, PtrVT));
4005 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4006 MachinePointerInfo(), false, false, 0));
4007 // Calculate and remember argument location.
4008 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4013 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4014 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4015 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4016 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4017 MachineFunction &MF = DAG.getMachineFunction();
4019 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4020 // might overwrite each other in case of tail call optimization.
4021 SmallVector<SDValue, 8> MemOpChains2;
4022 // Do not flag preceding copytoreg stuff together with the following stuff.
4024 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4026 if (!MemOpChains2.empty())
4027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4029 // Store the return address to the appropriate stack slot.
4030 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4031 isPPC64, isDarwinABI, dl);
4033 // Emit callseq_end just before tailcall node.
4034 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4035 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4036 InFlag = Chain.getValue(1);
4039 // Is this global address that of a function that can be called by name? (as
4040 // opposed to something that must hold a descriptor for an indirect call).
4041 static bool isFunctionGlobalAddress(SDValue Callee) {
4042 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4043 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4044 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4047 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4054 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4055 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4056 bool isTailCall, bool IsPatchPoint,
4057 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4058 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4059 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4061 bool isPPC64 = Subtarget.isPPC64();
4062 bool isSVR4ABI = Subtarget.isSVR4ABI();
4063 bool isELFv2ABI = Subtarget.isELFv2ABI();
4065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4066 NodeTys.push_back(MVT::Other); // Returns a chain
4067 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4069 unsigned CallOpc = PPCISD::CALL;
4071 bool needIndirectCall = true;
4072 if (!isSVR4ABI || !isPPC64)
4073 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4074 // If this is an absolute destination address, use the munged value.
4075 Callee = SDValue(Dest, 0);
4076 needIndirectCall = false;
4079 if (isFunctionGlobalAddress(Callee)) {
4080 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4081 // A call to a TLS address is actually an indirect call to a
4082 // thread-specific pointer.
4083 unsigned OpFlags = 0;
4084 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4085 (Subtarget.getTargetTriple().isMacOSX() &&
4086 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4087 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4088 (Subtarget.isTargetELF() && !isPPC64 &&
4089 !G->getGlobal()->hasLocalLinkage() &&
4090 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4091 // PC-relative references to external symbols should go through $stub,
4092 // unless we're building with the leopard linker or later, which
4093 // automatically synthesizes these stubs.
4094 OpFlags = PPCII::MO_PLT_OR_STUB;
4097 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4098 // every direct call is) turn it into a TargetGlobalAddress /
4099 // TargetExternalSymbol node so that legalize doesn't hack it.
4100 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4101 Callee.getValueType(), 0, OpFlags);
4102 needIndirectCall = false;
4105 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4106 unsigned char OpFlags = 0;
4108 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4109 (Subtarget.getTargetTriple().isMacOSX() &&
4110 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4111 (Subtarget.isTargetELF() && !isPPC64 &&
4112 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4113 // PC-relative references to external symbols should go through $stub,
4114 // unless we're building with the leopard linker or later, which
4115 // automatically synthesizes these stubs.
4116 OpFlags = PPCII::MO_PLT_OR_STUB;
4119 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4121 needIndirectCall = false;
4125 // We'll form an invalid direct call when lowering a patchpoint; the full
4126 // sequence for an indirect call is complicated, and many of the
4127 // instructions introduced might have side effects (and, thus, can't be
4128 // removed later). The call itself will be removed as soon as the
4129 // argument/return lowering is complete, so the fact that it has the wrong
4130 // kind of operands should not really matter.
4131 needIndirectCall = false;
4134 if (needIndirectCall) {
4135 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4136 // to do the call, we can't use PPCISD::CALL.
4137 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4139 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4140 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4141 // entry point, but to the function descriptor (the function entry point
4142 // address is part of the function descriptor though).
4143 // The function descriptor is a three doubleword structure with the
4144 // following fields: function entry point, TOC base address and
4145 // environment pointer.
4146 // Thus for a call through a function pointer, the following actions need
4148 // 1. Save the TOC of the caller in the TOC save area of its stack
4149 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4150 // 2. Load the address of the function entry point from the function
4152 // 3. Load the TOC of the callee from the function descriptor into r2.
4153 // 4. Load the environment pointer from the function descriptor into
4155 // 5. Branch to the function entry point address.
4156 // 6. On return of the callee, the TOC of the caller needs to be
4157 // restored (this is done in FinishCall()).
4159 // The loads are scheduled at the beginning of the call sequence, and the
4160 // register copies are flagged together to ensure that no other
4161 // operations can be scheduled in between. E.g. without flagging the
4162 // copies together, a TOC access in the caller could be scheduled between
4163 // the assignment of the callee TOC and the branch to the callee, which
4164 // results in the TOC access going through the TOC of the callee instead
4165 // of going through the TOC of the caller, which leads to incorrect code.
4167 // Load the address of the function entry point from the function
4169 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4170 if (LDChain.getValueType() == MVT::Glue)
4171 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4173 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4175 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4176 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4177 false, false, LoadsInv, 8);
4179 // Load environment pointer into r11.
4180 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4181 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4182 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4183 MPI.getWithOffset(16), false, false,
4186 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4187 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4188 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4189 MPI.getWithOffset(8), false, false,
4192 setUsesTOCBasePtr(DAG);
4193 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4195 Chain = TOCVal.getValue(0);
4196 InFlag = TOCVal.getValue(1);
4198 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4201 Chain = EnvVal.getValue(0);
4202 InFlag = EnvVal.getValue(1);
4204 MTCTROps[0] = Chain;
4205 MTCTROps[1] = LoadFuncPtr;
4206 MTCTROps[2] = InFlag;
4209 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4210 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4211 InFlag = Chain.getValue(1);
4214 NodeTys.push_back(MVT::Other);
4215 NodeTys.push_back(MVT::Glue);
4216 Ops.push_back(Chain);
4217 CallOpc = PPCISD::BCTRL;
4218 Callee.setNode(nullptr);
4219 // Add use of X11 (holding environment pointer)
4220 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
4221 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4222 // Add CTR register as callee so a bctr can be emitted later.
4224 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4227 // If this is a direct call, pass the chain and the callee.
4228 if (Callee.getNode()) {
4229 Ops.push_back(Chain);
4230 Ops.push_back(Callee);
4232 // If this is a tail call add stack pointer delta.
4234 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4236 // Add argument registers to the end of the list so that they are known live
4238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4239 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4240 RegsToPass[i].second.getValueType()));
4242 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4244 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4245 setUsesTOCBasePtr(DAG);
4246 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4253 bool isLocalCall(const SDValue &Callee)
4255 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4256 return G->getGlobal()->isStrongDefinitionForLinker();
4261 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4262 CallingConv::ID CallConv, bool isVarArg,
4263 const SmallVectorImpl<ISD::InputArg> &Ins,
4264 SDLoc dl, SelectionDAG &DAG,
4265 SmallVectorImpl<SDValue> &InVals) const {
4267 SmallVector<CCValAssign, 16> RVLocs;
4268 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4270 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4272 // Copy all of the result registers out of their specified physreg.
4273 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4274 CCValAssign &VA = RVLocs[i];
4275 assert(VA.isRegLoc() && "Can only return in registers!");
4277 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4278 VA.getLocReg(), VA.getLocVT(), InFlag);
4279 Chain = Val.getValue(1);
4280 InFlag = Val.getValue(2);
4282 switch (VA.getLocInfo()) {
4283 default: llvm_unreachable("Unknown loc info!");
4284 case CCValAssign::Full: break;
4285 case CCValAssign::AExt:
4286 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4288 case CCValAssign::ZExt:
4289 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4290 DAG.getValueType(VA.getValVT()));
4291 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4293 case CCValAssign::SExt:
4294 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4295 DAG.getValueType(VA.getValVT()));
4296 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4300 InVals.push_back(Val);
4307 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4308 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4310 SmallVector<std::pair<unsigned, SDValue>, 8>
4312 SDValue InFlag, SDValue Chain,
4313 SDValue CallSeqStart, SDValue &Callee,
4314 int SPDiff, unsigned NumBytes,
4315 const SmallVectorImpl<ISD::InputArg> &Ins,
4316 SmallVectorImpl<SDValue> &InVals,
4317 ImmutableCallSite *CS) const {
4319 std::vector<EVT> NodeTys;
4320 SmallVector<SDValue, 8> Ops;
4321 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4322 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
4323 Ops, NodeTys, CS, Subtarget);
4325 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4326 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4327 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4329 // When performing tail call optimization the callee pops its arguments off
4330 // the stack. Account for this here so these bytes can be pushed back on in
4331 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4332 int BytesCalleePops =
4333 (CallConv == CallingConv::Fast &&
4334 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4336 // Add a register mask operand representing the call-preserved registers.
4337 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4338 const uint32_t *Mask =
4339 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4340 assert(Mask && "Missing call preserved mask for calling convention");
4341 Ops.push_back(DAG.getRegisterMask(Mask));
4343 if (InFlag.getNode())
4344 Ops.push_back(InFlag);
4348 assert(((Callee.getOpcode() == ISD::Register &&
4349 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4350 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4351 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4352 isa<ConstantSDNode>(Callee)) &&
4353 "Expecting an global address, external symbol, absolute value or register");
4355 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4356 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4359 // Add a NOP immediately after the branch instruction when using the 64-bit
4360 // SVR4 ABI. At link time, if caller and callee are in a different module and
4361 // thus have a different TOC, the call will be replaced with a call to a stub
4362 // function which saves the current TOC, loads the TOC of the callee and
4363 // branches to the callee. The NOP will be replaced with a load instruction
4364 // which restores the TOC of the caller from the TOC save slot of the current
4365 // stack frame. If caller and callee belong to the same module (and have the
4366 // same TOC), the NOP will remain unchanged.
4368 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4370 if (CallOpc == PPCISD::BCTRL) {
4371 // This is a call through a function pointer.
4372 // Restore the caller TOC from the save area into R2.
4373 // See PrepareCall() for more information about calls through function
4374 // pointers in the 64-bit SVR4 ABI.
4375 // We are using a target-specific load with r2 hard coded, because the
4376 // result of a target-independent load would never go directly into r2,
4377 // since r2 is a reserved register (which prevents the register allocator
4378 // from allocating it), resulting in an additional register being
4379 // allocated and an unnecessary move instruction being generated.
4380 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4382 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4383 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4384 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4385 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4386 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4388 // The address needs to go after the chain input but before the flag (or
4389 // any other variadic arguments).
4390 Ops.insert(std::next(Ops.begin()), AddTOC);
4391 } else if ((CallOpc == PPCISD::CALL) &&
4392 (!isLocalCall(Callee) ||
4393 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4394 // Otherwise insert NOP for non-local calls.
4395 CallOpc = PPCISD::CALL_NOP;
4398 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4399 InFlag = Chain.getValue(1);
4401 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4402 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4405 InFlag = Chain.getValue(1);
4407 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4408 Ins, dl, DAG, InVals);
4412 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4413 SmallVectorImpl<SDValue> &InVals) const {
4414 SelectionDAG &DAG = CLI.DAG;
4416 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4417 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4418 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4419 SDValue Chain = CLI.Chain;
4420 SDValue Callee = CLI.Callee;
4421 bool &isTailCall = CLI.IsTailCall;
4422 CallingConv::ID CallConv = CLI.CallConv;
4423 bool isVarArg = CLI.IsVarArg;
4424 bool IsPatchPoint = CLI.IsPatchPoint;
4425 ImmutableCallSite *CS = CLI.CS;
4428 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4431 if (!isTailCall && CS && CS->isMustTailCall())
4432 report_fatal_error("failed to perform tail call elimination on a call "
4433 "site marked musttail");
4435 if (Subtarget.isSVR4ABI()) {
4436 if (Subtarget.isPPC64())
4437 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4438 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4439 dl, DAG, InVals, CS);
4441 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4442 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4443 dl, DAG, InVals, CS);
4446 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4447 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4448 dl, DAG, InVals, CS);
4452 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4453 CallingConv::ID CallConv, bool isVarArg,
4454 bool isTailCall, bool IsPatchPoint,
4455 const SmallVectorImpl<ISD::OutputArg> &Outs,
4456 const SmallVectorImpl<SDValue> &OutVals,
4457 const SmallVectorImpl<ISD::InputArg> &Ins,
4458 SDLoc dl, SelectionDAG &DAG,
4459 SmallVectorImpl<SDValue> &InVals,
4460 ImmutableCallSite *CS) const {
4461 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4462 // of the 32-bit SVR4 ABI stack frame layout.
4464 assert((CallConv == CallingConv::C ||
4465 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4467 unsigned PtrByteSize = 4;
4469 MachineFunction &MF = DAG.getMachineFunction();
4471 // Mark this function as potentially containing a function that contains a
4472 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4473 // and restoring the callers stack pointer in this functions epilog. This is
4474 // done because by tail calling the called function might overwrite the value
4475 // in this function's (MF) stack pointer stack slot 0(SP).
4476 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4477 CallConv == CallingConv::Fast)
4478 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4480 // Count how many bytes are to be pushed on the stack, including the linkage
4481 // area, parameter list area and the part of the local variable space which
4482 // contains copies of aggregates which are passed by value.
4484 // Assign locations to all of the outgoing arguments.
4485 SmallVector<CCValAssign, 16> ArgLocs;
4486 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4489 // Reserve space for the linkage area on the stack.
4490 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4494 // Handle fixed and variable vector arguments differently.
4495 // Fixed vector arguments go into registers as long as registers are
4496 // available. Variable vector arguments always go into memory.
4497 unsigned NumArgs = Outs.size();
4499 for (unsigned i = 0; i != NumArgs; ++i) {
4500 MVT ArgVT = Outs[i].VT;
4501 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4504 if (Outs[i].IsFixed) {
4505 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4508 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4514 errs() << "Call operand #" << i << " has unhandled type "
4515 << EVT(ArgVT).getEVTString() << "\n";
4517 llvm_unreachable(nullptr);
4521 // All arguments are treated the same.
4522 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4525 // Assign locations to all of the outgoing aggregate by value arguments.
4526 SmallVector<CCValAssign, 16> ByValArgLocs;
4527 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4528 ByValArgLocs, *DAG.getContext());
4530 // Reserve stack space for the allocations in CCInfo.
4531 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4533 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4535 // Size of the linkage area, parameter list area and the part of the local
4536 // space variable where copies of aggregates which are passed by value are
4538 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4540 // Calculate by how many bytes the stack has to be adjusted in case of tail
4541 // call optimization.
4542 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4544 // Adjust the stack pointer for the new arguments...
4545 // These operations are automatically eliminated by the prolog/epilog pass
4546 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4548 SDValue CallSeqStart = Chain;
4550 // Load the return address and frame pointer so it can be moved somewhere else
4553 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4556 // Set up a copy of the stack pointer for use loading and storing any
4557 // arguments that may not fit in the registers available for argument
4559 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4561 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4562 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4563 SmallVector<SDValue, 8> MemOpChains;
4565 bool seenFloatArg = false;
4566 // Walk the register/memloc assignments, inserting copies/loads.
4567 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4570 CCValAssign &VA = ArgLocs[i];
4571 SDValue Arg = OutVals[i];
4572 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4574 if (Flags.isByVal()) {
4575 // Argument is an aggregate which is passed by value, thus we need to
4576 // create a copy of it in the local variable space of the current stack
4577 // frame (which is the stack frame of the caller) and pass the address of
4578 // this copy to the callee.
4579 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4580 CCValAssign &ByValVA = ByValArgLocs[j++];
4581 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4583 // Memory reserved in the local variable space of the callers stack frame.
4584 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4586 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4587 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4589 // Create a copy of the argument in the local area of the current
4591 SDValue MemcpyCall =
4592 CreateCopyOfByValArgument(Arg, PtrOff,
4593 CallSeqStart.getNode()->getOperand(0),
4596 // This must go outside the CALLSEQ_START..END.
4597 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4598 CallSeqStart.getNode()->getOperand(1),
4600 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4601 NewCallSeqStart.getNode());
4602 Chain = CallSeqStart = NewCallSeqStart;
4604 // Pass the address of the aggregate copy on the stack either in a
4605 // physical register or in the parameter list area of the current stack
4606 // frame to the callee.
4610 if (VA.isRegLoc()) {
4611 if (Arg.getValueType() == MVT::i1)
4612 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4614 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4615 // Put argument in a physical register.
4616 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4618 // Put argument in the parameter list area of the current stack frame.
4619 assert(VA.isMemLoc());
4620 unsigned LocMemOffset = VA.getLocMemOffset();
4623 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4624 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4626 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4627 MachinePointerInfo(),
4630 // Calculate and remember argument location.
4631 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4637 if (!MemOpChains.empty())
4638 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4640 // Build a sequence of copy-to-reg nodes chained together with token chain
4641 // and flag operands which copy the outgoing args into the appropriate regs.
4643 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4644 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4645 RegsToPass[i].second, InFlag);
4646 InFlag = Chain.getValue(1);
4649 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4652 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4653 SDValue Ops[] = { Chain, InFlag };
4655 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4656 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4658 InFlag = Chain.getValue(1);
4662 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4663 false, TailCallArguments);
4665 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4666 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4667 NumBytes, Ins, InVals, CS);
4670 // Copy an argument into memory, being careful to do this outside the
4671 // call sequence for the call to which the argument belongs.
4673 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4674 SDValue CallSeqStart,
4675 ISD::ArgFlagsTy Flags,
4678 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4679 CallSeqStart.getNode()->getOperand(0),
4681 // The MEMCPY must go outside the CALLSEQ_START..END.
4682 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4683 CallSeqStart.getNode()->getOperand(1),
4685 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4686 NewCallSeqStart.getNode());
4687 return NewCallSeqStart;
4691 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4692 CallingConv::ID CallConv, bool isVarArg,
4693 bool isTailCall, bool IsPatchPoint,
4694 const SmallVectorImpl<ISD::OutputArg> &Outs,
4695 const SmallVectorImpl<SDValue> &OutVals,
4696 const SmallVectorImpl<ISD::InputArg> &Ins,
4697 SDLoc dl, SelectionDAG &DAG,
4698 SmallVectorImpl<SDValue> &InVals,
4699 ImmutableCallSite *CS) const {
4701 bool isELFv2ABI = Subtarget.isELFv2ABI();
4702 bool isLittleEndian = Subtarget.isLittleEndian();
4703 unsigned NumOps = Outs.size();
4705 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4706 unsigned PtrByteSize = 8;
4708 MachineFunction &MF = DAG.getMachineFunction();
4710 // Mark this function as potentially containing a function that contains a
4711 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4712 // and restoring the callers stack pointer in this functions epilog. This is
4713 // done because by tail calling the called function might overwrite the value
4714 // in this function's (MF) stack pointer stack slot 0(SP).
4715 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4716 CallConv == CallingConv::Fast)
4717 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4719 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4720 "fastcc not supported on varargs functions");
4722 // Count how many bytes are to be pushed on the stack, including the linkage
4723 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4724 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4725 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4726 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4727 unsigned NumBytes = LinkageSize;
4728 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4729 unsigned &QFPR_idx = FPR_idx;
4731 static const MCPhysReg GPR[] = {
4732 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4733 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4735 static const MCPhysReg VR[] = {
4736 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4737 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4739 static const MCPhysReg VSRH[] = {
4740 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4741 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4744 const unsigned NumGPRs = array_lengthof(GPR);
4745 const unsigned NumFPRs = 13;
4746 const unsigned NumVRs = array_lengthof(VR);
4747 const unsigned NumQFPRs = NumFPRs;
4749 // When using the fast calling convention, we don't provide backing for
4750 // arguments that will be in registers.
4751 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4753 // Add up all the space actually used.
4754 for (unsigned i = 0; i != NumOps; ++i) {
4755 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4756 EVT ArgVT = Outs[i].VT;
4757 EVT OrigVT = Outs[i].ArgVT;
4759 if (CallConv == CallingConv::Fast) {
4760 if (Flags.isByVal())
4761 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4763 switch (ArgVT.getSimpleVT().SimpleTy) {
4764 default: llvm_unreachable("Unexpected ValueType for argument!");
4768 if (++NumGPRsUsed <= NumGPRs)
4777 if (++NumVRsUsed <= NumVRs)
4781 // When using QPX, this is handled like a FP register, otherwise, it
4782 // is an Altivec register.
4783 if (Subtarget.hasQPX()) {
4784 if (++NumFPRsUsed <= NumFPRs)
4787 if (++NumVRsUsed <= NumVRs)
4793 case MVT::v4f64: // QPX
4794 case MVT::v4i1: // QPX
4795 if (++NumFPRsUsed <= NumFPRs)
4801 /* Respect alignment of argument on the stack. */
4803 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4804 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4806 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4807 if (Flags.isInConsecutiveRegsLast())
4808 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4811 unsigned NumBytesActuallyUsed = NumBytes;
4813 // The prolog code of the callee may store up to 8 GPR argument registers to
4814 // the stack, allowing va_start to index over them in memory if its varargs.
4815 // Because we cannot tell if this is needed on the caller side, we have to
4816 // conservatively assume that it is needed. As such, make sure we have at
4817 // least enough stack space for the caller to store the 8 GPRs.
4818 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4819 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4821 // Tail call needs the stack to be aligned.
4822 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4823 CallConv == CallingConv::Fast)
4824 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4826 // Calculate by how many bytes the stack has to be adjusted in case of tail
4827 // call optimization.
4828 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4830 // To protect arguments on the stack from being clobbered in a tail call,
4831 // force all the loads to happen before doing any other lowering.
4833 Chain = DAG.getStackArgumentTokenFactor(Chain);
4835 // Adjust the stack pointer for the new arguments...
4836 // These operations are automatically eliminated by the prolog/epilog pass
4837 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4839 SDValue CallSeqStart = Chain;
4841 // Load the return address and frame pointer so it can be move somewhere else
4844 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4847 // Set up a copy of the stack pointer for use loading and storing any
4848 // arguments that may not fit in the registers available for argument
4850 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4852 // Figure out which arguments are going to go in registers, and which in
4853 // memory. Also, if this is a vararg function, floating point operations
4854 // must be stored to our stack, and loaded into integer regs as well, if
4855 // any integer regs are available for argument passing.
4856 unsigned ArgOffset = LinkageSize;
4858 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4859 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4861 SmallVector<SDValue, 8> MemOpChains;
4862 for (unsigned i = 0; i != NumOps; ++i) {
4863 SDValue Arg = OutVals[i];
4864 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4865 EVT ArgVT = Outs[i].VT;
4866 EVT OrigVT = Outs[i].ArgVT;
4868 // PtrOff will be used to store the current argument to the stack if a
4869 // register cannot be found for it.
4872 // We re-align the argument offset for each argument, except when using the
4873 // fast calling convention, when we need to make sure we do that only when
4874 // we'll actually use a stack slot.
4875 auto ComputePtrOff = [&]() {
4876 /* Respect alignment of argument on the stack. */
4878 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4879 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4881 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4883 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4886 if (CallConv != CallingConv::Fast) {
4889 /* Compute GPR index associated with argument offset. */
4890 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4891 GPR_idx = std::min(GPR_idx, NumGPRs);
4894 // Promote integers to 64-bit values.
4895 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4896 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4897 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4898 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4901 // FIXME memcpy is used way more than necessary. Correctness first.
4902 // Note: "by value" is code for passing a structure by value, not
4904 if (Flags.isByVal()) {
4905 // Note: Size includes alignment padding, so
4906 // struct x { short a; char b; }
4907 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4908 // These are the proper values we need for right-justifying the
4909 // aggregate in a parameter register.
4910 unsigned Size = Flags.getByValSize();
4912 // An empty aggregate parameter takes up no storage and no
4917 if (CallConv == CallingConv::Fast)
4920 // All aggregates smaller than 8 bytes must be passed right-justified.
4921 if (Size==1 || Size==2 || Size==4) {
4922 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4923 if (GPR_idx != NumGPRs) {
4924 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4925 MachinePointerInfo(), VT,
4926 false, false, false, 0);
4927 MemOpChains.push_back(Load.getValue(1));
4928 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4930 ArgOffset += PtrByteSize;
4935 if (GPR_idx == NumGPRs && Size < 8) {
4936 SDValue AddPtr = PtrOff;
4937 if (!isLittleEndian) {
4938 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4939 PtrOff.getValueType());
4940 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4942 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4945 ArgOffset += PtrByteSize;
4948 // Copy entire object into memory. There are cases where gcc-generated
4949 // code assumes it is there, even if it could be put entirely into
4950 // registers. (This is not what the doc says.)
4952 // FIXME: The above statement is likely due to a misunderstanding of the
4953 // documents. All arguments must be copied into the parameter area BY
4954 // THE CALLEE in the event that the callee takes the address of any
4955 // formal argument. That has not yet been implemented. However, it is
4956 // reasonable to use the stack area as a staging area for the register
4959 // Skip this for small aggregates, as we will use the same slot for a
4960 // right-justified copy, below.
4962 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4966 // When a register is available, pass a small aggregate right-justified.
4967 if (Size < 8 && GPR_idx != NumGPRs) {
4968 // The easiest way to get this right-justified in a register
4969 // is to copy the structure into the rightmost portion of a
4970 // local variable slot, then load the whole slot into the
4972 // FIXME: The memcpy seems to produce pretty awful code for
4973 // small aggregates, particularly for packed ones.
4974 // FIXME: It would be preferable to use the slot in the
4975 // parameter save area instead of a new local variable.
4976 SDValue AddPtr = PtrOff;
4977 if (!isLittleEndian) {
4978 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
4979 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4981 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4985 // Load the slot into the register.
4986 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4987 MachinePointerInfo(),
4988 false, false, false, 0);
4989 MemOpChains.push_back(Load.getValue(1));
4990 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4992 // Done with this argument.
4993 ArgOffset += PtrByteSize;
4997 // For aggregates larger than PtrByteSize, copy the pieces of the
4998 // object that fit into registers from the parameter save area.
4999 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5000 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5001 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5002 if (GPR_idx != NumGPRs) {
5003 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5004 MachinePointerInfo(),
5005 false, false, false, 0);
5006 MemOpChains.push_back(Load.getValue(1));
5007 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5008 ArgOffset += PtrByteSize;
5010 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5017 switch (Arg.getSimpleValueType().SimpleTy) {
5018 default: llvm_unreachable("Unexpected ValueType for argument!");
5022 // These can be scalar arguments or elements of an integer array type
5023 // passed directly. Clang may use those instead of "byval" aggregate
5024 // types to avoid forcing arguments to memory unnecessarily.
5025 if (GPR_idx != NumGPRs) {
5026 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5028 if (CallConv == CallingConv::Fast)
5031 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5032 true, isTailCall, false, MemOpChains,
5033 TailCallArguments, dl);
5034 if (CallConv == CallingConv::Fast)
5035 ArgOffset += PtrByteSize;
5037 if (CallConv != CallingConv::Fast)
5038 ArgOffset += PtrByteSize;
5042 // These can be scalar arguments or elements of a float array type
5043 // passed directly. The latter are used to implement ELFv2 homogenous
5044 // float aggregates.
5046 // Named arguments go into FPRs first, and once they overflow, the
5047 // remaining arguments go into GPRs and then the parameter save area.
5048 // Unnamed arguments for vararg functions always go to GPRs and
5049 // then the parameter save area. For now, put all arguments to vararg
5050 // routines always in both locations (FPR *and* GPR or stack slot).
5051 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5052 bool NeededLoad = false;
5054 // First load the argument into the next available FPR.
5055 if (FPR_idx != NumFPRs)
5056 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5058 // Next, load the argument into GPR or stack slot if needed.
5059 if (!NeedGPROrStack)
5061 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5062 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5063 // once we support fp <-> gpr moves.
5065 // In the non-vararg case, this can only ever happen in the
5066 // presence of f32 array types, since otherwise we never run
5067 // out of FPRs before running out of GPRs.
5070 // Double values are always passed in a single GPR.
5071 if (Arg.getValueType() != MVT::f32) {
5072 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5074 // Non-array float values are extended and passed in a GPR.
5075 } else if (!Flags.isInConsecutiveRegs()) {
5076 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5077 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5079 // If we have an array of floats, we collect every odd element
5080 // together with its predecessor into one GPR.
5081 } else if (ArgOffset % PtrByteSize != 0) {
5083 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5084 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5085 if (!isLittleEndian)
5087 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5089 // The final element, if even, goes into the first half of a GPR.
5090 } else if (Flags.isInConsecutiveRegsLast()) {
5091 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5092 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5093 if (!isLittleEndian)
5094 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5095 DAG.getConstant(32, dl, MVT::i32));
5097 // Non-final even elements are skipped; they will be handled
5098 // together the with subsequent argument on the next go-around.
5102 if (ArgVal.getNode())
5103 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5105 if (CallConv == CallingConv::Fast)
5108 // Single-precision floating-point values are mapped to the
5109 // second (rightmost) word of the stack doubleword.
5110 if (Arg.getValueType() == MVT::f32 &&
5111 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5112 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5113 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5116 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5117 true, isTailCall, false, MemOpChains,
5118 TailCallArguments, dl);
5122 // When passing an array of floats, the array occupies consecutive
5123 // space in the argument area; only round up to the next doubleword
5124 // at the end of the array. Otherwise, each float takes 8 bytes.
5125 if (CallConv != CallingConv::Fast || NeededLoad) {
5126 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5127 Flags.isInConsecutiveRegs()) ? 4 : 8;
5128 if (Flags.isInConsecutiveRegsLast())
5129 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5140 if (!Subtarget.hasQPX()) {
5141 // These can be scalar arguments or elements of a vector array type
5142 // passed directly. The latter are used to implement ELFv2 homogenous
5143 // vector aggregates.
5145 // For a varargs call, named arguments go into VRs or on the stack as
5146 // usual; unnamed arguments always go to the stack or the corresponding
5147 // GPRs when within range. For now, we always put the value in both
5148 // locations (or even all three).
5150 // We could elide this store in the case where the object fits
5151 // entirely in R registers. Maybe later.
5152 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5153 MachinePointerInfo(), false, false, 0);
5154 MemOpChains.push_back(Store);
5155 if (VR_idx != NumVRs) {
5156 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5157 MachinePointerInfo(),
5158 false, false, false, 0);
5159 MemOpChains.push_back(Load.getValue(1));
5161 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5162 Arg.getSimpleValueType() == MVT::v2i64) ?
5163 VSRH[VR_idx] : VR[VR_idx];
5166 RegsToPass.push_back(std::make_pair(VReg, Load));
5169 for (unsigned i=0; i<16; i+=PtrByteSize) {
5170 if (GPR_idx == NumGPRs)
5172 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5173 DAG.getConstant(i, dl, PtrVT));
5174 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5175 false, false, false, 0);
5176 MemOpChains.push_back(Load.getValue(1));
5177 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5182 // Non-varargs Altivec params go into VRs or on the stack.
5183 if (VR_idx != NumVRs) {
5184 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5185 Arg.getSimpleValueType() == MVT::v2i64) ?
5186 VSRH[VR_idx] : VR[VR_idx];
5189 RegsToPass.push_back(std::make_pair(VReg, Arg));
5191 if (CallConv == CallingConv::Fast)
5194 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5195 true, isTailCall, true, MemOpChains,
5196 TailCallArguments, dl);
5197 if (CallConv == CallingConv::Fast)
5201 if (CallConv != CallingConv::Fast)
5206 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5207 "Invalid QPX parameter type");
5212 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5214 // We could elide this store in the case where the object fits
5215 // entirely in R registers. Maybe later.
5216 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5217 MachinePointerInfo(), false, false, 0);
5218 MemOpChains.push_back(Store);
5219 if (QFPR_idx != NumQFPRs) {
5220 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5221 Store, PtrOff, MachinePointerInfo(),
5222 false, false, false, 0);
5223 MemOpChains.push_back(Load.getValue(1));
5224 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5226 ArgOffset += (IsF32 ? 16 : 32);
5227 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5228 if (GPR_idx == NumGPRs)
5230 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5231 DAG.getConstant(i, dl, PtrVT));
5232 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5233 false, false, false, 0);
5234 MemOpChains.push_back(Load.getValue(1));
5235 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5240 // Non-varargs QPX params go into registers or on the stack.
5241 if (QFPR_idx != NumQFPRs) {
5242 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5244 if (CallConv == CallingConv::Fast)
5247 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5248 true, isTailCall, true, MemOpChains,
5249 TailCallArguments, dl);
5250 if (CallConv == CallingConv::Fast)
5251 ArgOffset += (IsF32 ? 16 : 32);
5254 if (CallConv != CallingConv::Fast)
5255 ArgOffset += (IsF32 ? 16 : 32);
5261 assert(NumBytesActuallyUsed == ArgOffset);
5262 (void)NumBytesActuallyUsed;
5264 if (!MemOpChains.empty())
5265 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5267 // Check if this is an indirect call (MTCTR/BCTRL).
5268 // See PrepareCall() for more information about calls through function
5269 // pointers in the 64-bit SVR4 ABI.
5270 if (!isTailCall && !IsPatchPoint &&
5271 !isFunctionGlobalAddress(Callee) &&
5272 !isa<ExternalSymbolSDNode>(Callee)) {
5273 // Load r2 into a virtual register and store it to the TOC save area.
5274 setUsesTOCBasePtr(DAG);
5275 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5276 // TOC save area offset.
5277 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5278 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5279 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5280 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5281 MachinePointerInfo::getStack(TOCSaveOffset),
5283 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5284 // This does not mean the MTCTR instruction must use R12; it's easier
5285 // to model this as an extra parameter, so do that.
5286 if (isELFv2ABI && !IsPatchPoint)
5287 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5290 // Build a sequence of copy-to-reg nodes chained together with token chain
5291 // and flag operands which copy the outgoing args into the appropriate regs.
5293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5294 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5295 RegsToPass[i].second, InFlag);
5296 InFlag = Chain.getValue(1);
5300 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5301 FPOp, true, TailCallArguments);
5303 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5304 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5305 NumBytes, Ins, InVals, CS);
5309 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5310 CallingConv::ID CallConv, bool isVarArg,
5311 bool isTailCall, bool IsPatchPoint,
5312 const SmallVectorImpl<ISD::OutputArg> &Outs,
5313 const SmallVectorImpl<SDValue> &OutVals,
5314 const SmallVectorImpl<ISD::InputArg> &Ins,
5315 SDLoc dl, SelectionDAG &DAG,
5316 SmallVectorImpl<SDValue> &InVals,
5317 ImmutableCallSite *CS) const {
5319 unsigned NumOps = Outs.size();
5321 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5322 bool isPPC64 = PtrVT == MVT::i64;
5323 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5325 MachineFunction &MF = DAG.getMachineFunction();
5327 // Mark this function as potentially containing a function that contains a
5328 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5329 // and restoring the callers stack pointer in this functions epilog. This is
5330 // done because by tail calling the called function might overwrite the value
5331 // in this function's (MF) stack pointer stack slot 0(SP).
5332 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5333 CallConv == CallingConv::Fast)
5334 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5336 // Count how many bytes are to be pushed on the stack, including the linkage
5337 // area, and parameter passing area. We start with 24/48 bytes, which is
5338 // prereserved space for [SP][CR][LR][3 x unused].
5339 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5340 unsigned NumBytes = LinkageSize;
5342 // Add up all the space actually used.
5343 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5344 // they all go in registers, but we must reserve stack space for them for
5345 // possible use by the caller. In varargs or 64-bit calls, parameters are
5346 // assigned stack space in order, with padding so Altivec parameters are
5348 unsigned nAltivecParamsAtEnd = 0;
5349 for (unsigned i = 0; i != NumOps; ++i) {
5350 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5351 EVT ArgVT = Outs[i].VT;
5352 // Varargs Altivec parameters are padded to a 16 byte boundary.
5353 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5354 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5355 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5356 if (!isVarArg && !isPPC64) {
5357 // Non-varargs Altivec parameters go after all the non-Altivec
5358 // parameters; handle those later so we know how much padding we need.
5359 nAltivecParamsAtEnd++;
5362 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5363 NumBytes = ((NumBytes+15)/16)*16;
5365 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5368 // Allow for Altivec parameters at the end, if needed.
5369 if (nAltivecParamsAtEnd) {
5370 NumBytes = ((NumBytes+15)/16)*16;
5371 NumBytes += 16*nAltivecParamsAtEnd;
5374 // The prolog code of the callee may store up to 8 GPR argument registers to
5375 // the stack, allowing va_start to index over them in memory if its varargs.
5376 // Because we cannot tell if this is needed on the caller side, we have to
5377 // conservatively assume that it is needed. As such, make sure we have at
5378 // least enough stack space for the caller to store the 8 GPRs.
5379 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5381 // Tail call needs the stack to be aligned.
5382 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5383 CallConv == CallingConv::Fast)
5384 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5386 // Calculate by how many bytes the stack has to be adjusted in case of tail
5387 // call optimization.
5388 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5390 // To protect arguments on the stack from being clobbered in a tail call,
5391 // force all the loads to happen before doing any other lowering.
5393 Chain = DAG.getStackArgumentTokenFactor(Chain);
5395 // Adjust the stack pointer for the new arguments...
5396 // These operations are automatically eliminated by the prolog/epilog pass
5397 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5399 SDValue CallSeqStart = Chain;
5401 // Load the return address and frame pointer so it can be move somewhere else
5404 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5407 // Set up a copy of the stack pointer for use loading and storing any
5408 // arguments that may not fit in the registers available for argument
5412 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5414 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5416 // Figure out which arguments are going to go in registers, and which in
5417 // memory. Also, if this is a vararg function, floating point operations
5418 // must be stored to our stack, and loaded into integer regs as well, if
5419 // any integer regs are available for argument passing.
5420 unsigned ArgOffset = LinkageSize;
5421 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5423 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5424 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5425 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5427 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5428 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5429 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5431 static const MCPhysReg VR[] = {
5432 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5433 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5435 const unsigned NumGPRs = array_lengthof(GPR_32);
5436 const unsigned NumFPRs = 13;
5437 const unsigned NumVRs = array_lengthof(VR);
5439 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5441 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5442 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5444 SmallVector<SDValue, 8> MemOpChains;
5445 for (unsigned i = 0; i != NumOps; ++i) {
5446 SDValue Arg = OutVals[i];
5447 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5449 // PtrOff will be used to store the current argument to the stack if a
5450 // register cannot be found for it.
5453 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5455 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5457 // On PPC64, promote integers to 64-bit values.
5458 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5459 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5460 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5461 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5464 // FIXME memcpy is used way more than necessary. Correctness first.
5465 // Note: "by value" is code for passing a structure by value, not
5467 if (Flags.isByVal()) {
5468 unsigned Size = Flags.getByValSize();
5469 // Very small objects are passed right-justified. Everything else is
5470 // passed left-justified.
5471 if (Size==1 || Size==2) {
5472 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5473 if (GPR_idx != NumGPRs) {
5474 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5475 MachinePointerInfo(), VT,
5476 false, false, false, 0);
5477 MemOpChains.push_back(Load.getValue(1));
5478 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5480 ArgOffset += PtrByteSize;
5482 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5483 PtrOff.getValueType());
5484 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5485 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5488 ArgOffset += PtrByteSize;
5492 // Copy entire object into memory. There are cases where gcc-generated
5493 // code assumes it is there, even if it could be put entirely into
5494 // registers. (This is not what the doc says.)
5495 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5499 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5500 // copy the pieces of the object that fit into registers from the
5501 // parameter save area.
5502 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5503 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5504 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5505 if (GPR_idx != NumGPRs) {
5506 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5507 MachinePointerInfo(),
5508 false, false, false, 0);
5509 MemOpChains.push_back(Load.getValue(1));
5510 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5511 ArgOffset += PtrByteSize;
5513 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5520 switch (Arg.getSimpleValueType().SimpleTy) {
5521 default: llvm_unreachable("Unexpected ValueType for argument!");
5525 if (GPR_idx != NumGPRs) {
5526 if (Arg.getValueType() == MVT::i1)
5527 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5529 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5531 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5532 isPPC64, isTailCall, false, MemOpChains,
5533 TailCallArguments, dl);
5535 ArgOffset += PtrByteSize;
5539 if (FPR_idx != NumFPRs) {
5540 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5543 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5544 MachinePointerInfo(), false, false, 0);
5545 MemOpChains.push_back(Store);
5547 // Float varargs are always shadowed in available integer registers
5548 if (GPR_idx != NumGPRs) {
5549 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5550 MachinePointerInfo(), false, false,
5552 MemOpChains.push_back(Load.getValue(1));
5553 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5555 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5556 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5557 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5558 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5559 MachinePointerInfo(),
5560 false, false, false, 0);
5561 MemOpChains.push_back(Load.getValue(1));
5562 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5565 // If we have any FPRs remaining, we may also have GPRs remaining.
5566 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5568 if (GPR_idx != NumGPRs)
5570 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5571 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5575 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5576 isPPC64, isTailCall, false, MemOpChains,
5577 TailCallArguments, dl);
5581 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5588 // These go aligned on the stack, or in the corresponding R registers
5589 // when within range. The Darwin PPC ABI doc claims they also go in
5590 // V registers; in fact gcc does this only for arguments that are
5591 // prototyped, not for those that match the ... We do it for all
5592 // arguments, seems to work.
5593 while (ArgOffset % 16 !=0) {
5594 ArgOffset += PtrByteSize;
5595 if (GPR_idx != NumGPRs)
5598 // We could elide this store in the case where the object fits
5599 // entirely in R registers. Maybe later.
5600 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5601 DAG.getConstant(ArgOffset, dl, PtrVT));
5602 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5603 MachinePointerInfo(), false, false, 0);
5604 MemOpChains.push_back(Store);
5605 if (VR_idx != NumVRs) {
5606 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5607 MachinePointerInfo(),
5608 false, false, false, 0);
5609 MemOpChains.push_back(Load.getValue(1));
5610 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5613 for (unsigned i=0; i<16; i+=PtrByteSize) {
5614 if (GPR_idx == NumGPRs)
5616 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5617 DAG.getConstant(i, dl, PtrVT));
5618 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5619 false, false, false, 0);
5620 MemOpChains.push_back(Load.getValue(1));
5621 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5626 // Non-varargs Altivec params generally go in registers, but have
5627 // stack space allocated at the end.
5628 if (VR_idx != NumVRs) {
5629 // Doesn't have GPR space allocated.
5630 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5631 } else if (nAltivecParamsAtEnd==0) {
5632 // We are emitting Altivec params in order.
5633 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5634 isPPC64, isTailCall, true, MemOpChains,
5635 TailCallArguments, dl);
5641 // If all Altivec parameters fit in registers, as they usually do,
5642 // they get stack space following the non-Altivec parameters. We
5643 // don't track this here because nobody below needs it.
5644 // If there are more Altivec parameters than fit in registers emit
5646 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5648 // Offset is aligned; skip 1st 12 params which go in V registers.
5649 ArgOffset = ((ArgOffset+15)/16)*16;
5651 for (unsigned i = 0; i != NumOps; ++i) {
5652 SDValue Arg = OutVals[i];
5653 EVT ArgType = Outs[i].VT;
5654 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5655 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5658 // We are emitting Altivec params in order.
5659 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5660 isPPC64, isTailCall, true, MemOpChains,
5661 TailCallArguments, dl);
5668 if (!MemOpChains.empty())
5669 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5671 // On Darwin, R12 must contain the address of an indirect callee. This does
5672 // not mean the MTCTR instruction must use R12; it's easier to model this as
5673 // an extra parameter, so do that.
5675 !isFunctionGlobalAddress(Callee) &&
5676 !isa<ExternalSymbolSDNode>(Callee) &&
5677 !isBLACompatibleAddress(Callee, DAG))
5678 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5679 PPC::R12), Callee));
5681 // Build a sequence of copy-to-reg nodes chained together with token chain
5682 // and flag operands which copy the outgoing args into the appropriate regs.
5684 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5685 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5686 RegsToPass[i].second, InFlag);
5687 InFlag = Chain.getValue(1);
5691 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5692 FPOp, true, TailCallArguments);
5694 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5695 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5696 NumBytes, Ins, InVals, CS);
5700 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5701 MachineFunction &MF, bool isVarArg,
5702 const SmallVectorImpl<ISD::OutputArg> &Outs,
5703 LLVMContext &Context) const {
5704 SmallVector<CCValAssign, 16> RVLocs;
5705 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5706 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5710 PPCTargetLowering::LowerReturn(SDValue Chain,
5711 CallingConv::ID CallConv, bool isVarArg,
5712 const SmallVectorImpl<ISD::OutputArg> &Outs,
5713 const SmallVectorImpl<SDValue> &OutVals,
5714 SDLoc dl, SelectionDAG &DAG) const {
5716 SmallVector<CCValAssign, 16> RVLocs;
5717 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5719 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5722 SmallVector<SDValue, 4> RetOps(1, Chain);
5724 // Copy the result values into the output registers.
5725 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5726 CCValAssign &VA = RVLocs[i];
5727 assert(VA.isRegLoc() && "Can only return in registers!");
5729 SDValue Arg = OutVals[i];
5731 switch (VA.getLocInfo()) {
5732 default: llvm_unreachable("Unknown loc info!");
5733 case CCValAssign::Full: break;
5734 case CCValAssign::AExt:
5735 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5737 case CCValAssign::ZExt:
5738 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5740 case CCValAssign::SExt:
5741 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5745 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5746 Flag = Chain.getValue(1);
5747 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5750 RetOps[0] = Chain; // Update chain.
5752 // Add the flag if we have it.
5754 RetOps.push_back(Flag);
5756 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5759 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5760 const PPCSubtarget &Subtarget) const {
5761 // When we pop the dynamic allocation we need to restore the SP link.
5764 // Get the corect type for pointers.
5765 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5767 // Construct the stack pointer operand.
5768 bool isPPC64 = Subtarget.isPPC64();
5769 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5770 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5772 // Get the operands for the STACKRESTORE.
5773 SDValue Chain = Op.getOperand(0);
5774 SDValue SaveSP = Op.getOperand(1);
5776 // Load the old link SP.
5777 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5778 MachinePointerInfo(),
5779 false, false, false, 0);
5781 // Restore the stack pointer.
5782 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5784 // Store the old link SP.
5785 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5792 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5793 MachineFunction &MF = DAG.getMachineFunction();
5794 bool isPPC64 = Subtarget.isPPC64();
5795 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5797 // Get current frame pointer save index. The users of this index will be
5798 // primarily DYNALLOC instructions.
5799 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5800 int RASI = FI->getReturnAddrSaveIndex();
5802 // If the frame pointer save index hasn't been defined yet.
5804 // Find out what the fix offset of the frame pointer save area.
5805 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5806 // Allocate the frame index for frame pointer save area.
5807 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5809 FI->setReturnAddrSaveIndex(RASI);
5811 return DAG.getFrameIndex(RASI, PtrVT);
5815 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5816 MachineFunction &MF = DAG.getMachineFunction();
5817 bool isPPC64 = Subtarget.isPPC64();
5818 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5820 // Get current frame pointer save index. The users of this index will be
5821 // primarily DYNALLOC instructions.
5822 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5823 int FPSI = FI->getFramePointerSaveIndex();
5825 // If the frame pointer save index hasn't been defined yet.
5827 // Find out what the fix offset of the frame pointer save area.
5828 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5829 // Allocate the frame index for frame pointer save area.
5830 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5832 FI->setFramePointerSaveIndex(FPSI);
5834 return DAG.getFrameIndex(FPSI, PtrVT);
5837 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5839 const PPCSubtarget &Subtarget) const {
5841 SDValue Chain = Op.getOperand(0);
5842 SDValue Size = Op.getOperand(1);
5845 // Get the corect type for pointers.
5846 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5848 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5849 DAG.getConstant(0, dl, PtrVT), Size);
5850 // Construct a node for the frame pointer save index.
5851 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5852 // Build a DYNALLOC node.
5853 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5854 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5855 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5858 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5859 SelectionDAG &DAG) const {
5861 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5862 DAG.getVTList(MVT::i32, MVT::Other),
5863 Op.getOperand(0), Op.getOperand(1));
5866 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5867 SelectionDAG &DAG) const {
5869 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5870 Op.getOperand(0), Op.getOperand(1));
5873 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5874 if (Op.getValueType().isVector())
5875 return LowerVectorLoad(Op, DAG);
5877 assert(Op.getValueType() == MVT::i1 &&
5878 "Custom lowering only for i1 loads");
5880 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5883 LoadSDNode *LD = cast<LoadSDNode>(Op);
5885 SDValue Chain = LD->getChain();
5886 SDValue BasePtr = LD->getBasePtr();
5887 MachineMemOperand *MMO = LD->getMemOperand();
5889 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5890 BasePtr, MVT::i8, MMO);
5891 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5893 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5894 return DAG.getMergeValues(Ops, dl);
5897 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5898 if (Op.getOperand(1).getValueType().isVector())
5899 return LowerVectorStore(Op, DAG);
5901 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5902 "Custom lowering only for i1 stores");
5904 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5907 StoreSDNode *ST = cast<StoreSDNode>(Op);
5909 SDValue Chain = ST->getChain();
5910 SDValue BasePtr = ST->getBasePtr();
5911 SDValue Value = ST->getValue();
5912 MachineMemOperand *MMO = ST->getMemOperand();
5914 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5915 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5918 // FIXME: Remove this once the ANDI glue bug is fixed:
5919 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5920 assert(Op.getValueType() == MVT::i1 &&
5921 "Custom lowering only for i1 results");
5924 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5928 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5930 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5931 // Not FP? Not a fsel.
5932 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5933 !Op.getOperand(2).getValueType().isFloatingPoint())
5936 // We might be able to do better than this under some circumstances, but in
5937 // general, fsel-based lowering of select is a finite-math-only optimization.
5938 // For more information, see section F.3 of the 2.06 ISA specification.
5939 if (!DAG.getTarget().Options.NoInfsFPMath ||
5940 !DAG.getTarget().Options.NoNaNsFPMath)
5943 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5945 EVT ResVT = Op.getValueType();
5946 EVT CmpVT = Op.getOperand(0).getValueType();
5947 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5948 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5951 // If the RHS of the comparison is a 0.0, we don't need to do the
5952 // subtraction at all.
5954 if (isFloatingPointZero(RHS))
5956 default: break; // SETUO etc aren't handled by fsel.
5960 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5961 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5962 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5963 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5964 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5965 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5966 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5969 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5972 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5973 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5974 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5977 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5980 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5981 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5982 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5983 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5988 default: break; // SETUO etc aren't handled by fsel.
5992 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5993 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5994 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5995 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5996 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5997 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5998 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5999 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6002 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6003 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6004 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6005 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6008 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6009 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6010 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6011 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6014 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6015 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6016 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6017 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6020 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6021 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6022 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6023 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6028 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6031 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6032 SDValue Src = Op.getOperand(0);
6033 if (Src.getValueType() == MVT::f32)
6034 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6037 switch (Op.getSimpleValueType().SimpleTy) {
6038 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6041 Op.getOpcode() == ISD::FP_TO_SINT
6043 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6047 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6048 "i64 FP_TO_UINT is supported only with FPCVT");
6049 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6055 // Convert the FP value to an int value through memory.
6056 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6057 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6058 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6059 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6060 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
6062 // Emit a store to the stack slot.
6065 MachineFunction &MF = DAG.getMachineFunction();
6066 MachineMemOperand *MMO =
6067 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6068 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6069 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6070 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6072 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6073 MPI, false, false, 0);
6075 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6077 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6078 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6079 DAG.getConstant(4, dl, FIPtr.getValueType()));
6080 MPI = MPI.getWithOffset(4);
6088 /// \brief Custom lowers floating point to integer conversions to use
6089 /// the direct move instructions available in ISA 2.07 to avoid the
6090 /// need for load/store combinations.
6091 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6094 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6095 SDValue Src = Op.getOperand(0);
6097 if (Src.getValueType() == MVT::f32)
6098 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6101 switch (Op.getSimpleValueType().SimpleTy) {
6102 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6105 Op.getOpcode() == ISD::FP_TO_SINT
6107 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6109 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6112 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6113 "i64 FP_TO_UINT is supported only with FPCVT");
6114 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6117 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6123 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6125 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6126 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6129 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6131 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6132 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6136 // We're trying to insert a regular store, S, and then a load, L. If the
6137 // incoming value, O, is a load, we might just be able to have our load use the
6138 // address used by O. However, we don't know if anything else will store to
6139 // that address before we can load from it. To prevent this situation, we need
6140 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6141 // the same chain operand as O, we create a token factor from the chain results
6142 // of O and L, and we replace all uses of O's chain result with that token
6143 // factor (see spliceIntoChain below for this last part).
6144 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6147 ISD::LoadExtType ET) const {
6149 if (ET == ISD::NON_EXTLOAD &&
6150 (Op.getOpcode() == ISD::FP_TO_UINT ||
6151 Op.getOpcode() == ISD::FP_TO_SINT) &&
6152 isOperationLegalOrCustom(Op.getOpcode(),
6153 Op.getOperand(0).getValueType())) {
6155 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6159 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6160 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6161 LD->isNonTemporal())
6163 if (LD->getMemoryVT() != MemVT)
6166 RLI.Ptr = LD->getBasePtr();
6167 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6168 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6169 "Non-pre-inc AM on PPC?");
6170 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6174 RLI.Chain = LD->getChain();
6175 RLI.MPI = LD->getPointerInfo();
6176 RLI.IsInvariant = LD->isInvariant();
6177 RLI.Alignment = LD->getAlignment();
6178 RLI.AAInfo = LD->getAAInfo();
6179 RLI.Ranges = LD->getRanges();
6181 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6185 // Given the head of the old chain, ResChain, insert a token factor containing
6186 // it and NewResChain, and make users of ResChain now be users of that token
6188 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6189 SDValue NewResChain,
6190 SelectionDAG &DAG) const {
6194 SDLoc dl(NewResChain);
6196 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6197 NewResChain, DAG.getUNDEF(MVT::Other));
6198 assert(TF.getNode() != NewResChain.getNode() &&
6199 "A new TF really is required here");
6201 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6202 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6205 /// \brief Custom lowers integer to floating point conversions to use
6206 /// the direct move instructions available in ISA 2.07 to avoid the
6207 /// need for load/store combinations.
6208 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6211 assert((Op.getValueType() == MVT::f32 ||
6212 Op.getValueType() == MVT::f64) &&
6213 "Invalid floating point type as target of conversion");
6214 assert(Subtarget.hasFPCVT() &&
6215 "Int to FP conversions with direct moves require FPCVT");
6217 SDValue Src = Op.getOperand(0);
6218 bool SinglePrec = Op.getValueType() == MVT::f32;
6219 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6220 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6221 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6222 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6225 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6227 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6230 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6231 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6237 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6238 SelectionDAG &DAG) const {
6241 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6242 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6245 SDValue Value = Op.getOperand(0);
6246 // The values are now known to be -1 (false) or 1 (true). To convert this
6247 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6248 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6249 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6251 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6252 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6253 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6255 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6257 if (Op.getValueType() != MVT::v4f64)
6258 Value = DAG.getNode(ISD::FP_ROUND, dl,
6259 Op.getValueType(), Value,
6260 DAG.getIntPtrConstant(1, dl));
6264 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6265 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6268 if (Op.getOperand(0).getValueType() == MVT::i1)
6269 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6270 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6271 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6273 // If we have direct moves, we can do all the conversion, skip the store/load
6274 // however, without FPCVT we can't do most conversions.
6275 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6276 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6278 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6279 "UINT_TO_FP is supported only with FPCVT");
6281 // If we have FCFIDS, then use it when converting to single-precision.
6282 // Otherwise, convert to double-precision and then round.
6283 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6284 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6286 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6288 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6292 if (Op.getOperand(0).getValueType() == MVT::i64) {
6293 SDValue SINT = Op.getOperand(0);
6294 // When converting to single-precision, we actually need to convert
6295 // to double-precision first and then round to single-precision.
6296 // To avoid double-rounding effects during that operation, we have
6297 // to prepare the input operand. Bits that might be truncated when
6298 // converting to double-precision are replaced by a bit that won't
6299 // be lost at this stage, but is below the single-precision rounding
6302 // However, if -enable-unsafe-fp-math is in effect, accept double
6303 // rounding to avoid the extra overhead.
6304 if (Op.getValueType() == MVT::f32 &&
6305 !Subtarget.hasFPCVT() &&
6306 !DAG.getTarget().Options.UnsafeFPMath) {
6308 // Twiddle input to make sure the low 11 bits are zero. (If this
6309 // is the case, we are guaranteed the value will fit into the 53 bit
6310 // mantissa of an IEEE double-precision value without rounding.)
6311 // If any of those low 11 bits were not zero originally, make sure
6312 // bit 12 (value 2048) is set instead, so that the final rounding
6313 // to single-precision gets the correct result.
6314 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6315 SINT, DAG.getConstant(2047, dl, MVT::i64));
6316 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6317 Round, DAG.getConstant(2047, dl, MVT::i64));
6318 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6319 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6320 Round, DAG.getConstant(-2048, dl, MVT::i64));
6322 // However, we cannot use that value unconditionally: if the magnitude
6323 // of the input value is small, the bit-twiddling we did above might
6324 // end up visibly changing the output. Fortunately, in that case, we
6325 // don't need to twiddle bits since the original input will convert
6326 // exactly to double-precision floating-point already. Therefore,
6327 // construct a conditional to use the original value if the top 11
6328 // bits are all sign-bit copies, and use the rounded value computed
6330 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6331 SINT, DAG.getConstant(53, dl, MVT::i32));
6332 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6333 Cond, DAG.getConstant(1, dl, MVT::i64));
6334 Cond = DAG.getSetCC(dl, MVT::i32,
6335 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6337 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6343 MachineFunction &MF = DAG.getMachineFunction();
6344 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6345 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6346 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6348 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6349 } else if (Subtarget.hasLFIWAX() &&
6350 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6351 MachineMemOperand *MMO =
6352 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6353 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6354 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6355 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6356 DAG.getVTList(MVT::f64, MVT::Other),
6357 Ops, MVT::i32, MMO);
6358 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6359 } else if (Subtarget.hasFPCVT() &&
6360 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6361 MachineMemOperand *MMO =
6362 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6363 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6364 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6365 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6366 DAG.getVTList(MVT::f64, MVT::Other),
6367 Ops, MVT::i32, MMO);
6368 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6369 } else if (((Subtarget.hasLFIWAX() &&
6370 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6371 (Subtarget.hasFPCVT() &&
6372 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6373 SINT.getOperand(0).getValueType() == MVT::i32) {
6374 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6375 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6377 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6378 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6381 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6382 MachinePointerInfo::getFixedStack(FrameIdx),
6385 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6386 "Expected an i32 store");
6390 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6393 MachineMemOperand *MMO =
6394 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6395 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6396 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6397 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6398 PPCISD::LFIWZX : PPCISD::LFIWAX,
6399 dl, DAG.getVTList(MVT::f64, MVT::Other),
6400 Ops, MVT::i32, MMO);
6402 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6404 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6406 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6407 FP = DAG.getNode(ISD::FP_ROUND, dl,
6408 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6412 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6413 "Unhandled INT_TO_FP type in custom expander!");
6414 // Since we only generate this in 64-bit mode, we can take advantage of
6415 // 64-bit registers. In particular, sign extend the input value into the
6416 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6417 // then lfd it and fcfid it.
6418 MachineFunction &MF = DAG.getMachineFunction();
6419 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6423 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6426 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6428 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6429 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6431 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6432 MachinePointerInfo::getFixedStack(FrameIdx),
6435 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6436 "Expected an i32 store");
6440 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6444 MachineMemOperand *MMO =
6445 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6446 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6447 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6448 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6449 PPCISD::LFIWZX : PPCISD::LFIWAX,
6450 dl, DAG.getVTList(MVT::f64, MVT::Other),
6451 Ops, MVT::i32, MMO);
6453 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6455 assert(Subtarget.isPPC64() &&
6456 "i32->FP without LFIWAX supported only on PPC64");
6458 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6459 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6461 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6464 // STD the extended value into the stack slot.
6465 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6466 MachinePointerInfo::getFixedStack(FrameIdx),
6469 // Load the value as a double.
6470 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6471 MachinePointerInfo::getFixedStack(FrameIdx),
6472 false, false, false, 0);
6475 // FCFID it and return it.
6476 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6477 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6478 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6479 DAG.getIntPtrConstant(0, dl));
6483 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6484 SelectionDAG &DAG) const {
6487 The rounding mode is in bits 30:31 of FPSR, and has the following
6494 FLT_ROUNDS, on the other hand, expects the following:
6501 To perform the conversion, we do:
6502 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6505 MachineFunction &MF = DAG.getMachineFunction();
6506 EVT VT = Op.getValueType();
6507 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6509 // Save FP Control Word to register
6511 MVT::f64, // return register
6512 MVT::Glue // unused in this context
6514 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6516 // Save FP register to stack slot
6517 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6518 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6519 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6520 StackSlot, MachinePointerInfo(), false, false,0);
6522 // Load FP Control Word from low 32 bits of stack slot.
6523 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6524 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6525 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6526 false, false, false, 0);
6528 // Transform as necessary
6530 DAG.getNode(ISD::AND, dl, MVT::i32,
6531 CWD, DAG.getConstant(3, dl, MVT::i32));
6533 DAG.getNode(ISD::SRL, dl, MVT::i32,
6534 DAG.getNode(ISD::AND, dl, MVT::i32,
6535 DAG.getNode(ISD::XOR, dl, MVT::i32,
6536 CWD, DAG.getConstant(3, dl, MVT::i32)),
6537 DAG.getConstant(3, dl, MVT::i32)),
6538 DAG.getConstant(1, dl, MVT::i32));
6541 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6543 return DAG.getNode((VT.getSizeInBits() < 16 ?
6544 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6547 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6548 EVT VT = Op.getValueType();
6549 unsigned BitWidth = VT.getSizeInBits();
6551 assert(Op.getNumOperands() == 3 &&
6552 VT == Op.getOperand(1).getValueType() &&
6555 // Expand into a bunch of logical ops. Note that these ops
6556 // depend on the PPC behavior for oversized shift amounts.
6557 SDValue Lo = Op.getOperand(0);
6558 SDValue Hi = Op.getOperand(1);
6559 SDValue Amt = Op.getOperand(2);
6560 EVT AmtVT = Amt.getValueType();
6562 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6563 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6564 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6565 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6566 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6567 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6568 DAG.getConstant(-BitWidth, dl, AmtVT));
6569 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6570 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6571 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6572 SDValue OutOps[] = { OutLo, OutHi };
6573 return DAG.getMergeValues(OutOps, dl);
6576 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6577 EVT VT = Op.getValueType();
6579 unsigned BitWidth = VT.getSizeInBits();
6580 assert(Op.getNumOperands() == 3 &&
6581 VT == Op.getOperand(1).getValueType() &&
6584 // Expand into a bunch of logical ops. Note that these ops
6585 // depend on the PPC behavior for oversized shift amounts.
6586 SDValue Lo = Op.getOperand(0);
6587 SDValue Hi = Op.getOperand(1);
6588 SDValue Amt = Op.getOperand(2);
6589 EVT AmtVT = Amt.getValueType();
6591 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6592 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6593 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6594 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6595 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6596 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6597 DAG.getConstant(-BitWidth, dl, AmtVT));
6598 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6599 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6600 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6601 SDValue OutOps[] = { OutLo, OutHi };
6602 return DAG.getMergeValues(OutOps, dl);
6605 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6607 EVT VT = Op.getValueType();
6608 unsigned BitWidth = VT.getSizeInBits();
6609 assert(Op.getNumOperands() == 3 &&
6610 VT == Op.getOperand(1).getValueType() &&
6613 // Expand into a bunch of logical ops, followed by a select_cc.
6614 SDValue Lo = Op.getOperand(0);
6615 SDValue Hi = Op.getOperand(1);
6616 SDValue Amt = Op.getOperand(2);
6617 EVT AmtVT = Amt.getValueType();
6619 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6620 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6621 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6622 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6623 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6624 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6625 DAG.getConstant(-BitWidth, dl, AmtVT));
6626 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6627 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6628 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6629 Tmp4, Tmp6, ISD::SETLE);
6630 SDValue OutOps[] = { OutLo, OutHi };
6631 return DAG.getMergeValues(OutOps, dl);
6634 //===----------------------------------------------------------------------===//
6635 // Vector related lowering.
6638 /// BuildSplatI - Build a canonical splati of Val with an element size of
6639 /// SplatSize. Cast the result to VT.
6640 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6641 SelectionDAG &DAG, SDLoc dl) {
6642 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6644 static const MVT VTys[] = { // canonical VT to use for each size.
6645 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6648 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6650 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6654 EVT CanonicalVT = VTys[SplatSize-1];
6656 // Build a canonical splat for this value.
6657 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6658 SmallVector<SDValue, 8> Ops;
6659 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6660 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6661 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6664 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6665 /// specified intrinsic ID.
6666 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6667 SelectionDAG &DAG, SDLoc dl,
6668 EVT DestVT = MVT::Other) {
6669 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6670 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6671 DAG.getConstant(IID, dl, MVT::i32), Op);
6674 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6675 /// specified intrinsic ID.
6676 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6677 SelectionDAG &DAG, SDLoc dl,
6678 EVT DestVT = MVT::Other) {
6679 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6680 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6681 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6684 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6685 /// specified intrinsic ID.
6686 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6687 SDValue Op2, SelectionDAG &DAG,
6688 SDLoc dl, EVT DestVT = MVT::Other) {
6689 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6690 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6691 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6695 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6696 /// amount. The result has the specified value type.
6697 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6698 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6699 // Force LHS/RHS to be the right type.
6700 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6701 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6704 for (unsigned i = 0; i != 16; ++i)
6706 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6707 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6710 // If this is a case we can't handle, return null and let the default
6711 // expansion code take care of it. If we CAN select this case, and if it
6712 // selects to a single instruction, return Op. Otherwise, if we can codegen
6713 // this case more efficiently than a constant pool load, lower it to the
6714 // sequence of ops that should be used.
6715 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6716 SelectionDAG &DAG) const {
6718 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6719 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6721 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6722 // We first build an i32 vector, load it into a QPX register,
6723 // then convert it to a floating-point vector and compare it
6724 // to a zero vector to get the boolean result.
6725 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6726 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6727 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6728 EVT PtrVT = getPointerTy();
6729 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6731 assert(BVN->getNumOperands() == 4 &&
6732 "BUILD_VECTOR for v4i1 does not have 4 operands");
6734 bool IsConst = true;
6735 for (unsigned i = 0; i < 4; ++i) {
6736 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6737 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6745 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6747 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6749 SmallVector<Constant*, 4> CV(4, NegOne);
6750 for (unsigned i = 0; i < 4; ++i) {
6751 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6752 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6753 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6754 getConstantIntValue()->isZero())
6760 Constant *CP = ConstantVector::get(CV);
6761 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(),
6762 16 /* alignment */);
6764 SmallVector<SDValue, 2> Ops;
6765 Ops.push_back(DAG.getEntryNode());
6766 Ops.push_back(CPIdx);
6768 SmallVector<EVT, 2> ValueVTs;
6769 ValueVTs.push_back(MVT::v4i1);
6770 ValueVTs.push_back(MVT::Other); // chain
6771 SDVTList VTs = DAG.getVTList(ValueVTs);
6773 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6774 dl, VTs, Ops, MVT::v4f32,
6775 MachinePointerInfo::getConstantPool());
6778 SmallVector<SDValue, 4> Stores;
6779 for (unsigned i = 0; i < 4; ++i) {
6780 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6782 unsigned Offset = 4*i;
6783 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6784 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6786 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6787 if (StoreSize > 4) {
6788 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6789 BVN->getOperand(i), Idx,
6790 PtrInfo.getWithOffset(Offset),
6791 MVT::i32, false, false, 0));
6793 SDValue StoreValue = BVN->getOperand(i);
6795 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6797 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6799 PtrInfo.getWithOffset(Offset),
6805 if (!Stores.empty())
6806 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6808 StoreChain = DAG.getEntryNode();
6810 // Now load from v4i32 into the QPX register; this will extend it to
6811 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6812 // is typed as v4f64 because the QPX register integer states are not
6813 // explicitly represented.
6815 SmallVector<SDValue, 2> Ops;
6816 Ops.push_back(StoreChain);
6817 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6818 Ops.push_back(FIdx);
6820 SmallVector<EVT, 2> ValueVTs;
6821 ValueVTs.push_back(MVT::v4f64);
6822 ValueVTs.push_back(MVT::Other); // chain
6823 SDVTList VTs = DAG.getVTList(ValueVTs);
6825 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6826 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6827 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6828 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6831 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6832 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6833 FPZeros, FPZeros, FPZeros, FPZeros);
6835 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6838 // All other QPX vectors are handled by generic code.
6839 if (Subtarget.hasQPX())
6842 // Check if this is a splat of a constant value.
6843 APInt APSplatBits, APSplatUndef;
6844 unsigned SplatBitSize;
6846 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6847 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6851 unsigned SplatBits = APSplatBits.getZExtValue();
6852 unsigned SplatUndef = APSplatUndef.getZExtValue();
6853 unsigned SplatSize = SplatBitSize / 8;
6855 // First, handle single instruction cases.
6858 if (SplatBits == 0) {
6859 // Canonicalize all zero vectors to be v4i32.
6860 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6861 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6862 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6863 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6868 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6869 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6871 if (SextVal >= -16 && SextVal <= 15)
6872 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6875 // Two instruction sequences.
6877 // If this value is in the range [-32,30] and is even, use:
6878 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6879 // If this value is in the range [17,31] and is odd, use:
6880 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6881 // If this value is in the range [-31,-17] and is odd, use:
6882 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6883 // Note the last two are three-instruction sequences.
6884 if (SextVal >= -32 && SextVal <= 31) {
6885 // To avoid having these optimizations undone by constant folding,
6886 // we convert to a pseudo that will be expanded later into one of
6888 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6889 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6890 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6891 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6892 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6893 if (VT == Op.getValueType())
6896 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6899 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6900 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6902 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6903 // Make -1 and vspltisw -1:
6904 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6906 // Make the VSLW intrinsic, computing 0x8000_0000.
6907 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6910 // xor by OnesV to invert it.
6911 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6912 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6915 // Check to see if this is a wide variety of vsplti*, binop self cases.
6916 static const signed char SplatCsts[] = {
6917 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6918 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6921 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6922 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6923 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6924 int i = SplatCsts[idx];
6926 // Figure out what shift amount will be used by altivec if shifted by i in
6928 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6930 // vsplti + shl self.
6931 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6932 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6933 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6934 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6935 Intrinsic::ppc_altivec_vslw
6937 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6938 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6941 // vsplti + srl self.
6942 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6943 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6944 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6945 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6946 Intrinsic::ppc_altivec_vsrw
6948 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6949 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6952 // vsplti + sra self.
6953 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6954 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6955 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6956 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6957 Intrinsic::ppc_altivec_vsraw
6959 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6960 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6963 // vsplti + rol self.
6964 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6965 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6966 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6967 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6968 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6969 Intrinsic::ppc_altivec_vrlw
6971 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6972 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6975 // t = vsplti c, result = vsldoi t, t, 1
6976 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6977 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6978 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6980 // t = vsplti c, result = vsldoi t, t, 2
6981 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6982 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6983 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6985 // t = vsplti c, result = vsldoi t, t, 3
6986 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6987 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6988 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6995 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6996 /// the specified operations to build the shuffle.
6997 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6998 SDValue RHS, SelectionDAG &DAG,
7000 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7001 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7002 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7005 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7017 if (OpNum == OP_COPY) {
7018 if (LHSID == (1*9+2)*9+3) return LHS;
7019 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7023 SDValue OpLHS, OpRHS;
7024 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7025 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7029 default: llvm_unreachable("Unknown i32 permute!");
7031 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7032 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7033 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7034 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7037 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7038 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7039 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7040 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7043 for (unsigned i = 0; i != 16; ++i)
7044 ShufIdxs[i] = (i&3)+0;
7047 for (unsigned i = 0; i != 16; ++i)
7048 ShufIdxs[i] = (i&3)+4;
7051 for (unsigned i = 0; i != 16; ++i)
7052 ShufIdxs[i] = (i&3)+8;
7055 for (unsigned i = 0; i != 16; ++i)
7056 ShufIdxs[i] = (i&3)+12;
7059 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7061 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7063 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7065 EVT VT = OpLHS.getValueType();
7066 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7067 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7068 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7069 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7072 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7073 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7074 /// return the code it can be lowered into. Worst case, it can always be
7075 /// lowered into a vperm.
7076 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7077 SelectionDAG &DAG) const {
7079 SDValue V1 = Op.getOperand(0);
7080 SDValue V2 = Op.getOperand(1);
7081 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7082 EVT VT = Op.getValueType();
7083 bool isLittleEndian = Subtarget.isLittleEndian();
7085 if (Subtarget.hasQPX()) {
7086 if (VT.getVectorNumElements() != 4)
7089 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7091 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7092 if (AlignIdx != -1) {
7093 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7094 DAG.getConstant(AlignIdx, dl, MVT::i32));
7095 } else if (SVOp->isSplat()) {
7096 int SplatIdx = SVOp->getSplatIndex();
7097 if (SplatIdx >= 4) {
7102 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7105 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7106 DAG.getConstant(SplatIdx, dl, MVT::i32));
7109 // Lower this into a qvgpci/qvfperm pair.
7111 // Compute the qvgpci literal
7113 for (unsigned i = 0; i < 4; ++i) {
7114 int m = SVOp->getMaskElt(i);
7115 unsigned mm = m >= 0 ? (unsigned) m : i;
7116 idx |= mm << (3-i)*3;
7119 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7120 DAG.getConstant(idx, dl, MVT::i32));
7121 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7124 // Cases that are handled by instructions that take permute immediates
7125 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7126 // selected by the instruction selector.
7127 if (V2.getOpcode() == ISD::UNDEF) {
7128 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7129 PPC::isSplatShuffleMask(SVOp, 2) ||
7130 PPC::isSplatShuffleMask(SVOp, 4) ||
7131 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7132 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7133 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7134 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7135 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7136 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7137 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7138 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7139 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7140 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7141 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7142 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
7147 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7148 // and produce a fixed permutation. If any of these match, do not lower to
7150 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7151 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7152 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7153 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7154 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7155 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7156 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7157 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7158 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7159 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7160 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7161 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7162 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
7165 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7166 // perfect shuffle table to emit an optimal matching sequence.
7167 ArrayRef<int> PermMask = SVOp->getMask();
7169 unsigned PFIndexes[4];
7170 bool isFourElementShuffle = true;
7171 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7172 unsigned EltNo = 8; // Start out undef.
7173 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7174 if (PermMask[i*4+j] < 0)
7175 continue; // Undef, ignore it.
7177 unsigned ByteSource = PermMask[i*4+j];
7178 if ((ByteSource & 3) != j) {
7179 isFourElementShuffle = false;
7184 EltNo = ByteSource/4;
7185 } else if (EltNo != ByteSource/4) {
7186 isFourElementShuffle = false;
7190 PFIndexes[i] = EltNo;
7193 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7194 // perfect shuffle vector to determine if it is cost effective to do this as
7195 // discrete instructions, or whether we should use a vperm.
7196 // For now, we skip this for little endian until such time as we have a
7197 // little-endian perfect shuffle table.
7198 if (isFourElementShuffle && !isLittleEndian) {
7199 // Compute the index in the perfect shuffle table.
7200 unsigned PFTableIndex =
7201 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7203 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7204 unsigned Cost = (PFEntry >> 30);
7206 // Determining when to avoid vperm is tricky. Many things affect the cost
7207 // of vperm, particularly how many times the perm mask needs to be computed.
7208 // For example, if the perm mask can be hoisted out of a loop or is already
7209 // used (perhaps because there are multiple permutes with the same shuffle
7210 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7211 // the loop requires an extra register.
7213 // As a compromise, we only emit discrete instructions if the shuffle can be
7214 // generated in 3 or fewer operations. When we have loop information
7215 // available, if this block is within a loop, we should avoid using vperm
7216 // for 3-operation perms and use a constant pool load instead.
7218 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7221 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7222 // vector that will get spilled to the constant pool.
7223 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7225 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7226 // that it is in input element units, not in bytes. Convert now.
7228 // For little endian, the order of the input vectors is reversed, and
7229 // the permutation mask is complemented with respect to 31. This is
7230 // necessary to produce proper semantics with the big-endian-biased vperm
7232 EVT EltVT = V1.getValueType().getVectorElementType();
7233 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7235 SmallVector<SDValue, 16> ResultMask;
7236 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7237 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7239 for (unsigned j = 0; j != BytesPerElement; ++j)
7241 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7244 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7248 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7251 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7254 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7258 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7259 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7260 /// information about the intrinsic.
7261 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7262 bool &isDot, const PPCSubtarget &Subtarget) {
7263 unsigned IntrinsicID =
7264 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7267 switch (IntrinsicID) {
7268 default: return false;
7269 // Comparison predicates.
7270 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7271 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7272 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7273 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7274 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7275 case Intrinsic::ppc_altivec_vcmpequd_p:
7276 if (Subtarget.hasP8Altivec()) {
7284 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7285 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7286 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7287 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7288 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7289 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7290 if (Subtarget.hasP8Altivec()) {
7298 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7299 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7300 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7301 case Intrinsic::ppc_altivec_vcmpgtud_p:
7302 if (Subtarget.hasP8Altivec()) {
7311 // Normal Comparisons.
7312 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7313 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7314 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7315 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7316 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7317 case Intrinsic::ppc_altivec_vcmpequd:
7318 if (Subtarget.hasP8Altivec()) {
7326 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7327 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7328 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7329 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7330 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7331 case Intrinsic::ppc_altivec_vcmpgtsd:
7332 if (Subtarget.hasP8Altivec()) {
7340 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7341 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7342 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7343 case Intrinsic::ppc_altivec_vcmpgtud:
7344 if (Subtarget.hasP8Altivec()) {
7356 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7357 /// lower, do it, otherwise return null.
7358 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7359 SelectionDAG &DAG) const {
7360 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7361 // opcode number of the comparison.
7365 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7366 return SDValue(); // Don't custom lower most intrinsics.
7368 // If this is a non-dot comparison, make the VCMP node and we are done.
7370 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7371 Op.getOperand(1), Op.getOperand(2),
7372 DAG.getConstant(CompareOpc, dl, MVT::i32));
7373 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7376 // Create the PPCISD altivec 'dot' comparison node.
7378 Op.getOperand(2), // LHS
7379 Op.getOperand(3), // RHS
7380 DAG.getConstant(CompareOpc, dl, MVT::i32)
7382 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7383 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7385 // Now that we have the comparison, emit a copy from the CR to a GPR.
7386 // This is flagged to the above dot comparison.
7387 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7388 DAG.getRegister(PPC::CR6, MVT::i32),
7389 CompNode.getValue(1));
7391 // Unpack the result based on how the target uses it.
7392 unsigned BitNo; // Bit # of CR6.
7393 bool InvertBit; // Invert result?
7394 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7395 default: // Can't happen, don't crash on invalid number though.
7396 case 0: // Return the value of the EQ bit of CR6.
7397 BitNo = 0; InvertBit = false;
7399 case 1: // Return the inverted value of the EQ bit of CR6.
7400 BitNo = 0; InvertBit = true;
7402 case 2: // Return the value of the LT bit of CR6.
7403 BitNo = 2; InvertBit = false;
7405 case 3: // Return the inverted value of the LT bit of CR6.
7406 BitNo = 2; InvertBit = true;
7410 // Shift the bit into the low position.
7411 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7412 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7414 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7415 DAG.getConstant(1, dl, MVT::i32));
7417 // If we are supposed to, toggle the bit.
7419 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7420 DAG.getConstant(1, dl, MVT::i32));
7424 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7425 SelectionDAG &DAG) const {
7427 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7428 // instructions), but for smaller types, we need to first extend up to v2i32
7429 // before doing going farther.
7430 if (Op.getValueType() == MVT::v2i64) {
7431 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7432 if (ExtVT != MVT::v2i32) {
7433 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7434 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7435 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7436 ExtVT.getVectorElementType(), 4)));
7437 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7438 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7439 DAG.getValueType(MVT::v2i32));
7448 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7449 SelectionDAG &DAG) const {
7451 // Create a stack slot that is 16-byte aligned.
7452 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7453 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7454 EVT PtrVT = getPointerTy();
7455 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7457 // Store the input value into Value#0 of the stack slot.
7458 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7459 Op.getOperand(0), FIdx, MachinePointerInfo(),
7462 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7463 false, false, false, 0);
7466 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7467 SelectionDAG &DAG) const {
7469 SDNode *N = Op.getNode();
7471 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7472 "Unknown extract_vector_elt type");
7474 SDValue Value = N->getOperand(0);
7476 // The first part of this is like the store lowering except that we don't
7477 // need to track the chain.
7479 // The values are now known to be -1 (false) or 1 (true). To convert this
7480 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7481 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7482 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7484 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7485 // understand how to form the extending load.
7486 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7487 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7488 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7490 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7492 // Now convert to an integer and store.
7493 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7494 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7497 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7498 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7499 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7500 EVT PtrVT = getPointerTy();
7501 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7503 SDValue StoreChain = DAG.getEntryNode();
7504 SmallVector<SDValue, 2> Ops;
7505 Ops.push_back(StoreChain);
7506 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7507 Ops.push_back(Value);
7508 Ops.push_back(FIdx);
7510 SmallVector<EVT, 2> ValueVTs;
7511 ValueVTs.push_back(MVT::Other); // chain
7512 SDVTList VTs = DAG.getVTList(ValueVTs);
7514 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7515 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7517 // Extract the value requested.
7518 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7519 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7520 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7522 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7523 PtrInfo.getWithOffset(Offset),
7524 false, false, false, 0);
7526 if (!Subtarget.useCRBits())
7529 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7532 /// Lowering for QPX v4i1 loads
7533 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7534 SelectionDAG &DAG) const {
7536 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7537 SDValue LoadChain = LN->getChain();
7538 SDValue BasePtr = LN->getBasePtr();
7540 if (Op.getValueType() == MVT::v4f64 ||
7541 Op.getValueType() == MVT::v4f32) {
7542 EVT MemVT = LN->getMemoryVT();
7543 unsigned Alignment = LN->getAlignment();
7545 // If this load is properly aligned, then it is legal.
7546 if (Alignment >= MemVT.getStoreSize())
7549 EVT ScalarVT = Op.getValueType().getScalarType(),
7550 ScalarMemVT = MemVT.getScalarType();
7551 unsigned Stride = ScalarMemVT.getStoreSize();
7553 SmallVector<SDValue, 8> Vals, LoadChains;
7554 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7556 if (ScalarVT != ScalarMemVT)
7558 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7560 LN->getPointerInfo().getWithOffset(Idx*Stride),
7561 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7562 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7566 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7567 LN->getPointerInfo().getWithOffset(Idx*Stride),
7568 LN->isVolatile(), LN->isNonTemporal(),
7569 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7572 if (Idx == 0 && LN->isIndexed()) {
7573 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7574 "Unknown addressing mode on vector load");
7575 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7576 LN->getAddressingMode());
7579 Vals.push_back(Load);
7580 LoadChains.push_back(Load.getValue(1));
7582 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7583 DAG.getConstant(Stride, dl,
7584 BasePtr.getValueType()));
7587 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7588 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7589 Op.getValueType(), Vals);
7591 if (LN->isIndexed()) {
7592 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7593 return DAG.getMergeValues(RetOps, dl);
7596 SDValue RetOps[] = { Value, TF };
7597 return DAG.getMergeValues(RetOps, dl);
7600 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7601 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7603 // To lower v4i1 from a byte array, we load the byte elements of the
7604 // vector and then reuse the BUILD_VECTOR logic.
7606 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7607 for (unsigned i = 0; i < 4; ++i) {
7608 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7609 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7611 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7612 dl, MVT::i32, LoadChain, Idx,
7613 LN->getPointerInfo().getWithOffset(i),
7614 MVT::i8 /* memory type */,
7615 LN->isVolatile(), LN->isNonTemporal(),
7617 1 /* alignment */, LN->getAAInfo()));
7618 VectElmtChains.push_back(VectElmts[i].getValue(1));
7621 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7622 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7624 SDValue RVals[] = { Value, LoadChain };
7625 return DAG.getMergeValues(RVals, dl);
7628 /// Lowering for QPX v4i1 stores
7629 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7630 SelectionDAG &DAG) const {
7632 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7633 SDValue StoreChain = SN->getChain();
7634 SDValue BasePtr = SN->getBasePtr();
7635 SDValue Value = SN->getValue();
7637 if (Value.getValueType() == MVT::v4f64 ||
7638 Value.getValueType() == MVT::v4f32) {
7639 EVT MemVT = SN->getMemoryVT();
7640 unsigned Alignment = SN->getAlignment();
7642 // If this store is properly aligned, then it is legal.
7643 if (Alignment >= MemVT.getStoreSize())
7646 EVT ScalarVT = Value.getValueType().getScalarType(),
7647 ScalarMemVT = MemVT.getScalarType();
7648 unsigned Stride = ScalarMemVT.getStoreSize();
7650 SmallVector<SDValue, 8> Stores;
7651 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7654 DAG.getConstant(Idx, dl, getVectorIdxTy()));
7656 if (ScalarVT != ScalarMemVT)
7658 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7659 SN->getPointerInfo().getWithOffset(Idx*Stride),
7660 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7661 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7664 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7665 SN->getPointerInfo().getWithOffset(Idx*Stride),
7666 SN->isVolatile(), SN->isNonTemporal(),
7667 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7669 if (Idx == 0 && SN->isIndexed()) {
7670 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7671 "Unknown addressing mode on vector store");
7672 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7673 SN->getAddressingMode());
7676 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7677 DAG.getConstant(Stride, dl,
7678 BasePtr.getValueType()));
7679 Stores.push_back(Store);
7682 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7684 if (SN->isIndexed()) {
7685 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7686 return DAG.getMergeValues(RetOps, dl);
7692 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7693 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7695 // The values are now known to be -1 (false) or 1 (true). To convert this
7696 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7697 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7698 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7700 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7701 // understand how to form the extending load.
7702 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7703 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7704 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7706 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7708 // Now convert to an integer and store.
7709 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7710 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7713 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7714 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7715 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7716 EVT PtrVT = getPointerTy();
7717 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7719 SmallVector<SDValue, 2> Ops;
7720 Ops.push_back(StoreChain);
7721 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7722 Ops.push_back(Value);
7723 Ops.push_back(FIdx);
7725 SmallVector<EVT, 2> ValueVTs;
7726 ValueVTs.push_back(MVT::Other); // chain
7727 SDVTList VTs = DAG.getVTList(ValueVTs);
7729 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7730 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7732 // Move data into the byte array.
7733 SmallVector<SDValue, 4> Loads, LoadChains;
7734 for (unsigned i = 0; i < 4; ++i) {
7735 unsigned Offset = 4*i;
7736 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7737 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7739 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7740 PtrInfo.getWithOffset(Offset),
7741 false, false, false, 0));
7742 LoadChains.push_back(Loads[i].getValue(1));
7745 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7747 SmallVector<SDValue, 4> Stores;
7748 for (unsigned i = 0; i < 4; ++i) {
7749 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7750 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7752 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7753 SN->getPointerInfo().getWithOffset(i),
7754 MVT::i8 /* memory type */,
7755 SN->isNonTemporal(), SN->isVolatile(),
7756 1 /* alignment */, SN->getAAInfo()));
7759 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7764 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7766 if (Op.getValueType() == MVT::v4i32) {
7767 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7769 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7770 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7772 SDValue RHSSwap = // = vrlw RHS, 16
7773 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7775 // Shrinkify inputs to v8i16.
7776 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7777 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7778 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7780 // Low parts multiplied together, generating 32-bit results (we ignore the
7782 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7783 LHS, RHS, DAG, dl, MVT::v4i32);
7785 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7786 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7787 // Shift the high parts up 16 bits.
7788 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7790 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7791 } else if (Op.getValueType() == MVT::v8i16) {
7792 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7794 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7796 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7797 LHS, RHS, Zero, DAG, dl);
7798 } else if (Op.getValueType() == MVT::v16i8) {
7799 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7800 bool isLittleEndian = Subtarget.isLittleEndian();
7802 // Multiply the even 8-bit parts, producing 16-bit sums.
7803 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7804 LHS, RHS, DAG, dl, MVT::v8i16);
7805 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7807 // Multiply the odd 8-bit parts, producing 16-bit sums.
7808 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7809 LHS, RHS, DAG, dl, MVT::v8i16);
7810 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7812 // Merge the results together. Because vmuleub and vmuloub are
7813 // instructions with a big-endian bias, we must reverse the
7814 // element numbering and reverse the meaning of "odd" and "even"
7815 // when generating little endian code.
7817 for (unsigned i = 0; i != 8; ++i) {
7818 if (isLittleEndian) {
7820 Ops[i*2+1] = 2*i+16;
7823 Ops[i*2+1] = 2*i+1+16;
7827 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7829 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7831 llvm_unreachable("Unknown mul to lower!");
7835 /// LowerOperation - Provide custom lowering hooks for some operations.
7837 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7838 switch (Op.getOpcode()) {
7839 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7840 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7841 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7842 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7843 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7844 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7845 case ISD::SETCC: return LowerSETCC(Op, DAG);
7846 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7847 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7849 return LowerVASTART(Op, DAG, Subtarget);
7852 return LowerVAARG(Op, DAG, Subtarget);
7855 return LowerVACOPY(Op, DAG, Subtarget);
7857 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7858 case ISD::DYNAMIC_STACKALLOC:
7859 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7861 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7862 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7864 case ISD::LOAD: return LowerLOAD(Op, DAG);
7865 case ISD::STORE: return LowerSTORE(Op, DAG);
7866 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7867 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7868 case ISD::FP_TO_UINT:
7869 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7871 case ISD::UINT_TO_FP:
7872 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7873 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7875 // Lower 64-bit shifts.
7876 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7877 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7878 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7880 // Vector-related lowering.
7881 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7882 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7883 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7884 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7885 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7886 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7887 case ISD::MUL: return LowerMUL(Op, DAG);
7889 // For counter-based loop handling.
7890 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7892 // Frame & Return address.
7893 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7894 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7898 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7899 SmallVectorImpl<SDValue>&Results,
7900 SelectionDAG &DAG) const {
7902 switch (N->getOpcode()) {
7904 llvm_unreachable("Do not know how to custom type legalize this operation!");
7905 case ISD::READCYCLECOUNTER: {
7906 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7907 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7909 Results.push_back(RTB);
7910 Results.push_back(RTB.getValue(1));
7911 Results.push_back(RTB.getValue(2));
7914 case ISD::INTRINSIC_W_CHAIN: {
7915 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7916 Intrinsic::ppc_is_decremented_ctr_nonzero)
7919 assert(N->getValueType(0) == MVT::i1 &&
7920 "Unexpected result type for CTR decrement intrinsic");
7921 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
7922 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7923 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7926 Results.push_back(NewInt);
7927 Results.push_back(NewInt.getValue(1));
7931 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7934 EVT VT = N->getValueType(0);
7936 if (VT == MVT::i64) {
7937 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7939 Results.push_back(NewNode);
7940 Results.push_back(NewNode.getValue(1));
7944 case ISD::FP_ROUND_INREG: {
7945 assert(N->getValueType(0) == MVT::ppcf128);
7946 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7947 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7948 MVT::f64, N->getOperand(0),
7949 DAG.getIntPtrConstant(0, dl));
7950 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7951 MVT::f64, N->getOperand(0),
7952 DAG.getIntPtrConstant(1, dl));
7954 // Add the two halves of the long double in round-to-zero mode.
7955 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
7957 // We know the low half is about to be thrown away, so just use something
7959 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
7963 case ISD::FP_TO_SINT:
7964 case ISD::FP_TO_UINT:
7965 // LowerFP_TO_INT() can only handle f32 and f64.
7966 if (N->getOperand(0).getValueType() == MVT::ppcf128)
7968 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
7974 //===----------------------------------------------------------------------===//
7975 // Other Lowering Code
7976 //===----------------------------------------------------------------------===//
7978 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
7979 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7980 Function *Func = Intrinsic::getDeclaration(M, Id);
7981 return Builder.CreateCall(Func, {});
7984 // The mappings for emitLeading/TrailingFence is taken from
7985 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
7986 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
7987 AtomicOrdering Ord, bool IsStore,
7988 bool IsLoad) const {
7989 if (Ord == SequentiallyConsistent)
7990 return callIntrinsic(Builder, Intrinsic::ppc_sync);
7991 if (isAtLeastRelease(Ord))
7992 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7996 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
7997 AtomicOrdering Ord, bool IsStore,
7998 bool IsLoad) const {
7999 if (IsLoad && isAtLeastAcquire(Ord))
8000 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8001 // FIXME: this is too conservative, a dependent branch + isync is enough.
8002 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8003 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8004 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8009 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8010 unsigned AtomicSize,
8011 unsigned BinOpcode) const {
8012 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8013 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8015 auto LoadMnemonic = PPC::LDARX;
8016 auto StoreMnemonic = PPC::STDCX;
8017 switch (AtomicSize) {
8019 llvm_unreachable("Unexpected size of atomic entity");
8021 LoadMnemonic = PPC::LBARX;
8022 StoreMnemonic = PPC::STBCX;
8023 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8026 LoadMnemonic = PPC::LHARX;
8027 StoreMnemonic = PPC::STHCX;
8028 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8031 LoadMnemonic = PPC::LWARX;
8032 StoreMnemonic = PPC::STWCX;
8035 LoadMnemonic = PPC::LDARX;
8036 StoreMnemonic = PPC::STDCX;
8040 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8041 MachineFunction *F = BB->getParent();
8042 MachineFunction::iterator It = BB;
8045 unsigned dest = MI->getOperand(0).getReg();
8046 unsigned ptrA = MI->getOperand(1).getReg();
8047 unsigned ptrB = MI->getOperand(2).getReg();
8048 unsigned incr = MI->getOperand(3).getReg();
8049 DebugLoc dl = MI->getDebugLoc();
8051 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8052 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8053 F->insert(It, loopMBB);
8054 F->insert(It, exitMBB);
8055 exitMBB->splice(exitMBB->begin(), BB,
8056 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8057 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8059 MachineRegisterInfo &RegInfo = F->getRegInfo();
8060 unsigned TmpReg = (!BinOpcode) ? incr :
8061 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8062 : &PPC::GPRCRegClass);
8066 // fallthrough --> loopMBB
8067 BB->addSuccessor(loopMBB);
8070 // l[wd]arx dest, ptr
8071 // add r0, dest, incr
8072 // st[wd]cx. r0, ptr
8074 // fallthrough --> exitMBB
8076 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8077 .addReg(ptrA).addReg(ptrB);
8079 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8080 BuildMI(BB, dl, TII->get(StoreMnemonic))
8081 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8082 BuildMI(BB, dl, TII->get(PPC::BCC))
8083 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8084 BB->addSuccessor(loopMBB);
8085 BB->addSuccessor(exitMBB);
8094 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8095 MachineBasicBlock *BB,
8096 bool is8bit, // operation
8097 unsigned BinOpcode) const {
8098 // If we support part-word atomic mnemonics, just use them
8099 if (Subtarget.hasPartwordAtomics())
8100 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8102 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8103 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8104 // In 64 bit mode we have to use 64 bits for addresses, even though the
8105 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8106 // registers without caring whether they're 32 or 64, but here we're
8107 // doing actual arithmetic on the addresses.
8108 bool is64bit = Subtarget.isPPC64();
8109 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8111 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8112 MachineFunction *F = BB->getParent();
8113 MachineFunction::iterator It = BB;
8116 unsigned dest = MI->getOperand(0).getReg();
8117 unsigned ptrA = MI->getOperand(1).getReg();
8118 unsigned ptrB = MI->getOperand(2).getReg();
8119 unsigned incr = MI->getOperand(3).getReg();
8120 DebugLoc dl = MI->getDebugLoc();
8122 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8123 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8124 F->insert(It, loopMBB);
8125 F->insert(It, exitMBB);
8126 exitMBB->splice(exitMBB->begin(), BB,
8127 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8128 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8130 MachineRegisterInfo &RegInfo = F->getRegInfo();
8131 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8132 : &PPC::GPRCRegClass;
8133 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8134 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8135 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8136 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8137 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8138 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8139 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8140 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8141 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8142 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8143 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8145 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8149 // fallthrough --> loopMBB
8150 BB->addSuccessor(loopMBB);
8152 // The 4-byte load must be aligned, while a char or short may be
8153 // anywhere in the word. Hence all this nasty bookkeeping code.
8154 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8155 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8156 // xori shift, shift1, 24 [16]
8157 // rlwinm ptr, ptr1, 0, 0, 29
8158 // slw incr2, incr, shift
8159 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8160 // slw mask, mask2, shift
8162 // lwarx tmpDest, ptr
8163 // add tmp, tmpDest, incr2
8164 // andc tmp2, tmpDest, mask
8165 // and tmp3, tmp, mask
8166 // or tmp4, tmp3, tmp2
8169 // fallthrough --> exitMBB
8170 // srw dest, tmpDest, shift
8171 if (ptrA != ZeroReg) {
8172 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8173 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8174 .addReg(ptrA).addReg(ptrB);
8178 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8179 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8180 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8181 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8183 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8184 .addReg(Ptr1Reg).addImm(0).addImm(61);
8186 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8187 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8188 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8189 .addReg(incr).addReg(ShiftReg);
8191 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8193 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8194 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8196 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8197 .addReg(Mask2Reg).addReg(ShiftReg);
8200 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8201 .addReg(ZeroReg).addReg(PtrReg);
8203 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8204 .addReg(Incr2Reg).addReg(TmpDestReg);
8205 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8206 .addReg(TmpDestReg).addReg(MaskReg);
8207 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8208 .addReg(TmpReg).addReg(MaskReg);
8209 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8210 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8211 BuildMI(BB, dl, TII->get(PPC::STWCX))
8212 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8213 BuildMI(BB, dl, TII->get(PPC::BCC))
8214 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8215 BB->addSuccessor(loopMBB);
8216 BB->addSuccessor(exitMBB);
8221 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8226 llvm::MachineBasicBlock*
8227 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8228 MachineBasicBlock *MBB) const {
8229 DebugLoc DL = MI->getDebugLoc();
8230 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8232 MachineFunction *MF = MBB->getParent();
8233 MachineRegisterInfo &MRI = MF->getRegInfo();
8235 const BasicBlock *BB = MBB->getBasicBlock();
8236 MachineFunction::iterator I = MBB;
8240 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8241 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8243 unsigned DstReg = MI->getOperand(0).getReg();
8244 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8245 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8246 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8247 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8249 MVT PVT = getPointerTy();
8250 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8251 "Invalid Pointer Size!");
8252 // For v = setjmp(buf), we generate
8255 // SjLjSetup mainMBB
8261 // buf[LabelOffset] = LR
8265 // v = phi(main, restore)
8268 MachineBasicBlock *thisMBB = MBB;
8269 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8270 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8271 MF->insert(I, mainMBB);
8272 MF->insert(I, sinkMBB);
8274 MachineInstrBuilder MIB;
8276 // Transfer the remainder of BB and its successor edges to sinkMBB.
8277 sinkMBB->splice(sinkMBB->begin(), MBB,
8278 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8279 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8281 // Note that the structure of the jmp_buf used here is not compatible
8282 // with that used by libc, and is not designed to be. Specifically, it
8283 // stores only those 'reserved' registers that LLVM does not otherwise
8284 // understand how to spill. Also, by convention, by the time this
8285 // intrinsic is called, Clang has already stored the frame address in the
8286 // first slot of the buffer and stack address in the third. Following the
8287 // X86 target code, we'll store the jump address in the second slot. We also
8288 // need to save the TOC pointer (R2) to handle jumps between shared
8289 // libraries, and that will be stored in the fourth slot. The thread
8290 // identifier (R13) is not affected.
8293 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8294 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8295 const int64_t BPOffset = 4 * PVT.getStoreSize();
8297 // Prepare IP either in reg.
8298 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8299 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8300 unsigned BufReg = MI->getOperand(1).getReg();
8302 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8303 setUsesTOCBasePtr(*MBB->getParent());
8304 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8308 MIB.setMemRefs(MMOBegin, MMOEnd);
8311 // Naked functions never have a base pointer, and so we use r1. For all
8312 // other functions, this decision must be delayed until during PEI.
8314 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8315 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8317 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8319 MIB = BuildMI(*thisMBB, MI, DL,
8320 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8324 MIB.setMemRefs(MMOBegin, MMOEnd);
8327 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8328 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8329 MIB.addRegMask(TRI->getNoPreservedMask());
8331 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8333 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8335 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8337 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8338 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8343 BuildMI(mainMBB, DL,
8344 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8347 if (Subtarget.isPPC64()) {
8348 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8350 .addImm(LabelOffset)
8353 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8355 .addImm(LabelOffset)
8359 MIB.setMemRefs(MMOBegin, MMOEnd);
8361 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8362 mainMBB->addSuccessor(sinkMBB);
8365 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8366 TII->get(PPC::PHI), DstReg)
8367 .addReg(mainDstReg).addMBB(mainMBB)
8368 .addReg(restoreDstReg).addMBB(thisMBB);
8370 MI->eraseFromParent();
8375 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8376 MachineBasicBlock *MBB) const {
8377 DebugLoc DL = MI->getDebugLoc();
8378 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8380 MachineFunction *MF = MBB->getParent();
8381 MachineRegisterInfo &MRI = MF->getRegInfo();
8384 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8385 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8387 MVT PVT = getPointerTy();
8388 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8389 "Invalid Pointer Size!");
8391 const TargetRegisterClass *RC =
8392 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8393 unsigned Tmp = MRI.createVirtualRegister(RC);
8394 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8395 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8396 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8400 : (Subtarget.isSVR4ABI() &&
8401 MF->getTarget().getRelocationModel() == Reloc::PIC_
8405 MachineInstrBuilder MIB;
8407 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8408 const int64_t SPOffset = 2 * PVT.getStoreSize();
8409 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8410 const int64_t BPOffset = 4 * PVT.getStoreSize();
8412 unsigned BufReg = MI->getOperand(0).getReg();
8414 // Reload FP (the jumped-to function may not have had a
8415 // frame pointer, and if so, then its r31 will be restored
8417 if (PVT == MVT::i64) {
8418 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8422 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8426 MIB.setMemRefs(MMOBegin, MMOEnd);
8429 if (PVT == MVT::i64) {
8430 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8431 .addImm(LabelOffset)
8434 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8435 .addImm(LabelOffset)
8438 MIB.setMemRefs(MMOBegin, MMOEnd);
8441 if (PVT == MVT::i64) {
8442 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8446 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8450 MIB.setMemRefs(MMOBegin, MMOEnd);
8453 if (PVT == MVT::i64) {
8454 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8458 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8462 MIB.setMemRefs(MMOBegin, MMOEnd);
8465 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8466 setUsesTOCBasePtr(*MBB->getParent());
8467 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8471 MIB.setMemRefs(MMOBegin, MMOEnd);
8475 BuildMI(*MBB, MI, DL,
8476 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8477 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8479 MI->eraseFromParent();
8484 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8485 MachineBasicBlock *BB) const {
8486 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8487 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8488 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8489 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8490 // Call lowering should have added an r2 operand to indicate a dependence
8491 // on the TOC base pointer value. It can't however, because there is no
8492 // way to mark the dependence as implicit there, and so the stackmap code
8493 // will confuse it with a regular operand. Instead, add the dependence
8495 setUsesTOCBasePtr(*BB->getParent());
8496 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8499 return emitPatchPoint(MI, BB);
8502 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8503 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8504 return emitEHSjLjSetJmp(MI, BB);
8505 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8506 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8507 return emitEHSjLjLongJmp(MI, BB);
8510 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8512 // To "insert" these instructions we actually have to insert their
8513 // control-flow patterns.
8514 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8515 MachineFunction::iterator It = BB;
8518 MachineFunction *F = BB->getParent();
8520 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8521 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8522 MI->getOpcode() == PPC::SELECT_I4 ||
8523 MI->getOpcode() == PPC::SELECT_I8)) {
8524 SmallVector<MachineOperand, 2> Cond;
8525 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8526 MI->getOpcode() == PPC::SELECT_CC_I8)
8527 Cond.push_back(MI->getOperand(4));
8529 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8530 Cond.push_back(MI->getOperand(1));
8532 DebugLoc dl = MI->getDebugLoc();
8533 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8534 Cond, MI->getOperand(2).getReg(),
8535 MI->getOperand(3).getReg());
8536 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8537 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8538 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8539 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8540 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8541 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8542 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8543 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8544 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8545 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8546 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8547 MI->getOpcode() == PPC::SELECT_I4 ||
8548 MI->getOpcode() == PPC::SELECT_I8 ||
8549 MI->getOpcode() == PPC::SELECT_F4 ||
8550 MI->getOpcode() == PPC::SELECT_F8 ||
8551 MI->getOpcode() == PPC::SELECT_QFRC ||
8552 MI->getOpcode() == PPC::SELECT_QSRC ||
8553 MI->getOpcode() == PPC::SELECT_QBRC ||
8554 MI->getOpcode() == PPC::SELECT_VRRC ||
8555 MI->getOpcode() == PPC::SELECT_VSFRC ||
8556 MI->getOpcode() == PPC::SELECT_VSSRC ||
8557 MI->getOpcode() == PPC::SELECT_VSRC) {
8558 // The incoming instruction knows the destination vreg to set, the
8559 // condition code register to branch on, the true/false values to
8560 // select between, and a branch opcode to use.
8565 // cmpTY ccX, r1, r2
8567 // fallthrough --> copy0MBB
8568 MachineBasicBlock *thisMBB = BB;
8569 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8570 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8571 DebugLoc dl = MI->getDebugLoc();
8572 F->insert(It, copy0MBB);
8573 F->insert(It, sinkMBB);
8575 // Transfer the remainder of BB and its successor edges to sinkMBB.
8576 sinkMBB->splice(sinkMBB->begin(), BB,
8577 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8578 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8580 // Next, add the true and fallthrough blocks as its successors.
8581 BB->addSuccessor(copy0MBB);
8582 BB->addSuccessor(sinkMBB);
8584 if (MI->getOpcode() == PPC::SELECT_I4 ||
8585 MI->getOpcode() == PPC::SELECT_I8 ||
8586 MI->getOpcode() == PPC::SELECT_F4 ||
8587 MI->getOpcode() == PPC::SELECT_F8 ||
8588 MI->getOpcode() == PPC::SELECT_QFRC ||
8589 MI->getOpcode() == PPC::SELECT_QSRC ||
8590 MI->getOpcode() == PPC::SELECT_QBRC ||
8591 MI->getOpcode() == PPC::SELECT_VRRC ||
8592 MI->getOpcode() == PPC::SELECT_VSFRC ||
8593 MI->getOpcode() == PPC::SELECT_VSSRC ||
8594 MI->getOpcode() == PPC::SELECT_VSRC) {
8595 BuildMI(BB, dl, TII->get(PPC::BC))
8596 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8598 unsigned SelectPred = MI->getOperand(4).getImm();
8599 BuildMI(BB, dl, TII->get(PPC::BCC))
8600 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8604 // %FalseValue = ...
8605 // # fallthrough to sinkMBB
8608 // Update machine-CFG edges
8609 BB->addSuccessor(sinkMBB);
8612 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8615 BuildMI(*BB, BB->begin(), dl,
8616 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8617 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8618 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8619 } else if (MI->getOpcode() == PPC::ReadTB) {
8620 // To read the 64-bit time-base register on a 32-bit target, we read the
8621 // two halves. Should the counter have wrapped while it was being read, we
8622 // need to try again.
8625 // mfspr Rx,TBU # load from TBU
8626 // mfspr Ry,TB # load from TB
8627 // mfspr Rz,TBU # load from TBU
8628 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8629 // bne readLoop # branch if they're not equal
8632 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8633 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8634 DebugLoc dl = MI->getDebugLoc();
8635 F->insert(It, readMBB);
8636 F->insert(It, sinkMBB);
8638 // Transfer the remainder of BB and its successor edges to sinkMBB.
8639 sinkMBB->splice(sinkMBB->begin(), BB,
8640 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8641 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8643 BB->addSuccessor(readMBB);
8646 MachineRegisterInfo &RegInfo = F->getRegInfo();
8647 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8648 unsigned LoReg = MI->getOperand(0).getReg();
8649 unsigned HiReg = MI->getOperand(1).getReg();
8651 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8652 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8653 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8655 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8657 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8658 .addReg(HiReg).addReg(ReadAgainReg);
8659 BuildMI(BB, dl, TII->get(PPC::BCC))
8660 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8662 BB->addSuccessor(readMBB);
8663 BB->addSuccessor(sinkMBB);
8665 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8666 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8667 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8668 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8669 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8670 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8671 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8672 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8674 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8675 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8676 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8677 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8678 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8679 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8680 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8681 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8683 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8684 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8685 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8686 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8687 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8688 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8689 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8690 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8692 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8693 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8694 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8695 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8696 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8697 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8698 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8699 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8701 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8702 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8703 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8704 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8705 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8706 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8707 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8708 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8710 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8711 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8712 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8713 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8714 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8715 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8716 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8717 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8719 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8720 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8721 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8722 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8723 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8724 BB = EmitAtomicBinary(MI, BB, 4, 0);
8725 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8726 BB = EmitAtomicBinary(MI, BB, 8, 0);
8728 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8729 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8730 (Subtarget.hasPartwordAtomics() &&
8731 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8732 (Subtarget.hasPartwordAtomics() &&
8733 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8734 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8736 auto LoadMnemonic = PPC::LDARX;
8737 auto StoreMnemonic = PPC::STDCX;
8738 switch(MI->getOpcode()) {
8740 llvm_unreachable("Compare and swap of unknown size");
8741 case PPC::ATOMIC_CMP_SWAP_I8:
8742 LoadMnemonic = PPC::LBARX;
8743 StoreMnemonic = PPC::STBCX;
8744 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8746 case PPC::ATOMIC_CMP_SWAP_I16:
8747 LoadMnemonic = PPC::LHARX;
8748 StoreMnemonic = PPC::STHCX;
8749 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8751 case PPC::ATOMIC_CMP_SWAP_I32:
8752 LoadMnemonic = PPC::LWARX;
8753 StoreMnemonic = PPC::STWCX;
8755 case PPC::ATOMIC_CMP_SWAP_I64:
8756 LoadMnemonic = PPC::LDARX;
8757 StoreMnemonic = PPC::STDCX;
8760 unsigned dest = MI->getOperand(0).getReg();
8761 unsigned ptrA = MI->getOperand(1).getReg();
8762 unsigned ptrB = MI->getOperand(2).getReg();
8763 unsigned oldval = MI->getOperand(3).getReg();
8764 unsigned newval = MI->getOperand(4).getReg();
8765 DebugLoc dl = MI->getDebugLoc();
8767 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8768 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8769 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8770 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8771 F->insert(It, loop1MBB);
8772 F->insert(It, loop2MBB);
8773 F->insert(It, midMBB);
8774 F->insert(It, exitMBB);
8775 exitMBB->splice(exitMBB->begin(), BB,
8776 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8777 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8781 // fallthrough --> loopMBB
8782 BB->addSuccessor(loop1MBB);
8785 // l[bhwd]arx dest, ptr
8786 // cmp[wd] dest, oldval
8789 // st[bhwd]cx. newval, ptr
8793 // st[bhwd]cx. dest, ptr
8796 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8797 .addReg(ptrA).addReg(ptrB);
8798 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8799 .addReg(oldval).addReg(dest);
8800 BuildMI(BB, dl, TII->get(PPC::BCC))
8801 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8802 BB->addSuccessor(loop2MBB);
8803 BB->addSuccessor(midMBB);
8806 BuildMI(BB, dl, TII->get(StoreMnemonic))
8807 .addReg(newval).addReg(ptrA).addReg(ptrB);
8808 BuildMI(BB, dl, TII->get(PPC::BCC))
8809 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8810 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8811 BB->addSuccessor(loop1MBB);
8812 BB->addSuccessor(exitMBB);
8815 BuildMI(BB, dl, TII->get(StoreMnemonic))
8816 .addReg(dest).addReg(ptrA).addReg(ptrB);
8817 BB->addSuccessor(exitMBB);
8822 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8823 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8824 // We must use 64-bit registers for addresses when targeting 64-bit,
8825 // since we're actually doing arithmetic on them. Other registers
8827 bool is64bit = Subtarget.isPPC64();
8828 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8830 unsigned dest = MI->getOperand(0).getReg();
8831 unsigned ptrA = MI->getOperand(1).getReg();
8832 unsigned ptrB = MI->getOperand(2).getReg();
8833 unsigned oldval = MI->getOperand(3).getReg();
8834 unsigned newval = MI->getOperand(4).getReg();
8835 DebugLoc dl = MI->getDebugLoc();
8837 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8838 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8839 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8840 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8841 F->insert(It, loop1MBB);
8842 F->insert(It, loop2MBB);
8843 F->insert(It, midMBB);
8844 F->insert(It, exitMBB);
8845 exitMBB->splice(exitMBB->begin(), BB,
8846 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8847 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8849 MachineRegisterInfo &RegInfo = F->getRegInfo();
8850 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8851 : &PPC::GPRCRegClass;
8852 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8853 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8854 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8855 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8856 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8857 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8858 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8859 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8860 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8861 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8862 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8863 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8864 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8866 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8867 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8870 // fallthrough --> loopMBB
8871 BB->addSuccessor(loop1MBB);
8873 // The 4-byte load must be aligned, while a char or short may be
8874 // anywhere in the word. Hence all this nasty bookkeeping code.
8875 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8876 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8877 // xori shift, shift1, 24 [16]
8878 // rlwinm ptr, ptr1, 0, 0, 29
8879 // slw newval2, newval, shift
8880 // slw oldval2, oldval,shift
8881 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8882 // slw mask, mask2, shift
8883 // and newval3, newval2, mask
8884 // and oldval3, oldval2, mask
8886 // lwarx tmpDest, ptr
8887 // and tmp, tmpDest, mask
8888 // cmpw tmp, oldval3
8891 // andc tmp2, tmpDest, mask
8892 // or tmp4, tmp2, newval3
8897 // stwcx. tmpDest, ptr
8899 // srw dest, tmpDest, shift
8900 if (ptrA != ZeroReg) {
8901 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8902 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8903 .addReg(ptrA).addReg(ptrB);
8907 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8908 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8909 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8910 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8912 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8913 .addReg(Ptr1Reg).addImm(0).addImm(61);
8915 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8916 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8917 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8918 .addReg(newval).addReg(ShiftReg);
8919 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8920 .addReg(oldval).addReg(ShiftReg);
8922 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8924 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8925 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8926 .addReg(Mask3Reg).addImm(65535);
8928 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8929 .addReg(Mask2Reg).addReg(ShiftReg);
8930 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8931 .addReg(NewVal2Reg).addReg(MaskReg);
8932 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8933 .addReg(OldVal2Reg).addReg(MaskReg);
8936 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8937 .addReg(ZeroReg).addReg(PtrReg);
8938 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8939 .addReg(TmpDestReg).addReg(MaskReg);
8940 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8941 .addReg(TmpReg).addReg(OldVal3Reg);
8942 BuildMI(BB, dl, TII->get(PPC::BCC))
8943 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8944 BB->addSuccessor(loop2MBB);
8945 BB->addSuccessor(midMBB);
8948 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8949 .addReg(TmpDestReg).addReg(MaskReg);
8950 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8951 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8952 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8953 .addReg(ZeroReg).addReg(PtrReg);
8954 BuildMI(BB, dl, TII->get(PPC::BCC))
8955 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8956 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8957 BB->addSuccessor(loop1MBB);
8958 BB->addSuccessor(exitMBB);
8961 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
8962 .addReg(ZeroReg).addReg(PtrReg);
8963 BB->addSuccessor(exitMBB);
8968 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
8970 } else if (MI->getOpcode() == PPC::FADDrtz) {
8971 // This pseudo performs an FADD with rounding mode temporarily forced
8972 // to round-to-zero. We emit this via custom inserter since the FPSCR
8973 // is not modeled at the SelectionDAG level.
8974 unsigned Dest = MI->getOperand(0).getReg();
8975 unsigned Src1 = MI->getOperand(1).getReg();
8976 unsigned Src2 = MI->getOperand(2).getReg();
8977 DebugLoc dl = MI->getDebugLoc();
8979 MachineRegisterInfo &RegInfo = F->getRegInfo();
8980 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
8982 // Save FPSCR value.
8983 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
8985 // Set rounding mode to round-to-zero.
8986 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
8987 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
8989 // Perform addition.
8990 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
8992 // Restore FPSCR value.
8993 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
8994 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8995 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
8996 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8997 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
8998 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8999 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9000 PPC::ANDIo8 : PPC::ANDIo;
9001 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9002 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9004 MachineRegisterInfo &RegInfo = F->getRegInfo();
9005 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9006 &PPC::GPRCRegClass :
9007 &PPC::G8RCRegClass);
9009 DebugLoc dl = MI->getDebugLoc();
9010 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9011 .addReg(MI->getOperand(1).getReg()).addImm(1);
9012 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9013 MI->getOperand(0).getReg())
9014 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9015 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9016 DebugLoc Dl = MI->getDebugLoc();
9017 MachineRegisterInfo &RegInfo = F->getRegInfo();
9018 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9019 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9022 llvm_unreachable("Unexpected instr type to insert");
9025 MI->eraseFromParent(); // The pseudo instruction is gone now.
9029 //===----------------------------------------------------------------------===//
9030 // Target Optimization Hooks
9031 //===----------------------------------------------------------------------===//
9033 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9034 DAGCombinerInfo &DCI,
9035 unsigned &RefinementSteps,
9036 bool &UseOneConstNR) const {
9037 EVT VT = Operand.getValueType();
9038 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9039 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9040 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9041 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9042 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9043 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9044 // Convergence is quadratic, so we essentially double the number of digits
9045 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9046 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9047 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9048 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9049 if (VT.getScalarType() == MVT::f64)
9051 UseOneConstNR = true;
9052 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9057 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9058 DAGCombinerInfo &DCI,
9059 unsigned &RefinementSteps) const {
9060 EVT VT = Operand.getValueType();
9061 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9062 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9063 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9064 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9065 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9066 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9067 // Convergence is quadratic, so we essentially double the number of digits
9068 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9069 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9070 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9071 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9072 if (VT.getScalarType() == MVT::f64)
9074 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9079 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9080 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9081 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9082 // enabled for division), this functionality is redundant with the default
9083 // combiner logic (once the division -> reciprocal/multiply transformation
9084 // has taken place). As a result, this matters more for older cores than for
9087 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9088 // reciprocal if there are two or more FDIVs (for embedded cores with only
9089 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9090 switch (Subtarget.getDarwinDirective()) {
9092 return NumUsers > 2;
9095 case PPC::DIR_E500mc:
9096 case PPC::DIR_E5500:
9097 return NumUsers > 1;
9101 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9102 unsigned Bytes, int Dist,
9103 SelectionDAG &DAG) {
9104 if (VT.getSizeInBits() / 8 != Bytes)
9107 SDValue BaseLoc = Base->getBasePtr();
9108 if (Loc.getOpcode() == ISD::FrameIndex) {
9109 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9111 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9112 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9113 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9114 int FS = MFI->getObjectSize(FI);
9115 int BFS = MFI->getObjectSize(BFI);
9116 if (FS != BFS || FS != (int)Bytes) return false;
9117 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9121 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
9122 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
9125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9126 const GlobalValue *GV1 = nullptr;
9127 const GlobalValue *GV2 = nullptr;
9128 int64_t Offset1 = 0;
9129 int64_t Offset2 = 0;
9130 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9131 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9132 if (isGA1 && isGA2 && GV1 == GV2)
9133 return Offset1 == (Offset2 + Dist*Bytes);
9137 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9138 // not enforce equality of the chain operands.
9139 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9140 unsigned Bytes, int Dist,
9141 SelectionDAG &DAG) {
9142 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9143 EVT VT = LS->getMemoryVT();
9144 SDValue Loc = LS->getBasePtr();
9145 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9148 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9150 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9151 default: return false;
9152 case Intrinsic::ppc_qpx_qvlfd:
9153 case Intrinsic::ppc_qpx_qvlfda:
9156 case Intrinsic::ppc_qpx_qvlfs:
9157 case Intrinsic::ppc_qpx_qvlfsa:
9160 case Intrinsic::ppc_qpx_qvlfcd:
9161 case Intrinsic::ppc_qpx_qvlfcda:
9164 case Intrinsic::ppc_qpx_qvlfcs:
9165 case Intrinsic::ppc_qpx_qvlfcsa:
9168 case Intrinsic::ppc_qpx_qvlfiwa:
9169 case Intrinsic::ppc_qpx_qvlfiwz:
9170 case Intrinsic::ppc_altivec_lvx:
9171 case Intrinsic::ppc_altivec_lvxl:
9172 case Intrinsic::ppc_vsx_lxvw4x:
9175 case Intrinsic::ppc_vsx_lxvd2x:
9178 case Intrinsic::ppc_altivec_lvebx:
9181 case Intrinsic::ppc_altivec_lvehx:
9184 case Intrinsic::ppc_altivec_lvewx:
9189 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9192 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9194 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9195 default: return false;
9196 case Intrinsic::ppc_qpx_qvstfd:
9197 case Intrinsic::ppc_qpx_qvstfda:
9200 case Intrinsic::ppc_qpx_qvstfs:
9201 case Intrinsic::ppc_qpx_qvstfsa:
9204 case Intrinsic::ppc_qpx_qvstfcd:
9205 case Intrinsic::ppc_qpx_qvstfcda:
9208 case Intrinsic::ppc_qpx_qvstfcs:
9209 case Intrinsic::ppc_qpx_qvstfcsa:
9212 case Intrinsic::ppc_qpx_qvstfiw:
9213 case Intrinsic::ppc_qpx_qvstfiwa:
9214 case Intrinsic::ppc_altivec_stvx:
9215 case Intrinsic::ppc_altivec_stvxl:
9216 case Intrinsic::ppc_vsx_stxvw4x:
9219 case Intrinsic::ppc_vsx_stxvd2x:
9222 case Intrinsic::ppc_altivec_stvebx:
9225 case Intrinsic::ppc_altivec_stvehx:
9228 case Intrinsic::ppc_altivec_stvewx:
9233 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9239 // Return true is there is a nearyby consecutive load to the one provided
9240 // (regardless of alignment). We search up and down the chain, looking though
9241 // token factors and other loads (but nothing else). As a result, a true result
9242 // indicates that it is safe to create a new consecutive load adjacent to the
9244 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9245 SDValue Chain = LD->getChain();
9246 EVT VT = LD->getMemoryVT();
9248 SmallSet<SDNode *, 16> LoadRoots;
9249 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9250 SmallSet<SDNode *, 16> Visited;
9252 // First, search up the chain, branching to follow all token-factor operands.
9253 // If we find a consecutive load, then we're done, otherwise, record all
9254 // nodes just above the top-level loads and token factors.
9255 while (!Queue.empty()) {
9256 SDNode *ChainNext = Queue.pop_back_val();
9257 if (!Visited.insert(ChainNext).second)
9260 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9261 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9264 if (!Visited.count(ChainLD->getChain().getNode()))
9265 Queue.push_back(ChainLD->getChain().getNode());
9266 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9267 for (const SDUse &O : ChainNext->ops())
9268 if (!Visited.count(O.getNode()))
9269 Queue.push_back(O.getNode());
9271 LoadRoots.insert(ChainNext);
9274 // Second, search down the chain, starting from the top-level nodes recorded
9275 // in the first phase. These top-level nodes are the nodes just above all
9276 // loads and token factors. Starting with their uses, recursively look though
9277 // all loads (just the chain uses) and token factors to find a consecutive
9282 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9283 IE = LoadRoots.end(); I != IE; ++I) {
9284 Queue.push_back(*I);
9286 while (!Queue.empty()) {
9287 SDNode *LoadRoot = Queue.pop_back_val();
9288 if (!Visited.insert(LoadRoot).second)
9291 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9292 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9295 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9296 UE = LoadRoot->use_end(); UI != UE; ++UI)
9297 if (((isa<MemSDNode>(*UI) &&
9298 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9299 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9300 Queue.push_back(*UI);
9307 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9308 DAGCombinerInfo &DCI) const {
9309 SelectionDAG &DAG = DCI.DAG;
9312 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9313 // If we're tracking CR bits, we need to be careful that we don't have:
9314 // trunc(binary-ops(zext(x), zext(y)))
9316 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9317 // such that we're unnecessarily moving things into GPRs when it would be
9318 // better to keep them in CR bits.
9320 // Note that trunc here can be an actual i1 trunc, or can be the effective
9321 // truncation that comes from a setcc or select_cc.
9322 if (N->getOpcode() == ISD::TRUNCATE &&
9323 N->getValueType(0) != MVT::i1)
9326 if (N->getOperand(0).getValueType() != MVT::i32 &&
9327 N->getOperand(0).getValueType() != MVT::i64)
9330 if (N->getOpcode() == ISD::SETCC ||
9331 N->getOpcode() == ISD::SELECT_CC) {
9332 // If we're looking at a comparison, then we need to make sure that the
9333 // high bits (all except for the first) don't matter the result.
9335 cast<CondCodeSDNode>(N->getOperand(
9336 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9337 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9339 if (ISD::isSignedIntSetCC(CC)) {
9340 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9341 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9343 } else if (ISD::isUnsignedIntSetCC(CC)) {
9344 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9345 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9346 !DAG.MaskedValueIsZero(N->getOperand(1),
9347 APInt::getHighBitsSet(OpBits, OpBits-1)))
9350 // This is neither a signed nor an unsigned comparison, just make sure
9351 // that the high bits are equal.
9352 APInt Op1Zero, Op1One;
9353 APInt Op2Zero, Op2One;
9354 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9355 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9357 // We don't really care about what is known about the first bit (if
9358 // anything), so clear it in all masks prior to comparing them.
9359 Op1Zero.clearBit(0); Op1One.clearBit(0);
9360 Op2Zero.clearBit(0); Op2One.clearBit(0);
9362 if (Op1Zero != Op2Zero || Op1One != Op2One)
9367 // We now know that the higher-order bits are irrelevant, we just need to
9368 // make sure that all of the intermediate operations are bit operations, and
9369 // all inputs are extensions.
9370 if (N->getOperand(0).getOpcode() != ISD::AND &&
9371 N->getOperand(0).getOpcode() != ISD::OR &&
9372 N->getOperand(0).getOpcode() != ISD::XOR &&
9373 N->getOperand(0).getOpcode() != ISD::SELECT &&
9374 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9375 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9376 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9377 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9378 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9381 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9382 N->getOperand(1).getOpcode() != ISD::AND &&
9383 N->getOperand(1).getOpcode() != ISD::OR &&
9384 N->getOperand(1).getOpcode() != ISD::XOR &&
9385 N->getOperand(1).getOpcode() != ISD::SELECT &&
9386 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9387 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9388 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9389 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9390 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9393 SmallVector<SDValue, 4> Inputs;
9394 SmallVector<SDValue, 8> BinOps, PromOps;
9395 SmallPtrSet<SDNode *, 16> Visited;
9397 for (unsigned i = 0; i < 2; ++i) {
9398 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9399 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9400 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9401 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9402 isa<ConstantSDNode>(N->getOperand(i)))
9403 Inputs.push_back(N->getOperand(i));
9405 BinOps.push_back(N->getOperand(i));
9407 if (N->getOpcode() == ISD::TRUNCATE)
9411 // Visit all inputs, collect all binary operations (and, or, xor and
9412 // select) that are all fed by extensions.
9413 while (!BinOps.empty()) {
9414 SDValue BinOp = BinOps.back();
9417 if (!Visited.insert(BinOp.getNode()).second)
9420 PromOps.push_back(BinOp);
9422 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9423 // The condition of the select is not promoted.
9424 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9426 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9429 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9430 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9431 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9432 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9433 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9434 Inputs.push_back(BinOp.getOperand(i));
9435 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9436 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9437 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9438 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9439 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9440 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9441 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9442 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9443 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9444 BinOps.push_back(BinOp.getOperand(i));
9446 // We have an input that is not an extension or another binary
9447 // operation; we'll abort this transformation.
9453 // Make sure that this is a self-contained cluster of operations (which
9454 // is not quite the same thing as saying that everything has only one
9456 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9457 if (isa<ConstantSDNode>(Inputs[i]))
9460 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9461 UE = Inputs[i].getNode()->use_end();
9464 if (User != N && !Visited.count(User))
9467 // Make sure that we're not going to promote the non-output-value
9468 // operand(s) or SELECT or SELECT_CC.
9469 // FIXME: Although we could sometimes handle this, and it does occur in
9470 // practice that one of the condition inputs to the select is also one of
9471 // the outputs, we currently can't deal with this.
9472 if (User->getOpcode() == ISD::SELECT) {
9473 if (User->getOperand(0) == Inputs[i])
9475 } else if (User->getOpcode() == ISD::SELECT_CC) {
9476 if (User->getOperand(0) == Inputs[i] ||
9477 User->getOperand(1) == Inputs[i])
9483 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9484 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9485 UE = PromOps[i].getNode()->use_end();
9488 if (User != N && !Visited.count(User))
9491 // Make sure that we're not going to promote the non-output-value
9492 // operand(s) or SELECT or SELECT_CC.
9493 // FIXME: Although we could sometimes handle this, and it does occur in
9494 // practice that one of the condition inputs to the select is also one of
9495 // the outputs, we currently can't deal with this.
9496 if (User->getOpcode() == ISD::SELECT) {
9497 if (User->getOperand(0) == PromOps[i])
9499 } else if (User->getOpcode() == ISD::SELECT_CC) {
9500 if (User->getOperand(0) == PromOps[i] ||
9501 User->getOperand(1) == PromOps[i])
9507 // Replace all inputs with the extension operand.
9508 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9509 // Constants may have users outside the cluster of to-be-promoted nodes,
9510 // and so we need to replace those as we do the promotions.
9511 if (isa<ConstantSDNode>(Inputs[i]))
9514 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9517 // Replace all operations (these are all the same, but have a different
9518 // (i1) return type). DAG.getNode will validate that the types of
9519 // a binary operator match, so go through the list in reverse so that
9520 // we've likely promoted both operands first. Any intermediate truncations or
9521 // extensions disappear.
9522 while (!PromOps.empty()) {
9523 SDValue PromOp = PromOps.back();
9526 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9527 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9528 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9529 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9530 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9531 PromOp.getOperand(0).getValueType() != MVT::i1) {
9532 // The operand is not yet ready (see comment below).
9533 PromOps.insert(PromOps.begin(), PromOp);
9537 SDValue RepValue = PromOp.getOperand(0);
9538 if (isa<ConstantSDNode>(RepValue))
9539 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9541 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9546 switch (PromOp.getOpcode()) {
9547 default: C = 0; break;
9548 case ISD::SELECT: C = 1; break;
9549 case ISD::SELECT_CC: C = 2; break;
9552 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9553 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9554 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9555 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9556 // The to-be-promoted operands of this node have not yet been
9557 // promoted (this should be rare because we're going through the
9558 // list backward, but if one of the operands has several users in
9559 // this cluster of to-be-promoted nodes, it is possible).
9560 PromOps.insert(PromOps.begin(), PromOp);
9564 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9565 PromOp.getNode()->op_end());
9567 // If there are any constant inputs, make sure they're replaced now.
9568 for (unsigned i = 0; i < 2; ++i)
9569 if (isa<ConstantSDNode>(Ops[C+i]))
9570 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9572 DAG.ReplaceAllUsesOfValueWith(PromOp,
9573 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9576 // Now we're left with the initial truncation itself.
9577 if (N->getOpcode() == ISD::TRUNCATE)
9578 return N->getOperand(0);
9580 // Otherwise, this is a comparison. The operands to be compared have just
9581 // changed type (to i1), but everything else is the same.
9582 return SDValue(N, 0);
9585 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9586 DAGCombinerInfo &DCI) const {
9587 SelectionDAG &DAG = DCI.DAG;
9590 // If we're tracking CR bits, we need to be careful that we don't have:
9591 // zext(binary-ops(trunc(x), trunc(y)))
9593 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9594 // such that we're unnecessarily moving things into CR bits that can more
9595 // efficiently stay in GPRs. Note that if we're not certain that the high
9596 // bits are set as required by the final extension, we still may need to do
9597 // some masking to get the proper behavior.
9599 // This same functionality is important on PPC64 when dealing with
9600 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9601 // the return values of functions. Because it is so similar, it is handled
9604 if (N->getValueType(0) != MVT::i32 &&
9605 N->getValueType(0) != MVT::i64)
9608 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9609 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9612 if (N->getOperand(0).getOpcode() != ISD::AND &&
9613 N->getOperand(0).getOpcode() != ISD::OR &&
9614 N->getOperand(0).getOpcode() != ISD::XOR &&
9615 N->getOperand(0).getOpcode() != ISD::SELECT &&
9616 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9619 SmallVector<SDValue, 4> Inputs;
9620 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9621 SmallPtrSet<SDNode *, 16> Visited;
9623 // Visit all inputs, collect all binary operations (and, or, xor and
9624 // select) that are all fed by truncations.
9625 while (!BinOps.empty()) {
9626 SDValue BinOp = BinOps.back();
9629 if (!Visited.insert(BinOp.getNode()).second)
9632 PromOps.push_back(BinOp);
9634 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9635 // The condition of the select is not promoted.
9636 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9638 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9641 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9642 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9643 Inputs.push_back(BinOp.getOperand(i));
9644 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9645 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9646 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9647 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9648 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9649 BinOps.push_back(BinOp.getOperand(i));
9651 // We have an input that is not a truncation or another binary
9652 // operation; we'll abort this transformation.
9658 // The operands of a select that must be truncated when the select is
9659 // promoted because the operand is actually part of the to-be-promoted set.
9660 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9662 // Make sure that this is a self-contained cluster of operations (which
9663 // is not quite the same thing as saying that everything has only one
9665 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9666 if (isa<ConstantSDNode>(Inputs[i]))
9669 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9670 UE = Inputs[i].getNode()->use_end();
9673 if (User != N && !Visited.count(User))
9676 // If we're going to promote the non-output-value operand(s) or SELECT or
9677 // SELECT_CC, record them for truncation.
9678 if (User->getOpcode() == ISD::SELECT) {
9679 if (User->getOperand(0) == Inputs[i])
9680 SelectTruncOp[0].insert(std::make_pair(User,
9681 User->getOperand(0).getValueType()));
9682 } else if (User->getOpcode() == ISD::SELECT_CC) {
9683 if (User->getOperand(0) == Inputs[i])
9684 SelectTruncOp[0].insert(std::make_pair(User,
9685 User->getOperand(0).getValueType()));
9686 if (User->getOperand(1) == Inputs[i])
9687 SelectTruncOp[1].insert(std::make_pair(User,
9688 User->getOperand(1).getValueType()));
9693 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9694 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9695 UE = PromOps[i].getNode()->use_end();
9698 if (User != N && !Visited.count(User))
9701 // If we're going to promote the non-output-value operand(s) or SELECT or
9702 // SELECT_CC, record them for truncation.
9703 if (User->getOpcode() == ISD::SELECT) {
9704 if (User->getOperand(0) == PromOps[i])
9705 SelectTruncOp[0].insert(std::make_pair(User,
9706 User->getOperand(0).getValueType()));
9707 } else if (User->getOpcode() == ISD::SELECT_CC) {
9708 if (User->getOperand(0) == PromOps[i])
9709 SelectTruncOp[0].insert(std::make_pair(User,
9710 User->getOperand(0).getValueType()));
9711 if (User->getOperand(1) == PromOps[i])
9712 SelectTruncOp[1].insert(std::make_pair(User,
9713 User->getOperand(1).getValueType()));
9718 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9719 bool ReallyNeedsExt = false;
9720 if (N->getOpcode() != ISD::ANY_EXTEND) {
9721 // If all of the inputs are not already sign/zero extended, then
9722 // we'll still need to do that at the end.
9723 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9724 if (isa<ConstantSDNode>(Inputs[i]))
9728 Inputs[i].getOperand(0).getValueSizeInBits();
9729 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9731 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9732 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9733 APInt::getHighBitsSet(OpBits,
9734 OpBits-PromBits))) ||
9735 (N->getOpcode() == ISD::SIGN_EXTEND &&
9736 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9737 (OpBits-(PromBits-1)))) {
9738 ReallyNeedsExt = true;
9744 // Replace all inputs, either with the truncation operand, or a
9745 // truncation or extension to the final output type.
9746 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9747 // Constant inputs need to be replaced with the to-be-promoted nodes that
9748 // use them because they might have users outside of the cluster of
9750 if (isa<ConstantSDNode>(Inputs[i]))
9753 SDValue InSrc = Inputs[i].getOperand(0);
9754 if (Inputs[i].getValueType() == N->getValueType(0))
9755 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9756 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9757 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9758 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9759 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9760 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9761 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9763 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9764 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9767 // Replace all operations (these are all the same, but have a different
9768 // (promoted) return type). DAG.getNode will validate that the types of
9769 // a binary operator match, so go through the list in reverse so that
9770 // we've likely promoted both operands first.
9771 while (!PromOps.empty()) {
9772 SDValue PromOp = PromOps.back();
9776 switch (PromOp.getOpcode()) {
9777 default: C = 0; break;
9778 case ISD::SELECT: C = 1; break;
9779 case ISD::SELECT_CC: C = 2; break;
9782 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9783 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9784 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9785 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9786 // The to-be-promoted operands of this node have not yet been
9787 // promoted (this should be rare because we're going through the
9788 // list backward, but if one of the operands has several users in
9789 // this cluster of to-be-promoted nodes, it is possible).
9790 PromOps.insert(PromOps.begin(), PromOp);
9794 // For SELECT and SELECT_CC nodes, we do a similar check for any
9795 // to-be-promoted comparison inputs.
9796 if (PromOp.getOpcode() == ISD::SELECT ||
9797 PromOp.getOpcode() == ISD::SELECT_CC) {
9798 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9799 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9800 (SelectTruncOp[1].count(PromOp.getNode()) &&
9801 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9802 PromOps.insert(PromOps.begin(), PromOp);
9807 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9808 PromOp.getNode()->op_end());
9810 // If this node has constant inputs, then they'll need to be promoted here.
9811 for (unsigned i = 0; i < 2; ++i) {
9812 if (!isa<ConstantSDNode>(Ops[C+i]))
9814 if (Ops[C+i].getValueType() == N->getValueType(0))
9817 if (N->getOpcode() == ISD::SIGN_EXTEND)
9818 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9819 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9820 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9822 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9825 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9826 // truncate them again to the original value type.
9827 if (PromOp.getOpcode() == ISD::SELECT ||
9828 PromOp.getOpcode() == ISD::SELECT_CC) {
9829 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9830 if (SI0 != SelectTruncOp[0].end())
9831 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9832 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9833 if (SI1 != SelectTruncOp[1].end())
9834 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9837 DAG.ReplaceAllUsesOfValueWith(PromOp,
9838 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9841 // Now we're left with the initial extension itself.
9842 if (!ReallyNeedsExt)
9843 return N->getOperand(0);
9845 // To zero extend, just mask off everything except for the first bit (in the
9847 if (N->getOpcode() == ISD::ZERO_EXTEND)
9848 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9849 DAG.getConstant(APInt::getLowBitsSet(
9850 N->getValueSizeInBits(0), PromBits),
9851 dl, N->getValueType(0)));
9853 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9854 "Invalid extension type");
9855 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
9857 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9858 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9859 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9860 N->getOperand(0), ShiftCst), ShiftCst);
9863 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9864 DAGCombinerInfo &DCI) const {
9865 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9866 N->getOpcode() == ISD::UINT_TO_FP) &&
9867 "Need an int -> FP conversion node here");
9869 if (!Subtarget.has64BitSupport())
9872 SelectionDAG &DAG = DCI.DAG;
9876 // Don't handle ppc_fp128 here or i1 conversions.
9877 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9879 if (Op.getOperand(0).getValueType() == MVT::i1)
9882 // For i32 intermediate values, unfortunately, the conversion functions
9883 // leave the upper 32 bits of the value are undefined. Within the set of
9884 // scalar instructions, we have no method for zero- or sign-extending the
9885 // value. Thus, we cannot handle i32 intermediate values here.
9886 if (Op.getOperand(0).getValueType() == MVT::i32)
9889 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9890 "UINT_TO_FP is supported only with FPCVT");
9892 // If we have FCFIDS, then use it when converting to single-precision.
9893 // Otherwise, convert to double-precision and then round.
9894 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9895 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9897 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9899 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9903 // If we're converting from a float, to an int, and back to a float again,
9904 // then we don't need the store/load pair at all.
9905 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9906 Subtarget.hasFPCVT()) ||
9907 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9908 SDValue Src = Op.getOperand(0).getOperand(0);
9909 if (Src.getValueType() == MVT::f32) {
9910 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9911 DCI.AddToWorklist(Src.getNode());
9915 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9918 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9919 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9921 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9922 FP = DAG.getNode(ISD::FP_ROUND, dl,
9923 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
9924 DCI.AddToWorklist(FP.getNode());
9933 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9934 // builtins) into loads with swaps.
9935 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9936 DAGCombinerInfo &DCI) const {
9937 SelectionDAG &DAG = DCI.DAG;
9941 MachineMemOperand *MMO;
9943 switch (N->getOpcode()) {
9945 llvm_unreachable("Unexpected opcode for little endian VSX load");
9947 LoadSDNode *LD = cast<LoadSDNode>(N);
9948 Chain = LD->getChain();
9949 Base = LD->getBasePtr();
9950 MMO = LD->getMemOperand();
9951 // If the MMO suggests this isn't a load of a full vector, leave
9952 // things alone. For a built-in, we have to make the change for
9953 // correctness, so if there is a size problem that will be a bug.
9954 if (MMO->getSize() < 16)
9958 case ISD::INTRINSIC_W_CHAIN: {
9959 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9960 Chain = Intrin->getChain();
9961 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
9962 // us what we want. Get operand 2 instead.
9963 Base = Intrin->getOperand(2);
9964 MMO = Intrin->getMemOperand();
9969 MVT VecTy = N->getValueType(0).getSimpleVT();
9970 SDValue LoadOps[] = { Chain, Base };
9971 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9972 DAG.getVTList(VecTy, MVT::Other),
9973 LoadOps, VecTy, MMO);
9974 DCI.AddToWorklist(Load.getNode());
9975 Chain = Load.getValue(1);
9976 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9977 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9978 DCI.AddToWorklist(Swap.getNode());
9982 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
9983 // builtins) into stores with swaps.
9984 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
9985 DAGCombinerInfo &DCI) const {
9986 SelectionDAG &DAG = DCI.DAG;
9991 MachineMemOperand *MMO;
9993 switch (N->getOpcode()) {
9995 llvm_unreachable("Unexpected opcode for little endian VSX store");
9997 StoreSDNode *ST = cast<StoreSDNode>(N);
9998 Chain = ST->getChain();
9999 Base = ST->getBasePtr();
10000 MMO = ST->getMemOperand();
10002 // If the MMO suggests this isn't a store of a full vector, leave
10003 // things alone. For a built-in, we have to make the change for
10004 // correctness, so if there is a size problem that will be a bug.
10005 if (MMO->getSize() < 16)
10009 case ISD::INTRINSIC_VOID: {
10010 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10011 Chain = Intrin->getChain();
10012 // Intrin->getBasePtr() oddly does not get what we want.
10013 Base = Intrin->getOperand(3);
10014 MMO = Intrin->getMemOperand();
10020 SDValue Src = N->getOperand(SrcOpnd);
10021 MVT VecTy = Src.getValueType().getSimpleVT();
10022 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10023 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10024 DCI.AddToWorklist(Swap.getNode());
10025 Chain = Swap.getValue(1);
10026 SDValue StoreOps[] = { Chain, Swap, Base };
10027 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10028 DAG.getVTList(MVT::Other),
10029 StoreOps, VecTy, MMO);
10030 DCI.AddToWorklist(Store.getNode());
10034 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10035 DAGCombinerInfo &DCI) const {
10036 SelectionDAG &DAG = DCI.DAG;
10038 switch (N->getOpcode()) {
10041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10042 if (C->isNullValue()) // 0 << V -> 0.
10043 return N->getOperand(0);
10047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10048 if (C->isNullValue()) // 0 >>u V -> 0.
10049 return N->getOperand(0);
10053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10054 if (C->isNullValue() || // 0 >>s V -> 0.
10055 C->isAllOnesValue()) // -1 >>s V -> -1.
10056 return N->getOperand(0);
10059 case ISD::SIGN_EXTEND:
10060 case ISD::ZERO_EXTEND:
10061 case ISD::ANY_EXTEND:
10062 return DAGCombineExtBoolTrunc(N, DCI);
10063 case ISD::TRUNCATE:
10065 case ISD::SELECT_CC:
10066 return DAGCombineTruncBoolExt(N, DCI);
10067 case ISD::SINT_TO_FP:
10068 case ISD::UINT_TO_FP:
10069 return combineFPToIntToFP(N, DCI);
10071 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10072 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10073 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10074 N->getOperand(1).getValueType() == MVT::i32 &&
10075 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10076 SDValue Val = N->getOperand(1).getOperand(0);
10077 if (Val.getValueType() == MVT::f32) {
10078 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10079 DCI.AddToWorklist(Val.getNode());
10081 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10082 DCI.AddToWorklist(Val.getNode());
10085 N->getOperand(0), Val, N->getOperand(2),
10086 DAG.getValueType(N->getOperand(1).getValueType())
10089 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10090 DAG.getVTList(MVT::Other), Ops,
10091 cast<StoreSDNode>(N)->getMemoryVT(),
10092 cast<StoreSDNode>(N)->getMemOperand());
10093 DCI.AddToWorklist(Val.getNode());
10097 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10098 if (cast<StoreSDNode>(N)->isUnindexed() &&
10099 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10100 N->getOperand(1).getNode()->hasOneUse() &&
10101 (N->getOperand(1).getValueType() == MVT::i32 ||
10102 N->getOperand(1).getValueType() == MVT::i16 ||
10103 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10104 N->getOperand(1).getValueType() == MVT::i64))) {
10105 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10106 // Do an any-extend to 32-bits if this is a half-word input.
10107 if (BSwapOp.getValueType() == MVT::i16)
10108 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10111 N->getOperand(0), BSwapOp, N->getOperand(2),
10112 DAG.getValueType(N->getOperand(1).getValueType())
10115 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10116 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10117 cast<StoreSDNode>(N)->getMemOperand());
10120 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10121 EVT VT = N->getOperand(1).getValueType();
10122 if (VT.isSimple()) {
10123 MVT StoreVT = VT.getSimpleVT();
10124 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10125 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10126 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10127 return expandVSXStoreForLE(N, DCI);
10132 LoadSDNode *LD = cast<LoadSDNode>(N);
10133 EVT VT = LD->getValueType(0);
10135 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10136 if (VT.isSimple()) {
10137 MVT LoadVT = VT.getSimpleVT();
10138 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10139 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10140 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10141 return expandVSXLoadForLE(N, DCI);
10144 EVT MemVT = LD->getMemoryVT();
10145 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10146 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
10147 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10148 unsigned ScalarABIAlignment = getDataLayout()->getABITypeAlignment(STy);
10149 if (LD->isUnindexed() && VT.isVector() &&
10150 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10151 // P8 and later hardware should just use LOAD.
10152 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10153 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10154 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10155 LD->getAlignment() >= ScalarABIAlignment)) &&
10156 LD->getAlignment() < ABIAlignment) {
10157 // This is a type-legal unaligned Altivec or QPX load.
10158 SDValue Chain = LD->getChain();
10159 SDValue Ptr = LD->getBasePtr();
10160 bool isLittleEndian = Subtarget.isLittleEndian();
10162 // This implements the loading of unaligned vectors as described in
10163 // the venerable Apple Velocity Engine overview. Specifically:
10164 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10165 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10167 // The general idea is to expand a sequence of one or more unaligned
10168 // loads into an alignment-based permutation-control instruction (lvsl
10169 // or lvsr), a series of regular vector loads (which always truncate
10170 // their input address to an aligned address), and a series of
10171 // permutations. The results of these permutations are the requested
10172 // loaded values. The trick is that the last "extra" load is not taken
10173 // from the address you might suspect (sizeof(vector) bytes after the
10174 // last requested load), but rather sizeof(vector) - 1 bytes after the
10175 // last requested vector. The point of this is to avoid a page fault if
10176 // the base address happened to be aligned. This works because if the
10177 // base address is aligned, then adding less than a full vector length
10178 // will cause the last vector in the sequence to be (re)loaded.
10179 // Otherwise, the next vector will be fetched as you might suspect was
10182 // We might be able to reuse the permutation generation from
10183 // a different base address offset from this one by an aligned amount.
10184 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10185 // optimization later.
10186 Intrinsic::ID Intr, IntrLD, IntrPerm;
10187 MVT PermCntlTy, PermTy, LDTy;
10188 if (Subtarget.hasAltivec()) {
10189 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10190 Intrinsic::ppc_altivec_lvsl;
10191 IntrLD = Intrinsic::ppc_altivec_lvx;
10192 IntrPerm = Intrinsic::ppc_altivec_vperm;
10193 PermCntlTy = MVT::v16i8;
10194 PermTy = MVT::v4i32;
10197 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10198 Intrinsic::ppc_qpx_qvlpcls;
10199 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10200 Intrinsic::ppc_qpx_qvlfs;
10201 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10202 PermCntlTy = MVT::v4f64;
10203 PermTy = MVT::v4f64;
10204 LDTy = MemVT.getSimpleVT();
10207 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10209 // Create the new MMO for the new base load. It is like the original MMO,
10210 // but represents an area in memory almost twice the vector size centered
10211 // on the original address. If the address is unaligned, we might start
10212 // reading up to (sizeof(vector)-1) bytes below the address of the
10213 // original unaligned load.
10214 MachineFunction &MF = DAG.getMachineFunction();
10215 MachineMemOperand *BaseMMO =
10216 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
10217 2*MemVT.getStoreSize()-1);
10219 // Create the new base load.
10220 SDValue LDXIntID = DAG.getTargetConstant(IntrLD, dl, getPointerTy());
10221 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10223 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10224 DAG.getVTList(PermTy, MVT::Other),
10225 BaseLoadOps, LDTy, BaseMMO);
10227 // Note that the value of IncOffset (which is provided to the next
10228 // load's pointer info offset value, and thus used to calculate the
10229 // alignment), and the value of IncValue (which is actually used to
10230 // increment the pointer value) are different! This is because we
10231 // require the next load to appear to be aligned, even though it
10232 // is actually offset from the base pointer by a lesser amount.
10233 int IncOffset = VT.getSizeInBits() / 8;
10234 int IncValue = IncOffset;
10236 // Walk (both up and down) the chain looking for another load at the real
10237 // (aligned) offset (the alignment of the other load does not matter in
10238 // this case). If found, then do not use the offset reduction trick, as
10239 // that will prevent the loads from being later combined (as they would
10240 // otherwise be duplicates).
10241 if (!findConsecutiveLoad(LD, DAG))
10244 SDValue Increment = DAG.getConstant(IncValue, dl, getPointerTy());
10245 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10247 MachineMemOperand *ExtraMMO =
10248 MF.getMachineMemOperand(LD->getMemOperand(),
10249 1, 2*MemVT.getStoreSize()-1);
10250 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10251 SDValue ExtraLoad =
10252 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10253 DAG.getVTList(PermTy, MVT::Other),
10254 ExtraLoadOps, LDTy, ExtraMMO);
10256 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10257 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10259 // Because vperm has a big-endian bias, we must reverse the order
10260 // of the input vectors and complement the permute control vector
10261 // when generating little endian code. We have already handled the
10262 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10263 // and ExtraLoad here.
10265 if (isLittleEndian)
10266 Perm = BuildIntrinsicOp(IntrPerm,
10267 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10269 Perm = BuildIntrinsicOp(IntrPerm,
10270 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10273 Perm = Subtarget.hasAltivec() ?
10274 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10275 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10276 DAG.getTargetConstant(1, dl, MVT::i64));
10277 // second argument is 1 because this rounding
10278 // is always exact.
10280 // The output of the permutation is our loaded result, the TokenFactor is
10282 DCI.CombineTo(N, Perm, TF);
10283 return SDValue(N, 0);
10287 case ISD::INTRINSIC_WO_CHAIN: {
10288 bool isLittleEndian = Subtarget.isLittleEndian();
10289 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10290 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10291 : Intrinsic::ppc_altivec_lvsl);
10292 if ((IID == Intr ||
10293 IID == Intrinsic::ppc_qpx_qvlpcld ||
10294 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10295 N->getOperand(1)->getOpcode() == ISD::ADD) {
10296 SDValue Add = N->getOperand(1);
10298 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10299 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10301 if (DAG.MaskedValueIsZero(
10302 Add->getOperand(1),
10303 APInt::getAllOnesValue(Bits /* alignment */)
10305 Add.getValueType().getScalarType().getSizeInBits()))) {
10306 SDNode *BasePtr = Add->getOperand(0).getNode();
10307 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10308 UE = BasePtr->use_end();
10310 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10311 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10312 // We've found another LVSL/LVSR, and this address is an aligned
10313 // multiple of that one. The results will be the same, so use the
10314 // one we've just found instead.
10316 return SDValue(*UI, 0);
10321 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10322 SDNode *BasePtr = Add->getOperand(0).getNode();
10323 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10324 UE = BasePtr->use_end(); UI != UE; ++UI) {
10325 if (UI->getOpcode() == ISD::ADD &&
10326 isa<ConstantSDNode>(UI->getOperand(1)) &&
10327 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10328 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10329 (1ULL << Bits) == 0) {
10330 SDNode *OtherAdd = *UI;
10331 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10332 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10333 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10334 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10335 return SDValue(*VI, 0);
10345 case ISD::INTRINSIC_W_CHAIN: {
10346 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10347 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10348 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10351 case Intrinsic::ppc_vsx_lxvw4x:
10352 case Intrinsic::ppc_vsx_lxvd2x:
10353 return expandVSXLoadForLE(N, DCI);
10358 case ISD::INTRINSIC_VOID: {
10359 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10360 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10361 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10364 case Intrinsic::ppc_vsx_stxvw4x:
10365 case Intrinsic::ppc_vsx_stxvd2x:
10366 return expandVSXStoreForLE(N, DCI);
10372 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10373 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10374 N->getOperand(0).hasOneUse() &&
10375 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10376 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10377 N->getValueType(0) == MVT::i64))) {
10378 SDValue Load = N->getOperand(0);
10379 LoadSDNode *LD = cast<LoadSDNode>(Load);
10380 // Create the byte-swapping load.
10382 LD->getChain(), // Chain
10383 LD->getBasePtr(), // Ptr
10384 DAG.getValueType(N->getValueType(0)) // VT
10387 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10388 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10389 MVT::i64 : MVT::i32, MVT::Other),
10390 Ops, LD->getMemoryVT(), LD->getMemOperand());
10392 // If this is an i16 load, insert the truncate.
10393 SDValue ResVal = BSLoad;
10394 if (N->getValueType(0) == MVT::i16)
10395 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10397 // First, combine the bswap away. This makes the value produced by the
10399 DCI.CombineTo(N, ResVal);
10401 // Next, combine the load away, we give it a bogus result value but a real
10402 // chain result. The result value is dead because the bswap is dead.
10403 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10405 // Return N so it doesn't get rechecked!
10406 return SDValue(N, 0);
10410 case PPCISD::VCMP: {
10411 // If a VCMPo node already exists with exactly the same operands as this
10412 // node, use its result instead of this node (VCMPo computes both a CR6 and
10413 // a normal output).
10415 if (!N->getOperand(0).hasOneUse() &&
10416 !N->getOperand(1).hasOneUse() &&
10417 !N->getOperand(2).hasOneUse()) {
10419 // Scan all of the users of the LHS, looking for VCMPo's that match.
10420 SDNode *VCMPoNode = nullptr;
10422 SDNode *LHSN = N->getOperand(0).getNode();
10423 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10425 if (UI->getOpcode() == PPCISD::VCMPo &&
10426 UI->getOperand(1) == N->getOperand(1) &&
10427 UI->getOperand(2) == N->getOperand(2) &&
10428 UI->getOperand(0) == N->getOperand(0)) {
10433 // If there is no VCMPo node, or if the flag value has a single use, don't
10435 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10438 // Look at the (necessarily single) use of the flag value. If it has a
10439 // chain, this transformation is more complex. Note that multiple things
10440 // could use the value result, which we should ignore.
10441 SDNode *FlagUser = nullptr;
10442 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10443 FlagUser == nullptr; ++UI) {
10444 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10445 SDNode *User = *UI;
10446 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10447 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10454 // If the user is a MFOCRF instruction, we know this is safe.
10455 // Otherwise we give up for right now.
10456 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10457 return SDValue(VCMPoNode, 0);
10461 case ISD::BRCOND: {
10462 SDValue Cond = N->getOperand(1);
10463 SDValue Target = N->getOperand(2);
10465 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10466 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10467 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10469 // We now need to make the intrinsic dead (it cannot be instruction
10471 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10472 assert(Cond.getNode()->hasOneUse() &&
10473 "Counter decrement has more than one use");
10475 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10476 N->getOperand(0), Target);
10481 // If this is a branch on an altivec predicate comparison, lower this so
10482 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10483 // lowering is done pre-legalize, because the legalizer lowers the predicate
10484 // compare down to code that is difficult to reassemble.
10485 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10486 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10488 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10489 // value. If so, pass-through the AND to get to the intrinsic.
10490 if (LHS.getOpcode() == ISD::AND &&
10491 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10492 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10493 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10494 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10495 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10497 LHS = LHS.getOperand(0);
10499 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10500 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10501 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10502 isa<ConstantSDNode>(RHS)) {
10503 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10504 "Counter decrement comparison is not EQ or NE");
10506 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10507 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10508 (CC == ISD::SETNE && !Val);
10510 // We now need to make the intrinsic dead (it cannot be instruction
10512 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10513 assert(LHS.getNode()->hasOneUse() &&
10514 "Counter decrement has more than one use");
10516 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10517 N->getOperand(0), N->getOperand(4));
10523 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10524 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10525 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10526 assert(isDot && "Can't compare against a vector result!");
10528 // If this is a comparison against something other than 0/1, then we know
10529 // that the condition is never/always true.
10530 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10531 if (Val != 0 && Val != 1) {
10532 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10533 return N->getOperand(0);
10534 // Always !=, turn it into an unconditional branch.
10535 return DAG.getNode(ISD::BR, dl, MVT::Other,
10536 N->getOperand(0), N->getOperand(4));
10539 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10541 // Create the PPCISD altivec 'dot' comparison node.
10543 LHS.getOperand(2), // LHS of compare
10544 LHS.getOperand(3), // RHS of compare
10545 DAG.getConstant(CompareOpc, dl, MVT::i32)
10547 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10548 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10550 // Unpack the result based on how the target uses it.
10551 PPC::Predicate CompOpc;
10552 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10553 default: // Can't happen, don't crash on invalid number though.
10554 case 0: // Branch on the value of the EQ bit of CR6.
10555 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10557 case 1: // Branch on the inverted value of the EQ bit of CR6.
10558 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10560 case 2: // Branch on the value of the LT bit of CR6.
10561 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10563 case 3: // Branch on the inverted value of the LT bit of CR6.
10564 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10568 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10569 DAG.getConstant(CompOpc, dl, MVT::i32),
10570 DAG.getRegister(PPC::CR6, MVT::i32),
10571 N->getOperand(4), CompNode.getValue(1));
10581 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10583 std::vector<SDNode *> *Created) const {
10584 // fold (sdiv X, pow2)
10585 EVT VT = N->getValueType(0);
10586 if (VT == MVT::i64 && !Subtarget.isPPC64())
10588 if ((VT != MVT::i32 && VT != MVT::i64) ||
10589 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10593 SDValue N0 = N->getOperand(0);
10595 bool IsNegPow2 = (-Divisor).isPowerOf2();
10596 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10597 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10599 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10601 Created->push_back(Op.getNode());
10604 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10606 Created->push_back(Op.getNode());
10612 //===----------------------------------------------------------------------===//
10613 // Inline Assembly Support
10614 //===----------------------------------------------------------------------===//
10616 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10619 const SelectionDAG &DAG,
10620 unsigned Depth) const {
10621 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10622 switch (Op.getOpcode()) {
10624 case PPCISD::LBRX: {
10625 // lhbrx is known to have the top bits cleared out.
10626 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10627 KnownZero = 0xFFFF0000;
10630 case ISD::INTRINSIC_WO_CHAIN: {
10631 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10633 case Intrinsic::ppc_altivec_vcmpbfp_p:
10634 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10635 case Intrinsic::ppc_altivec_vcmpequb_p:
10636 case Intrinsic::ppc_altivec_vcmpequh_p:
10637 case Intrinsic::ppc_altivec_vcmpequw_p:
10638 case Intrinsic::ppc_altivec_vcmpequd_p:
10639 case Intrinsic::ppc_altivec_vcmpgefp_p:
10640 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10641 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10642 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10643 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10644 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10645 case Intrinsic::ppc_altivec_vcmpgtub_p:
10646 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10647 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10648 case Intrinsic::ppc_altivec_vcmpgtud_p:
10649 KnownZero = ~1U; // All bits but the low one are known to be zero.
10656 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10657 switch (Subtarget.getDarwinDirective()) {
10660 case PPC::DIR_PWR4:
10661 case PPC::DIR_PWR5:
10662 case PPC::DIR_PWR5X:
10663 case PPC::DIR_PWR6:
10664 case PPC::DIR_PWR6X:
10665 case PPC::DIR_PWR7:
10666 case PPC::DIR_PWR8: {
10670 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10672 // For small loops (between 5 and 8 instructions), align to a 32-byte
10673 // boundary so that the entire loop fits in one instruction-cache line.
10674 uint64_t LoopSize = 0;
10675 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10676 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10677 LoopSize += TII->GetInstSizeInBytes(J);
10679 if (LoopSize > 16 && LoopSize <= 32)
10686 return TargetLowering::getPrefLoopAlignment(ML);
10689 /// getConstraintType - Given a constraint, return the type of
10690 /// constraint it is for this target.
10691 PPCTargetLowering::ConstraintType
10692 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10693 if (Constraint.size() == 1) {
10694 switch (Constraint[0]) {
10701 return C_RegisterClass;
10703 // FIXME: While Z does indicate a memory constraint, it specifically
10704 // indicates an r+r address (used in conjunction with the 'y' modifier
10705 // in the replacement string). Currently, we're forcing the base
10706 // register to be r0 in the asm printer (which is interpreted as zero)
10707 // and forming the complete address in the second register. This is
10711 } else if (Constraint == "wc") { // individual CR bits.
10712 return C_RegisterClass;
10713 } else if (Constraint == "wa" || Constraint == "wd" ||
10714 Constraint == "wf" || Constraint == "ws") {
10715 return C_RegisterClass; // VSX registers.
10717 return TargetLowering::getConstraintType(Constraint);
10720 /// Examine constraint type and operand type and determine a weight value.
10721 /// This object must already have been set up with the operand type
10722 /// and the current alternative constraint selected.
10723 TargetLowering::ConstraintWeight
10724 PPCTargetLowering::getSingleConstraintMatchWeight(
10725 AsmOperandInfo &info, const char *constraint) const {
10726 ConstraintWeight weight = CW_Invalid;
10727 Value *CallOperandVal = info.CallOperandVal;
10728 // If we don't have a value, we can't do a match,
10729 // but allow it at the lowest weight.
10730 if (!CallOperandVal)
10732 Type *type = CallOperandVal->getType();
10734 // Look at the constraint type.
10735 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10736 return CW_Register; // an individual CR bit.
10737 else if ((StringRef(constraint) == "wa" ||
10738 StringRef(constraint) == "wd" ||
10739 StringRef(constraint) == "wf") &&
10740 type->isVectorTy())
10741 return CW_Register;
10742 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10743 return CW_Register;
10745 switch (*constraint) {
10747 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10750 if (type->isIntegerTy())
10751 weight = CW_Register;
10754 if (type->isFloatTy())
10755 weight = CW_Register;
10758 if (type->isDoubleTy())
10759 weight = CW_Register;
10762 if (type->isVectorTy())
10763 weight = CW_Register;
10766 weight = CW_Register;
10769 weight = CW_Memory;
10775 std::pair<unsigned, const TargetRegisterClass *>
10776 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10777 StringRef Constraint,
10779 if (Constraint.size() == 1) {
10780 // GCC RS6000 Constraint Letters
10781 switch (Constraint[0]) {
10782 case 'b': // R1-R31
10783 if (VT == MVT::i64 && Subtarget.isPPC64())
10784 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10785 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10786 case 'r': // R0-R31
10787 if (VT == MVT::i64 && Subtarget.isPPC64())
10788 return std::make_pair(0U, &PPC::G8RCRegClass);
10789 return std::make_pair(0U, &PPC::GPRCRegClass);
10791 if (VT == MVT::f32 || VT == MVT::i32)
10792 return std::make_pair(0U, &PPC::F4RCRegClass);
10793 if (VT == MVT::f64 || VT == MVT::i64)
10794 return std::make_pair(0U, &PPC::F8RCRegClass);
10795 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10796 return std::make_pair(0U, &PPC::QFRCRegClass);
10797 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10798 return std::make_pair(0U, &PPC::QSRCRegClass);
10801 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10802 return std::make_pair(0U, &PPC::QFRCRegClass);
10803 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10804 return std::make_pair(0U, &PPC::QSRCRegClass);
10805 return std::make_pair(0U, &PPC::VRRCRegClass);
10807 return std::make_pair(0U, &PPC::CRRCRegClass);
10809 } else if (Constraint == "wc") { // an individual CR bit.
10810 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10811 } else if (Constraint == "wa" || Constraint == "wd" ||
10812 Constraint == "wf") {
10813 return std::make_pair(0U, &PPC::VSRCRegClass);
10814 } else if (Constraint == "ws") {
10815 if (VT == MVT::f32)
10816 return std::make_pair(0U, &PPC::VSSRCRegClass);
10818 return std::make_pair(0U, &PPC::VSFRCRegClass);
10821 std::pair<unsigned, const TargetRegisterClass *> R =
10822 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10824 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10825 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10826 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10828 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10829 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10830 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10831 PPC::GPRCRegClass.contains(R.first))
10832 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10833 PPC::sub_32, &PPC::G8RCRegClass),
10834 &PPC::G8RCRegClass);
10836 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10837 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10838 R.first = PPC::CR0;
10839 R.second = &PPC::CRRCRegClass;
10846 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10847 /// vector. If it is invalid, don't add anything to Ops.
10848 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10849 std::string &Constraint,
10850 std::vector<SDValue>&Ops,
10851 SelectionDAG &DAG) const {
10854 // Only support length 1 constraints.
10855 if (Constraint.length() > 1) return;
10857 char Letter = Constraint[0];
10868 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10869 if (!CST) return; // Must be an immediate to match.
10871 int64_t Value = CST->getSExtValue();
10872 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10873 // numbers are printed as such.
10875 default: llvm_unreachable("Unknown constraint letter!");
10876 case 'I': // "I" is a signed 16-bit constant.
10877 if (isInt<16>(Value))
10878 Result = DAG.getTargetConstant(Value, dl, TCVT);
10880 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10881 if (isShiftedUInt<16, 16>(Value))
10882 Result = DAG.getTargetConstant(Value, dl, TCVT);
10884 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10885 if (isShiftedInt<16, 16>(Value))
10886 Result = DAG.getTargetConstant(Value, dl, TCVT);
10888 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10889 if (isUInt<16>(Value))
10890 Result = DAG.getTargetConstant(Value, dl, TCVT);
10892 case 'M': // "M" is a constant that is greater than 31.
10894 Result = DAG.getTargetConstant(Value, dl, TCVT);
10896 case 'N': // "N" is a positive constant that is an exact power of two.
10897 if (Value > 0 && isPowerOf2_64(Value))
10898 Result = DAG.getTargetConstant(Value, dl, TCVT);
10900 case 'O': // "O" is the constant zero.
10902 Result = DAG.getTargetConstant(Value, dl, TCVT);
10904 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10905 if (isInt<16>(-Value))
10906 Result = DAG.getTargetConstant(Value, dl, TCVT);
10913 if (Result.getNode()) {
10914 Ops.push_back(Result);
10918 // Handle standard constraint letters.
10919 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10922 // isLegalAddressingMode - Return true if the addressing mode represented
10923 // by AM is legal for this target, for a load/store of the specified type.
10924 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10926 unsigned AS) const {
10927 // PPC does not allow r+i addressing modes for vectors!
10928 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10931 // PPC allows a sign-extended 16-bit immediate field.
10932 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10935 // No global is ever allowed as a base.
10939 // PPC only support r+r,
10940 switch (AM.Scale) {
10941 case 0: // "r+i" or just "i", depending on HasBaseReg.
10944 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
10946 // Otherwise we have r+r or r+i.
10949 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
10951 // Allow 2*r as r+r.
10954 // No other scales are supported.
10961 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
10962 SelectionDAG &DAG) const {
10963 MachineFunction &MF = DAG.getMachineFunction();
10964 MachineFrameInfo *MFI = MF.getFrameInfo();
10965 MFI->setReturnAddressIsTaken(true);
10967 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
10971 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10973 // Make sure the function does not optimize away the store of the RA to
10975 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
10976 FuncInfo->setLRStoreRequired();
10977 bool isPPC64 = Subtarget.isPPC64();
10980 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10982 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
10983 isPPC64 ? MVT::i64 : MVT::i32);
10984 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10985 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10986 FrameAddr, Offset),
10987 MachinePointerInfo(), false, false, false, 0);
10990 // Just load the return address off the stack.
10991 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
10992 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10993 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10996 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
10997 SelectionDAG &DAG) const {
10999 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11001 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
11002 bool isPPC64 = PtrVT == MVT::i64;
11004 MachineFunction &MF = DAG.getMachineFunction();
11005 MachineFrameInfo *MFI = MF.getFrameInfo();
11006 MFI->setFrameAddressIsTaken(true);
11008 // Naked functions never have a frame pointer, and so we use r1. For all
11009 // other functions, this decision must be delayed until during PEI.
11011 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11012 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11014 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11016 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11019 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11020 FrameAddr, MachinePointerInfo(), false, false,
11025 // FIXME? Maybe this could be a TableGen attribute on some registers and
11026 // this table could be generated automatically from RegInfo.
11027 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
11029 bool isPPC64 = Subtarget.isPPC64();
11030 bool isDarwinABI = Subtarget.isDarwinABI();
11032 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11033 (!isPPC64 && VT != MVT::i32))
11034 report_fatal_error("Invalid register global variable type");
11036 bool is64Bit = isPPC64 && VT == MVT::i64;
11037 unsigned Reg = StringSwitch<unsigned>(RegName)
11038 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11039 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11040 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11041 (is64Bit ? PPC::X13 : PPC::R13))
11046 report_fatal_error("Invalid register name global variable");
11050 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11051 // The PowerPC target isn't yet aware of offsets.
11055 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11057 unsigned Intrinsic) const {
11059 switch (Intrinsic) {
11060 case Intrinsic::ppc_qpx_qvlfd:
11061 case Intrinsic::ppc_qpx_qvlfs:
11062 case Intrinsic::ppc_qpx_qvlfcd:
11063 case Intrinsic::ppc_qpx_qvlfcs:
11064 case Intrinsic::ppc_qpx_qvlfiwa:
11065 case Intrinsic::ppc_qpx_qvlfiwz:
11066 case Intrinsic::ppc_altivec_lvx:
11067 case Intrinsic::ppc_altivec_lvxl:
11068 case Intrinsic::ppc_altivec_lvebx:
11069 case Intrinsic::ppc_altivec_lvehx:
11070 case Intrinsic::ppc_altivec_lvewx:
11071 case Intrinsic::ppc_vsx_lxvd2x:
11072 case Intrinsic::ppc_vsx_lxvw4x: {
11074 switch (Intrinsic) {
11075 case Intrinsic::ppc_altivec_lvebx:
11078 case Intrinsic::ppc_altivec_lvehx:
11081 case Intrinsic::ppc_altivec_lvewx:
11084 case Intrinsic::ppc_vsx_lxvd2x:
11087 case Intrinsic::ppc_qpx_qvlfd:
11090 case Intrinsic::ppc_qpx_qvlfs:
11093 case Intrinsic::ppc_qpx_qvlfcd:
11096 case Intrinsic::ppc_qpx_qvlfcs:
11104 Info.opc = ISD::INTRINSIC_W_CHAIN;
11106 Info.ptrVal = I.getArgOperand(0);
11107 Info.offset = -VT.getStoreSize()+1;
11108 Info.size = 2*VT.getStoreSize()-1;
11111 Info.readMem = true;
11112 Info.writeMem = false;
11115 case Intrinsic::ppc_qpx_qvlfda:
11116 case Intrinsic::ppc_qpx_qvlfsa:
11117 case Intrinsic::ppc_qpx_qvlfcda:
11118 case Intrinsic::ppc_qpx_qvlfcsa:
11119 case Intrinsic::ppc_qpx_qvlfiwaa:
11120 case Intrinsic::ppc_qpx_qvlfiwza: {
11122 switch (Intrinsic) {
11123 case Intrinsic::ppc_qpx_qvlfda:
11126 case Intrinsic::ppc_qpx_qvlfsa:
11129 case Intrinsic::ppc_qpx_qvlfcda:
11132 case Intrinsic::ppc_qpx_qvlfcsa:
11140 Info.opc = ISD::INTRINSIC_W_CHAIN;
11142 Info.ptrVal = I.getArgOperand(0);
11144 Info.size = VT.getStoreSize();
11147 Info.readMem = true;
11148 Info.writeMem = false;
11151 case Intrinsic::ppc_qpx_qvstfd:
11152 case Intrinsic::ppc_qpx_qvstfs:
11153 case Intrinsic::ppc_qpx_qvstfcd:
11154 case Intrinsic::ppc_qpx_qvstfcs:
11155 case Intrinsic::ppc_qpx_qvstfiw:
11156 case Intrinsic::ppc_altivec_stvx:
11157 case Intrinsic::ppc_altivec_stvxl:
11158 case Intrinsic::ppc_altivec_stvebx:
11159 case Intrinsic::ppc_altivec_stvehx:
11160 case Intrinsic::ppc_altivec_stvewx:
11161 case Intrinsic::ppc_vsx_stxvd2x:
11162 case Intrinsic::ppc_vsx_stxvw4x: {
11164 switch (Intrinsic) {
11165 case Intrinsic::ppc_altivec_stvebx:
11168 case Intrinsic::ppc_altivec_stvehx:
11171 case Intrinsic::ppc_altivec_stvewx:
11174 case Intrinsic::ppc_vsx_stxvd2x:
11177 case Intrinsic::ppc_qpx_qvstfd:
11180 case Intrinsic::ppc_qpx_qvstfs:
11183 case Intrinsic::ppc_qpx_qvstfcd:
11186 case Intrinsic::ppc_qpx_qvstfcs:
11194 Info.opc = ISD::INTRINSIC_VOID;
11196 Info.ptrVal = I.getArgOperand(1);
11197 Info.offset = -VT.getStoreSize()+1;
11198 Info.size = 2*VT.getStoreSize()-1;
11201 Info.readMem = false;
11202 Info.writeMem = true;
11205 case Intrinsic::ppc_qpx_qvstfda:
11206 case Intrinsic::ppc_qpx_qvstfsa:
11207 case Intrinsic::ppc_qpx_qvstfcda:
11208 case Intrinsic::ppc_qpx_qvstfcsa:
11209 case Intrinsic::ppc_qpx_qvstfiwa: {
11211 switch (Intrinsic) {
11212 case Intrinsic::ppc_qpx_qvstfda:
11215 case Intrinsic::ppc_qpx_qvstfsa:
11218 case Intrinsic::ppc_qpx_qvstfcda:
11221 case Intrinsic::ppc_qpx_qvstfcsa:
11229 Info.opc = ISD::INTRINSIC_VOID;
11231 Info.ptrVal = I.getArgOperand(1);
11233 Info.size = VT.getStoreSize();
11236 Info.readMem = false;
11237 Info.writeMem = true;
11247 /// getOptimalMemOpType - Returns the target specific optimal type for load
11248 /// and store operations as a result of memset, memcpy, and memmove
11249 /// lowering. If DstAlign is zero that means it's safe to destination
11250 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11251 /// means there isn't a need to check it against alignment requirement,
11252 /// probably because the source does not need to be loaded. If 'IsMemset' is
11253 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11254 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11255 /// source is constant so it does not need to be loaded.
11256 /// It returns EVT::Other if the type should be determined using generic
11257 /// target-independent logic.
11258 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11259 unsigned DstAlign, unsigned SrcAlign,
11260 bool IsMemset, bool ZeroMemset,
11262 MachineFunction &MF) const {
11263 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11264 const Function *F = MF.getFunction();
11265 // When expanding a memset, require at least two QPX instructions to cover
11266 // the cost of loading the value to be stored from the constant pool.
11267 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11268 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11269 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11273 // We should use Altivec/VSX loads and stores when available. For unaligned
11274 // addresses, unaligned VSX loads are only fast starting with the P8.
11275 if (Subtarget.hasAltivec() && Size >= 16 &&
11276 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11277 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11281 if (Subtarget.isPPC64()) {
11288 /// \brief Returns true if it is beneficial to convert a load of a constant
11289 /// to just the constant itself.
11290 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11292 assert(Ty->isIntegerTy());
11294 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11295 if (BitSize == 0 || BitSize > 64)
11300 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11301 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11303 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11304 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11305 return NumBits1 == 64 && NumBits2 == 32;
11308 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11309 if (!VT1.isInteger() || !VT2.isInteger())
11311 unsigned NumBits1 = VT1.getSizeInBits();
11312 unsigned NumBits2 = VT2.getSizeInBits();
11313 return NumBits1 == 64 && NumBits2 == 32;
11316 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11317 // Generally speaking, zexts are not free, but they are free when they can be
11318 // folded with other operations.
11319 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11320 EVT MemVT = LD->getMemoryVT();
11321 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11322 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11323 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11324 LD->getExtensionType() == ISD::ZEXTLOAD))
11328 // FIXME: Add other cases...
11329 // - 32-bit shifts with a zext to i64
11330 // - zext after ctlz, bswap, etc.
11331 // - zext after and by a constant mask
11333 return TargetLowering::isZExtFree(Val, VT2);
11336 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11337 assert(VT.isFloatingPoint());
11341 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11342 return isInt<16>(Imm) || isUInt<16>(Imm);
11345 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11346 return isInt<16>(Imm) || isUInt<16>(Imm);
11349 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11352 bool *Fast) const {
11353 if (DisablePPCUnaligned)
11356 // PowerPC supports unaligned memory access for simple non-vector types.
11357 // Although accessing unaligned addresses is not as efficient as accessing
11358 // aligned addresses, it is generally more efficient than manual expansion,
11359 // and generally only traps for software emulation when crossing page
11362 if (!VT.isSimple())
11365 if (VT.getSimpleVT().isVector()) {
11366 if (Subtarget.hasVSX()) {
11367 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11368 VT != MVT::v4f32 && VT != MVT::v4i32)
11375 if (VT == MVT::ppcf128)
11384 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11385 VT = VT.getScalarType();
11387 if (!VT.isSimple())
11390 switch (VT.getSimpleVT().SimpleTy) {
11402 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11403 // LR is a callee-save register, but we must treat it as clobbered by any call
11404 // site. Hence we include LR in the scratch registers, which are in turn added
11405 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11406 // to CTR, which is used by any indirect call.
11407 static const MCPhysReg ScratchRegs[] = {
11408 PPC::X12, PPC::LR8, PPC::CTR8, 0
11411 return ScratchRegs;
11415 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11416 EVT VT , unsigned DefinedValues) const {
11417 if (VT == MVT::v2i64)
11420 if (Subtarget.hasQPX()) {
11421 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11425 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11428 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11429 if (DisableILPPref || Subtarget.enableMachineScheduler())
11430 return TargetLowering::getSchedulingPreference(N);
11435 // Create a fast isel object.
11437 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11438 const TargetLibraryInfo *LibInfo) const {
11439 return PPC::createFastISel(FuncInfo, LibInfo);