1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
101 if (Subtarget.useCRBits()) {
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 if (isPPC64 || Subtarget.hasFPCVT()) {
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
107 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
118 setOperationAction(ISD::STORE, MVT::i1, Custom);
120 // FIXME: Remove this once the ANDI glue bug is fixed:
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
124 for (MVT VT : MVT::integer_valuetypes()) {
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setTruncStoreAction(VT, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
185 Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (MVT VT : MVT::vector_valuetypes()) {
404 // add/sub are legal for all supported vector VT's.
405 setOperationAction(ISD::ADD , VT, Legal);
406 setOperationAction(ISD::SUB , VT, Legal);
408 // Vector instructions introduced in P8
409 if (Subtarget.hasP8Altivec()) {
410 setOperationAction(ISD::CTPOP, VT, Legal);
411 setOperationAction(ISD::CTLZ, VT, Legal);
414 setOperationAction(ISD::CTPOP, VT, Expand);
415 setOperationAction(ISD::CTLZ, VT, Expand);
418 // We promote all shuffles to v16i8.
419 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
420 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
422 // We promote all non-typed operations to v4i32.
423 setOperationAction(ISD::AND , VT, Promote);
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
425 setOperationAction(ISD::OR , VT, Promote);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
427 setOperationAction(ISD::XOR , VT, Promote);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
431 setOperationAction(ISD::SELECT, VT, Promote);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
433 setOperationAction(ISD::STORE, VT, Promote);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
436 // No other operations are legal.
437 setOperationAction(ISD::MUL , VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UDIV, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
442 setOperationAction(ISD::FDIV, VT, Expand);
443 setOperationAction(ISD::FREM, VT, Expand);
444 setOperationAction(ISD::FNEG, VT, Expand);
445 setOperationAction(ISD::FSQRT, VT, Expand);
446 setOperationAction(ISD::FLOG, VT, Expand);
447 setOperationAction(ISD::FLOG10, VT, Expand);
448 setOperationAction(ISD::FLOG2, VT, Expand);
449 setOperationAction(ISD::FEXP, VT, Expand);
450 setOperationAction(ISD::FEXP2, VT, Expand);
451 setOperationAction(ISD::FSIN, VT, Expand);
452 setOperationAction(ISD::FCOS, VT, Expand);
453 setOperationAction(ISD::FABS, VT, Expand);
454 setOperationAction(ISD::FPOWI, VT, Expand);
455 setOperationAction(ISD::FFLOOR, VT, Expand);
456 setOperationAction(ISD::FCEIL, VT, Expand);
457 setOperationAction(ISD::FTRUNC, VT, Expand);
458 setOperationAction(ISD::FRINT, VT, Expand);
459 setOperationAction(ISD::FNEARBYINT, VT, Expand);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
463 setOperationAction(ISD::MULHU, VT, Expand);
464 setOperationAction(ISD::MULHS, VT, Expand);
465 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
466 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::UDIVREM, VT, Expand);
468 setOperationAction(ISD::SDIVREM, VT, Expand);
469 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
470 setOperationAction(ISD::FPOW, VT, Expand);
471 setOperationAction(ISD::BSWAP, VT, Expand);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
473 setOperationAction(ISD::CTTZ, VT, Expand);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
475 setOperationAction(ISD::VSELECT, VT, Expand);
476 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
478 for (MVT InnerVT : MVT::vector_valuetypes()) {
479 setTruncStoreAction(VT, InnerVT, Expand);
480 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
481 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
486 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
487 // with merges, splats, etc.
488 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
494 setOperationAction(ISD::SELECT, MVT::v4i32,
495 Subtarget.useCRBits() ? Legal : Expand);
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
514 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
519 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
520 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
521 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
523 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
524 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
527 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
528 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
531 // Altivec does not contain unordered floating-point compare instructions
532 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
533 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
567 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
568 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
570 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
572 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
574 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
575 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
577 // VSX v2i64 only supports non-arithmetic operations.
578 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
579 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
581 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
583 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
585 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
587 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
588 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
590 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
592 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
594 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
595 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
596 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
597 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
599 // Vector operation legalization checks the result type of
600 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
602 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
606 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
609 if (Subtarget.hasP8Altivec())
610 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
613 if (Subtarget.has64BitSupport())
614 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
616 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
619 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
620 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
623 setBooleanContents(ZeroOrOneBooleanContent);
624 // Altivec instructions set fields to all zeros or all ones.
625 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
628 // These libcalls are not available in 32-bit.
629 setLibcallName(RTLIB::SHL_I128, nullptr);
630 setLibcallName(RTLIB::SRL_I128, nullptr);
631 setLibcallName(RTLIB::SRA_I128, nullptr);
635 setStackPointerRegisterToSaveRestore(PPC::X1);
636 setExceptionPointerRegister(PPC::X3);
637 setExceptionSelectorRegister(PPC::X4);
639 setStackPointerRegisterToSaveRestore(PPC::R1);
640 setExceptionPointerRegister(PPC::R3);
641 setExceptionSelectorRegister(PPC::R4);
644 // We have target-specific dag combine patterns for the following nodes:
645 setTargetDAGCombine(ISD::SINT_TO_FP);
646 if (Subtarget.hasFPCVT())
647 setTargetDAGCombine(ISD::UINT_TO_FP);
648 setTargetDAGCombine(ISD::LOAD);
649 setTargetDAGCombine(ISD::STORE);
650 setTargetDAGCombine(ISD::BR_CC);
651 if (Subtarget.useCRBits())
652 setTargetDAGCombine(ISD::BRCOND);
653 setTargetDAGCombine(ISD::BSWAP);
654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
655 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
656 setTargetDAGCombine(ISD::INTRINSIC_VOID);
658 setTargetDAGCombine(ISD::SIGN_EXTEND);
659 setTargetDAGCombine(ISD::ZERO_EXTEND);
660 setTargetDAGCombine(ISD::ANY_EXTEND);
662 if (Subtarget.useCRBits()) {
663 setTargetDAGCombine(ISD::TRUNCATE);
664 setTargetDAGCombine(ISD::SETCC);
665 setTargetDAGCombine(ISD::SELECT_CC);
668 // Use reciprocal estimates.
669 if (TM.Options.UnsafeFPMath) {
670 setTargetDAGCombine(ISD::FDIV);
671 setTargetDAGCombine(ISD::FSQRT);
674 // Darwin long double math library functions have $LDBL128 appended.
675 if (Subtarget.isDarwin()) {
676 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
677 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
678 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
679 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
680 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
681 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
682 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
683 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
684 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
685 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
688 // With 32 condition bits, we don't need to sink (and duplicate) compares
689 // aggressively in CodeGenPrep.
690 if (Subtarget.useCRBits()) {
691 setHasMultipleConditionRegisters();
692 setJumpIsExpensive();
695 setMinFunctionAlignment(2);
696 if (Subtarget.isDarwin())
697 setPrefFunctionAlignment(4);
699 switch (Subtarget.getDarwinDirective()) {
703 case PPC::DIR_E500mc:
712 setPrefFunctionAlignment(4);
713 setPrefLoopAlignment(4);
717 setInsertFencesForAtomic(true);
719 if (Subtarget.enableMachineScheduler())
720 setSchedulingPreference(Sched::Source);
722 setSchedulingPreference(Sched::Hybrid);
724 computeRegisterProperties();
726 // The Freescale cores do better with aggressive inlining of memcpy and
727 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
728 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
729 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
730 MaxStoresPerMemset = 32;
731 MaxStoresPerMemsetOptSize = 16;
732 MaxStoresPerMemcpy = 32;
733 MaxStoresPerMemcpyOptSize = 8;
734 MaxStoresPerMemmove = 32;
735 MaxStoresPerMemmoveOptSize = 8;
739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
740 /// the desired ByVal argument alignment.
741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
742 unsigned MaxMaxAlign) {
743 if (MaxAlign == MaxMaxAlign)
745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
746 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
748 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
750 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
751 unsigned EltAlign = 0;
752 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
753 if (EltAlign > MaxAlign)
755 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
756 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
757 unsigned EltAlign = 0;
758 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
759 if (EltAlign > MaxAlign)
761 if (MaxAlign == MaxMaxAlign)
767 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
768 /// function arguments in the caller parameter area.
769 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
770 // Darwin passes everything on 4 byte boundary.
771 if (Subtarget.isDarwin())
774 // 16byte and wider vectors are passed on 16byte boundary.
775 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
776 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
777 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
778 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
782 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
784 default: return nullptr;
785 case PPCISD::FSEL: return "PPCISD::FSEL";
786 case PPCISD::FCFID: return "PPCISD::FCFID";
787 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
788 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
789 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
790 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
791 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
792 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
793 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
794 case PPCISD::FRE: return "PPCISD::FRE";
795 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
796 case PPCISD::STFIWX: return "PPCISD::STFIWX";
797 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
798 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
799 case PPCISD::VPERM: return "PPCISD::VPERM";
800 case PPCISD::CMPB: return "PPCISD::CMPB";
801 case PPCISD::Hi: return "PPCISD::Hi";
802 case PPCISD::Lo: return "PPCISD::Lo";
803 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
804 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
805 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
806 case PPCISD::SRL: return "PPCISD::SRL";
807 case PPCISD::SRA: return "PPCISD::SRA";
808 case PPCISD::SHL: return "PPCISD::SHL";
809 case PPCISD::CALL: return "PPCISD::CALL";
810 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
811 case PPCISD::MTCTR: return "PPCISD::MTCTR";
812 case PPCISD::BCTRL: return "PPCISD::BCTRL";
813 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
814 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
815 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
816 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
817 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
818 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
819 case PPCISD::VCMP: return "PPCISD::VCMP";
820 case PPCISD::VCMPo: return "PPCISD::VCMPo";
821 case PPCISD::LBRX: return "PPCISD::LBRX";
822 case PPCISD::STBRX: return "PPCISD::STBRX";
823 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
824 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
825 case PPCISD::LARX: return "PPCISD::LARX";
826 case PPCISD::STCX: return "PPCISD::STCX";
827 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
828 case PPCISD::BDNZ: return "PPCISD::BDNZ";
829 case PPCISD::BDZ: return "PPCISD::BDZ";
830 case PPCISD::MFFS: return "PPCISD::MFFS";
831 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
832 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
833 case PPCISD::CR6SET: return "PPCISD::CR6SET";
834 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
835 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
836 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
837 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
838 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
839 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
840 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
841 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
842 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
843 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
844 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
845 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
846 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
847 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
848 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
849 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
850 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
851 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
852 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
853 case PPCISD::SC: return "PPCISD::SC";
857 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
859 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
860 return VT.changeVectorElementTypeToInteger();
863 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
864 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
868 //===----------------------------------------------------------------------===//
869 // Node matching predicates, for use by the tblgen matching code.
870 //===----------------------------------------------------------------------===//
872 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
873 static bool isFloatingPointZero(SDValue Op) {
874 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
875 return CFP->getValueAPF().isZero();
876 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
877 // Maybe this has already been legalized into the constant pool?
878 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
879 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
880 return CFP->getValueAPF().isZero();
885 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
886 /// true if Op is undef or if it matches the specified value.
887 static bool isConstantOrUndef(int Op, int Val) {
888 return Op < 0 || Op == Val;
891 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
892 /// VPKUHUM instruction.
893 /// The ShuffleKind distinguishes between big-endian operations with
894 /// two different inputs (0), either-endian operations with two identical
895 /// inputs (1), and little-endian operantion with two different inputs (2).
896 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
897 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
899 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
900 if (ShuffleKind == 0) {
903 for (unsigned i = 0; i != 16; ++i)
904 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
906 } else if (ShuffleKind == 2) {
909 for (unsigned i = 0; i != 16; ++i)
910 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
912 } else if (ShuffleKind == 1) {
913 unsigned j = IsLE ? 0 : 1;
914 for (unsigned i = 0; i != 8; ++i)
915 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
916 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
922 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
923 /// VPKUWUM instruction.
924 /// The ShuffleKind distinguishes between big-endian operations with
925 /// two different inputs (0), either-endian operations with two identical
926 /// inputs (1), and little-endian operantion with two different inputs (2).
927 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
928 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
930 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
931 if (ShuffleKind == 0) {
934 for (unsigned i = 0; i != 16; i += 2)
935 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
936 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
938 } else if (ShuffleKind == 2) {
941 for (unsigned i = 0; i != 16; i += 2)
942 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
943 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
945 } else if (ShuffleKind == 1) {
946 unsigned j = IsLE ? 0 : 2;
947 for (unsigned i = 0; i != 8; i += 2)
948 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
949 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
950 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
951 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
957 /// isVMerge - Common function, used to match vmrg* shuffles.
959 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
960 unsigned LHSStart, unsigned RHSStart) {
961 if (N->getValueType(0) != MVT::v16i8)
963 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
964 "Unsupported merge size!");
966 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
967 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
968 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
969 LHSStart+j+i*UnitSize) ||
970 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
971 RHSStart+j+i*UnitSize))
977 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
978 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
979 /// The ShuffleKind distinguishes between big-endian merges with two
980 /// different inputs (0), either-endian merges with two identical inputs (1),
981 /// and little-endian merges with two different inputs (2). For the latter,
982 /// the input operands are swapped (see PPCInstrAltivec.td).
983 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
984 unsigned ShuffleKind, SelectionDAG &DAG) {
985 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
986 if (ShuffleKind == 1) // unary
987 return isVMerge(N, UnitSize, 0, 0);
988 else if (ShuffleKind == 2) // swapped
989 return isVMerge(N, UnitSize, 0, 16);
993 if (ShuffleKind == 1) // unary
994 return isVMerge(N, UnitSize, 8, 8);
995 else if (ShuffleKind == 0) // normal
996 return isVMerge(N, UnitSize, 8, 24);
1002 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1003 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1004 /// The ShuffleKind distinguishes between big-endian merges with two
1005 /// different inputs (0), either-endian merges with two identical inputs (1),
1006 /// and little-endian merges with two different inputs (2). For the latter,
1007 /// the input operands are swapped (see PPCInstrAltivec.td).
1008 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1009 unsigned ShuffleKind, SelectionDAG &DAG) {
1010 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1011 if (ShuffleKind == 1) // unary
1012 return isVMerge(N, UnitSize, 8, 8);
1013 else if (ShuffleKind == 2) // swapped
1014 return isVMerge(N, UnitSize, 8, 24);
1018 if (ShuffleKind == 1) // unary
1019 return isVMerge(N, UnitSize, 0, 0);
1020 else if (ShuffleKind == 0) // normal
1021 return isVMerge(N, UnitSize, 0, 16);
1028 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1029 /// amount, otherwise return -1.
1030 /// The ShuffleKind distinguishes between big-endian operations with two
1031 /// different inputs (0), either-endian operations with two identical inputs
1032 /// (1), and little-endian operations with two different inputs (2). For the
1033 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1034 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1035 SelectionDAG &DAG) {
1036 if (N->getValueType(0) != MVT::v16i8)
1039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1041 // Find the first non-undef value in the shuffle mask.
1043 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1046 if (i == 16) return -1; // all undef.
1048 // Otherwise, check to see if the rest of the elements are consecutively
1049 // numbered from this value.
1050 unsigned ShiftAmt = SVOp->getMaskElt(i);
1051 if (ShiftAmt < i) return -1;
1054 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1056 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1057 // Check the rest of the elements to see if they are consecutive.
1058 for (++i; i != 16; ++i)
1059 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1061 } else if (ShuffleKind == 1) {
1062 // Check the rest of the elements to see if they are consecutive.
1063 for (++i; i != 16; ++i)
1064 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1069 if (ShuffleKind == 2 && isLE)
1070 ShiftAmt = 16 - ShiftAmt;
1075 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1076 /// specifies a splat of a single element that is suitable for input to
1077 /// VSPLTB/VSPLTH/VSPLTW.
1078 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1079 assert(N->getValueType(0) == MVT::v16i8 &&
1080 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1082 // This is a splat operation if each element of the permute is the same, and
1083 // if the value doesn't reference the second vector.
1084 unsigned ElementBase = N->getMaskElt(0);
1086 // FIXME: Handle UNDEF elements too!
1087 if (ElementBase >= 16)
1090 // Check that the indices are consecutive, in the case of a multi-byte element
1091 // splatted with a v16i8 mask.
1092 for (unsigned i = 1; i != EltSize; ++i)
1093 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1096 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1097 if (N->getMaskElt(i) < 0) continue;
1098 for (unsigned j = 0; j != EltSize; ++j)
1099 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1105 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1107 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1108 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1110 APInt APVal, APUndef;
1114 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1115 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1116 return CFP->getValueAPF().isNegZero();
1121 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1122 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1123 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1124 SelectionDAG &DAG) {
1125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1126 assert(isSplatShuffleMask(SVOp, EltSize));
1127 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1128 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1130 return SVOp->getMaskElt(0) / EltSize;
1133 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1134 /// by using a vspltis[bhw] instruction of the specified element size, return
1135 /// the constant being splatted. The ByteSize field indicates the number of
1136 /// bytes of each element [124] -> [bhw].
1137 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1138 SDValue OpVal(nullptr, 0);
1140 // If ByteSize of the splat is bigger than the element size of the
1141 // build_vector, then we have a case where we are checking for a splat where
1142 // multiple elements of the buildvector are folded together into a single
1143 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1144 unsigned EltSize = 16/N->getNumOperands();
1145 if (EltSize < ByteSize) {
1146 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1147 SDValue UniquedVals[4];
1148 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1150 // See if all of the elements in the buildvector agree across.
1151 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1152 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1153 // If the element isn't a constant, bail fully out.
1154 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1157 if (!UniquedVals[i&(Multiple-1)].getNode())
1158 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1159 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1160 return SDValue(); // no match.
1163 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1164 // either constant or undef values that are identical for each chunk. See
1165 // if these chunks can form into a larger vspltis*.
1167 // Check to see if all of the leading entries are either 0 or -1. If
1168 // neither, then this won't fit into the immediate field.
1169 bool LeadingZero = true;
1170 bool LeadingOnes = true;
1171 for (unsigned i = 0; i != Multiple-1; ++i) {
1172 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1174 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1175 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1177 // Finally, check the least significant entry.
1179 if (!UniquedVals[Multiple-1].getNode())
1180 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1181 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1183 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1186 if (!UniquedVals[Multiple-1].getNode())
1187 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1188 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1189 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1190 return DAG.getTargetConstant(Val, MVT::i32);
1196 // Check to see if this buildvec has a single non-undef value in its elements.
1197 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1198 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1199 if (!OpVal.getNode())
1200 OpVal = N->getOperand(i);
1201 else if (OpVal != N->getOperand(i))
1205 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1207 unsigned ValSizeInBytes = EltSize;
1209 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1210 Value = CN->getZExtValue();
1211 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1212 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1213 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1216 // If the splat value is larger than the element value, then we can never do
1217 // this splat. The only case that we could fit the replicated bits into our
1218 // immediate field for would be zero, and we prefer to use vxor for it.
1219 if (ValSizeInBytes < ByteSize) return SDValue();
1221 // If the element value is larger than the splat value, cut it in half and
1222 // check to see if the two halves are equal. Continue doing this until we
1223 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1224 while (ValSizeInBytes > ByteSize) {
1225 ValSizeInBytes >>= 1;
1227 // If the top half equals the bottom half, we're still ok.
1228 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1229 (Value & ((1 << (8*ValSizeInBytes))-1)))
1233 // Properly sign extend the value.
1234 int MaskVal = SignExtend32(Value, ByteSize * 8);
1236 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1237 if (MaskVal == 0) return SDValue();
1239 // Finally, if this value fits in a 5 bit sext field, return it
1240 if (SignExtend32<5>(MaskVal) == MaskVal)
1241 return DAG.getTargetConstant(MaskVal, MVT::i32);
1245 //===----------------------------------------------------------------------===//
1246 // Addressing Mode Selection
1247 //===----------------------------------------------------------------------===//
1249 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1250 /// or 64-bit immediate, and if the value can be accurately represented as a
1251 /// sign extension from a 16-bit value. If so, this returns true and the
1253 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1254 if (!isa<ConstantSDNode>(N))
1257 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1258 if (N->getValueType(0) == MVT::i32)
1259 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1261 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1263 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1264 return isIntS16Immediate(Op.getNode(), Imm);
1268 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1269 /// can be represented as an indexed [r+r] operation. Returns false if it
1270 /// can be more efficiently represented with [r+imm].
1271 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1273 SelectionDAG &DAG) const {
1275 if (N.getOpcode() == ISD::ADD) {
1276 if (isIntS16Immediate(N.getOperand(1), imm))
1277 return false; // r+i
1278 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1279 return false; // r+i
1281 Base = N.getOperand(0);
1282 Index = N.getOperand(1);
1284 } else if (N.getOpcode() == ISD::OR) {
1285 if (isIntS16Immediate(N.getOperand(1), imm))
1286 return false; // r+i can fold it if we can.
1288 // If this is an or of disjoint bitfields, we can codegen this as an add
1289 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1291 APInt LHSKnownZero, LHSKnownOne;
1292 APInt RHSKnownZero, RHSKnownOne;
1293 DAG.computeKnownBits(N.getOperand(0),
1294 LHSKnownZero, LHSKnownOne);
1296 if (LHSKnownZero.getBoolValue()) {
1297 DAG.computeKnownBits(N.getOperand(1),
1298 RHSKnownZero, RHSKnownOne);
1299 // If all of the bits are known zero on the LHS or RHS, the add won't
1301 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1302 Base = N.getOperand(0);
1303 Index = N.getOperand(1);
1312 // If we happen to be doing an i64 load or store into a stack slot that has
1313 // less than a 4-byte alignment, then the frame-index elimination may need to
1314 // use an indexed load or store instruction (because the offset may not be a
1315 // multiple of 4). The extra register needed to hold the offset comes from the
1316 // register scavenger, and it is possible that the scavenger will need to use
1317 // an emergency spill slot. As a result, we need to make sure that a spill slot
1318 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1320 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1321 // FIXME: This does not handle the LWA case.
1325 // NOTE: We'll exclude negative FIs here, which come from argument
1326 // lowering, because there are no known test cases triggering this problem
1327 // using packed structures (or similar). We can remove this exclusion if
1328 // we find such a test case. The reason why this is so test-case driven is
1329 // because this entire 'fixup' is only to prevent crashes (from the
1330 // register scavenger) on not-really-valid inputs. For example, if we have:
1332 // %b = bitcast i1* %a to i64*
1333 // store i64* a, i64 b
1334 // then the store should really be marked as 'align 1', but is not. If it
1335 // were marked as 'align 1' then the indexed form would have been
1336 // instruction-selected initially, and the problem this 'fixup' is preventing
1337 // won't happen regardless.
1341 MachineFunction &MF = DAG.getMachineFunction();
1342 MachineFrameInfo *MFI = MF.getFrameInfo();
1344 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1348 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1349 FuncInfo->setHasNonRISpills();
1352 /// Returns true if the address N can be represented by a base register plus
1353 /// a signed 16-bit displacement [r+imm], and if it is not better
1354 /// represented as reg+reg. If Aligned is true, only accept displacements
1355 /// suitable for STD and friends, i.e. multiples of 4.
1356 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1359 bool Aligned) const {
1360 // FIXME dl should come from parent load or store, not from address
1362 // If this can be more profitably realized as r+r, fail.
1363 if (SelectAddressRegReg(N, Disp, Base, DAG))
1366 if (N.getOpcode() == ISD::ADD) {
1368 if (isIntS16Immediate(N.getOperand(1), imm) &&
1369 (!Aligned || (imm & 3) == 0)) {
1370 Disp = DAG.getTargetConstant(imm, N.getValueType());
1371 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1372 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1373 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1375 Base = N.getOperand(0);
1377 return true; // [r+i]
1378 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1379 // Match LOAD (ADD (X, Lo(G))).
1380 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1381 && "Cannot handle constant offsets yet!");
1382 Disp = N.getOperand(1).getOperand(0); // The global address.
1383 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1384 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1385 Disp.getOpcode() == ISD::TargetConstantPool ||
1386 Disp.getOpcode() == ISD::TargetJumpTable);
1387 Base = N.getOperand(0);
1388 return true; // [&g+r]
1390 } else if (N.getOpcode() == ISD::OR) {
1392 if (isIntS16Immediate(N.getOperand(1), imm) &&
1393 (!Aligned || (imm & 3) == 0)) {
1394 // If this is an or of disjoint bitfields, we can codegen this as an add
1395 // (for better address arithmetic) if the LHS and RHS of the OR are
1396 // provably disjoint.
1397 APInt LHSKnownZero, LHSKnownOne;
1398 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1400 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1401 // If all of the bits are known zero on the LHS or RHS, the add won't
1403 if (FrameIndexSDNode *FI =
1404 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1405 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1406 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1408 Base = N.getOperand(0);
1410 Disp = DAG.getTargetConstant(imm, N.getValueType());
1414 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1415 // Loading from a constant address.
1417 // If this address fits entirely in a 16-bit sext immediate field, codegen
1420 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1421 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1422 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1423 CN->getValueType(0));
1427 // Handle 32-bit sext immediates with LIS + addr mode.
1428 if ((CN->getValueType(0) == MVT::i32 ||
1429 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1430 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1431 int Addr = (int)CN->getZExtValue();
1433 // Otherwise, break this down into an LIS + disp.
1434 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1436 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1437 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1438 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1443 Disp = DAG.getTargetConstant(0, getPointerTy());
1444 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1445 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1446 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1449 return true; // [r+0]
1452 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1453 /// represented as an indexed [r+r] operation.
1454 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1456 SelectionDAG &DAG) const {
1457 // Check to see if we can easily represent this as an [r+r] address. This
1458 // will fail if it thinks that the address is more profitably represented as
1459 // reg+imm, e.g. where imm = 0.
1460 if (SelectAddressRegReg(N, Base, Index, DAG))
1463 // If the operand is an addition, always emit this as [r+r], since this is
1464 // better (for code size, and execution, as the memop does the add for free)
1465 // than emitting an explicit add.
1466 if (N.getOpcode() == ISD::ADD) {
1467 Base = N.getOperand(0);
1468 Index = N.getOperand(1);
1472 // Otherwise, do it the hard way, using R0 as the base register.
1473 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1479 /// getPreIndexedAddressParts - returns true by value, base pointer and
1480 /// offset pointer and addressing mode by reference if the node's address
1481 /// can be legally represented as pre-indexed load / store address.
1482 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1484 ISD::MemIndexedMode &AM,
1485 SelectionDAG &DAG) const {
1486 if (DisablePPCPreinc) return false;
1492 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1493 Ptr = LD->getBasePtr();
1494 VT = LD->getMemoryVT();
1495 Alignment = LD->getAlignment();
1496 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1497 Ptr = ST->getBasePtr();
1498 VT = ST->getMemoryVT();
1499 Alignment = ST->getAlignment();
1504 // PowerPC doesn't have preinc load/store instructions for vectors.
1508 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1510 // Common code will reject creating a pre-inc form if the base pointer
1511 // is a frame index, or if N is a store and the base pointer is either
1512 // the same as or a predecessor of the value being stored. Check for
1513 // those situations here, and try with swapped Base/Offset instead.
1516 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1519 SDValue Val = cast<StoreSDNode>(N)->getValue();
1520 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1525 std::swap(Base, Offset);
1531 // LDU/STU can only handle immediates that are a multiple of 4.
1532 if (VT != MVT::i64) {
1533 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1536 // LDU/STU need an address with at least 4-byte alignment.
1540 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1544 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1545 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1546 // sext i32 to i64 when addr mode is r+i.
1547 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1548 LD->getExtensionType() == ISD::SEXTLOAD &&
1549 isa<ConstantSDNode>(Offset))
1557 //===----------------------------------------------------------------------===//
1558 // LowerOperation implementation
1559 //===----------------------------------------------------------------------===//
1561 /// GetLabelAccessInfo - Return true if we should reference labels using a
1562 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1563 static bool GetLabelAccessInfo(const TargetMachine &TM,
1564 const PPCSubtarget &Subtarget,
1565 unsigned &HiOpFlags, unsigned &LoOpFlags,
1566 const GlobalValue *GV = nullptr) {
1567 HiOpFlags = PPCII::MO_HA;
1568 LoOpFlags = PPCII::MO_LO;
1570 // Don't use the pic base if not in PIC relocation model.
1571 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1574 HiOpFlags |= PPCII::MO_PIC_FLAG;
1575 LoOpFlags |= PPCII::MO_PIC_FLAG;
1578 // If this is a reference to a global value that requires a non-lazy-ptr, make
1579 // sure that instruction lowering adds it.
1580 if (GV && Subtarget.hasLazyResolverStub(GV, TM)) {
1581 HiOpFlags |= PPCII::MO_NLP_FLAG;
1582 LoOpFlags |= PPCII::MO_NLP_FLAG;
1584 if (GV->hasHiddenVisibility()) {
1585 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1586 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1593 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1594 SelectionDAG &DAG) {
1595 EVT PtrVT = HiPart.getValueType();
1596 SDValue Zero = DAG.getConstant(0, PtrVT);
1599 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1600 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1602 // With PIC, the first instruction is actually "GR+hi(&G)".
1604 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1605 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1607 // Generate non-pic code that has direct accesses to the constant pool.
1608 // The address of the global is just (hi(&g)+lo(&g)).
1609 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1612 static void setUsesTOCBasePtr(MachineFunction &MF) {
1613 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1614 FuncInfo->setUsesTOCBasePtr();
1617 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1618 setUsesTOCBasePtr(DAG.getMachineFunction());
1621 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1622 SelectionDAG &DAG) const {
1623 EVT PtrVT = Op.getValueType();
1624 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1625 const Constant *C = CP->getConstVal();
1627 // 64-bit SVR4 ABI code is always position-independent.
1628 // The actual address of the GlobalValue is stored in the TOC.
1629 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1630 setUsesTOCBasePtr(DAG);
1631 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1632 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1633 DAG.getRegister(PPC::X2, MVT::i64));
1636 unsigned MOHiFlag, MOLoFlag;
1638 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1640 if (isPIC && Subtarget.isSVR4ABI()) {
1641 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1642 PPCII::MO_PIC_FLAG);
1644 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1645 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1649 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1651 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1652 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1655 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1656 EVT PtrVT = Op.getValueType();
1657 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1659 // 64-bit SVR4 ABI code is always position-independent.
1660 // The actual address of the GlobalValue is stored in the TOC.
1661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1662 setUsesTOCBasePtr(DAG);
1663 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1664 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1665 DAG.getRegister(PPC::X2, MVT::i64));
1668 unsigned MOHiFlag, MOLoFlag;
1670 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1672 if (isPIC && Subtarget.isSVR4ABI()) {
1673 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1674 PPCII::MO_PIC_FLAG);
1676 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1677 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1680 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1681 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1682 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1685 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1689 const BlockAddress *BA = BASDN->getBlockAddress();
1691 // 64-bit SVR4 ABI code is always position-independent.
1692 // The actual BlockAddress is stored in the TOC.
1693 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1694 setUsesTOCBasePtr(DAG);
1695 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1702 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1703 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1704 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1705 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1708 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1709 SelectionDAG &DAG) const {
1711 // FIXME: TLS addresses currently use medium model code sequences,
1712 // which is the most useful form. Eventually support for small and
1713 // large models could be added if users need it, at the cost of
1714 // additional complexity.
1715 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1717 const GlobalValue *GV = GA->getGlobal();
1718 EVT PtrVT = getPointerTy();
1719 bool is64bit = Subtarget.isPPC64();
1720 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1721 PICLevel::Level picLevel = M->getPICLevel();
1723 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1725 if (Model == TLSModel::LocalExec) {
1726 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1727 PPCII::MO_TPREL_HA);
1728 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 PPCII::MO_TPREL_LO);
1730 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1731 is64bit ? MVT::i64 : MVT::i32);
1732 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1733 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1736 if (Model == TLSModel::InitialExec) {
1737 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1738 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1742 setUsesTOCBasePtr(DAG);
1743 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1744 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1745 PtrVT, GOTReg, TGA);
1747 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1748 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1749 PtrVT, TGA, GOTPtr);
1750 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1753 if (Model == TLSModel::GeneralDynamic) {
1754 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1757 setUsesTOCBasePtr(DAG);
1758 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1759 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1762 if (picLevel == PICLevel::Small)
1763 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1765 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1767 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
1771 if (Model == TLSModel::LocalDynamic) {
1772 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1775 setUsesTOCBasePtr(DAG);
1776 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1777 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1780 if (picLevel == PICLevel::Small)
1781 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1783 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1785 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
1786 PtrVT, GOTPtr, TGA, TGA);
1787 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
1788 PtrVT, TLSAddr, TGA);
1789 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1792 llvm_unreachable("Unknown TLS model!");
1795 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1796 SelectionDAG &DAG) const {
1797 EVT PtrVT = Op.getValueType();
1798 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1800 const GlobalValue *GV = GSDN->getGlobal();
1802 // 64-bit SVR4 ABI code is always position-independent.
1803 // The actual address of the GlobalValue is stored in the TOC.
1804 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1805 setUsesTOCBasePtr(DAG);
1806 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1807 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1808 DAG.getRegister(PPC::X2, MVT::i64));
1811 unsigned MOHiFlag, MOLoFlag;
1813 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
1815 if (isPIC && Subtarget.isSVR4ABI()) {
1816 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1818 PPCII::MO_PIC_FLAG);
1819 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1820 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1824 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1826 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1828 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1830 // If the global reference is actually to a non-lazy-pointer, we have to do an
1831 // extra load to get the address of the global.
1832 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1833 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1834 false, false, false, 0);
1838 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1839 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1842 if (Op.getValueType() == MVT::v2i64) {
1843 // When the operands themselves are v2i64 values, we need to do something
1844 // special because VSX has no underlying comparison operations for these.
1845 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1846 // Equality can be handled by casting to the legal type for Altivec
1847 // comparisons, everything else needs to be expanded.
1848 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1849 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1850 DAG.getSetCC(dl, MVT::v4i32,
1851 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1852 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1859 // We handle most of these in the usual way.
1863 // If we're comparing for equality to zero, expose the fact that this is
1864 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1865 // fold the new nodes.
1866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1867 if (C->isNullValue() && CC == ISD::SETEQ) {
1868 EVT VT = Op.getOperand(0).getValueType();
1869 SDValue Zext = Op.getOperand(0);
1870 if (VT.bitsLT(MVT::i32)) {
1872 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1874 unsigned Log2b = Log2_32(VT.getSizeInBits());
1875 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1876 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1877 DAG.getConstant(Log2b, MVT::i32));
1878 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1880 // Leave comparisons against 0 and -1 alone for now, since they're usually
1881 // optimized. FIXME: revisit this when we can custom lower all setcc
1883 if (C->isAllOnesValue() || C->isNullValue())
1887 // If we have an integer seteq/setne, turn it into a compare against zero
1888 // by xor'ing the rhs with the lhs, which is faster than setting a
1889 // condition register, reading it back out, and masking the correct bit. The
1890 // normal approach here uses sub to do this instead of xor. Using xor exposes
1891 // the result to other bit-twiddling opportunities.
1892 EVT LHSVT = Op.getOperand(0).getValueType();
1893 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1894 EVT VT = Op.getValueType();
1895 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1897 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1902 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1903 const PPCSubtarget &Subtarget) const {
1904 SDNode *Node = Op.getNode();
1905 EVT VT = Node->getValueType(0);
1906 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1907 SDValue InChain = Node->getOperand(0);
1908 SDValue VAListPtr = Node->getOperand(1);
1909 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1912 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1915 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1916 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1917 false, false, false, 0);
1918 InChain = GprIndex.getValue(1);
1920 if (VT == MVT::i64) {
1921 // Check if GprIndex is even
1922 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1923 DAG.getConstant(1, MVT::i32));
1924 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1925 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1926 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1927 DAG.getConstant(1, MVT::i32));
1928 // Align GprIndex to be even if it isn't
1929 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1933 // fpr index is 1 byte after gpr
1934 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1935 DAG.getConstant(1, MVT::i32));
1938 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1939 FprPtr, MachinePointerInfo(SV), MVT::i8,
1940 false, false, false, 0);
1941 InChain = FprIndex.getValue(1);
1943 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1944 DAG.getConstant(8, MVT::i32));
1946 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1947 DAG.getConstant(4, MVT::i32));
1950 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1951 MachinePointerInfo(), false, false,
1953 InChain = OverflowArea.getValue(1);
1955 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1956 MachinePointerInfo(), false, false,
1958 InChain = RegSaveArea.getValue(1);
1960 // select overflow_area if index > 8
1961 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1962 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1964 // adjustment constant gpr_index * 4/8
1965 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1966 VT.isInteger() ? GprIndex : FprIndex,
1967 DAG.getConstant(VT.isInteger() ? 4 : 8,
1970 // OurReg = RegSaveArea + RegConstant
1971 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1974 // Floating types are 32 bytes into RegSaveArea
1975 if (VT.isFloatingPoint())
1976 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1977 DAG.getConstant(32, MVT::i32));
1979 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1980 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1981 VT.isInteger() ? GprIndex : FprIndex,
1982 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1985 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1986 VT.isInteger() ? VAListPtr : FprPtr,
1987 MachinePointerInfo(SV),
1988 MVT::i8, false, false, 0);
1990 // determine if we should load from reg_save_area or overflow_area
1991 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1993 // increase overflow_area by 4/8 if gpr/fpr > 8
1994 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1995 DAG.getConstant(VT.isInteger() ? 4 : 8,
1998 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2001 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2003 MachinePointerInfo(),
2004 MVT::i32, false, false, 0);
2006 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2007 false, false, false, 0);
2010 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2011 const PPCSubtarget &Subtarget) const {
2012 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2014 // We have to copy the entire va_list struct:
2015 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2016 return DAG.getMemcpy(Op.getOperand(0), Op,
2017 Op.getOperand(1), Op.getOperand(2),
2018 DAG.getConstant(12, MVT::i32), 8, false, true,
2019 MachinePointerInfo(), MachinePointerInfo());
2022 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2023 SelectionDAG &DAG) const {
2024 return Op.getOperand(0);
2027 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2028 SelectionDAG &DAG) const {
2029 SDValue Chain = Op.getOperand(0);
2030 SDValue Trmp = Op.getOperand(1); // trampoline
2031 SDValue FPtr = Op.getOperand(2); // nested function
2032 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2035 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2036 bool isPPC64 = (PtrVT == MVT::i64);
2038 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2041 TargetLowering::ArgListTy Args;
2042 TargetLowering::ArgListEntry Entry;
2044 Entry.Ty = IntPtrTy;
2045 Entry.Node = Trmp; Args.push_back(Entry);
2047 // TrampSize == (isPPC64 ? 48 : 40);
2048 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2049 isPPC64 ? MVT::i64 : MVT::i32);
2050 Args.push_back(Entry);
2052 Entry.Node = FPtr; Args.push_back(Entry);
2053 Entry.Node = Nest; Args.push_back(Entry);
2055 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2056 TargetLowering::CallLoweringInfo CLI(DAG);
2057 CLI.setDebugLoc(dl).setChain(Chain)
2058 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2059 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2060 std::move(Args), 0);
2062 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2063 return CallResult.second;
2066 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2067 const PPCSubtarget &Subtarget) const {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2073 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2074 // vastart just stores the address of the VarArgsFrameIndex slot into the
2075 // memory location argument.
2076 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2077 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2078 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2079 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2080 MachinePointerInfo(SV),
2084 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2085 // We suppose the given va_list is already allocated.
2088 // char gpr; /* index into the array of 8 GPRs
2089 // * stored in the register save area
2090 // * gpr=0 corresponds to r3,
2091 // * gpr=1 to r4, etc.
2093 // char fpr; /* index into the array of 8 FPRs
2094 // * stored in the register save area
2095 // * fpr=0 corresponds to f1,
2096 // * fpr=1 to f2, etc.
2098 // char *overflow_arg_area;
2099 // /* location on stack that holds
2100 // * the next overflow argument
2102 // char *reg_save_area;
2103 // /* where r3:r10 and f1:f8 (if saved)
2109 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2110 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2113 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2115 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2117 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2120 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2121 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2123 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2124 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2126 uint64_t FPROffset = 1;
2127 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2129 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2131 // Store first byte : number of int regs
2132 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2134 MachinePointerInfo(SV),
2135 MVT::i8, false, false, 0);
2136 uint64_t nextOffset = FPROffset;
2137 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2140 // Store second byte : number of float regs
2141 SDValue secondStore =
2142 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2143 MachinePointerInfo(SV, nextOffset), MVT::i8,
2145 nextOffset += StackOffset;
2146 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2148 // Store second word : arguments given on stack
2149 SDValue thirdStore =
2150 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2151 MachinePointerInfo(SV, nextOffset),
2153 nextOffset += FrameOffset;
2154 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2156 // Store third word : arguments given in registers
2157 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2158 MachinePointerInfo(SV, nextOffset),
2163 #include "PPCGenCallingConv.inc"
2165 // Function whose sole purpose is to kill compiler warnings
2166 // stemming from unused functions included from PPCGenCallingConv.inc.
2167 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2168 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2171 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2172 CCValAssign::LocInfo &LocInfo,
2173 ISD::ArgFlagsTy &ArgFlags,
2178 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2180 CCValAssign::LocInfo &LocInfo,
2181 ISD::ArgFlagsTy &ArgFlags,
2183 static const MCPhysReg ArgRegs[] = {
2184 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2185 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2187 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2189 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2191 // Skip one register if the first unallocated register has an even register
2192 // number and there are still argument registers available which have not been
2193 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2194 // need to skip a register if RegNum is odd.
2195 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2196 State.AllocateReg(ArgRegs[RegNum]);
2199 // Always return false here, as this function only makes sure that the first
2200 // unallocated register has an odd register number and does not actually
2201 // allocate a register for the current argument.
2205 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2207 CCValAssign::LocInfo &LocInfo,
2208 ISD::ArgFlagsTy &ArgFlags,
2210 static const MCPhysReg ArgRegs[] = {
2211 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2215 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2217 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2219 // If there is only one Floating-point register left we need to put both f64
2220 // values of a split ppc_fp128 value on the stack.
2221 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2222 State.AllocateReg(ArgRegs[RegNum]);
2225 // Always return false here, as this function only makes sure that the two f64
2226 // values a ppc_fp128 value is split into are both passed in registers or both
2227 // passed on the stack and does not actually allocate a register for the
2228 // current argument.
2232 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2234 static const MCPhysReg *GetFPR() {
2235 static const MCPhysReg FPR[] = {
2236 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2237 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2243 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2245 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2246 unsigned PtrByteSize) {
2247 unsigned ArgSize = ArgVT.getStoreSize();
2248 if (Flags.isByVal())
2249 ArgSize = Flags.getByValSize();
2251 // Round up to multiples of the pointer size, except for array members,
2252 // which are always packed.
2253 if (!Flags.isInConsecutiveRegs())
2254 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2259 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2261 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2262 ISD::ArgFlagsTy Flags,
2263 unsigned PtrByteSize) {
2264 unsigned Align = PtrByteSize;
2266 // Altivec parameters are padded to a 16 byte boundary.
2267 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2268 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2269 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2272 // ByVal parameters are aligned as requested.
2273 if (Flags.isByVal()) {
2274 unsigned BVAlign = Flags.getByValAlign();
2275 if (BVAlign > PtrByteSize) {
2276 if (BVAlign % PtrByteSize != 0)
2278 "ByVal alignment is not a multiple of the pointer size");
2284 // Array members are always packed to their original alignment.
2285 if (Flags.isInConsecutiveRegs()) {
2286 // If the array member was split into multiple registers, the first
2287 // needs to be aligned to the size of the full type. (Except for
2288 // ppcf128, which is only aligned as its f64 components.)
2289 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2290 Align = OrigVT.getStoreSize();
2292 Align = ArgVT.getStoreSize();
2298 /// CalculateStackSlotUsed - Return whether this argument will use its
2299 /// stack slot (instead of being passed in registers). ArgOffset,
2300 /// AvailableFPRs, and AvailableVRs must hold the current argument
2301 /// position, and will be updated to account for this argument.
2302 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2303 ISD::ArgFlagsTy Flags,
2304 unsigned PtrByteSize,
2305 unsigned LinkageSize,
2306 unsigned ParamAreaSize,
2307 unsigned &ArgOffset,
2308 unsigned &AvailableFPRs,
2309 unsigned &AvailableVRs) {
2310 bool UseMemory = false;
2312 // Respect alignment of argument on the stack.
2314 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2315 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2316 // If there's no space left in the argument save area, we must
2317 // use memory (this check also catches zero-sized arguments).
2318 if (ArgOffset >= LinkageSize + ParamAreaSize)
2321 // Allocate argument on the stack.
2322 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2323 if (Flags.isInConsecutiveRegsLast())
2324 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2325 // If we overran the argument save area, we must use memory
2326 // (this check catches arguments passed partially in memory)
2327 if (ArgOffset > LinkageSize + ParamAreaSize)
2330 // However, if the argument is actually passed in an FPR or a VR,
2331 // we don't use memory after all.
2332 if (!Flags.isByVal()) {
2333 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2334 if (AvailableFPRs > 0) {
2338 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2339 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2340 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2341 if (AvailableVRs > 0) {
2350 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2351 /// ensure minimum alignment required for target.
2352 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2353 unsigned NumBytes) {
2354 unsigned TargetAlign = Lowering->getStackAlignment();
2355 unsigned AlignMask = TargetAlign - 1;
2356 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2361 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2362 CallingConv::ID CallConv, bool isVarArg,
2363 const SmallVectorImpl<ISD::InputArg>
2365 SDLoc dl, SelectionDAG &DAG,
2366 SmallVectorImpl<SDValue> &InVals)
2368 if (Subtarget.isSVR4ABI()) {
2369 if (Subtarget.isPPC64())
2370 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2373 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2376 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2382 PPCTargetLowering::LowerFormalArguments_32SVR4(
2384 CallingConv::ID CallConv, bool isVarArg,
2385 const SmallVectorImpl<ISD::InputArg>
2387 SDLoc dl, SelectionDAG &DAG,
2388 SmallVectorImpl<SDValue> &InVals) const {
2390 // 32-bit SVR4 ABI Stack Frame Layout:
2391 // +-----------------------------------+
2392 // +--> | Back chain |
2393 // | +-----------------------------------+
2394 // | | Floating-point register save area |
2395 // | +-----------------------------------+
2396 // | | General register save area |
2397 // | +-----------------------------------+
2398 // | | CR save word |
2399 // | +-----------------------------------+
2400 // | | VRSAVE save word |
2401 // | +-----------------------------------+
2402 // | | Alignment padding |
2403 // | +-----------------------------------+
2404 // | | Vector register save area |
2405 // | +-----------------------------------+
2406 // | | Local variable space |
2407 // | +-----------------------------------+
2408 // | | Parameter list area |
2409 // | +-----------------------------------+
2410 // | | LR save word |
2411 // | +-----------------------------------+
2412 // SP--> +--- | Back chain |
2413 // +-----------------------------------+
2416 // System V Application Binary Interface PowerPC Processor Supplement
2417 // AltiVec Technology Programming Interface Manual
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2423 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2424 // Potential tail calls could cause overwriting of argument stack slots.
2425 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2426 (CallConv == CallingConv::Fast));
2427 unsigned PtrByteSize = 4;
2429 // Assign locations to all of the incoming arguments.
2430 SmallVector<CCValAssign, 16> ArgLocs;
2431 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2434 // Reserve space for the linkage area on the stack.
2435 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2436 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2438 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2440 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2441 CCValAssign &VA = ArgLocs[i];
2443 // Arguments stored in registers.
2444 if (VA.isRegLoc()) {
2445 const TargetRegisterClass *RC;
2446 EVT ValVT = VA.getValVT();
2448 switch (ValVT.getSimpleVT().SimpleTy) {
2450 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2453 RC = &PPC::GPRCRegClass;
2456 RC = &PPC::F4RCRegClass;
2459 if (Subtarget.hasVSX())
2460 RC = &PPC::VSFRCRegClass;
2462 RC = &PPC::F8RCRegClass;
2468 RC = &PPC::VRRCRegClass;
2472 RC = &PPC::VSHRCRegClass;
2476 // Transform the arguments stored in physical registers into virtual ones.
2477 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2478 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2479 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2481 if (ValVT == MVT::i1)
2482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2484 InVals.push_back(ArgValue);
2486 // Argument stored in memory.
2487 assert(VA.isMemLoc());
2489 unsigned ArgSize = VA.getLocVT().getStoreSize();
2490 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2493 // Create load nodes to retrieve arguments from the stack.
2494 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2495 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2496 MachinePointerInfo(),
2497 false, false, false, 0));
2501 // Assign locations to all of the incoming aggregate by value arguments.
2502 // Aggregates passed by value are stored in the local variable space of the
2503 // caller's stack frame, right above the parameter list area.
2504 SmallVector<CCValAssign, 16> ByValArgLocs;
2505 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2506 ByValArgLocs, *DAG.getContext());
2508 // Reserve stack space for the allocations in CCInfo.
2509 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2511 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2513 // Area that is at least reserved in the caller of this function.
2514 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2515 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2517 // Set the size that is at least reserved in caller of this function. Tail
2518 // call optimized function's reserved stack space needs to be aligned so that
2519 // taking the difference between two stack areas will result in an aligned
2522 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2523 FuncInfo->setMinReservedArea(MinReservedArea);
2525 SmallVector<SDValue, 8> MemOps;
2527 // If the function takes variable number of arguments, make a frame index for
2528 // the start of the first vararg value... for expansion of llvm.va_start.
2530 static const MCPhysReg GPArgRegs[] = {
2531 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2532 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2534 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2536 static const MCPhysReg FPArgRegs[] = {
2537 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2540 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2541 if (DisablePPCFloatInVariadic)
2544 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2546 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2549 // Make room for NumGPArgRegs and NumFPArgRegs.
2550 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2551 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2553 FuncInfo->setVarArgsStackOffset(
2554 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2555 CCInfo.getNextStackOffset(), true));
2557 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2558 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2560 // The fixed integer arguments of a variadic function are stored to the
2561 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2562 // the result of va_next.
2563 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2564 // Get an existing live-in vreg, or add a new one.
2565 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2567 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2569 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2570 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2571 MachinePointerInfo(), false, false, 0);
2572 MemOps.push_back(Store);
2573 // Increment the address by four for the next argument to store
2574 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2575 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2578 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2580 // The double arguments are stored to the VarArgsFrameIndex
2582 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2583 // Get an existing live-in vreg, or add a new one.
2584 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2586 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2589 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2590 MachinePointerInfo(), false, false, 0);
2591 MemOps.push_back(Store);
2592 // Increment the address by eight for the next argument to store
2593 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2595 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2599 if (!MemOps.empty())
2600 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2605 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2606 // value to MVT::i64 and then truncate to the correct register size.
2608 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2609 SelectionDAG &DAG, SDValue ArgVal,
2612 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2613 DAG.getValueType(ObjectVT));
2614 else if (Flags.isZExt())
2615 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2616 DAG.getValueType(ObjectVT));
2618 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2622 PPCTargetLowering::LowerFormalArguments_64SVR4(
2624 CallingConv::ID CallConv, bool isVarArg,
2625 const SmallVectorImpl<ISD::InputArg>
2627 SDLoc dl, SelectionDAG &DAG,
2628 SmallVectorImpl<SDValue> &InVals) const {
2629 // TODO: add description of PPC stack frame format, or at least some docs.
2631 bool isELFv2ABI = Subtarget.isELFv2ABI();
2632 bool isLittleEndian = Subtarget.isLittleEndian();
2633 MachineFunction &MF = DAG.getMachineFunction();
2634 MachineFrameInfo *MFI = MF.getFrameInfo();
2635 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2637 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2638 "fastcc not supported on varargs functions");
2640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2641 // Potential tail calls could cause overwriting of argument stack slots.
2642 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2643 (CallConv == CallingConv::Fast));
2644 unsigned PtrByteSize = 8;
2646 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2649 static const MCPhysReg GPR[] = {
2650 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2651 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2654 static const MCPhysReg *FPR = GetFPR();
2656 static const MCPhysReg VR[] = {
2657 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2658 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2660 static const MCPhysReg VSRH[] = {
2661 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2662 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2665 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2666 const unsigned Num_FPR_Regs = 13;
2667 const unsigned Num_VR_Regs = array_lengthof(VR);
2669 // Do a first pass over the arguments to determine whether the ABI
2670 // guarantees that our caller has allocated the parameter save area
2671 // on its stack frame. In the ELFv1 ABI, this is always the case;
2672 // in the ELFv2 ABI, it is true if this is a vararg function or if
2673 // any parameter is located in a stack slot.
2675 bool HasParameterArea = !isELFv2ABI || isVarArg;
2676 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2677 unsigned NumBytes = LinkageSize;
2678 unsigned AvailableFPRs = Num_FPR_Regs;
2679 unsigned AvailableVRs = Num_VR_Regs;
2680 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2681 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2682 PtrByteSize, LinkageSize, ParamAreaSize,
2683 NumBytes, AvailableFPRs, AvailableVRs))
2684 HasParameterArea = true;
2686 // Add DAG nodes to load the arguments or copy them out of registers. On
2687 // entry to a function on PPC, the arguments start after the linkage area,
2688 // although the first ones are often in registers.
2690 unsigned ArgOffset = LinkageSize;
2691 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2692 SmallVector<SDValue, 8> MemOps;
2693 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2694 unsigned CurArgIdx = 0;
2695 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2697 bool needsLoad = false;
2698 EVT ObjectVT = Ins[ArgNo].VT;
2699 EVT OrigVT = Ins[ArgNo].ArgVT;
2700 unsigned ObjSize = ObjectVT.getStoreSize();
2701 unsigned ArgSize = ObjSize;
2702 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2703 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2704 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2706 // We re-align the argument offset for each argument, except when using the
2707 // fast calling convention, when we need to make sure we do that only when
2708 // we'll actually use a stack slot.
2709 unsigned CurArgOffset, Align;
2710 auto ComputeArgOffset = [&]() {
2711 /* Respect alignment of argument on the stack. */
2712 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2713 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2714 CurArgOffset = ArgOffset;
2717 if (CallConv != CallingConv::Fast) {
2720 /* Compute GPR index associated with argument offset. */
2721 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2722 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2725 // FIXME the codegen can be much improved in some cases.
2726 // We do not have to keep everything in memory.
2727 if (Flags.isByVal()) {
2728 if (CallConv == CallingConv::Fast)
2731 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2732 ObjSize = Flags.getByValSize();
2733 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2734 // Empty aggregate parameters do not take up registers. Examples:
2738 // etc. However, we have to provide a place-holder in InVals, so
2739 // pretend we have an 8-byte item at the current address for that
2742 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2743 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2744 InVals.push_back(FIN);
2748 // Create a stack object covering all stack doublewords occupied
2749 // by the argument. If the argument is (fully or partially) on
2750 // the stack, or if the argument is fully in registers but the
2751 // caller has allocated the parameter save anyway, we can refer
2752 // directly to the caller's stack frame. Otherwise, create a
2753 // local copy in our own frame.
2755 if (HasParameterArea ||
2756 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2757 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2759 FI = MFI->CreateStackObject(ArgSize, Align, false);
2760 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2762 // Handle aggregates smaller than 8 bytes.
2763 if (ObjSize < PtrByteSize) {
2764 // The value of the object is its address, which differs from the
2765 // address of the enclosing doubleword on big-endian systems.
2767 if (!isLittleEndian) {
2768 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2769 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2771 InVals.push_back(Arg);
2773 if (GPR_idx != Num_GPR_Regs) {
2774 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2775 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2778 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2779 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2780 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2781 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2782 MachinePointerInfo(FuncArg),
2783 ObjType, false, false, 0);
2785 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2786 // store the whole register as-is to the parameter save area
2788 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2789 MachinePointerInfo(FuncArg),
2793 MemOps.push_back(Store);
2795 // Whether we copied from a register or not, advance the offset
2796 // into the parameter save area by a full doubleword.
2797 ArgOffset += PtrByteSize;
2801 // The value of the object is its address, which is the address of
2802 // its first stack doubleword.
2803 InVals.push_back(FIN);
2805 // Store whatever pieces of the object are in registers to memory.
2806 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2807 if (GPR_idx == Num_GPR_Regs)
2810 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2811 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2814 SDValue Off = DAG.getConstant(j, PtrVT);
2815 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2817 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2818 MachinePointerInfo(FuncArg, j),
2820 MemOps.push_back(Store);
2823 ArgOffset += ArgSize;
2827 switch (ObjectVT.getSimpleVT().SimpleTy) {
2828 default: llvm_unreachable("Unhandled argument type!");
2832 // These can be scalar arguments or elements of an integer array type
2833 // passed directly. Clang may use those instead of "byval" aggregate
2834 // types to avoid forcing arguments to memory unnecessarily.
2835 if (GPR_idx != Num_GPR_Regs) {
2836 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2837 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2839 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2840 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2841 // value to MVT::i64 and then truncate to the correct register size.
2842 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2844 if (CallConv == CallingConv::Fast)
2848 ArgSize = PtrByteSize;
2850 if (CallConv != CallingConv::Fast || needsLoad)
2856 // These can be scalar arguments or elements of a float array type
2857 // passed directly. The latter are used to implement ELFv2 homogenous
2858 // float aggregates.
2859 if (FPR_idx != Num_FPR_Regs) {
2862 if (ObjectVT == MVT::f32)
2863 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2865 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
2866 ? &PPC::VSFRCRegClass
2867 : &PPC::F8RCRegClass);
2869 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2871 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2872 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
2873 // once we support fp <-> gpr moves.
2875 // This can only ever happen in the presence of f32 array types,
2876 // since otherwise we never run out of FPRs before running out
2878 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2879 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2881 if (ObjectVT == MVT::f32) {
2882 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2883 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2884 DAG.getConstant(32, MVT::i32));
2885 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2888 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2890 if (CallConv == CallingConv::Fast)
2896 // When passing an array of floats, the array occupies consecutive
2897 // space in the argument area; only round up to the next doubleword
2898 // at the end of the array. Otherwise, each float takes 8 bytes.
2899 if (CallConv != CallingConv::Fast || needsLoad) {
2900 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2901 ArgOffset += ArgSize;
2902 if (Flags.isInConsecutiveRegsLast())
2903 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2912 // These can be scalar arguments or elements of a vector array type
2913 // passed directly. The latter are used to implement ELFv2 homogenous
2914 // vector aggregates.
2915 if (VR_idx != Num_VR_Regs) {
2916 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2917 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2918 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2919 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2922 if (CallConv == CallingConv::Fast)
2927 if (CallConv != CallingConv::Fast || needsLoad)
2932 // We need to load the argument to a virtual register if we determined
2933 // above that we ran out of physical registers of the appropriate type.
2935 if (ObjSize < ArgSize && !isLittleEndian)
2936 CurArgOffset += ArgSize - ObjSize;
2937 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2938 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2939 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2940 false, false, false, 0);
2943 InVals.push_back(ArgVal);
2946 // Area that is at least reserved in the caller of this function.
2947 unsigned MinReservedArea;
2948 if (HasParameterArea)
2949 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2951 MinReservedArea = LinkageSize;
2953 // Set the size that is at least reserved in caller of this function. Tail
2954 // call optimized functions' reserved stack space needs to be aligned so that
2955 // taking the difference between two stack areas will result in an aligned
2958 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2959 FuncInfo->setMinReservedArea(MinReservedArea);
2961 // If the function takes variable number of arguments, make a frame index for
2962 // the start of the first vararg value... for expansion of llvm.va_start.
2964 int Depth = ArgOffset;
2966 FuncInfo->setVarArgsFrameIndex(
2967 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2968 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2970 // If this function is vararg, store any remaining integer argument regs
2971 // to their spots on the stack so that they may be loaded by deferencing the
2972 // result of va_next.
2973 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2974 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2975 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2976 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2977 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2978 MachinePointerInfo(), false, false, 0);
2979 MemOps.push_back(Store);
2980 // Increment the address by four for the next argument to store
2981 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2982 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2986 if (!MemOps.empty())
2987 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2993 PPCTargetLowering::LowerFormalArguments_Darwin(
2995 CallingConv::ID CallConv, bool isVarArg,
2996 const SmallVectorImpl<ISD::InputArg>
2998 SDLoc dl, SelectionDAG &DAG,
2999 SmallVectorImpl<SDValue> &InVals) const {
3000 // TODO: add description of PPC stack frame format, or at least some docs.
3002 MachineFunction &MF = DAG.getMachineFunction();
3003 MachineFrameInfo *MFI = MF.getFrameInfo();
3004 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3006 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3007 bool isPPC64 = PtrVT == MVT::i64;
3008 // Potential tail calls could cause overwriting of argument stack slots.
3009 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3010 (CallConv == CallingConv::Fast));
3011 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3013 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
3015 unsigned ArgOffset = LinkageSize;
3016 // Area that is at least reserved in caller of this function.
3017 unsigned MinReservedArea = ArgOffset;
3019 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3020 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3021 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3023 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3024 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3025 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3028 static const MCPhysReg *FPR = GetFPR();
3030 static const MCPhysReg VR[] = {
3031 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3032 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3035 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3036 const unsigned Num_FPR_Regs = 13;
3037 const unsigned Num_VR_Regs = array_lengthof( VR);
3039 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3041 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3043 // In 32-bit non-varargs functions, the stack space for vectors is after the
3044 // stack space for non-vectors. We do not use this space unless we have
3045 // too many vectors to fit in registers, something that only occurs in
3046 // constructed examples:), but we have to walk the arglist to figure
3047 // that out...for the pathological case, compute VecArgOffset as the
3048 // start of the vector parameter area. Computing VecArgOffset is the
3049 // entire point of the following loop.
3050 unsigned VecArgOffset = ArgOffset;
3051 if (!isVarArg && !isPPC64) {
3052 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3054 EVT ObjectVT = Ins[ArgNo].VT;
3055 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3057 if (Flags.isByVal()) {
3058 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3059 unsigned ObjSize = Flags.getByValSize();
3061 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3062 VecArgOffset += ArgSize;
3066 switch(ObjectVT.getSimpleVT().SimpleTy) {
3067 default: llvm_unreachable("Unhandled argument type!");
3073 case MVT::i64: // PPC64
3075 // FIXME: We are guaranteed to be !isPPC64 at this point.
3076 // Does MVT::i64 apply?
3083 // Nothing to do, we're only looking at Nonvector args here.
3088 // We've found where the vector parameter area in memory is. Skip the
3089 // first 12 parameters; these don't use that memory.
3090 VecArgOffset = ((VecArgOffset+15)/16)*16;
3091 VecArgOffset += 12*16;
3093 // Add DAG nodes to load the arguments or copy them out of registers. On
3094 // entry to a function on PPC, the arguments start after the linkage area,
3095 // although the first ones are often in registers.
3097 SmallVector<SDValue, 8> MemOps;
3098 unsigned nAltivecParamsAtEnd = 0;
3099 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3100 unsigned CurArgIdx = 0;
3101 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3103 bool needsLoad = false;
3104 EVT ObjectVT = Ins[ArgNo].VT;
3105 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3106 unsigned ArgSize = ObjSize;
3107 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3108 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3109 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3111 unsigned CurArgOffset = ArgOffset;
3113 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3114 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3115 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3116 if (isVarArg || isPPC64) {
3117 MinReservedArea = ((MinReservedArea+15)/16)*16;
3118 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3121 } else nAltivecParamsAtEnd++;
3123 // Calculate min reserved area.
3124 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3128 // FIXME the codegen can be much improved in some cases.
3129 // We do not have to keep everything in memory.
3130 if (Flags.isByVal()) {
3131 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3132 ObjSize = Flags.getByValSize();
3133 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3134 // Objects of size 1 and 2 are right justified, everything else is
3135 // left justified. This means the memory address is adjusted forwards.
3136 if (ObjSize==1 || ObjSize==2) {
3137 CurArgOffset = CurArgOffset + (4 - ObjSize);
3139 // The value of the object is its address.
3140 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3141 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3142 InVals.push_back(FIN);
3143 if (ObjSize==1 || ObjSize==2) {
3144 if (GPR_idx != Num_GPR_Regs) {
3147 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3149 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3150 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3151 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3152 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3153 MachinePointerInfo(FuncArg),
3154 ObjType, false, false, 0);
3155 MemOps.push_back(Store);
3159 ArgOffset += PtrByteSize;
3163 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3164 // Store whatever pieces of the object are in registers
3165 // to memory. ArgOffset will be the address of the beginning
3167 if (GPR_idx != Num_GPR_Regs) {
3170 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3172 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3173 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3174 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3175 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3176 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3177 MachinePointerInfo(FuncArg, j),
3179 MemOps.push_back(Store);
3181 ArgOffset += PtrByteSize;
3183 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3190 switch (ObjectVT.getSimpleVT().SimpleTy) {
3191 default: llvm_unreachable("Unhandled argument type!");
3195 if (GPR_idx != Num_GPR_Regs) {
3196 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3197 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3199 if (ObjectVT == MVT::i1)
3200 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3205 ArgSize = PtrByteSize;
3207 // All int arguments reserve stack space in the Darwin ABI.
3208 ArgOffset += PtrByteSize;
3212 case MVT::i64: // PPC64
3213 if (GPR_idx != Num_GPR_Regs) {
3214 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3215 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3217 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3218 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3219 // value to MVT::i64 and then truncate to the correct register size.
3220 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3225 ArgSize = PtrByteSize;
3227 // All int arguments reserve stack space in the Darwin ABI.
3233 // Every 4 bytes of argument space consumes one of the GPRs available for
3234 // argument passing.
3235 if (GPR_idx != Num_GPR_Regs) {
3237 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3240 if (FPR_idx != Num_FPR_Regs) {
3243 if (ObjectVT == MVT::f32)
3244 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3246 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3248 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3254 // All FP arguments reserve stack space in the Darwin ABI.
3255 ArgOffset += isPPC64 ? 8 : ObjSize;
3261 // Note that vector arguments in registers don't reserve stack space,
3262 // except in varargs functions.
3263 if (VR_idx != Num_VR_Regs) {
3264 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3265 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3267 while ((ArgOffset % 16) != 0) {
3268 ArgOffset += PtrByteSize;
3269 if (GPR_idx != Num_GPR_Regs)
3273 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3277 if (!isVarArg && !isPPC64) {
3278 // Vectors go after all the nonvectors.
3279 CurArgOffset = VecArgOffset;
3282 // Vectors are aligned.
3283 ArgOffset = ((ArgOffset+15)/16)*16;
3284 CurArgOffset = ArgOffset;
3292 // We need to load the argument to a virtual register if we determined above
3293 // that we ran out of physical registers of the appropriate type.
3295 int FI = MFI->CreateFixedObject(ObjSize,
3296 CurArgOffset + (ArgSize - ObjSize),
3298 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3299 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3300 false, false, false, 0);
3303 InVals.push_back(ArgVal);
3306 // Allow for Altivec parameters at the end, if needed.
3307 if (nAltivecParamsAtEnd) {
3308 MinReservedArea = ((MinReservedArea+15)/16)*16;
3309 MinReservedArea += 16*nAltivecParamsAtEnd;
3312 // Area that is at least reserved in the caller of this function.
3313 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3315 // Set the size that is at least reserved in caller of this function. Tail
3316 // call optimized functions' reserved stack space needs to be aligned so that
3317 // taking the difference between two stack areas will result in an aligned
3320 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3321 FuncInfo->setMinReservedArea(MinReservedArea);
3323 // If the function takes variable number of arguments, make a frame index for
3324 // the start of the first vararg value... for expansion of llvm.va_start.
3326 int Depth = ArgOffset;
3328 FuncInfo->setVarArgsFrameIndex(
3329 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3331 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3333 // If this function is vararg, store any remaining integer argument regs
3334 // to their spots on the stack so that they may be loaded by deferencing the
3335 // result of va_next.
3336 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3340 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3342 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3344 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3345 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3346 MachinePointerInfo(), false, false, 0);
3347 MemOps.push_back(Store);
3348 // Increment the address by four for the next argument to store
3349 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3350 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3354 if (!MemOps.empty())
3355 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3360 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3361 /// adjusted to accommodate the arguments for the tailcall.
3362 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3363 unsigned ParamSize) {
3365 if (!isTailCall) return 0;
3367 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3368 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3369 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3370 // Remember only if the new adjustement is bigger.
3371 if (SPDiff < FI->getTailCallSPDelta())
3372 FI->setTailCallSPDelta(SPDiff);
3377 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3378 /// for tail call optimization. Targets which want to do tail call
3379 /// optimization should implement this function.
3381 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3382 CallingConv::ID CalleeCC,
3384 const SmallVectorImpl<ISD::InputArg> &Ins,
3385 SelectionDAG& DAG) const {
3386 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3389 // Variable argument functions are not supported.
3393 MachineFunction &MF = DAG.getMachineFunction();
3394 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3395 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3396 // Functions containing by val parameters are not supported.
3397 for (unsigned i = 0; i != Ins.size(); i++) {
3398 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3399 if (Flags.isByVal()) return false;
3402 // Non-PIC/GOT tail calls are supported.
3403 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3406 // At the moment we can only do local tail calls (in same module, hidden
3407 // or protected) if we are generating PIC.
3408 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3409 return G->getGlobal()->hasHiddenVisibility()
3410 || G->getGlobal()->hasProtectedVisibility();
3416 /// isCallCompatibleAddress - Return the immediate to use if the specified
3417 /// 32-bit value is representable in the immediate field of a BxA instruction.
3418 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3420 if (!C) return nullptr;
3422 int Addr = C->getZExtValue();
3423 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3424 SignExtend32<26>(Addr) != Addr)
3425 return nullptr; // Top 6 bits have to be sext of immediate.
3427 return DAG.getConstant((int)C->getZExtValue() >> 2,
3428 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3433 struct TailCallArgumentInfo {
3438 TailCallArgumentInfo() : FrameIdx(0) {}
3443 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3445 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3447 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3448 SmallVectorImpl<SDValue> &MemOpChains,
3450 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3451 SDValue Arg = TailCallArgs[i].Arg;
3452 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3453 int FI = TailCallArgs[i].FrameIdx;
3454 // Store relative to framepointer.
3455 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3456 MachinePointerInfo::getFixedStack(FI),
3461 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3462 /// the appropriate stack slot for the tail call optimized function call.
3463 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3464 MachineFunction &MF,
3473 // Calculate the new stack slot for the return address.
3474 int SlotSize = isPPC64 ? 8 : 4;
3475 int NewRetAddrLoc = SPDiff +
3476 MF.getSubtarget<PPCSubtarget>()
3478 ->getReturnSaveOffset();
3479 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3480 NewRetAddrLoc, true);
3481 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3482 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3483 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3484 MachinePointerInfo::getFixedStack(NewRetAddr),
3487 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3488 // slot as the FP is never overwritten.
3491 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3492 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3494 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3495 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3496 MachinePointerInfo::getFixedStack(NewFPIdx),
3503 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3504 /// the position of the argument.
3506 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3507 SDValue Arg, int SPDiff, unsigned ArgOffset,
3508 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3509 int Offset = ArgOffset + SPDiff;
3510 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3511 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3512 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3513 SDValue FIN = DAG.getFrameIndex(FI, VT);
3514 TailCallArgumentInfo Info;
3516 Info.FrameIdxOp = FIN;
3518 TailCallArguments.push_back(Info);
3521 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3522 /// stack slot. Returns the chain as result and the loaded frame pointers in
3523 /// LROpOut/FPOpout. Used when tail calling.
3524 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3532 // Load the LR and FP stack slot for later adjusting.
3533 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3534 LROpOut = getReturnAddrFrameIndex(DAG);
3535 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3536 false, false, false, 0);
3537 Chain = SDValue(LROpOut.getNode(), 1);
3539 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3540 // slot as the FP is never overwritten.
3542 FPOpOut = getFramePointerFrameIndex(DAG);
3543 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3544 false, false, false, 0);
3545 Chain = SDValue(FPOpOut.getNode(), 1);
3551 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3552 /// by "Src" to address "Dst" of size "Size". Alignment information is
3553 /// specified by the specific parameter attribute. The copy will be passed as
3554 /// a byval function parameter.
3555 /// Sometimes what we are copying is the end of a larger object, the part that
3556 /// does not fit in registers.
3558 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3559 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3561 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3562 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3563 false, false, MachinePointerInfo(),
3564 MachinePointerInfo());
3567 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3570 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3571 SDValue Arg, SDValue PtrOff, int SPDiff,
3572 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3573 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3574 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3576 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3581 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3583 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3584 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3585 DAG.getConstant(ArgOffset, PtrVT));
3587 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3588 MachinePointerInfo(), false, false, 0));
3589 // Calculate and remember argument location.
3590 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3595 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3596 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3597 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3598 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3599 MachineFunction &MF = DAG.getMachineFunction();
3601 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3602 // might overwrite each other in case of tail call optimization.
3603 SmallVector<SDValue, 8> MemOpChains2;
3604 // Do not flag preceding copytoreg stuff together with the following stuff.
3606 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3608 if (!MemOpChains2.empty())
3609 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3611 // Store the return address to the appropriate stack slot.
3612 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3613 isPPC64, isDarwinABI, dl);
3615 // Emit callseq_end just before tailcall node.
3616 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3617 DAG.getIntPtrConstant(0, true), InFlag, dl);
3618 InFlag = Chain.getValue(1);
3621 // Is this global address that of a function that can be called by name? (as
3622 // opposed to something that must hold a descriptor for an indirect call).
3623 static bool isFunctionGlobalAddress(SDValue Callee) {
3624 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3625 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3626 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3629 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3636 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3637 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3638 bool isTailCall, bool IsPatchPoint,
3639 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3640 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3641 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3643 bool isPPC64 = Subtarget.isPPC64();
3644 bool isSVR4ABI = Subtarget.isSVR4ABI();
3645 bool isELFv2ABI = Subtarget.isELFv2ABI();
3647 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3648 NodeTys.push_back(MVT::Other); // Returns a chain
3649 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3651 unsigned CallOpc = PPCISD::CALL;
3653 bool needIndirectCall = true;
3654 if (!isSVR4ABI || !isPPC64)
3655 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3656 // If this is an absolute destination address, use the munged value.
3657 Callee = SDValue(Dest, 0);
3658 needIndirectCall = false;
3661 if (isFunctionGlobalAddress(Callee)) {
3662 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3663 // A call to a TLS address is actually an indirect call to a
3664 // thread-specific pointer.
3665 unsigned OpFlags = 0;
3666 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3667 (Subtarget.getTargetTriple().isMacOSX() &&
3668 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3669 (G->getGlobal()->isDeclaration() ||
3670 G->getGlobal()->isWeakForLinker())) ||
3671 (Subtarget.isTargetELF() && !isPPC64 &&
3672 !G->getGlobal()->hasLocalLinkage() &&
3673 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3674 // PC-relative references to external symbols should go through $stub,
3675 // unless we're building with the leopard linker or later, which
3676 // automatically synthesizes these stubs.
3677 OpFlags = PPCII::MO_PLT_OR_STUB;
3680 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3681 // every direct call is) turn it into a TargetGlobalAddress /
3682 // TargetExternalSymbol node so that legalize doesn't hack it.
3683 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3684 Callee.getValueType(), 0, OpFlags);
3685 needIndirectCall = false;
3688 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3689 unsigned char OpFlags = 0;
3691 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3692 (Subtarget.getTargetTriple().isMacOSX() &&
3693 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3694 (Subtarget.isTargetELF() && !isPPC64 &&
3695 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3696 // PC-relative references to external symbols should go through $stub,
3697 // unless we're building with the leopard linker or later, which
3698 // automatically synthesizes these stubs.
3699 OpFlags = PPCII::MO_PLT_OR_STUB;
3702 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3704 needIndirectCall = false;
3708 // We'll form an invalid direct call when lowering a patchpoint; the full
3709 // sequence for an indirect call is complicated, and many of the
3710 // instructions introduced might have side effects (and, thus, can't be
3711 // removed later). The call itself will be removed as soon as the
3712 // argument/return lowering is complete, so the fact that it has the wrong
3713 // kind of operands should not really matter.
3714 needIndirectCall = false;
3717 if (needIndirectCall) {
3718 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3719 // to do the call, we can't use PPCISD::CALL.
3720 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3722 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3723 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3724 // entry point, but to the function descriptor (the function entry point
3725 // address is part of the function descriptor though).
3726 // The function descriptor is a three doubleword structure with the
3727 // following fields: function entry point, TOC base address and
3728 // environment pointer.
3729 // Thus for a call through a function pointer, the following actions need
3731 // 1. Save the TOC of the caller in the TOC save area of its stack
3732 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3733 // 2. Load the address of the function entry point from the function
3735 // 3. Load the TOC of the callee from the function descriptor into r2.
3736 // 4. Load the environment pointer from the function descriptor into
3738 // 5. Branch to the function entry point address.
3739 // 6. On return of the callee, the TOC of the caller needs to be
3740 // restored (this is done in FinishCall()).
3742 // The loads are scheduled at the beginning of the call sequence, and the
3743 // register copies are flagged together to ensure that no other
3744 // operations can be scheduled in between. E.g. without flagging the
3745 // copies together, a TOC access in the caller could be scheduled between
3746 // the assignment of the callee TOC and the branch to the callee, which
3747 // results in the TOC access going through the TOC of the callee instead
3748 // of going through the TOC of the caller, which leads to incorrect code.
3750 // Load the address of the function entry point from the function
3752 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3753 if (LDChain.getValueType() == MVT::Glue)
3754 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3756 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3758 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3759 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3760 false, false, LoadsInv, 8);
3762 // Load environment pointer into r11.
3763 SDValue PtrOff = DAG.getIntPtrConstant(16);
3764 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3765 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3766 MPI.getWithOffset(16), false, false,
3769 SDValue TOCOff = DAG.getIntPtrConstant(8);
3770 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3771 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3772 MPI.getWithOffset(8), false, false,
3775 setUsesTOCBasePtr(DAG);
3776 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3778 Chain = TOCVal.getValue(0);
3779 InFlag = TOCVal.getValue(1);
3781 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3784 Chain = EnvVal.getValue(0);
3785 InFlag = EnvVal.getValue(1);
3787 MTCTROps[0] = Chain;
3788 MTCTROps[1] = LoadFuncPtr;
3789 MTCTROps[2] = InFlag;
3792 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3793 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3794 InFlag = Chain.getValue(1);
3797 NodeTys.push_back(MVT::Other);
3798 NodeTys.push_back(MVT::Glue);
3799 Ops.push_back(Chain);
3800 CallOpc = PPCISD::BCTRL;
3801 Callee.setNode(nullptr);
3802 // Add use of X11 (holding environment pointer)
3803 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3804 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3805 // Add CTR register as callee so a bctr can be emitted later.
3807 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3810 // If this is a direct call, pass the chain and the callee.
3811 if (Callee.getNode()) {
3812 Ops.push_back(Chain);
3813 Ops.push_back(Callee);
3815 // If this is a tail call add stack pointer delta.
3817 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3819 // Add argument registers to the end of the list so that they are known live
3821 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3822 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3823 RegsToPass[i].second.getValueType()));
3825 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
3827 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
3828 setUsesTOCBasePtr(DAG);
3829 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3836 bool isLocalCall(const SDValue &Callee)
3838 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3839 return !G->getGlobal()->isDeclaration() &&
3840 !G->getGlobal()->isWeakForLinker();
3845 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3846 CallingConv::ID CallConv, bool isVarArg,
3847 const SmallVectorImpl<ISD::InputArg> &Ins,
3848 SDLoc dl, SelectionDAG &DAG,
3849 SmallVectorImpl<SDValue> &InVals) const {
3851 SmallVector<CCValAssign, 16> RVLocs;
3852 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3854 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3856 // Copy all of the result registers out of their specified physreg.
3857 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3858 CCValAssign &VA = RVLocs[i];
3859 assert(VA.isRegLoc() && "Can only return in registers!");
3861 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3862 VA.getLocReg(), VA.getLocVT(), InFlag);
3863 Chain = Val.getValue(1);
3864 InFlag = Val.getValue(2);
3866 switch (VA.getLocInfo()) {
3867 default: llvm_unreachable("Unknown loc info!");
3868 case CCValAssign::Full: break;
3869 case CCValAssign::AExt:
3870 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3872 case CCValAssign::ZExt:
3873 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3874 DAG.getValueType(VA.getValVT()));
3875 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3877 case CCValAssign::SExt:
3878 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3879 DAG.getValueType(VA.getValVT()));
3880 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3884 InVals.push_back(Val);
3891 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3892 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3894 SmallVector<std::pair<unsigned, SDValue>, 8>
3896 SDValue InFlag, SDValue Chain,
3897 SDValue CallSeqStart, SDValue &Callee,
3898 int SPDiff, unsigned NumBytes,
3899 const SmallVectorImpl<ISD::InputArg> &Ins,
3900 SmallVectorImpl<SDValue> &InVals,
3901 ImmutableCallSite *CS) const {
3903 bool isELFv2ABI = Subtarget.isELFv2ABI();
3904 std::vector<EVT> NodeTys;
3905 SmallVector<SDValue, 8> Ops;
3906 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3907 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3908 Ops, NodeTys, CS, Subtarget);
3910 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3911 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3912 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3914 // When performing tail call optimization the callee pops its arguments off
3915 // the stack. Account for this here so these bytes can be pushed back on in
3916 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3917 int BytesCalleePops =
3918 (CallConv == CallingConv::Fast &&
3919 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3921 // Add a register mask operand representing the call-preserved registers.
3922 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3923 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3924 assert(Mask && "Missing call preserved mask for calling convention");
3925 Ops.push_back(DAG.getRegisterMask(Mask));
3927 if (InFlag.getNode())
3928 Ops.push_back(InFlag);
3932 assert(((Callee.getOpcode() == ISD::Register &&
3933 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3934 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3935 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3936 isa<ConstantSDNode>(Callee)) &&
3937 "Expecting an global address, external symbol, absolute value or register");
3939 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3942 // Add a NOP immediately after the branch instruction when using the 64-bit
3943 // SVR4 ABI. At link time, if caller and callee are in a different module and
3944 // thus have a different TOC, the call will be replaced with a call to a stub
3945 // function which saves the current TOC, loads the TOC of the callee and
3946 // branches to the callee. The NOP will be replaced with a load instruction
3947 // which restores the TOC of the caller from the TOC save slot of the current
3948 // stack frame. If caller and callee belong to the same module (and have the
3949 // same TOC), the NOP will remain unchanged.
3951 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3953 if (CallOpc == PPCISD::BCTRL) {
3954 // This is a call through a function pointer.
3955 // Restore the caller TOC from the save area into R2.
3956 // See PrepareCall() for more information about calls through function
3957 // pointers in the 64-bit SVR4 ABI.
3958 // We are using a target-specific load with r2 hard coded, because the
3959 // result of a target-independent load would never go directly into r2,
3960 // since r2 is a reserved register (which prevents the register allocator
3961 // from allocating it), resulting in an additional register being
3962 // allocated and an unnecessary move instruction being generated.
3963 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3965 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3966 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3967 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3968 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3969 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3971 // The address needs to go after the chain input but before the flag (or
3972 // any other variadic arguments).
3973 Ops.insert(std::next(Ops.begin()), AddTOC);
3974 } else if ((CallOpc == PPCISD::CALL) &&
3975 (!isLocalCall(Callee) ||
3976 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
3977 // Otherwise insert NOP for non-local calls.
3978 CallOpc = PPCISD::CALL_NOP;
3981 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3982 InFlag = Chain.getValue(1);
3984 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3985 DAG.getIntPtrConstant(BytesCalleePops, true),
3988 InFlag = Chain.getValue(1);
3990 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3991 Ins, dl, DAG, InVals);
3995 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3996 SmallVectorImpl<SDValue> &InVals) const {
3997 SelectionDAG &DAG = CLI.DAG;
3999 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4000 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4001 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4002 SDValue Chain = CLI.Chain;
4003 SDValue Callee = CLI.Callee;
4004 bool &isTailCall = CLI.IsTailCall;
4005 CallingConv::ID CallConv = CLI.CallConv;
4006 bool isVarArg = CLI.IsVarArg;
4007 bool IsPatchPoint = CLI.IsPatchPoint;
4008 ImmutableCallSite *CS = CLI.CS;
4011 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4014 if (!isTailCall && CS && CS->isMustTailCall())
4015 report_fatal_error("failed to perform tail call elimination on a call "
4016 "site marked musttail");
4018 if (Subtarget.isSVR4ABI()) {
4019 if (Subtarget.isPPC64())
4020 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4021 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4022 dl, DAG, InVals, CS);
4024 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4025 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4026 dl, DAG, InVals, CS);
4029 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4030 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4031 dl, DAG, InVals, CS);
4035 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4036 CallingConv::ID CallConv, bool isVarArg,
4037 bool isTailCall, bool IsPatchPoint,
4038 const SmallVectorImpl<ISD::OutputArg> &Outs,
4039 const SmallVectorImpl<SDValue> &OutVals,
4040 const SmallVectorImpl<ISD::InputArg> &Ins,
4041 SDLoc dl, SelectionDAG &DAG,
4042 SmallVectorImpl<SDValue> &InVals,
4043 ImmutableCallSite *CS) const {
4044 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4045 // of the 32-bit SVR4 ABI stack frame layout.
4047 assert((CallConv == CallingConv::C ||
4048 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4050 unsigned PtrByteSize = 4;
4052 MachineFunction &MF = DAG.getMachineFunction();
4054 // Mark this function as potentially containing a function that contains a
4055 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4056 // and restoring the callers stack pointer in this functions epilog. This is
4057 // done because by tail calling the called function might overwrite the value
4058 // in this function's (MF) stack pointer stack slot 0(SP).
4059 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4060 CallConv == CallingConv::Fast)
4061 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4063 // Count how many bytes are to be pushed on the stack, including the linkage
4064 // area, parameter list area and the part of the local variable space which
4065 // contains copies of aggregates which are passed by value.
4067 // Assign locations to all of the outgoing arguments.
4068 SmallVector<CCValAssign, 16> ArgLocs;
4069 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4072 // Reserve space for the linkage area on the stack.
4073 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4077 // Handle fixed and variable vector arguments differently.
4078 // Fixed vector arguments go into registers as long as registers are
4079 // available. Variable vector arguments always go into memory.
4080 unsigned NumArgs = Outs.size();
4082 for (unsigned i = 0; i != NumArgs; ++i) {
4083 MVT ArgVT = Outs[i].VT;
4084 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4087 if (Outs[i].IsFixed) {
4088 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4091 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4097 errs() << "Call operand #" << i << " has unhandled type "
4098 << EVT(ArgVT).getEVTString() << "\n";
4100 llvm_unreachable(nullptr);
4104 // All arguments are treated the same.
4105 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4108 // Assign locations to all of the outgoing aggregate by value arguments.
4109 SmallVector<CCValAssign, 16> ByValArgLocs;
4110 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4111 ByValArgLocs, *DAG.getContext());
4113 // Reserve stack space for the allocations in CCInfo.
4114 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4116 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4118 // Size of the linkage area, parameter list area and the part of the local
4119 // space variable where copies of aggregates which are passed by value are
4121 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4123 // Calculate by how many bytes the stack has to be adjusted in case of tail
4124 // call optimization.
4125 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4127 // Adjust the stack pointer for the new arguments...
4128 // These operations are automatically eliminated by the prolog/epilog pass
4129 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4131 SDValue CallSeqStart = Chain;
4133 // Load the return address and frame pointer so it can be moved somewhere else
4136 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4139 // Set up a copy of the stack pointer for use loading and storing any
4140 // arguments that may not fit in the registers available for argument
4142 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4144 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4145 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4146 SmallVector<SDValue, 8> MemOpChains;
4148 bool seenFloatArg = false;
4149 // Walk the register/memloc assignments, inserting copies/loads.
4150 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4153 CCValAssign &VA = ArgLocs[i];
4154 SDValue Arg = OutVals[i];
4155 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4157 if (Flags.isByVal()) {
4158 // Argument is an aggregate which is passed by value, thus we need to
4159 // create a copy of it in the local variable space of the current stack
4160 // frame (which is the stack frame of the caller) and pass the address of
4161 // this copy to the callee.
4162 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4163 CCValAssign &ByValVA = ByValArgLocs[j++];
4164 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4166 // Memory reserved in the local variable space of the callers stack frame.
4167 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4169 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4170 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4172 // Create a copy of the argument in the local area of the current
4174 SDValue MemcpyCall =
4175 CreateCopyOfByValArgument(Arg, PtrOff,
4176 CallSeqStart.getNode()->getOperand(0),
4179 // This must go outside the CALLSEQ_START..END.
4180 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4181 CallSeqStart.getNode()->getOperand(1),
4183 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4184 NewCallSeqStart.getNode());
4185 Chain = CallSeqStart = NewCallSeqStart;
4187 // Pass the address of the aggregate copy on the stack either in a
4188 // physical register or in the parameter list area of the current stack
4189 // frame to the callee.
4193 if (VA.isRegLoc()) {
4194 if (Arg.getValueType() == MVT::i1)
4195 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4197 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4198 // Put argument in a physical register.
4199 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4201 // Put argument in the parameter list area of the current stack frame.
4202 assert(VA.isMemLoc());
4203 unsigned LocMemOffset = VA.getLocMemOffset();
4206 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4207 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4209 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4210 MachinePointerInfo(),
4213 // Calculate and remember argument location.
4214 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4220 if (!MemOpChains.empty())
4221 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4223 // Build a sequence of copy-to-reg nodes chained together with token chain
4224 // and flag operands which copy the outgoing args into the appropriate regs.
4226 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4227 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4228 RegsToPass[i].second, InFlag);
4229 InFlag = Chain.getValue(1);
4232 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4235 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4236 SDValue Ops[] = { Chain, InFlag };
4238 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4239 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4241 InFlag = Chain.getValue(1);
4245 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4246 false, TailCallArguments);
4248 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4249 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4250 NumBytes, Ins, InVals, CS);
4253 // Copy an argument into memory, being careful to do this outside the
4254 // call sequence for the call to which the argument belongs.
4256 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4257 SDValue CallSeqStart,
4258 ISD::ArgFlagsTy Flags,
4261 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4262 CallSeqStart.getNode()->getOperand(0),
4264 // The MEMCPY must go outside the CALLSEQ_START..END.
4265 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4266 CallSeqStart.getNode()->getOperand(1),
4268 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4269 NewCallSeqStart.getNode());
4270 return NewCallSeqStart;
4274 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4275 CallingConv::ID CallConv, bool isVarArg,
4276 bool isTailCall, bool IsPatchPoint,
4277 const SmallVectorImpl<ISD::OutputArg> &Outs,
4278 const SmallVectorImpl<SDValue> &OutVals,
4279 const SmallVectorImpl<ISD::InputArg> &Ins,
4280 SDLoc dl, SelectionDAG &DAG,
4281 SmallVectorImpl<SDValue> &InVals,
4282 ImmutableCallSite *CS) const {
4284 bool isELFv2ABI = Subtarget.isELFv2ABI();
4285 bool isLittleEndian = Subtarget.isLittleEndian();
4286 unsigned NumOps = Outs.size();
4288 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4289 unsigned PtrByteSize = 8;
4291 MachineFunction &MF = DAG.getMachineFunction();
4293 // Mark this function as potentially containing a function that contains a
4294 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4295 // and restoring the callers stack pointer in this functions epilog. This is
4296 // done because by tail calling the called function might overwrite the value
4297 // in this function's (MF) stack pointer stack slot 0(SP).
4298 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4299 CallConv == CallingConv::Fast)
4300 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4302 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4303 "fastcc not supported on varargs functions");
4305 // Count how many bytes are to be pushed on the stack, including the linkage
4306 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4307 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4308 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4309 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4311 unsigned NumBytes = LinkageSize;
4312 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4314 static const MCPhysReg GPR[] = {
4315 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4316 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4318 static const MCPhysReg *FPR = GetFPR();
4320 static const MCPhysReg VR[] = {
4321 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4322 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4324 static const MCPhysReg VSRH[] = {
4325 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4326 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4329 const unsigned NumGPRs = array_lengthof(GPR);
4330 const unsigned NumFPRs = 13;
4331 const unsigned NumVRs = array_lengthof(VR);
4333 // When using the fast calling convention, we don't provide backing for
4334 // arguments that will be in registers.
4335 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4337 // Add up all the space actually used.
4338 for (unsigned i = 0; i != NumOps; ++i) {
4339 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4340 EVT ArgVT = Outs[i].VT;
4341 EVT OrigVT = Outs[i].ArgVT;
4343 if (CallConv == CallingConv::Fast) {
4344 if (Flags.isByVal())
4345 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4347 switch (ArgVT.getSimpleVT().SimpleTy) {
4348 default: llvm_unreachable("Unexpected ValueType for argument!");
4352 if (++NumGPRsUsed <= NumGPRs)
4357 if (++NumFPRsUsed <= NumFPRs)
4366 if (++NumVRsUsed <= NumVRs)
4372 /* Respect alignment of argument on the stack. */
4374 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4375 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4377 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4378 if (Flags.isInConsecutiveRegsLast())
4379 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4382 unsigned NumBytesActuallyUsed = NumBytes;
4384 // The prolog code of the callee may store up to 8 GPR argument registers to
4385 // the stack, allowing va_start to index over them in memory if its varargs.
4386 // Because we cannot tell if this is needed on the caller side, we have to
4387 // conservatively assume that it is needed. As such, make sure we have at
4388 // least enough stack space for the caller to store the 8 GPRs.
4389 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4390 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4392 // Tail call needs the stack to be aligned.
4393 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4394 CallConv == CallingConv::Fast)
4395 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4397 // Calculate by how many bytes the stack has to be adjusted in case of tail
4398 // call optimization.
4399 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4401 // To protect arguments on the stack from being clobbered in a tail call,
4402 // force all the loads to happen before doing any other lowering.
4404 Chain = DAG.getStackArgumentTokenFactor(Chain);
4406 // Adjust the stack pointer for the new arguments...
4407 // These operations are automatically eliminated by the prolog/epilog pass
4408 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4410 SDValue CallSeqStart = Chain;
4412 // Load the return address and frame pointer so it can be move somewhere else
4415 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4418 // Set up a copy of the stack pointer for use loading and storing any
4419 // arguments that may not fit in the registers available for argument
4421 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4423 // Figure out which arguments are going to go in registers, and which in
4424 // memory. Also, if this is a vararg function, floating point operations
4425 // must be stored to our stack, and loaded into integer regs as well, if
4426 // any integer regs are available for argument passing.
4427 unsigned ArgOffset = LinkageSize;
4429 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4430 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4432 SmallVector<SDValue, 8> MemOpChains;
4433 for (unsigned i = 0; i != NumOps; ++i) {
4434 SDValue Arg = OutVals[i];
4435 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4436 EVT ArgVT = Outs[i].VT;
4437 EVT OrigVT = Outs[i].ArgVT;
4439 // PtrOff will be used to store the current argument to the stack if a
4440 // register cannot be found for it.
4443 // We re-align the argument offset for each argument, except when using the
4444 // fast calling convention, when we need to make sure we do that only when
4445 // we'll actually use a stack slot.
4446 auto ComputePtrOff = [&]() {
4447 /* Respect alignment of argument on the stack. */
4449 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4450 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4452 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4454 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4457 if (CallConv != CallingConv::Fast) {
4460 /* Compute GPR index associated with argument offset. */
4461 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4462 GPR_idx = std::min(GPR_idx, NumGPRs);
4465 // Promote integers to 64-bit values.
4466 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4467 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4468 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4469 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4472 // FIXME memcpy is used way more than necessary. Correctness first.
4473 // Note: "by value" is code for passing a structure by value, not
4475 if (Flags.isByVal()) {
4476 // Note: Size includes alignment padding, so
4477 // struct x { short a; char b; }
4478 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4479 // These are the proper values we need for right-justifying the
4480 // aggregate in a parameter register.
4481 unsigned Size = Flags.getByValSize();
4483 // An empty aggregate parameter takes up no storage and no
4488 if (CallConv == CallingConv::Fast)
4491 // All aggregates smaller than 8 bytes must be passed right-justified.
4492 if (Size==1 || Size==2 || Size==4) {
4493 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4494 if (GPR_idx != NumGPRs) {
4495 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4496 MachinePointerInfo(), VT,
4497 false, false, false, 0);
4498 MemOpChains.push_back(Load.getValue(1));
4499 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4501 ArgOffset += PtrByteSize;
4506 if (GPR_idx == NumGPRs && Size < 8) {
4507 SDValue AddPtr = PtrOff;
4508 if (!isLittleEndian) {
4509 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4510 PtrOff.getValueType());
4511 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4513 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4516 ArgOffset += PtrByteSize;
4519 // Copy entire object into memory. There are cases where gcc-generated
4520 // code assumes it is there, even if it could be put entirely into
4521 // registers. (This is not what the doc says.)
4523 // FIXME: The above statement is likely due to a misunderstanding of the
4524 // documents. All arguments must be copied into the parameter area BY
4525 // THE CALLEE in the event that the callee takes the address of any
4526 // formal argument. That has not yet been implemented. However, it is
4527 // reasonable to use the stack area as a staging area for the register
4530 // Skip this for small aggregates, as we will use the same slot for a
4531 // right-justified copy, below.
4533 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4537 // When a register is available, pass a small aggregate right-justified.
4538 if (Size < 8 && GPR_idx != NumGPRs) {
4539 // The easiest way to get this right-justified in a register
4540 // is to copy the structure into the rightmost portion of a
4541 // local variable slot, then load the whole slot into the
4543 // FIXME: The memcpy seems to produce pretty awful code for
4544 // small aggregates, particularly for packed ones.
4545 // FIXME: It would be preferable to use the slot in the
4546 // parameter save area instead of a new local variable.
4547 SDValue AddPtr = PtrOff;
4548 if (!isLittleEndian) {
4549 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4550 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4552 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4556 // Load the slot into the register.
4557 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4558 MachinePointerInfo(),
4559 false, false, false, 0);
4560 MemOpChains.push_back(Load.getValue(1));
4561 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4563 // Done with this argument.
4564 ArgOffset += PtrByteSize;
4568 // For aggregates larger than PtrByteSize, copy the pieces of the
4569 // object that fit into registers from the parameter save area.
4570 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4571 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4572 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4573 if (GPR_idx != NumGPRs) {
4574 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4575 MachinePointerInfo(),
4576 false, false, false, 0);
4577 MemOpChains.push_back(Load.getValue(1));
4578 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4579 ArgOffset += PtrByteSize;
4581 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4588 switch (Arg.getSimpleValueType().SimpleTy) {
4589 default: llvm_unreachable("Unexpected ValueType for argument!");
4593 // These can be scalar arguments or elements of an integer array type
4594 // passed directly. Clang may use those instead of "byval" aggregate
4595 // types to avoid forcing arguments to memory unnecessarily.
4596 if (GPR_idx != NumGPRs) {
4597 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4599 if (CallConv == CallingConv::Fast)
4602 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4603 true, isTailCall, false, MemOpChains,
4604 TailCallArguments, dl);
4605 if (CallConv == CallingConv::Fast)
4606 ArgOffset += PtrByteSize;
4608 if (CallConv != CallingConv::Fast)
4609 ArgOffset += PtrByteSize;
4613 // These can be scalar arguments or elements of a float array type
4614 // passed directly. The latter are used to implement ELFv2 homogenous
4615 // float aggregates.
4617 // Named arguments go into FPRs first, and once they overflow, the
4618 // remaining arguments go into GPRs and then the parameter save area.
4619 // Unnamed arguments for vararg functions always go to GPRs and
4620 // then the parameter save area. For now, put all arguments to vararg
4621 // routines always in both locations (FPR *and* GPR or stack slot).
4622 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4623 bool NeededLoad = false;
4625 // First load the argument into the next available FPR.
4626 if (FPR_idx != NumFPRs)
4627 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4629 // Next, load the argument into GPR or stack slot if needed.
4630 if (!NeedGPROrStack)
4632 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4633 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4634 // once we support fp <-> gpr moves.
4636 // In the non-vararg case, this can only ever happen in the
4637 // presence of f32 array types, since otherwise we never run
4638 // out of FPRs before running out of GPRs.
4641 // Double values are always passed in a single GPR.
4642 if (Arg.getValueType() != MVT::f32) {
4643 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4645 // Non-array float values are extended and passed in a GPR.
4646 } else if (!Flags.isInConsecutiveRegs()) {
4647 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4648 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4650 // If we have an array of floats, we collect every odd element
4651 // together with its predecessor into one GPR.
4652 } else if (ArgOffset % PtrByteSize != 0) {
4654 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4655 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4656 if (!isLittleEndian)
4658 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4660 // The final element, if even, goes into the first half of a GPR.
4661 } else if (Flags.isInConsecutiveRegsLast()) {
4662 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4663 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4664 if (!isLittleEndian)
4665 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4666 DAG.getConstant(32, MVT::i32));
4668 // Non-final even elements are skipped; they will be handled
4669 // together the with subsequent argument on the next go-around.
4673 if (ArgVal.getNode())
4674 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4676 if (CallConv == CallingConv::Fast)
4679 // Single-precision floating-point values are mapped to the
4680 // second (rightmost) word of the stack doubleword.
4681 if (Arg.getValueType() == MVT::f32 &&
4682 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4683 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4684 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4687 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4688 true, isTailCall, false, MemOpChains,
4689 TailCallArguments, dl);
4693 // When passing an array of floats, the array occupies consecutive
4694 // space in the argument area; only round up to the next doubleword
4695 // at the end of the array. Otherwise, each float takes 8 bytes.
4696 if (CallConv != CallingConv::Fast || NeededLoad) {
4697 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4698 Flags.isInConsecutiveRegs()) ? 4 : 8;
4699 if (Flags.isInConsecutiveRegsLast())
4700 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4710 // These can be scalar arguments or elements of a vector array type
4711 // passed directly. The latter are used to implement ELFv2 homogenous
4712 // vector aggregates.
4714 // For a varargs call, named arguments go into VRs or on the stack as
4715 // usual; unnamed arguments always go to the stack or the corresponding
4716 // GPRs when within range. For now, we always put the value in both
4717 // locations (or even all three).
4719 // We could elide this store in the case where the object fits
4720 // entirely in R registers. Maybe later.
4721 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4722 MachinePointerInfo(), false, false, 0);
4723 MemOpChains.push_back(Store);
4724 if (VR_idx != NumVRs) {
4725 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4726 MachinePointerInfo(),
4727 false, false, false, 0);
4728 MemOpChains.push_back(Load.getValue(1));
4730 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4731 Arg.getSimpleValueType() == MVT::v2i64) ?
4732 VSRH[VR_idx] : VR[VR_idx];
4735 RegsToPass.push_back(std::make_pair(VReg, Load));
4738 for (unsigned i=0; i<16; i+=PtrByteSize) {
4739 if (GPR_idx == NumGPRs)
4741 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4742 DAG.getConstant(i, PtrVT));
4743 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4744 false, false, false, 0);
4745 MemOpChains.push_back(Load.getValue(1));
4746 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4751 // Non-varargs Altivec params go into VRs or on the stack.
4752 if (VR_idx != NumVRs) {
4753 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4754 Arg.getSimpleValueType() == MVT::v2i64) ?
4755 VSRH[VR_idx] : VR[VR_idx];
4758 RegsToPass.push_back(std::make_pair(VReg, Arg));
4760 if (CallConv == CallingConv::Fast)
4763 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4764 true, isTailCall, true, MemOpChains,
4765 TailCallArguments, dl);
4766 if (CallConv == CallingConv::Fast)
4770 if (CallConv != CallingConv::Fast)
4776 assert(NumBytesActuallyUsed == ArgOffset);
4777 (void)NumBytesActuallyUsed;
4779 if (!MemOpChains.empty())
4780 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4782 // Check if this is an indirect call (MTCTR/BCTRL).
4783 // See PrepareCall() for more information about calls through function
4784 // pointers in the 64-bit SVR4 ABI.
4785 if (!isTailCall && !IsPatchPoint &&
4786 !isFunctionGlobalAddress(Callee) &&
4787 !isa<ExternalSymbolSDNode>(Callee)) {
4788 // Load r2 into a virtual register and store it to the TOC save area.
4789 setUsesTOCBasePtr(DAG);
4790 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4791 // TOC save area offset.
4792 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4793 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4794 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4795 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4796 MachinePointerInfo::getStack(TOCSaveOffset),
4798 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4799 // This does not mean the MTCTR instruction must use R12; it's easier
4800 // to model this as an extra parameter, so do that.
4801 if (isELFv2ABI && !IsPatchPoint)
4802 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4805 // Build a sequence of copy-to-reg nodes chained together with token chain
4806 // and flag operands which copy the outgoing args into the appropriate regs.
4808 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4809 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4810 RegsToPass[i].second, InFlag);
4811 InFlag = Chain.getValue(1);
4815 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4816 FPOp, true, TailCallArguments);
4818 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4819 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4820 NumBytes, Ins, InVals, CS);
4824 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4825 CallingConv::ID CallConv, bool isVarArg,
4826 bool isTailCall, bool IsPatchPoint,
4827 const SmallVectorImpl<ISD::OutputArg> &Outs,
4828 const SmallVectorImpl<SDValue> &OutVals,
4829 const SmallVectorImpl<ISD::InputArg> &Ins,
4830 SDLoc dl, SelectionDAG &DAG,
4831 SmallVectorImpl<SDValue> &InVals,
4832 ImmutableCallSite *CS) const {
4834 unsigned NumOps = Outs.size();
4836 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4837 bool isPPC64 = PtrVT == MVT::i64;
4838 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4840 MachineFunction &MF = DAG.getMachineFunction();
4842 // Mark this function as potentially containing a function that contains a
4843 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4844 // and restoring the callers stack pointer in this functions epilog. This is
4845 // done because by tail calling the called function might overwrite the value
4846 // in this function's (MF) stack pointer stack slot 0(SP).
4847 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4848 CallConv == CallingConv::Fast)
4849 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4851 // Count how many bytes are to be pushed on the stack, including the linkage
4852 // area, and parameter passing area. We start with 24/48 bytes, which is
4853 // prereserved space for [SP][CR][LR][3 x unused].
4854 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4856 unsigned NumBytes = LinkageSize;
4858 // Add up all the space actually used.
4859 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4860 // they all go in registers, but we must reserve stack space for them for
4861 // possible use by the caller. In varargs or 64-bit calls, parameters are
4862 // assigned stack space in order, with padding so Altivec parameters are
4864 unsigned nAltivecParamsAtEnd = 0;
4865 for (unsigned i = 0; i != NumOps; ++i) {
4866 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4867 EVT ArgVT = Outs[i].VT;
4868 // Varargs Altivec parameters are padded to a 16 byte boundary.
4869 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4870 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4871 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4872 if (!isVarArg && !isPPC64) {
4873 // Non-varargs Altivec parameters go after all the non-Altivec
4874 // parameters; handle those later so we know how much padding we need.
4875 nAltivecParamsAtEnd++;
4878 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4879 NumBytes = ((NumBytes+15)/16)*16;
4881 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4884 // Allow for Altivec parameters at the end, if needed.
4885 if (nAltivecParamsAtEnd) {
4886 NumBytes = ((NumBytes+15)/16)*16;
4887 NumBytes += 16*nAltivecParamsAtEnd;
4890 // The prolog code of the callee may store up to 8 GPR argument registers to
4891 // the stack, allowing va_start to index over them in memory if its varargs.
4892 // Because we cannot tell if this is needed on the caller side, we have to
4893 // conservatively assume that it is needed. As such, make sure we have at
4894 // least enough stack space for the caller to store the 8 GPRs.
4895 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4897 // Tail call needs the stack to be aligned.
4898 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4899 CallConv == CallingConv::Fast)
4900 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4902 // Calculate by how many bytes the stack has to be adjusted in case of tail
4903 // call optimization.
4904 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4906 // To protect arguments on the stack from being clobbered in a tail call,
4907 // force all the loads to happen before doing any other lowering.
4909 Chain = DAG.getStackArgumentTokenFactor(Chain);
4911 // Adjust the stack pointer for the new arguments...
4912 // These operations are automatically eliminated by the prolog/epilog pass
4913 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4915 SDValue CallSeqStart = Chain;
4917 // Load the return address and frame pointer so it can be move somewhere else
4920 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4923 // Set up a copy of the stack pointer for use loading and storing any
4924 // arguments that may not fit in the registers available for argument
4928 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4930 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4932 // Figure out which arguments are going to go in registers, and which in
4933 // memory. Also, if this is a vararg function, floating point operations
4934 // must be stored to our stack, and loaded into integer regs as well, if
4935 // any integer regs are available for argument passing.
4936 unsigned ArgOffset = LinkageSize;
4937 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4939 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4940 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4941 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4943 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4944 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4945 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4947 static const MCPhysReg *FPR = GetFPR();
4949 static const MCPhysReg VR[] = {
4950 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4951 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4953 const unsigned NumGPRs = array_lengthof(GPR_32);
4954 const unsigned NumFPRs = 13;
4955 const unsigned NumVRs = array_lengthof(VR);
4957 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4959 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4960 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4962 SmallVector<SDValue, 8> MemOpChains;
4963 for (unsigned i = 0; i != NumOps; ++i) {
4964 SDValue Arg = OutVals[i];
4965 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4967 // PtrOff will be used to store the current argument to the stack if a
4968 // register cannot be found for it.
4971 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4973 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4975 // On PPC64, promote integers to 64-bit values.
4976 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4977 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4978 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4979 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4982 // FIXME memcpy is used way more than necessary. Correctness first.
4983 // Note: "by value" is code for passing a structure by value, not
4985 if (Flags.isByVal()) {
4986 unsigned Size = Flags.getByValSize();
4987 // Very small objects are passed right-justified. Everything else is
4988 // passed left-justified.
4989 if (Size==1 || Size==2) {
4990 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4991 if (GPR_idx != NumGPRs) {
4992 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4993 MachinePointerInfo(), VT,
4994 false, false, false, 0);
4995 MemOpChains.push_back(Load.getValue(1));
4996 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4998 ArgOffset += PtrByteSize;
5000 SDValue Const = DAG.getConstant(PtrByteSize - Size,
5001 PtrOff.getValueType());
5002 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5003 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5006 ArgOffset += PtrByteSize;
5010 // Copy entire object into memory. There are cases where gcc-generated
5011 // code assumes it is there, even if it could be put entirely into
5012 // registers. (This is not what the doc says.)
5013 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5017 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5018 // copy the pieces of the object that fit into registers from the
5019 // parameter save area.
5020 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5021 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5022 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5023 if (GPR_idx != NumGPRs) {
5024 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5025 MachinePointerInfo(),
5026 false, false, false, 0);
5027 MemOpChains.push_back(Load.getValue(1));
5028 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5029 ArgOffset += PtrByteSize;
5031 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5038 switch (Arg.getSimpleValueType().SimpleTy) {
5039 default: llvm_unreachable("Unexpected ValueType for argument!");
5043 if (GPR_idx != NumGPRs) {
5044 if (Arg.getValueType() == MVT::i1)
5045 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5047 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5049 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5050 isPPC64, isTailCall, false, MemOpChains,
5051 TailCallArguments, dl);
5053 ArgOffset += PtrByteSize;
5057 if (FPR_idx != NumFPRs) {
5058 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5061 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5062 MachinePointerInfo(), false, false, 0);
5063 MemOpChains.push_back(Store);
5065 // Float varargs are always shadowed in available integer registers
5066 if (GPR_idx != NumGPRs) {
5067 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5068 MachinePointerInfo(), false, false,
5070 MemOpChains.push_back(Load.getValue(1));
5071 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5073 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5074 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5075 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5076 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5077 MachinePointerInfo(),
5078 false, false, false, 0);
5079 MemOpChains.push_back(Load.getValue(1));
5080 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5083 // If we have any FPRs remaining, we may also have GPRs remaining.
5084 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5086 if (GPR_idx != NumGPRs)
5088 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5089 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5093 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5094 isPPC64, isTailCall, false, MemOpChains,
5095 TailCallArguments, dl);
5099 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5106 // These go aligned on the stack, or in the corresponding R registers
5107 // when within range. The Darwin PPC ABI doc claims they also go in
5108 // V registers; in fact gcc does this only for arguments that are
5109 // prototyped, not for those that match the ... We do it for all
5110 // arguments, seems to work.
5111 while (ArgOffset % 16 !=0) {
5112 ArgOffset += PtrByteSize;
5113 if (GPR_idx != NumGPRs)
5116 // We could elide this store in the case where the object fits
5117 // entirely in R registers. Maybe later.
5118 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5119 DAG.getConstant(ArgOffset, PtrVT));
5120 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5121 MachinePointerInfo(), false, false, 0);
5122 MemOpChains.push_back(Store);
5123 if (VR_idx != NumVRs) {
5124 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5125 MachinePointerInfo(),
5126 false, false, false, 0);
5127 MemOpChains.push_back(Load.getValue(1));
5128 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5131 for (unsigned i=0; i<16; i+=PtrByteSize) {
5132 if (GPR_idx == NumGPRs)
5134 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5135 DAG.getConstant(i, PtrVT));
5136 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5137 false, false, false, 0);
5138 MemOpChains.push_back(Load.getValue(1));
5139 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5144 // Non-varargs Altivec params generally go in registers, but have
5145 // stack space allocated at the end.
5146 if (VR_idx != NumVRs) {
5147 // Doesn't have GPR space allocated.
5148 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5149 } else if (nAltivecParamsAtEnd==0) {
5150 // We are emitting Altivec params in order.
5151 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5152 isPPC64, isTailCall, true, MemOpChains,
5153 TailCallArguments, dl);
5159 // If all Altivec parameters fit in registers, as they usually do,
5160 // they get stack space following the non-Altivec parameters. We
5161 // don't track this here because nobody below needs it.
5162 // If there are more Altivec parameters than fit in registers emit
5164 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5166 // Offset is aligned; skip 1st 12 params which go in V registers.
5167 ArgOffset = ((ArgOffset+15)/16)*16;
5169 for (unsigned i = 0; i != NumOps; ++i) {
5170 SDValue Arg = OutVals[i];
5171 EVT ArgType = Outs[i].VT;
5172 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5173 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5176 // We are emitting Altivec params in order.
5177 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5178 isPPC64, isTailCall, true, MemOpChains,
5179 TailCallArguments, dl);
5186 if (!MemOpChains.empty())
5187 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5189 // On Darwin, R12 must contain the address of an indirect callee. This does
5190 // not mean the MTCTR instruction must use R12; it's easier to model this as
5191 // an extra parameter, so do that.
5193 !isFunctionGlobalAddress(Callee) &&
5194 !isa<ExternalSymbolSDNode>(Callee) &&
5195 !isBLACompatibleAddress(Callee, DAG))
5196 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5197 PPC::R12), Callee));
5199 // Build a sequence of copy-to-reg nodes chained together with token chain
5200 // and flag operands which copy the outgoing args into the appropriate regs.
5202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5203 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5204 RegsToPass[i].second, InFlag);
5205 InFlag = Chain.getValue(1);
5209 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5210 FPOp, true, TailCallArguments);
5212 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5213 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5214 NumBytes, Ins, InVals, CS);
5218 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5219 MachineFunction &MF, bool isVarArg,
5220 const SmallVectorImpl<ISD::OutputArg> &Outs,
5221 LLVMContext &Context) const {
5222 SmallVector<CCValAssign, 16> RVLocs;
5223 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5224 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5228 PPCTargetLowering::LowerReturn(SDValue Chain,
5229 CallingConv::ID CallConv, bool isVarArg,
5230 const SmallVectorImpl<ISD::OutputArg> &Outs,
5231 const SmallVectorImpl<SDValue> &OutVals,
5232 SDLoc dl, SelectionDAG &DAG) const {
5234 SmallVector<CCValAssign, 16> RVLocs;
5235 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5237 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5240 SmallVector<SDValue, 4> RetOps(1, Chain);
5242 // Copy the result values into the output registers.
5243 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5244 CCValAssign &VA = RVLocs[i];
5245 assert(VA.isRegLoc() && "Can only return in registers!");
5247 SDValue Arg = OutVals[i];
5249 switch (VA.getLocInfo()) {
5250 default: llvm_unreachable("Unknown loc info!");
5251 case CCValAssign::Full: break;
5252 case CCValAssign::AExt:
5253 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5255 case CCValAssign::ZExt:
5256 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5258 case CCValAssign::SExt:
5259 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5263 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5264 Flag = Chain.getValue(1);
5265 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5268 RetOps[0] = Chain; // Update chain.
5270 // Add the flag if we have it.
5272 RetOps.push_back(Flag);
5274 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5277 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5278 const PPCSubtarget &Subtarget) const {
5279 // When we pop the dynamic allocation we need to restore the SP link.
5282 // Get the corect type for pointers.
5283 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5285 // Construct the stack pointer operand.
5286 bool isPPC64 = Subtarget.isPPC64();
5287 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5288 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5290 // Get the operands for the STACKRESTORE.
5291 SDValue Chain = Op.getOperand(0);
5292 SDValue SaveSP = Op.getOperand(1);
5294 // Load the old link SP.
5295 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5296 MachinePointerInfo(),
5297 false, false, false, 0);
5299 // Restore the stack pointer.
5300 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5302 // Store the old link SP.
5303 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5310 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5311 MachineFunction &MF = DAG.getMachineFunction();
5312 bool isPPC64 = Subtarget.isPPC64();
5313 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5315 // Get current frame pointer save index. The users of this index will be
5316 // primarily DYNALLOC instructions.
5317 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5318 int RASI = FI->getReturnAddrSaveIndex();
5320 // If the frame pointer save index hasn't been defined yet.
5322 // Find out what the fix offset of the frame pointer save area.
5323 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5324 // Allocate the frame index for frame pointer save area.
5325 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5327 FI->setReturnAddrSaveIndex(RASI);
5329 return DAG.getFrameIndex(RASI, PtrVT);
5333 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5334 MachineFunction &MF = DAG.getMachineFunction();
5335 bool isPPC64 = Subtarget.isPPC64();
5336 bool isDarwinABI = Subtarget.isDarwinABI();
5337 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5339 // Get current frame pointer save index. The users of this index will be
5340 // primarily DYNALLOC instructions.
5341 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5342 int FPSI = FI->getFramePointerSaveIndex();
5344 // If the frame pointer save index hasn't been defined yet.
5346 // Find out what the fix offset of the frame pointer save area.
5347 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5350 // Allocate the frame index for frame pointer save area.
5351 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5353 FI->setFramePointerSaveIndex(FPSI);
5355 return DAG.getFrameIndex(FPSI, PtrVT);
5358 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5360 const PPCSubtarget &Subtarget) const {
5362 SDValue Chain = Op.getOperand(0);
5363 SDValue Size = Op.getOperand(1);
5366 // Get the corect type for pointers.
5367 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5369 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5370 DAG.getConstant(0, PtrVT), Size);
5371 // Construct a node for the frame pointer save index.
5372 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5373 // Build a DYNALLOC node.
5374 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5375 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5376 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5379 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5380 SelectionDAG &DAG) const {
5382 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5383 DAG.getVTList(MVT::i32, MVT::Other),
5384 Op.getOperand(0), Op.getOperand(1));
5387 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5388 SelectionDAG &DAG) const {
5390 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5391 Op.getOperand(0), Op.getOperand(1));
5394 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5395 assert(Op.getValueType() == MVT::i1 &&
5396 "Custom lowering only for i1 loads");
5398 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5401 LoadSDNode *LD = cast<LoadSDNode>(Op);
5403 SDValue Chain = LD->getChain();
5404 SDValue BasePtr = LD->getBasePtr();
5405 MachineMemOperand *MMO = LD->getMemOperand();
5407 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5408 BasePtr, MVT::i8, MMO);
5409 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5411 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5412 return DAG.getMergeValues(Ops, dl);
5415 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5416 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5417 "Custom lowering only for i1 stores");
5419 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5422 StoreSDNode *ST = cast<StoreSDNode>(Op);
5424 SDValue Chain = ST->getChain();
5425 SDValue BasePtr = ST->getBasePtr();
5426 SDValue Value = ST->getValue();
5427 MachineMemOperand *MMO = ST->getMemOperand();
5429 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5430 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5433 // FIXME: Remove this once the ANDI glue bug is fixed:
5434 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5435 assert(Op.getValueType() == MVT::i1 &&
5436 "Custom lowering only for i1 results");
5439 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5443 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5445 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5446 // Not FP? Not a fsel.
5447 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5448 !Op.getOperand(2).getValueType().isFloatingPoint())
5451 // We might be able to do better than this under some circumstances, but in
5452 // general, fsel-based lowering of select is a finite-math-only optimization.
5453 // For more information, see section F.3 of the 2.06 ISA specification.
5454 if (!DAG.getTarget().Options.NoInfsFPMath ||
5455 !DAG.getTarget().Options.NoNaNsFPMath)
5458 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5460 EVT ResVT = Op.getValueType();
5461 EVT CmpVT = Op.getOperand(0).getValueType();
5462 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5463 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5466 // If the RHS of the comparison is a 0.0, we don't need to do the
5467 // subtraction at all.
5469 if (isFloatingPointZero(RHS))
5471 default: break; // SETUO etc aren't handled by fsel.
5475 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5476 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5477 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5478 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5479 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5480 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5481 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5484 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5487 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5488 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5489 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5492 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5495 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5496 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5497 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5498 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5503 default: break; // SETUO etc aren't handled by fsel.
5507 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5508 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5509 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5510 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5511 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5512 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5513 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5514 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5517 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5518 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5519 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5520 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5523 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5524 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5525 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5526 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5529 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5530 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5531 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5532 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5535 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5536 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5537 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5538 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5543 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5546 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5547 SDValue Src = Op.getOperand(0);
5548 if (Src.getValueType() == MVT::f32)
5549 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5552 switch (Op.getSimpleValueType().SimpleTy) {
5553 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5556 Op.getOpcode() == ISD::FP_TO_SINT
5558 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5562 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5563 "i64 FP_TO_UINT is supported only with FPCVT");
5564 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5570 // Convert the FP value to an int value through memory.
5571 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5572 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5573 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5574 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5575 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5577 // Emit a store to the stack slot.
5580 MachineFunction &MF = DAG.getMachineFunction();
5581 MachineMemOperand *MMO =
5582 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5583 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5584 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5585 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5587 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5588 MPI, false, false, 0);
5590 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5592 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5593 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5594 DAG.getConstant(4, FIPtr.getValueType()));
5595 MPI = MPI.getWithOffset(4);
5603 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5606 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5608 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5609 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5613 // We're trying to insert a regular store, S, and then a load, L. If the
5614 // incoming value, O, is a load, we might just be able to have our load use the
5615 // address used by O. However, we don't know if anything else will store to
5616 // that address before we can load from it. To prevent this situation, we need
5617 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5618 // the same chain operand as O, we create a token factor from the chain results
5619 // of O and L, and we replace all uses of O's chain result with that token
5620 // factor (see spliceIntoChain below for this last part).
5621 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5624 ISD::LoadExtType ET) const {
5626 if (ET == ISD::NON_EXTLOAD &&
5627 (Op.getOpcode() == ISD::FP_TO_UINT ||
5628 Op.getOpcode() == ISD::FP_TO_SINT) &&
5629 isOperationLegalOrCustom(Op.getOpcode(),
5630 Op.getOperand(0).getValueType())) {
5632 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5636 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5637 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5638 LD->isNonTemporal())
5640 if (LD->getMemoryVT() != MemVT)
5643 RLI.Ptr = LD->getBasePtr();
5644 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5645 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5646 "Non-pre-inc AM on PPC?");
5647 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5651 RLI.Chain = LD->getChain();
5652 RLI.MPI = LD->getPointerInfo();
5653 RLI.IsInvariant = LD->isInvariant();
5654 RLI.Alignment = LD->getAlignment();
5655 RLI.AAInfo = LD->getAAInfo();
5656 RLI.Ranges = LD->getRanges();
5658 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5662 // Given the head of the old chain, ResChain, insert a token factor containing
5663 // it and NewResChain, and make users of ResChain now be users of that token
5665 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5666 SDValue NewResChain,
5667 SelectionDAG &DAG) const {
5671 SDLoc dl(NewResChain);
5673 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5674 NewResChain, DAG.getUNDEF(MVT::Other));
5675 assert(TF.getNode() != NewResChain.getNode() &&
5676 "A new TF really is required here");
5678 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5679 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5682 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5683 SelectionDAG &DAG) const {
5685 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5686 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5689 if (Op.getOperand(0).getValueType() == MVT::i1)
5690 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5691 DAG.getConstantFP(1.0, Op.getValueType()),
5692 DAG.getConstantFP(0.0, Op.getValueType()));
5694 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5695 "UINT_TO_FP is supported only with FPCVT");
5697 // If we have FCFIDS, then use it when converting to single-precision.
5698 // Otherwise, convert to double-precision and then round.
5699 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5700 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
5702 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
5704 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5708 if (Op.getOperand(0).getValueType() == MVT::i64) {
5709 SDValue SINT = Op.getOperand(0);
5710 // When converting to single-precision, we actually need to convert
5711 // to double-precision first and then round to single-precision.
5712 // To avoid double-rounding effects during that operation, we have
5713 // to prepare the input operand. Bits that might be truncated when
5714 // converting to double-precision are replaced by a bit that won't
5715 // be lost at this stage, but is below the single-precision rounding
5718 // However, if -enable-unsafe-fp-math is in effect, accept double
5719 // rounding to avoid the extra overhead.
5720 if (Op.getValueType() == MVT::f32 &&
5721 !Subtarget.hasFPCVT() &&
5722 !DAG.getTarget().Options.UnsafeFPMath) {
5724 // Twiddle input to make sure the low 11 bits are zero. (If this
5725 // is the case, we are guaranteed the value will fit into the 53 bit
5726 // mantissa of an IEEE double-precision value without rounding.)
5727 // If any of those low 11 bits were not zero originally, make sure
5728 // bit 12 (value 2048) is set instead, so that the final rounding
5729 // to single-precision gets the correct result.
5730 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5731 SINT, DAG.getConstant(2047, MVT::i64));
5732 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5733 Round, DAG.getConstant(2047, MVT::i64));
5734 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5735 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5736 Round, DAG.getConstant(-2048, MVT::i64));
5738 // However, we cannot use that value unconditionally: if the magnitude
5739 // of the input value is small, the bit-twiddling we did above might
5740 // end up visibly changing the output. Fortunately, in that case, we
5741 // don't need to twiddle bits since the original input will convert
5742 // exactly to double-precision floating-point already. Therefore,
5743 // construct a conditional to use the original value if the top 11
5744 // bits are all sign-bit copies, and use the rounded value computed
5746 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5747 SINT, DAG.getConstant(53, MVT::i32));
5748 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5749 Cond, DAG.getConstant(1, MVT::i64));
5750 Cond = DAG.getSetCC(dl, MVT::i32,
5751 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5753 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5759 MachineFunction &MF = DAG.getMachineFunction();
5760 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5761 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5762 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5764 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5765 } else if (Subtarget.hasLFIWAX() &&
5766 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5767 MachineMemOperand *MMO =
5768 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5769 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5770 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5771 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5772 DAG.getVTList(MVT::f64, MVT::Other),
5773 Ops, MVT::i32, MMO);
5774 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5775 } else if (Subtarget.hasFPCVT() &&
5776 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5777 MachineMemOperand *MMO =
5778 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5779 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5780 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5781 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5782 DAG.getVTList(MVT::f64, MVT::Other),
5783 Ops, MVT::i32, MMO);
5784 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5785 } else if (((Subtarget.hasLFIWAX() &&
5786 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5787 (Subtarget.hasFPCVT() &&
5788 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5789 SINT.getOperand(0).getValueType() == MVT::i32) {
5790 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5791 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5793 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5794 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5797 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5798 MachinePointerInfo::getFixedStack(FrameIdx),
5801 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5802 "Expected an i32 store");
5806 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5809 MachineMemOperand *MMO =
5810 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5811 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5812 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5813 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5814 PPCISD::LFIWZX : PPCISD::LFIWAX,
5815 dl, DAG.getVTList(MVT::f64, MVT::Other),
5816 Ops, MVT::i32, MMO);
5818 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5820 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5822 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5823 FP = DAG.getNode(ISD::FP_ROUND, dl,
5824 MVT::f32, FP, DAG.getIntPtrConstant(0));
5828 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5829 "Unhandled INT_TO_FP type in custom expander!");
5830 // Since we only generate this in 64-bit mode, we can take advantage of
5831 // 64-bit registers. In particular, sign extend the input value into the
5832 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5833 // then lfd it and fcfid it.
5834 MachineFunction &MF = DAG.getMachineFunction();
5835 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5836 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5839 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5842 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5844 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5845 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5847 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5848 MachinePointerInfo::getFixedStack(FrameIdx),
5851 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5852 "Expected an i32 store");
5856 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5860 MachineMemOperand *MMO =
5861 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5862 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5863 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5864 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5865 PPCISD::LFIWZX : PPCISD::LFIWAX,
5866 dl, DAG.getVTList(MVT::f64, MVT::Other),
5867 Ops, MVT::i32, MMO);
5869 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5871 assert(Subtarget.isPPC64() &&
5872 "i32->FP without LFIWAX supported only on PPC64");
5874 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5875 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5877 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5880 // STD the extended value into the stack slot.
5881 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5882 MachinePointerInfo::getFixedStack(FrameIdx),
5885 // Load the value as a double.
5886 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5887 MachinePointerInfo::getFixedStack(FrameIdx),
5888 false, false, false, 0);
5891 // FCFID it and return it.
5892 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5893 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5894 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5898 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5899 SelectionDAG &DAG) const {
5902 The rounding mode is in bits 30:31 of FPSR, and has the following
5909 FLT_ROUNDS, on the other hand, expects the following:
5916 To perform the conversion, we do:
5917 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5920 MachineFunction &MF = DAG.getMachineFunction();
5921 EVT VT = Op.getValueType();
5922 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5924 // Save FP Control Word to register
5926 MVT::f64, // return register
5927 MVT::Glue // unused in this context
5929 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5931 // Save FP register to stack slot
5932 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5933 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5934 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5935 StackSlot, MachinePointerInfo(), false, false,0);
5937 // Load FP Control Word from low 32 bits of stack slot.
5938 SDValue Four = DAG.getConstant(4, PtrVT);
5939 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5940 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5941 false, false, false, 0);
5943 // Transform as necessary
5945 DAG.getNode(ISD::AND, dl, MVT::i32,
5946 CWD, DAG.getConstant(3, MVT::i32));
5948 DAG.getNode(ISD::SRL, dl, MVT::i32,
5949 DAG.getNode(ISD::AND, dl, MVT::i32,
5950 DAG.getNode(ISD::XOR, dl, MVT::i32,
5951 CWD, DAG.getConstant(3, MVT::i32)),
5952 DAG.getConstant(3, MVT::i32)),
5953 DAG.getConstant(1, MVT::i32));
5956 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5958 return DAG.getNode((VT.getSizeInBits() < 16 ?
5959 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5962 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5963 EVT VT = Op.getValueType();
5964 unsigned BitWidth = VT.getSizeInBits();
5966 assert(Op.getNumOperands() == 3 &&
5967 VT == Op.getOperand(1).getValueType() &&
5970 // Expand into a bunch of logical ops. Note that these ops
5971 // depend on the PPC behavior for oversized shift amounts.
5972 SDValue Lo = Op.getOperand(0);
5973 SDValue Hi = Op.getOperand(1);
5974 SDValue Amt = Op.getOperand(2);
5975 EVT AmtVT = Amt.getValueType();
5977 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5978 DAG.getConstant(BitWidth, AmtVT), Amt);
5979 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5980 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5981 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5982 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5983 DAG.getConstant(-BitWidth, AmtVT));
5984 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5985 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5986 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5987 SDValue OutOps[] = { OutLo, OutHi };
5988 return DAG.getMergeValues(OutOps, dl);
5991 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5992 EVT VT = Op.getValueType();
5994 unsigned BitWidth = VT.getSizeInBits();
5995 assert(Op.getNumOperands() == 3 &&
5996 VT == Op.getOperand(1).getValueType() &&
5999 // Expand into a bunch of logical ops. Note that these ops
6000 // depend on the PPC behavior for oversized shift amounts.
6001 SDValue Lo = Op.getOperand(0);
6002 SDValue Hi = Op.getOperand(1);
6003 SDValue Amt = Op.getOperand(2);
6004 EVT AmtVT = Amt.getValueType();
6006 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6007 DAG.getConstant(BitWidth, AmtVT), Amt);
6008 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6009 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6010 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6011 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6012 DAG.getConstant(-BitWidth, AmtVT));
6013 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6014 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6015 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6016 SDValue OutOps[] = { OutLo, OutHi };
6017 return DAG.getMergeValues(OutOps, dl);
6020 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6022 EVT VT = Op.getValueType();
6023 unsigned BitWidth = VT.getSizeInBits();
6024 assert(Op.getNumOperands() == 3 &&
6025 VT == Op.getOperand(1).getValueType() &&
6028 // Expand into a bunch of logical ops, followed by a select_cc.
6029 SDValue Lo = Op.getOperand(0);
6030 SDValue Hi = Op.getOperand(1);
6031 SDValue Amt = Op.getOperand(2);
6032 EVT AmtVT = Amt.getValueType();
6034 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6035 DAG.getConstant(BitWidth, AmtVT), Amt);
6036 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6037 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6038 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6039 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6040 DAG.getConstant(-BitWidth, AmtVT));
6041 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6042 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6043 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6044 Tmp4, Tmp6, ISD::SETLE);
6045 SDValue OutOps[] = { OutLo, OutHi };
6046 return DAG.getMergeValues(OutOps, dl);
6049 //===----------------------------------------------------------------------===//
6050 // Vector related lowering.
6053 /// BuildSplatI - Build a canonical splati of Val with an element size of
6054 /// SplatSize. Cast the result to VT.
6055 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6056 SelectionDAG &DAG, SDLoc dl) {
6057 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6059 static const EVT VTys[] = { // canonical VT to use for each size.
6060 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6063 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6065 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6069 EVT CanonicalVT = VTys[SplatSize-1];
6071 // Build a canonical splat for this value.
6072 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6073 SmallVector<SDValue, 8> Ops;
6074 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6075 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6076 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6079 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6080 /// specified intrinsic ID.
6081 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6082 SelectionDAG &DAG, SDLoc dl,
6083 EVT DestVT = MVT::Other) {
6084 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6086 DAG.getConstant(IID, MVT::i32), Op);
6089 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6090 /// specified intrinsic ID.
6091 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6092 SelectionDAG &DAG, SDLoc dl,
6093 EVT DestVT = MVT::Other) {
6094 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6096 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6099 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6100 /// specified intrinsic ID.
6101 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6102 SDValue Op2, SelectionDAG &DAG,
6103 SDLoc dl, EVT DestVT = MVT::Other) {
6104 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6106 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6110 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6111 /// amount. The result has the specified value type.
6112 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6113 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6114 // Force LHS/RHS to be the right type.
6115 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6116 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6119 for (unsigned i = 0; i != 16; ++i)
6121 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6122 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6125 // If this is a case we can't handle, return null and let the default
6126 // expansion code take care of it. If we CAN select this case, and if it
6127 // selects to a single instruction, return Op. Otherwise, if we can codegen
6128 // this case more efficiently than a constant pool load, lower it to the
6129 // sequence of ops that should be used.
6130 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6131 SelectionDAG &DAG) const {
6133 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6134 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6136 // Check if this is a splat of a constant value.
6137 APInt APSplatBits, APSplatUndef;
6138 unsigned SplatBitSize;
6140 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6141 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6144 unsigned SplatBits = APSplatBits.getZExtValue();
6145 unsigned SplatUndef = APSplatUndef.getZExtValue();
6146 unsigned SplatSize = SplatBitSize / 8;
6148 // First, handle single instruction cases.
6151 if (SplatBits == 0) {
6152 // Canonicalize all zero vectors to be v4i32.
6153 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6154 SDValue Z = DAG.getConstant(0, MVT::i32);
6155 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6156 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6161 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6162 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6164 if (SextVal >= -16 && SextVal <= 15)
6165 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6168 // Two instruction sequences.
6170 // If this value is in the range [-32,30] and is even, use:
6171 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6172 // If this value is in the range [17,31] and is odd, use:
6173 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6174 // If this value is in the range [-31,-17] and is odd, use:
6175 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6176 // Note the last two are three-instruction sequences.
6177 if (SextVal >= -32 && SextVal <= 31) {
6178 // To avoid having these optimizations undone by constant folding,
6179 // we convert to a pseudo that will be expanded later into one of
6181 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6182 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6183 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6184 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6185 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6186 if (VT == Op.getValueType())
6189 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6192 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6193 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6195 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6196 // Make -1 and vspltisw -1:
6197 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6199 // Make the VSLW intrinsic, computing 0x8000_0000.
6200 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6203 // xor by OnesV to invert it.
6204 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6205 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6208 // The remaining cases assume either big endian element order or
6209 // a splat-size that equates to the element size of the vector
6210 // to be built. An example that doesn't work for little endian is
6211 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6212 // and a vector element size of 16 bits. The code below will
6213 // produce the vector in big endian element order, which for little
6214 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6216 // For now, just avoid these optimizations in that case.
6217 // FIXME: Develop correct optimizations for LE with mismatched
6218 // splat and element sizes.
6220 if (Subtarget.isLittleEndian() &&
6221 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6224 // Check to see if this is a wide variety of vsplti*, binop self cases.
6225 static const signed char SplatCsts[] = {
6226 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6227 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6230 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6231 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6232 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6233 int i = SplatCsts[idx];
6235 // Figure out what shift amount will be used by altivec if shifted by i in
6237 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6239 // vsplti + shl self.
6240 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6241 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6242 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6243 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6244 Intrinsic::ppc_altivec_vslw
6246 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6247 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6250 // vsplti + srl self.
6251 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6252 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6253 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6254 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6255 Intrinsic::ppc_altivec_vsrw
6257 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6258 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6261 // vsplti + sra self.
6262 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6263 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6264 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6265 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6266 Intrinsic::ppc_altivec_vsraw
6268 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6269 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6272 // vsplti + rol self.
6273 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6274 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6275 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6276 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6277 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6278 Intrinsic::ppc_altivec_vrlw
6280 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6281 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6284 // t = vsplti c, result = vsldoi t, t, 1
6285 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6286 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6287 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6289 // t = vsplti c, result = vsldoi t, t, 2
6290 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6291 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6292 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6294 // t = vsplti c, result = vsldoi t, t, 3
6295 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6296 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6297 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6304 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6305 /// the specified operations to build the shuffle.
6306 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6307 SDValue RHS, SelectionDAG &DAG,
6309 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6310 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6311 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6314 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6326 if (OpNum == OP_COPY) {
6327 if (LHSID == (1*9+2)*9+3) return LHS;
6328 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6332 SDValue OpLHS, OpRHS;
6333 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6334 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6338 default: llvm_unreachable("Unknown i32 permute!");
6340 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6341 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6342 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6343 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6346 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6347 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6348 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6349 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6352 for (unsigned i = 0; i != 16; ++i)
6353 ShufIdxs[i] = (i&3)+0;
6356 for (unsigned i = 0; i != 16; ++i)
6357 ShufIdxs[i] = (i&3)+4;
6360 for (unsigned i = 0; i != 16; ++i)
6361 ShufIdxs[i] = (i&3)+8;
6364 for (unsigned i = 0; i != 16; ++i)
6365 ShufIdxs[i] = (i&3)+12;
6368 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6370 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6372 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6374 EVT VT = OpLHS.getValueType();
6375 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6376 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6377 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6378 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6381 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6382 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6383 /// return the code it can be lowered into. Worst case, it can always be
6384 /// lowered into a vperm.
6385 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6386 SelectionDAG &DAG) const {
6388 SDValue V1 = Op.getOperand(0);
6389 SDValue V2 = Op.getOperand(1);
6390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6391 EVT VT = Op.getValueType();
6392 bool isLittleEndian = Subtarget.isLittleEndian();
6394 // Cases that are handled by instructions that take permute immediates
6395 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6396 // selected by the instruction selector.
6397 if (V2.getOpcode() == ISD::UNDEF) {
6398 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6399 PPC::isSplatShuffleMask(SVOp, 2) ||
6400 PPC::isSplatShuffleMask(SVOp, 4) ||
6401 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6402 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6403 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6404 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6405 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6406 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6407 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6408 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6409 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6414 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6415 // and produce a fixed permutation. If any of these match, do not lower to
6417 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6418 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6419 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6420 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6421 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6422 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6423 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6424 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6425 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6426 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6429 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6430 // perfect shuffle table to emit an optimal matching sequence.
6431 ArrayRef<int> PermMask = SVOp->getMask();
6433 unsigned PFIndexes[4];
6434 bool isFourElementShuffle = true;
6435 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6436 unsigned EltNo = 8; // Start out undef.
6437 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6438 if (PermMask[i*4+j] < 0)
6439 continue; // Undef, ignore it.
6441 unsigned ByteSource = PermMask[i*4+j];
6442 if ((ByteSource & 3) != j) {
6443 isFourElementShuffle = false;
6448 EltNo = ByteSource/4;
6449 } else if (EltNo != ByteSource/4) {
6450 isFourElementShuffle = false;
6454 PFIndexes[i] = EltNo;
6457 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6458 // perfect shuffle vector to determine if it is cost effective to do this as
6459 // discrete instructions, or whether we should use a vperm.
6460 // For now, we skip this for little endian until such time as we have a
6461 // little-endian perfect shuffle table.
6462 if (isFourElementShuffle && !isLittleEndian) {
6463 // Compute the index in the perfect shuffle table.
6464 unsigned PFTableIndex =
6465 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6467 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6468 unsigned Cost = (PFEntry >> 30);
6470 // Determining when to avoid vperm is tricky. Many things affect the cost
6471 // of vperm, particularly how many times the perm mask needs to be computed.
6472 // For example, if the perm mask can be hoisted out of a loop or is already
6473 // used (perhaps because there are multiple permutes with the same shuffle
6474 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6475 // the loop requires an extra register.
6477 // As a compromise, we only emit discrete instructions if the shuffle can be
6478 // generated in 3 or fewer operations. When we have loop information
6479 // available, if this block is within a loop, we should avoid using vperm
6480 // for 3-operation perms and use a constant pool load instead.
6482 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6485 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6486 // vector that will get spilled to the constant pool.
6487 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6489 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6490 // that it is in input element units, not in bytes. Convert now.
6492 // For little endian, the order of the input vectors is reversed, and
6493 // the permutation mask is complemented with respect to 31. This is
6494 // necessary to produce proper semantics with the big-endian-biased vperm
6496 EVT EltVT = V1.getValueType().getVectorElementType();
6497 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6499 SmallVector<SDValue, 16> ResultMask;
6500 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6501 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6503 for (unsigned j = 0; j != BytesPerElement; ++j)
6505 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6508 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6512 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6515 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6518 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6522 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6523 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6524 /// information about the intrinsic.
6525 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6527 unsigned IntrinsicID =
6528 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6531 switch (IntrinsicID) {
6532 default: return false;
6533 // Comparison predicates.
6534 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6535 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6536 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6537 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6538 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6539 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6540 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6541 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6542 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6543 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6544 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6545 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6546 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6548 // Normal Comparisons.
6549 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6550 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6551 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6552 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6553 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6554 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6555 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6556 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6557 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6558 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6559 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6560 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6561 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6566 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6567 /// lower, do it, otherwise return null.
6568 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6569 SelectionDAG &DAG) const {
6570 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6571 // opcode number of the comparison.
6575 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6576 return SDValue(); // Don't custom lower most intrinsics.
6578 // If this is a non-dot comparison, make the VCMP node and we are done.
6580 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6581 Op.getOperand(1), Op.getOperand(2),
6582 DAG.getConstant(CompareOpc, MVT::i32));
6583 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6586 // Create the PPCISD altivec 'dot' comparison node.
6588 Op.getOperand(2), // LHS
6589 Op.getOperand(3), // RHS
6590 DAG.getConstant(CompareOpc, MVT::i32)
6592 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6593 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6595 // Now that we have the comparison, emit a copy from the CR to a GPR.
6596 // This is flagged to the above dot comparison.
6597 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6598 DAG.getRegister(PPC::CR6, MVT::i32),
6599 CompNode.getValue(1));
6601 // Unpack the result based on how the target uses it.
6602 unsigned BitNo; // Bit # of CR6.
6603 bool InvertBit; // Invert result?
6604 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6605 default: // Can't happen, don't crash on invalid number though.
6606 case 0: // Return the value of the EQ bit of CR6.
6607 BitNo = 0; InvertBit = false;
6609 case 1: // Return the inverted value of the EQ bit of CR6.
6610 BitNo = 0; InvertBit = true;
6612 case 2: // Return the value of the LT bit of CR6.
6613 BitNo = 2; InvertBit = false;
6615 case 3: // Return the inverted value of the LT bit of CR6.
6616 BitNo = 2; InvertBit = true;
6620 // Shift the bit into the low position.
6621 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6622 DAG.getConstant(8-(3-BitNo), MVT::i32));
6624 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6625 DAG.getConstant(1, MVT::i32));
6627 // If we are supposed to, toggle the bit.
6629 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6630 DAG.getConstant(1, MVT::i32));
6634 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6635 SelectionDAG &DAG) const {
6637 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6638 // instructions), but for smaller types, we need to first extend up to v2i32
6639 // before doing going farther.
6640 if (Op.getValueType() == MVT::v2i64) {
6641 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6642 if (ExtVT != MVT::v2i32) {
6643 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6644 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6645 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6646 ExtVT.getVectorElementType(), 4)));
6647 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6648 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6649 DAG.getValueType(MVT::v2i32));
6658 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6659 SelectionDAG &DAG) const {
6661 // Create a stack slot that is 16-byte aligned.
6662 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6663 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6664 EVT PtrVT = getPointerTy();
6665 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6667 // Store the input value into Value#0 of the stack slot.
6668 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6669 Op.getOperand(0), FIdx, MachinePointerInfo(),
6672 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6673 false, false, false, 0);
6676 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6678 if (Op.getValueType() == MVT::v4i32) {
6679 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6681 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6682 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6684 SDValue RHSSwap = // = vrlw RHS, 16
6685 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6687 // Shrinkify inputs to v8i16.
6688 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6689 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6690 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6692 // Low parts multiplied together, generating 32-bit results (we ignore the
6694 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6695 LHS, RHS, DAG, dl, MVT::v4i32);
6697 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6698 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6699 // Shift the high parts up 16 bits.
6700 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6702 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6703 } else if (Op.getValueType() == MVT::v8i16) {
6704 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6706 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6708 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6709 LHS, RHS, Zero, DAG, dl);
6710 } else if (Op.getValueType() == MVT::v16i8) {
6711 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6712 bool isLittleEndian = Subtarget.isLittleEndian();
6714 // Multiply the even 8-bit parts, producing 16-bit sums.
6715 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6716 LHS, RHS, DAG, dl, MVT::v8i16);
6717 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6719 // Multiply the odd 8-bit parts, producing 16-bit sums.
6720 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6721 LHS, RHS, DAG, dl, MVT::v8i16);
6722 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6724 // Merge the results together. Because vmuleub and vmuloub are
6725 // instructions with a big-endian bias, we must reverse the
6726 // element numbering and reverse the meaning of "odd" and "even"
6727 // when generating little endian code.
6729 for (unsigned i = 0; i != 8; ++i) {
6730 if (isLittleEndian) {
6732 Ops[i*2+1] = 2*i+16;
6735 Ops[i*2+1] = 2*i+1+16;
6739 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6741 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6743 llvm_unreachable("Unknown mul to lower!");
6747 /// LowerOperation - Provide custom lowering hooks for some operations.
6749 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6750 switch (Op.getOpcode()) {
6751 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6752 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6753 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6754 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6755 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6756 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6757 case ISD::SETCC: return LowerSETCC(Op, DAG);
6758 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6759 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6761 return LowerVASTART(Op, DAG, Subtarget);
6764 return LowerVAARG(Op, DAG, Subtarget);
6767 return LowerVACOPY(Op, DAG, Subtarget);
6769 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6770 case ISD::DYNAMIC_STACKALLOC:
6771 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6773 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6774 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6776 case ISD::LOAD: return LowerLOAD(Op, DAG);
6777 case ISD::STORE: return LowerSTORE(Op, DAG);
6778 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6779 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6780 case ISD::FP_TO_UINT:
6781 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6783 case ISD::UINT_TO_FP:
6784 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6785 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6787 // Lower 64-bit shifts.
6788 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6789 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6790 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6792 // Vector-related lowering.
6793 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6794 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6795 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6796 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6797 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6798 case ISD::MUL: return LowerMUL(Op, DAG);
6800 // For counter-based loop handling.
6801 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6803 // Frame & Return address.
6804 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6805 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6809 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6810 SmallVectorImpl<SDValue>&Results,
6811 SelectionDAG &DAG) const {
6813 switch (N->getOpcode()) {
6815 llvm_unreachable("Do not know how to custom type legalize this operation!");
6816 case ISD::READCYCLECOUNTER: {
6817 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6818 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6820 Results.push_back(RTB);
6821 Results.push_back(RTB.getValue(1));
6822 Results.push_back(RTB.getValue(2));
6825 case ISD::INTRINSIC_W_CHAIN: {
6826 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6827 Intrinsic::ppc_is_decremented_ctr_nonzero)
6830 assert(N->getValueType(0) == MVT::i1 &&
6831 "Unexpected result type for CTR decrement intrinsic");
6832 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6833 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6834 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6837 Results.push_back(NewInt);
6838 Results.push_back(NewInt.getValue(1));
6842 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
6845 EVT VT = N->getValueType(0);
6847 if (VT == MVT::i64) {
6848 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6850 Results.push_back(NewNode);
6851 Results.push_back(NewNode.getValue(1));
6855 case ISD::FP_ROUND_INREG: {
6856 assert(N->getValueType(0) == MVT::ppcf128);
6857 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6858 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6859 MVT::f64, N->getOperand(0),
6860 DAG.getIntPtrConstant(0));
6861 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6862 MVT::f64, N->getOperand(0),
6863 DAG.getIntPtrConstant(1));
6865 // Add the two halves of the long double in round-to-zero mode.
6866 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6868 // We know the low half is about to be thrown away, so just use something
6870 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6874 case ISD::FP_TO_SINT:
6875 // LowerFP_TO_INT() can only handle f32 and f64.
6876 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6878 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6884 //===----------------------------------------------------------------------===//
6885 // Other Lowering Code
6886 //===----------------------------------------------------------------------===//
6888 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6889 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6890 Function *Func = Intrinsic::getDeclaration(M, Id);
6891 return Builder.CreateCall(Func);
6894 // The mappings for emitLeading/TrailingFence is taken from
6895 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6896 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6897 AtomicOrdering Ord, bool IsStore,
6898 bool IsLoad) const {
6899 if (Ord == SequentiallyConsistent)
6900 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6901 else if (isAtLeastRelease(Ord))
6902 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6907 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6908 AtomicOrdering Ord, bool IsStore,
6909 bool IsLoad) const {
6910 if (IsLoad && isAtLeastAcquire(Ord))
6911 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6912 // FIXME: this is too conservative, a dependent branch + isync is enough.
6913 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6914 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6915 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6921 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6922 bool is64bit, unsigned BinOpcode) const {
6923 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6924 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6926 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6927 MachineFunction *F = BB->getParent();
6928 MachineFunction::iterator It = BB;
6931 unsigned dest = MI->getOperand(0).getReg();
6932 unsigned ptrA = MI->getOperand(1).getReg();
6933 unsigned ptrB = MI->getOperand(2).getReg();
6934 unsigned incr = MI->getOperand(3).getReg();
6935 DebugLoc dl = MI->getDebugLoc();
6937 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6938 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6939 F->insert(It, loopMBB);
6940 F->insert(It, exitMBB);
6941 exitMBB->splice(exitMBB->begin(), BB,
6942 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6943 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6945 MachineRegisterInfo &RegInfo = F->getRegInfo();
6946 unsigned TmpReg = (!BinOpcode) ? incr :
6947 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6948 : &PPC::GPRCRegClass);
6952 // fallthrough --> loopMBB
6953 BB->addSuccessor(loopMBB);
6956 // l[wd]arx dest, ptr
6957 // add r0, dest, incr
6958 // st[wd]cx. r0, ptr
6960 // fallthrough --> exitMBB
6962 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6963 .addReg(ptrA).addReg(ptrB);
6965 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6966 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6967 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6968 BuildMI(BB, dl, TII->get(PPC::BCC))
6969 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6970 BB->addSuccessor(loopMBB);
6971 BB->addSuccessor(exitMBB);
6980 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6981 MachineBasicBlock *BB,
6982 bool is8bit, // operation
6983 unsigned BinOpcode) const {
6984 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6985 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6986 // In 64 bit mode we have to use 64 bits for addresses, even though the
6987 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6988 // registers without caring whether they're 32 or 64, but here we're
6989 // doing actual arithmetic on the addresses.
6990 bool is64bit = Subtarget.isPPC64();
6991 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6993 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6994 MachineFunction *F = BB->getParent();
6995 MachineFunction::iterator It = BB;
6998 unsigned dest = MI->getOperand(0).getReg();
6999 unsigned ptrA = MI->getOperand(1).getReg();
7000 unsigned ptrB = MI->getOperand(2).getReg();
7001 unsigned incr = MI->getOperand(3).getReg();
7002 DebugLoc dl = MI->getDebugLoc();
7004 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7005 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7006 F->insert(It, loopMBB);
7007 F->insert(It, exitMBB);
7008 exitMBB->splice(exitMBB->begin(), BB,
7009 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7010 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7012 MachineRegisterInfo &RegInfo = F->getRegInfo();
7013 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7014 : &PPC::GPRCRegClass;
7015 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7016 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7017 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7018 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7019 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7020 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7021 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7022 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7023 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7024 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7025 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7027 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7031 // fallthrough --> loopMBB
7032 BB->addSuccessor(loopMBB);
7034 // The 4-byte load must be aligned, while a char or short may be
7035 // anywhere in the word. Hence all this nasty bookkeeping code.
7036 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7037 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7038 // xori shift, shift1, 24 [16]
7039 // rlwinm ptr, ptr1, 0, 0, 29
7040 // slw incr2, incr, shift
7041 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7042 // slw mask, mask2, shift
7044 // lwarx tmpDest, ptr
7045 // add tmp, tmpDest, incr2
7046 // andc tmp2, tmpDest, mask
7047 // and tmp3, tmp, mask
7048 // or tmp4, tmp3, tmp2
7051 // fallthrough --> exitMBB
7052 // srw dest, tmpDest, shift
7053 if (ptrA != ZeroReg) {
7054 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7055 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7056 .addReg(ptrA).addReg(ptrB);
7060 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7061 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7062 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7063 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7065 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7066 .addReg(Ptr1Reg).addImm(0).addImm(61);
7068 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7069 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7070 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7071 .addReg(incr).addReg(ShiftReg);
7073 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7075 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7076 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7078 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7079 .addReg(Mask2Reg).addReg(ShiftReg);
7082 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7083 .addReg(ZeroReg).addReg(PtrReg);
7085 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7086 .addReg(Incr2Reg).addReg(TmpDestReg);
7087 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7088 .addReg(TmpDestReg).addReg(MaskReg);
7089 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7090 .addReg(TmpReg).addReg(MaskReg);
7091 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7092 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7093 BuildMI(BB, dl, TII->get(PPC::STWCX))
7094 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7095 BuildMI(BB, dl, TII->get(PPC::BCC))
7096 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7097 BB->addSuccessor(loopMBB);
7098 BB->addSuccessor(exitMBB);
7103 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7108 llvm::MachineBasicBlock*
7109 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7110 MachineBasicBlock *MBB) const {
7111 DebugLoc DL = MI->getDebugLoc();
7112 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7114 MachineFunction *MF = MBB->getParent();
7115 MachineRegisterInfo &MRI = MF->getRegInfo();
7117 const BasicBlock *BB = MBB->getBasicBlock();
7118 MachineFunction::iterator I = MBB;
7122 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7123 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7125 unsigned DstReg = MI->getOperand(0).getReg();
7126 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7127 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7128 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7129 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7131 MVT PVT = getPointerTy();
7132 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7133 "Invalid Pointer Size!");
7134 // For v = setjmp(buf), we generate
7137 // SjLjSetup mainMBB
7143 // buf[LabelOffset] = LR
7147 // v = phi(main, restore)
7150 MachineBasicBlock *thisMBB = MBB;
7151 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7152 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7153 MF->insert(I, mainMBB);
7154 MF->insert(I, sinkMBB);
7156 MachineInstrBuilder MIB;
7158 // Transfer the remainder of BB and its successor edges to sinkMBB.
7159 sinkMBB->splice(sinkMBB->begin(), MBB,
7160 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7161 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7163 // Note that the structure of the jmp_buf used here is not compatible
7164 // with that used by libc, and is not designed to be. Specifically, it
7165 // stores only those 'reserved' registers that LLVM does not otherwise
7166 // understand how to spill. Also, by convention, by the time this
7167 // intrinsic is called, Clang has already stored the frame address in the
7168 // first slot of the buffer and stack address in the third. Following the
7169 // X86 target code, we'll store the jump address in the second slot. We also
7170 // need to save the TOC pointer (R2) to handle jumps between shared
7171 // libraries, and that will be stored in the fourth slot. The thread
7172 // identifier (R13) is not affected.
7175 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7176 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7177 const int64_t BPOffset = 4 * PVT.getStoreSize();
7179 // Prepare IP either in reg.
7180 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7181 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7182 unsigned BufReg = MI->getOperand(1).getReg();
7184 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7185 setUsesTOCBasePtr(*MBB->getParent());
7186 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7190 MIB.setMemRefs(MMOBegin, MMOEnd);
7193 // Naked functions never have a base pointer, and so we use r1. For all
7194 // other functions, this decision must be delayed until during PEI.
7196 if (MF->getFunction()->getAttributes().hasAttribute(
7197 AttributeSet::FunctionIndex, Attribute::Naked))
7198 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7200 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7202 MIB = BuildMI(*thisMBB, MI, DL,
7203 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7207 MIB.setMemRefs(MMOBegin, MMOEnd);
7210 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7211 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
7212 MIB.addRegMask(TRI->getNoPreservedMask());
7214 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7216 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7218 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7220 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7221 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7226 BuildMI(mainMBB, DL,
7227 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7230 if (Subtarget.isPPC64()) {
7231 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7233 .addImm(LabelOffset)
7236 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7238 .addImm(LabelOffset)
7242 MIB.setMemRefs(MMOBegin, MMOEnd);
7244 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7245 mainMBB->addSuccessor(sinkMBB);
7248 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7249 TII->get(PPC::PHI), DstReg)
7250 .addReg(mainDstReg).addMBB(mainMBB)
7251 .addReg(restoreDstReg).addMBB(thisMBB);
7253 MI->eraseFromParent();
7258 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7259 MachineBasicBlock *MBB) const {
7260 DebugLoc DL = MI->getDebugLoc();
7261 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7263 MachineFunction *MF = MBB->getParent();
7264 MachineRegisterInfo &MRI = MF->getRegInfo();
7267 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7268 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7270 MVT PVT = getPointerTy();
7271 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7272 "Invalid Pointer Size!");
7274 const TargetRegisterClass *RC =
7275 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7276 unsigned Tmp = MRI.createVirtualRegister(RC);
7277 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7278 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7279 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7283 : (Subtarget.isSVR4ABI() &&
7284 MF->getTarget().getRelocationModel() == Reloc::PIC_
7288 MachineInstrBuilder MIB;
7290 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7291 const int64_t SPOffset = 2 * PVT.getStoreSize();
7292 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7293 const int64_t BPOffset = 4 * PVT.getStoreSize();
7295 unsigned BufReg = MI->getOperand(0).getReg();
7297 // Reload FP (the jumped-to function may not have had a
7298 // frame pointer, and if so, then its r31 will be restored
7300 if (PVT == MVT::i64) {
7301 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7305 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7309 MIB.setMemRefs(MMOBegin, MMOEnd);
7312 if (PVT == MVT::i64) {
7313 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7314 .addImm(LabelOffset)
7317 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7318 .addImm(LabelOffset)
7321 MIB.setMemRefs(MMOBegin, MMOEnd);
7324 if (PVT == MVT::i64) {
7325 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7329 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7333 MIB.setMemRefs(MMOBegin, MMOEnd);
7336 if (PVT == MVT::i64) {
7337 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7341 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7345 MIB.setMemRefs(MMOBegin, MMOEnd);
7348 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7349 setUsesTOCBasePtr(*MBB->getParent());
7350 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7354 MIB.setMemRefs(MMOBegin, MMOEnd);
7358 BuildMI(*MBB, MI, DL,
7359 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7360 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7362 MI->eraseFromParent();
7367 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7368 MachineBasicBlock *BB) const {
7369 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7370 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7371 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
7372 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7373 // Call lowering should have added an r2 operand to indicate a dependence
7374 // on the TOC base pointer value. It can't however, because there is no
7375 // way to mark the dependence as implicit there, and so the stackmap code
7376 // will confuse it with a regular operand. Instead, add the dependence
7378 setUsesTOCBasePtr(*BB->getParent());
7379 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
7382 return emitPatchPoint(MI, BB);
7385 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7386 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7387 return emitEHSjLjSetJmp(MI, BB);
7388 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7389 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7390 return emitEHSjLjLongJmp(MI, BB);
7393 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7395 // To "insert" these instructions we actually have to insert their
7396 // control-flow patterns.
7397 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7398 MachineFunction::iterator It = BB;
7401 MachineFunction *F = BB->getParent();
7403 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7404 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7405 MI->getOpcode() == PPC::SELECT_I4 ||
7406 MI->getOpcode() == PPC::SELECT_I8)) {
7407 SmallVector<MachineOperand, 2> Cond;
7408 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7409 MI->getOpcode() == PPC::SELECT_CC_I8)
7410 Cond.push_back(MI->getOperand(4));
7412 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7413 Cond.push_back(MI->getOperand(1));
7415 DebugLoc dl = MI->getDebugLoc();
7416 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7417 Cond, MI->getOperand(2).getReg(),
7418 MI->getOperand(3).getReg());
7419 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7420 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7421 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7422 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7423 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7424 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7425 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7426 MI->getOpcode() == PPC::SELECT_I4 ||
7427 MI->getOpcode() == PPC::SELECT_I8 ||
7428 MI->getOpcode() == PPC::SELECT_F4 ||
7429 MI->getOpcode() == PPC::SELECT_F8 ||
7430 MI->getOpcode() == PPC::SELECT_VRRC ||
7431 MI->getOpcode() == PPC::SELECT_VSFRC ||
7432 MI->getOpcode() == PPC::SELECT_VSRC) {
7433 // The incoming instruction knows the destination vreg to set, the
7434 // condition code register to branch on, the true/false values to
7435 // select between, and a branch opcode to use.
7440 // cmpTY ccX, r1, r2
7442 // fallthrough --> copy0MBB
7443 MachineBasicBlock *thisMBB = BB;
7444 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7445 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7446 DebugLoc dl = MI->getDebugLoc();
7447 F->insert(It, copy0MBB);
7448 F->insert(It, sinkMBB);
7450 // Transfer the remainder of BB and its successor edges to sinkMBB.
7451 sinkMBB->splice(sinkMBB->begin(), BB,
7452 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7453 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7455 // Next, add the true and fallthrough blocks as its successors.
7456 BB->addSuccessor(copy0MBB);
7457 BB->addSuccessor(sinkMBB);
7459 if (MI->getOpcode() == PPC::SELECT_I4 ||
7460 MI->getOpcode() == PPC::SELECT_I8 ||
7461 MI->getOpcode() == PPC::SELECT_F4 ||
7462 MI->getOpcode() == PPC::SELECT_F8 ||
7463 MI->getOpcode() == PPC::SELECT_VRRC ||
7464 MI->getOpcode() == PPC::SELECT_VSFRC ||
7465 MI->getOpcode() == PPC::SELECT_VSRC) {
7466 BuildMI(BB, dl, TII->get(PPC::BC))
7467 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7469 unsigned SelectPred = MI->getOperand(4).getImm();
7470 BuildMI(BB, dl, TII->get(PPC::BCC))
7471 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7475 // %FalseValue = ...
7476 // # fallthrough to sinkMBB
7479 // Update machine-CFG edges
7480 BB->addSuccessor(sinkMBB);
7483 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7486 BuildMI(*BB, BB->begin(), dl,
7487 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7488 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7489 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7490 } else if (MI->getOpcode() == PPC::ReadTB) {
7491 // To read the 64-bit time-base register on a 32-bit target, we read the
7492 // two halves. Should the counter have wrapped while it was being read, we
7493 // need to try again.
7496 // mfspr Rx,TBU # load from TBU
7497 // mfspr Ry,TB # load from TB
7498 // mfspr Rz,TBU # load from TBU
7499 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7500 // bne readLoop # branch if they're not equal
7503 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7504 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7505 DebugLoc dl = MI->getDebugLoc();
7506 F->insert(It, readMBB);
7507 F->insert(It, sinkMBB);
7509 // Transfer the remainder of BB and its successor edges to sinkMBB.
7510 sinkMBB->splice(sinkMBB->begin(), BB,
7511 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7512 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7514 BB->addSuccessor(readMBB);
7517 MachineRegisterInfo &RegInfo = F->getRegInfo();
7518 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7519 unsigned LoReg = MI->getOperand(0).getReg();
7520 unsigned HiReg = MI->getOperand(1).getReg();
7522 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7523 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7524 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7526 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7528 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7529 .addReg(HiReg).addReg(ReadAgainReg);
7530 BuildMI(BB, dl, TII->get(PPC::BCC))
7531 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7533 BB->addSuccessor(readMBB);
7534 BB->addSuccessor(sinkMBB);
7536 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7537 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7538 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7539 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7540 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7541 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7542 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7543 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7545 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7546 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7547 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7548 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7549 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7550 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7551 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7552 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7554 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7555 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7556 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7557 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7558 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7559 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7560 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7561 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7563 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7564 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7565 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7566 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7567 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7568 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7569 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7570 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7573 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7574 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7575 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7576 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7577 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7578 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7579 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7582 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7583 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7584 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7585 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7586 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7587 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7588 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7590 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7591 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7592 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7593 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7594 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7595 BB = EmitAtomicBinary(MI, BB, false, 0);
7596 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7597 BB = EmitAtomicBinary(MI, BB, true, 0);
7599 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7600 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7601 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7603 unsigned dest = MI->getOperand(0).getReg();
7604 unsigned ptrA = MI->getOperand(1).getReg();
7605 unsigned ptrB = MI->getOperand(2).getReg();
7606 unsigned oldval = MI->getOperand(3).getReg();
7607 unsigned newval = MI->getOperand(4).getReg();
7608 DebugLoc dl = MI->getDebugLoc();
7610 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7611 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7612 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7613 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7614 F->insert(It, loop1MBB);
7615 F->insert(It, loop2MBB);
7616 F->insert(It, midMBB);
7617 F->insert(It, exitMBB);
7618 exitMBB->splice(exitMBB->begin(), BB,
7619 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7620 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7624 // fallthrough --> loopMBB
7625 BB->addSuccessor(loop1MBB);
7628 // l[wd]arx dest, ptr
7629 // cmp[wd] dest, oldval
7632 // st[wd]cx. newval, ptr
7636 // st[wd]cx. dest, ptr
7639 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7640 .addReg(ptrA).addReg(ptrB);
7641 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7642 .addReg(oldval).addReg(dest);
7643 BuildMI(BB, dl, TII->get(PPC::BCC))
7644 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7645 BB->addSuccessor(loop2MBB);
7646 BB->addSuccessor(midMBB);
7649 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7650 .addReg(newval).addReg(ptrA).addReg(ptrB);
7651 BuildMI(BB, dl, TII->get(PPC::BCC))
7652 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7653 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7654 BB->addSuccessor(loop1MBB);
7655 BB->addSuccessor(exitMBB);
7658 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7659 .addReg(dest).addReg(ptrA).addReg(ptrB);
7660 BB->addSuccessor(exitMBB);
7665 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7666 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7667 // We must use 64-bit registers for addresses when targeting 64-bit,
7668 // since we're actually doing arithmetic on them. Other registers
7670 bool is64bit = Subtarget.isPPC64();
7671 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7673 unsigned dest = MI->getOperand(0).getReg();
7674 unsigned ptrA = MI->getOperand(1).getReg();
7675 unsigned ptrB = MI->getOperand(2).getReg();
7676 unsigned oldval = MI->getOperand(3).getReg();
7677 unsigned newval = MI->getOperand(4).getReg();
7678 DebugLoc dl = MI->getDebugLoc();
7680 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7681 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7682 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7683 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7684 F->insert(It, loop1MBB);
7685 F->insert(It, loop2MBB);
7686 F->insert(It, midMBB);
7687 F->insert(It, exitMBB);
7688 exitMBB->splice(exitMBB->begin(), BB,
7689 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7690 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7692 MachineRegisterInfo &RegInfo = F->getRegInfo();
7693 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7694 : &PPC::GPRCRegClass;
7695 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7696 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7697 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7698 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7699 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7700 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7701 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7702 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7703 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7704 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7705 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7706 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7707 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7709 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7710 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7713 // fallthrough --> loopMBB
7714 BB->addSuccessor(loop1MBB);
7716 // The 4-byte load must be aligned, while a char or short may be
7717 // anywhere in the word. Hence all this nasty bookkeeping code.
7718 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7719 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7720 // xori shift, shift1, 24 [16]
7721 // rlwinm ptr, ptr1, 0, 0, 29
7722 // slw newval2, newval, shift
7723 // slw oldval2, oldval,shift
7724 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7725 // slw mask, mask2, shift
7726 // and newval3, newval2, mask
7727 // and oldval3, oldval2, mask
7729 // lwarx tmpDest, ptr
7730 // and tmp, tmpDest, mask
7731 // cmpw tmp, oldval3
7734 // andc tmp2, tmpDest, mask
7735 // or tmp4, tmp2, newval3
7740 // stwcx. tmpDest, ptr
7742 // srw dest, tmpDest, shift
7743 if (ptrA != ZeroReg) {
7744 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7745 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7746 .addReg(ptrA).addReg(ptrB);
7750 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7751 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7752 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7753 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7755 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7756 .addReg(Ptr1Reg).addImm(0).addImm(61);
7758 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7759 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7760 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7761 .addReg(newval).addReg(ShiftReg);
7762 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7763 .addReg(oldval).addReg(ShiftReg);
7765 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7767 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7768 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7769 .addReg(Mask3Reg).addImm(65535);
7771 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7772 .addReg(Mask2Reg).addReg(ShiftReg);
7773 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7774 .addReg(NewVal2Reg).addReg(MaskReg);
7775 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7776 .addReg(OldVal2Reg).addReg(MaskReg);
7779 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7780 .addReg(ZeroReg).addReg(PtrReg);
7781 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7782 .addReg(TmpDestReg).addReg(MaskReg);
7783 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7784 .addReg(TmpReg).addReg(OldVal3Reg);
7785 BuildMI(BB, dl, TII->get(PPC::BCC))
7786 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7787 BB->addSuccessor(loop2MBB);
7788 BB->addSuccessor(midMBB);
7791 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7792 .addReg(TmpDestReg).addReg(MaskReg);
7793 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7794 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7795 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7796 .addReg(ZeroReg).addReg(PtrReg);
7797 BuildMI(BB, dl, TII->get(PPC::BCC))
7798 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7799 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7800 BB->addSuccessor(loop1MBB);
7801 BB->addSuccessor(exitMBB);
7804 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7805 .addReg(ZeroReg).addReg(PtrReg);
7806 BB->addSuccessor(exitMBB);
7811 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7813 } else if (MI->getOpcode() == PPC::FADDrtz) {
7814 // This pseudo performs an FADD with rounding mode temporarily forced
7815 // to round-to-zero. We emit this via custom inserter since the FPSCR
7816 // is not modeled at the SelectionDAG level.
7817 unsigned Dest = MI->getOperand(0).getReg();
7818 unsigned Src1 = MI->getOperand(1).getReg();
7819 unsigned Src2 = MI->getOperand(2).getReg();
7820 DebugLoc dl = MI->getDebugLoc();
7822 MachineRegisterInfo &RegInfo = F->getRegInfo();
7823 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7825 // Save FPSCR value.
7826 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7828 // Set rounding mode to round-to-zero.
7829 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7830 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7832 // Perform addition.
7833 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7835 // Restore FPSCR value.
7836 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7837 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7838 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7839 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7840 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7841 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7842 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7843 PPC::ANDIo8 : PPC::ANDIo;
7844 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7845 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7847 MachineRegisterInfo &RegInfo = F->getRegInfo();
7848 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7849 &PPC::GPRCRegClass :
7850 &PPC::G8RCRegClass);
7852 DebugLoc dl = MI->getDebugLoc();
7853 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7854 .addReg(MI->getOperand(1).getReg()).addImm(1);
7855 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7856 MI->getOperand(0).getReg())
7857 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7859 llvm_unreachable("Unexpected instr type to insert");
7862 MI->eraseFromParent(); // The pseudo instruction is gone now.
7866 //===----------------------------------------------------------------------===//
7867 // Target Optimization Hooks
7868 //===----------------------------------------------------------------------===//
7870 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7871 DAGCombinerInfo &DCI,
7872 unsigned &RefinementSteps,
7873 bool &UseOneConstNR) const {
7874 EVT VT = Operand.getValueType();
7875 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7876 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7877 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7878 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7879 // Convergence is quadratic, so we essentially double the number of digits
7880 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7881 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7882 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7883 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7884 if (VT.getScalarType() == MVT::f64)
7886 UseOneConstNR = true;
7887 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7892 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7893 DAGCombinerInfo &DCI,
7894 unsigned &RefinementSteps) const {
7895 EVT VT = Operand.getValueType();
7896 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7897 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7898 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7899 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7900 // Convergence is quadratic, so we essentially double the number of digits
7901 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7902 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7903 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7904 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7905 if (VT.getScalarType() == MVT::f64)
7907 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7912 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7913 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7914 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7915 // enabled for division), this functionality is redundant with the default
7916 // combiner logic (once the division -> reciprocal/multiply transformation
7917 // has taken place). As a result, this matters more for older cores than for
7920 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7921 // reciprocal if there are two or more FDIVs (for embedded cores with only
7922 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7923 switch (Subtarget.getDarwinDirective()) {
7925 return NumUsers > 2;
7928 case PPC::DIR_E500mc:
7929 case PPC::DIR_E5500:
7930 return NumUsers > 1;
7934 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7935 unsigned Bytes, int Dist,
7936 SelectionDAG &DAG) {
7937 if (VT.getSizeInBits() / 8 != Bytes)
7940 SDValue BaseLoc = Base->getBasePtr();
7941 if (Loc.getOpcode() == ISD::FrameIndex) {
7942 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7944 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7945 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7946 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7947 int FS = MFI->getObjectSize(FI);
7948 int BFS = MFI->getObjectSize(BFI);
7949 if (FS != BFS || FS != (int)Bytes) return false;
7950 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7954 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7955 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7958 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7959 const GlobalValue *GV1 = nullptr;
7960 const GlobalValue *GV2 = nullptr;
7961 int64_t Offset1 = 0;
7962 int64_t Offset2 = 0;
7963 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7964 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7965 if (isGA1 && isGA2 && GV1 == GV2)
7966 return Offset1 == (Offset2 + Dist*Bytes);
7970 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7971 // not enforce equality of the chain operands.
7972 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7973 unsigned Bytes, int Dist,
7974 SelectionDAG &DAG) {
7975 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7976 EVT VT = LS->getMemoryVT();
7977 SDValue Loc = LS->getBasePtr();
7978 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7981 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7983 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7984 default: return false;
7985 case Intrinsic::ppc_altivec_lvx:
7986 case Intrinsic::ppc_altivec_lvxl:
7987 case Intrinsic::ppc_vsx_lxvw4x:
7990 case Intrinsic::ppc_vsx_lxvd2x:
7993 case Intrinsic::ppc_altivec_lvebx:
7996 case Intrinsic::ppc_altivec_lvehx:
7999 case Intrinsic::ppc_altivec_lvewx:
8004 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
8007 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8009 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8010 default: return false;
8011 case Intrinsic::ppc_altivec_stvx:
8012 case Intrinsic::ppc_altivec_stvxl:
8013 case Intrinsic::ppc_vsx_stxvw4x:
8016 case Intrinsic::ppc_vsx_stxvd2x:
8019 case Intrinsic::ppc_altivec_stvebx:
8022 case Intrinsic::ppc_altivec_stvehx:
8025 case Intrinsic::ppc_altivec_stvewx:
8030 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8036 // Return true is there is a nearyby consecutive load to the one provided
8037 // (regardless of alignment). We search up and down the chain, looking though
8038 // token factors and other loads (but nothing else). As a result, a true result
8039 // indicates that it is safe to create a new consecutive load adjacent to the
8041 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8042 SDValue Chain = LD->getChain();
8043 EVT VT = LD->getMemoryVT();
8045 SmallSet<SDNode *, 16> LoadRoots;
8046 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8047 SmallSet<SDNode *, 16> Visited;
8049 // First, search up the chain, branching to follow all token-factor operands.
8050 // If we find a consecutive load, then we're done, otherwise, record all
8051 // nodes just above the top-level loads and token factors.
8052 while (!Queue.empty()) {
8053 SDNode *ChainNext = Queue.pop_back_val();
8054 if (!Visited.insert(ChainNext).second)
8057 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8058 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8061 if (!Visited.count(ChainLD->getChain().getNode()))
8062 Queue.push_back(ChainLD->getChain().getNode());
8063 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8064 for (const SDUse &O : ChainNext->ops())
8065 if (!Visited.count(O.getNode()))
8066 Queue.push_back(O.getNode());
8068 LoadRoots.insert(ChainNext);
8071 // Second, search down the chain, starting from the top-level nodes recorded
8072 // in the first phase. These top-level nodes are the nodes just above all
8073 // loads and token factors. Starting with their uses, recursively look though
8074 // all loads (just the chain uses) and token factors to find a consecutive
8079 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8080 IE = LoadRoots.end(); I != IE; ++I) {
8081 Queue.push_back(*I);
8083 while (!Queue.empty()) {
8084 SDNode *LoadRoot = Queue.pop_back_val();
8085 if (!Visited.insert(LoadRoot).second)
8088 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8089 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8092 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8093 UE = LoadRoot->use_end(); UI != UE; ++UI)
8094 if (((isa<MemSDNode>(*UI) &&
8095 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8096 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8097 Queue.push_back(*UI);
8104 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8105 DAGCombinerInfo &DCI) const {
8106 SelectionDAG &DAG = DCI.DAG;
8109 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
8110 // If we're tracking CR bits, we need to be careful that we don't have:
8111 // trunc(binary-ops(zext(x), zext(y)))
8113 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8114 // such that we're unnecessarily moving things into GPRs when it would be
8115 // better to keep them in CR bits.
8117 // Note that trunc here can be an actual i1 trunc, or can be the effective
8118 // truncation that comes from a setcc or select_cc.
8119 if (N->getOpcode() == ISD::TRUNCATE &&
8120 N->getValueType(0) != MVT::i1)
8123 if (N->getOperand(0).getValueType() != MVT::i32 &&
8124 N->getOperand(0).getValueType() != MVT::i64)
8127 if (N->getOpcode() == ISD::SETCC ||
8128 N->getOpcode() == ISD::SELECT_CC) {
8129 // If we're looking at a comparison, then we need to make sure that the
8130 // high bits (all except for the first) don't matter the result.
8132 cast<CondCodeSDNode>(N->getOperand(
8133 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8134 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8136 if (ISD::isSignedIntSetCC(CC)) {
8137 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8138 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8140 } else if (ISD::isUnsignedIntSetCC(CC)) {
8141 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8142 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8143 !DAG.MaskedValueIsZero(N->getOperand(1),
8144 APInt::getHighBitsSet(OpBits, OpBits-1)))
8147 // This is neither a signed nor an unsigned comparison, just make sure
8148 // that the high bits are equal.
8149 APInt Op1Zero, Op1One;
8150 APInt Op2Zero, Op2One;
8151 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8152 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8154 // We don't really care about what is known about the first bit (if
8155 // anything), so clear it in all masks prior to comparing them.
8156 Op1Zero.clearBit(0); Op1One.clearBit(0);
8157 Op2Zero.clearBit(0); Op2One.clearBit(0);
8159 if (Op1Zero != Op2Zero || Op1One != Op2One)
8164 // We now know that the higher-order bits are irrelevant, we just need to
8165 // make sure that all of the intermediate operations are bit operations, and
8166 // all inputs are extensions.
8167 if (N->getOperand(0).getOpcode() != ISD::AND &&
8168 N->getOperand(0).getOpcode() != ISD::OR &&
8169 N->getOperand(0).getOpcode() != ISD::XOR &&
8170 N->getOperand(0).getOpcode() != ISD::SELECT &&
8171 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8172 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8173 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8174 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8175 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8178 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8179 N->getOperand(1).getOpcode() != ISD::AND &&
8180 N->getOperand(1).getOpcode() != ISD::OR &&
8181 N->getOperand(1).getOpcode() != ISD::XOR &&
8182 N->getOperand(1).getOpcode() != ISD::SELECT &&
8183 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8184 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8185 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8186 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8187 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8190 SmallVector<SDValue, 4> Inputs;
8191 SmallVector<SDValue, 8> BinOps, PromOps;
8192 SmallPtrSet<SDNode *, 16> Visited;
8194 for (unsigned i = 0; i < 2; ++i) {
8195 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8196 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8197 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8198 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8199 isa<ConstantSDNode>(N->getOperand(i)))
8200 Inputs.push_back(N->getOperand(i));
8202 BinOps.push_back(N->getOperand(i));
8204 if (N->getOpcode() == ISD::TRUNCATE)
8208 // Visit all inputs, collect all binary operations (and, or, xor and
8209 // select) that are all fed by extensions.
8210 while (!BinOps.empty()) {
8211 SDValue BinOp = BinOps.back();
8214 if (!Visited.insert(BinOp.getNode()).second)
8217 PromOps.push_back(BinOp);
8219 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8220 // The condition of the select is not promoted.
8221 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8223 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8226 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8227 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8228 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8229 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8230 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8231 Inputs.push_back(BinOp.getOperand(i));
8232 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8233 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8234 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8235 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8236 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8237 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8238 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8239 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8240 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8241 BinOps.push_back(BinOp.getOperand(i));
8243 // We have an input that is not an extension or another binary
8244 // operation; we'll abort this transformation.
8250 // Make sure that this is a self-contained cluster of operations (which
8251 // is not quite the same thing as saying that everything has only one
8253 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8254 if (isa<ConstantSDNode>(Inputs[i]))
8257 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8258 UE = Inputs[i].getNode()->use_end();
8261 if (User != N && !Visited.count(User))
8264 // Make sure that we're not going to promote the non-output-value
8265 // operand(s) or SELECT or SELECT_CC.
8266 // FIXME: Although we could sometimes handle this, and it does occur in
8267 // practice that one of the condition inputs to the select is also one of
8268 // the outputs, we currently can't deal with this.
8269 if (User->getOpcode() == ISD::SELECT) {
8270 if (User->getOperand(0) == Inputs[i])
8272 } else if (User->getOpcode() == ISD::SELECT_CC) {
8273 if (User->getOperand(0) == Inputs[i] ||
8274 User->getOperand(1) == Inputs[i])
8280 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8281 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8282 UE = PromOps[i].getNode()->use_end();
8285 if (User != N && !Visited.count(User))
8288 // Make sure that we're not going to promote the non-output-value
8289 // operand(s) or SELECT or SELECT_CC.
8290 // FIXME: Although we could sometimes handle this, and it does occur in
8291 // practice that one of the condition inputs to the select is also one of
8292 // the outputs, we currently can't deal with this.
8293 if (User->getOpcode() == ISD::SELECT) {
8294 if (User->getOperand(0) == PromOps[i])
8296 } else if (User->getOpcode() == ISD::SELECT_CC) {
8297 if (User->getOperand(0) == PromOps[i] ||
8298 User->getOperand(1) == PromOps[i])
8304 // Replace all inputs with the extension operand.
8305 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8306 // Constants may have users outside the cluster of to-be-promoted nodes,
8307 // and so we need to replace those as we do the promotions.
8308 if (isa<ConstantSDNode>(Inputs[i]))
8311 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8314 // Replace all operations (these are all the same, but have a different
8315 // (i1) return type). DAG.getNode will validate that the types of
8316 // a binary operator match, so go through the list in reverse so that
8317 // we've likely promoted both operands first. Any intermediate truncations or
8318 // extensions disappear.
8319 while (!PromOps.empty()) {
8320 SDValue PromOp = PromOps.back();
8323 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8324 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8325 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8326 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8327 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8328 PromOp.getOperand(0).getValueType() != MVT::i1) {
8329 // The operand is not yet ready (see comment below).
8330 PromOps.insert(PromOps.begin(), PromOp);
8334 SDValue RepValue = PromOp.getOperand(0);
8335 if (isa<ConstantSDNode>(RepValue))
8336 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8338 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8343 switch (PromOp.getOpcode()) {
8344 default: C = 0; break;
8345 case ISD::SELECT: C = 1; break;
8346 case ISD::SELECT_CC: C = 2; break;
8349 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8350 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8351 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8352 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8353 // The to-be-promoted operands of this node have not yet been
8354 // promoted (this should be rare because we're going through the
8355 // list backward, but if one of the operands has several users in
8356 // this cluster of to-be-promoted nodes, it is possible).
8357 PromOps.insert(PromOps.begin(), PromOp);
8361 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8362 PromOp.getNode()->op_end());
8364 // If there are any constant inputs, make sure they're replaced now.
8365 for (unsigned i = 0; i < 2; ++i)
8366 if (isa<ConstantSDNode>(Ops[C+i]))
8367 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8369 DAG.ReplaceAllUsesOfValueWith(PromOp,
8370 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8373 // Now we're left with the initial truncation itself.
8374 if (N->getOpcode() == ISD::TRUNCATE)
8375 return N->getOperand(0);
8377 // Otherwise, this is a comparison. The operands to be compared have just
8378 // changed type (to i1), but everything else is the same.
8379 return SDValue(N, 0);
8382 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8383 DAGCombinerInfo &DCI) const {
8384 SelectionDAG &DAG = DCI.DAG;
8387 // If we're tracking CR bits, we need to be careful that we don't have:
8388 // zext(binary-ops(trunc(x), trunc(y)))
8390 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8391 // such that we're unnecessarily moving things into CR bits that can more
8392 // efficiently stay in GPRs. Note that if we're not certain that the high
8393 // bits are set as required by the final extension, we still may need to do
8394 // some masking to get the proper behavior.
8396 // This same functionality is important on PPC64 when dealing with
8397 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8398 // the return values of functions. Because it is so similar, it is handled
8401 if (N->getValueType(0) != MVT::i32 &&
8402 N->getValueType(0) != MVT::i64)
8405 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
8406 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
8409 if (N->getOperand(0).getOpcode() != ISD::AND &&
8410 N->getOperand(0).getOpcode() != ISD::OR &&
8411 N->getOperand(0).getOpcode() != ISD::XOR &&
8412 N->getOperand(0).getOpcode() != ISD::SELECT &&
8413 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8416 SmallVector<SDValue, 4> Inputs;
8417 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8418 SmallPtrSet<SDNode *, 16> Visited;
8420 // Visit all inputs, collect all binary operations (and, or, xor and
8421 // select) that are all fed by truncations.
8422 while (!BinOps.empty()) {
8423 SDValue BinOp = BinOps.back();
8426 if (!Visited.insert(BinOp.getNode()).second)
8429 PromOps.push_back(BinOp);
8431 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8432 // The condition of the select is not promoted.
8433 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8435 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8438 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8439 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8440 Inputs.push_back(BinOp.getOperand(i));
8441 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8442 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8443 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8444 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8445 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8446 BinOps.push_back(BinOp.getOperand(i));
8448 // We have an input that is not a truncation or another binary
8449 // operation; we'll abort this transformation.
8455 // The operands of a select that must be truncated when the select is
8456 // promoted because the operand is actually part of the to-be-promoted set.
8457 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8459 // Make sure that this is a self-contained cluster of operations (which
8460 // is not quite the same thing as saying that everything has only one
8462 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8463 if (isa<ConstantSDNode>(Inputs[i]))
8466 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8467 UE = Inputs[i].getNode()->use_end();
8470 if (User != N && !Visited.count(User))
8473 // If we're going to promote the non-output-value operand(s) or SELECT or
8474 // SELECT_CC, record them for truncation.
8475 if (User->getOpcode() == ISD::SELECT) {
8476 if (User->getOperand(0) == Inputs[i])
8477 SelectTruncOp[0].insert(std::make_pair(User,
8478 User->getOperand(0).getValueType()));
8479 } else if (User->getOpcode() == ISD::SELECT_CC) {
8480 if (User->getOperand(0) == Inputs[i])
8481 SelectTruncOp[0].insert(std::make_pair(User,
8482 User->getOperand(0).getValueType()));
8483 if (User->getOperand(1) == Inputs[i])
8484 SelectTruncOp[1].insert(std::make_pair(User,
8485 User->getOperand(1).getValueType()));
8490 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8491 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8492 UE = PromOps[i].getNode()->use_end();
8495 if (User != N && !Visited.count(User))
8498 // If we're going to promote the non-output-value operand(s) or SELECT or
8499 // SELECT_CC, record them for truncation.
8500 if (User->getOpcode() == ISD::SELECT) {
8501 if (User->getOperand(0) == PromOps[i])
8502 SelectTruncOp[0].insert(std::make_pair(User,
8503 User->getOperand(0).getValueType()));
8504 } else if (User->getOpcode() == ISD::SELECT_CC) {
8505 if (User->getOperand(0) == PromOps[i])
8506 SelectTruncOp[0].insert(std::make_pair(User,
8507 User->getOperand(0).getValueType()));
8508 if (User->getOperand(1) == PromOps[i])
8509 SelectTruncOp[1].insert(std::make_pair(User,
8510 User->getOperand(1).getValueType()));
8515 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8516 bool ReallyNeedsExt = false;
8517 if (N->getOpcode() != ISD::ANY_EXTEND) {
8518 // If all of the inputs are not already sign/zero extended, then
8519 // we'll still need to do that at the end.
8520 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8521 if (isa<ConstantSDNode>(Inputs[i]))
8525 Inputs[i].getOperand(0).getValueSizeInBits();
8526 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8528 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8529 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8530 APInt::getHighBitsSet(OpBits,
8531 OpBits-PromBits))) ||
8532 (N->getOpcode() == ISD::SIGN_EXTEND &&
8533 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8534 (OpBits-(PromBits-1)))) {
8535 ReallyNeedsExt = true;
8541 // Replace all inputs, either with the truncation operand, or a
8542 // truncation or extension to the final output type.
8543 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8544 // Constant inputs need to be replaced with the to-be-promoted nodes that
8545 // use them because they might have users outside of the cluster of
8547 if (isa<ConstantSDNode>(Inputs[i]))
8550 SDValue InSrc = Inputs[i].getOperand(0);
8551 if (Inputs[i].getValueType() == N->getValueType(0))
8552 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8553 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8554 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8555 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8556 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8557 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8558 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8560 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8561 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8564 // Replace all operations (these are all the same, but have a different
8565 // (promoted) return type). DAG.getNode will validate that the types of
8566 // a binary operator match, so go through the list in reverse so that
8567 // we've likely promoted both operands first.
8568 while (!PromOps.empty()) {
8569 SDValue PromOp = PromOps.back();
8573 switch (PromOp.getOpcode()) {
8574 default: C = 0; break;
8575 case ISD::SELECT: C = 1; break;
8576 case ISD::SELECT_CC: C = 2; break;
8579 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8580 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8581 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8582 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8583 // The to-be-promoted operands of this node have not yet been
8584 // promoted (this should be rare because we're going through the
8585 // list backward, but if one of the operands has several users in
8586 // this cluster of to-be-promoted nodes, it is possible).
8587 PromOps.insert(PromOps.begin(), PromOp);
8591 // For SELECT and SELECT_CC nodes, we do a similar check for any
8592 // to-be-promoted comparison inputs.
8593 if (PromOp.getOpcode() == ISD::SELECT ||
8594 PromOp.getOpcode() == ISD::SELECT_CC) {
8595 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8596 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8597 (SelectTruncOp[1].count(PromOp.getNode()) &&
8598 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8599 PromOps.insert(PromOps.begin(), PromOp);
8604 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8605 PromOp.getNode()->op_end());
8607 // If this node has constant inputs, then they'll need to be promoted here.
8608 for (unsigned i = 0; i < 2; ++i) {
8609 if (!isa<ConstantSDNode>(Ops[C+i]))
8611 if (Ops[C+i].getValueType() == N->getValueType(0))
8614 if (N->getOpcode() == ISD::SIGN_EXTEND)
8615 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8616 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8617 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8619 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8622 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8623 // truncate them again to the original value type.
8624 if (PromOp.getOpcode() == ISD::SELECT ||
8625 PromOp.getOpcode() == ISD::SELECT_CC) {
8626 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8627 if (SI0 != SelectTruncOp[0].end())
8628 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8629 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8630 if (SI1 != SelectTruncOp[1].end())
8631 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8634 DAG.ReplaceAllUsesOfValueWith(PromOp,
8635 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8638 // Now we're left with the initial extension itself.
8639 if (!ReallyNeedsExt)
8640 return N->getOperand(0);
8642 // To zero extend, just mask off everything except for the first bit (in the
8644 if (N->getOpcode() == ISD::ZERO_EXTEND)
8645 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8646 DAG.getConstant(APInt::getLowBitsSet(
8647 N->getValueSizeInBits(0), PromBits),
8648 N->getValueType(0)));
8650 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8651 "Invalid extension type");
8652 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8654 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8655 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8656 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8657 N->getOperand(0), ShiftCst), ShiftCst);
8660 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8661 DAGCombinerInfo &DCI) const {
8662 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8663 N->getOpcode() == ISD::UINT_TO_FP) &&
8664 "Need an int -> FP conversion node here");
8666 if (!Subtarget.has64BitSupport())
8669 SelectionDAG &DAG = DCI.DAG;
8673 // Don't handle ppc_fp128 here or i1 conversions.
8674 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8676 if (Op.getOperand(0).getValueType() == MVT::i1)
8679 // For i32 intermediate values, unfortunately, the conversion functions
8680 // leave the upper 32 bits of the value are undefined. Within the set of
8681 // scalar instructions, we have no method for zero- or sign-extending the
8682 // value. Thus, we cannot handle i32 intermediate values here.
8683 if (Op.getOperand(0).getValueType() == MVT::i32)
8686 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8687 "UINT_TO_FP is supported only with FPCVT");
8689 // If we have FCFIDS, then use it when converting to single-precision.
8690 // Otherwise, convert to double-precision and then round.
8691 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8692 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
8694 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
8696 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8700 // If we're converting from a float, to an int, and back to a float again,
8701 // then we don't need the store/load pair at all.
8702 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8703 Subtarget.hasFPCVT()) ||
8704 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8705 SDValue Src = Op.getOperand(0).getOperand(0);
8706 if (Src.getValueType() == MVT::f32) {
8707 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8708 DCI.AddToWorklist(Src.getNode());
8712 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8715 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8716 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8718 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8719 FP = DAG.getNode(ISD::FP_ROUND, dl,
8720 MVT::f32, FP, DAG.getIntPtrConstant(0));
8721 DCI.AddToWorklist(FP.getNode());
8730 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8731 // builtins) into loads with swaps.
8732 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8733 DAGCombinerInfo &DCI) const {
8734 SelectionDAG &DAG = DCI.DAG;
8738 MachineMemOperand *MMO;
8740 switch (N->getOpcode()) {
8742 llvm_unreachable("Unexpected opcode for little endian VSX load");
8744 LoadSDNode *LD = cast<LoadSDNode>(N);
8745 Chain = LD->getChain();
8746 Base = LD->getBasePtr();
8747 MMO = LD->getMemOperand();
8748 // If the MMO suggests this isn't a load of a full vector, leave
8749 // things alone. For a built-in, we have to make the change for
8750 // correctness, so if there is a size problem that will be a bug.
8751 if (MMO->getSize() < 16)
8755 case ISD::INTRINSIC_W_CHAIN: {
8756 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8757 Chain = Intrin->getChain();
8758 Base = Intrin->getBasePtr();
8759 MMO = Intrin->getMemOperand();
8764 MVT VecTy = N->getValueType(0).getSimpleVT();
8765 SDValue LoadOps[] = { Chain, Base };
8766 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8767 DAG.getVTList(VecTy, MVT::Other),
8768 LoadOps, VecTy, MMO);
8769 DCI.AddToWorklist(Load.getNode());
8770 Chain = Load.getValue(1);
8771 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8772 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8773 DCI.AddToWorklist(Swap.getNode());
8777 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8778 // builtins) into stores with swaps.
8779 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8780 DAGCombinerInfo &DCI) const {
8781 SelectionDAG &DAG = DCI.DAG;
8786 MachineMemOperand *MMO;
8788 switch (N->getOpcode()) {
8790 llvm_unreachable("Unexpected opcode for little endian VSX store");
8792 StoreSDNode *ST = cast<StoreSDNode>(N);
8793 Chain = ST->getChain();
8794 Base = ST->getBasePtr();
8795 MMO = ST->getMemOperand();
8797 // If the MMO suggests this isn't a store of a full vector, leave
8798 // things alone. For a built-in, we have to make the change for
8799 // correctness, so if there is a size problem that will be a bug.
8800 if (MMO->getSize() < 16)
8804 case ISD::INTRINSIC_VOID: {
8805 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8806 Chain = Intrin->getChain();
8807 // Intrin->getBasePtr() oddly does not get what we want.
8808 Base = Intrin->getOperand(3);
8809 MMO = Intrin->getMemOperand();
8815 SDValue Src = N->getOperand(SrcOpnd);
8816 MVT VecTy = Src.getValueType().getSimpleVT();
8817 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8818 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8819 DCI.AddToWorklist(Swap.getNode());
8820 Chain = Swap.getValue(1);
8821 SDValue StoreOps[] = { Chain, Swap, Base };
8822 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8823 DAG.getVTList(MVT::Other),
8824 StoreOps, VecTy, MMO);
8825 DCI.AddToWorklist(Store.getNode());
8829 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8830 DAGCombinerInfo &DCI) const {
8831 SelectionDAG &DAG = DCI.DAG;
8833 switch (N->getOpcode()) {
8836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8837 if (C->isNullValue()) // 0 << V -> 0.
8838 return N->getOperand(0);
8842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8843 if (C->isNullValue()) // 0 >>u V -> 0.
8844 return N->getOperand(0);
8848 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8849 if (C->isNullValue() || // 0 >>s V -> 0.
8850 C->isAllOnesValue()) // -1 >>s V -> -1.
8851 return N->getOperand(0);
8854 case ISD::SIGN_EXTEND:
8855 case ISD::ZERO_EXTEND:
8856 case ISD::ANY_EXTEND:
8857 return DAGCombineExtBoolTrunc(N, DCI);
8860 case ISD::SELECT_CC:
8861 return DAGCombineTruncBoolExt(N, DCI);
8862 case ISD::SINT_TO_FP:
8863 case ISD::UINT_TO_FP:
8864 return combineFPToIntToFP(N, DCI);
8866 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8867 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
8868 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8869 N->getOperand(1).getValueType() == MVT::i32 &&
8870 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8871 SDValue Val = N->getOperand(1).getOperand(0);
8872 if (Val.getValueType() == MVT::f32) {
8873 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8874 DCI.AddToWorklist(Val.getNode());
8876 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8877 DCI.AddToWorklist(Val.getNode());
8880 N->getOperand(0), Val, N->getOperand(2),
8881 DAG.getValueType(N->getOperand(1).getValueType())
8884 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8885 DAG.getVTList(MVT::Other), Ops,
8886 cast<StoreSDNode>(N)->getMemoryVT(),
8887 cast<StoreSDNode>(N)->getMemOperand());
8888 DCI.AddToWorklist(Val.getNode());
8892 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8893 if (cast<StoreSDNode>(N)->isUnindexed() &&
8894 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8895 N->getOperand(1).getNode()->hasOneUse() &&
8896 (N->getOperand(1).getValueType() == MVT::i32 ||
8897 N->getOperand(1).getValueType() == MVT::i16 ||
8898 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
8899 N->getOperand(1).getValueType() == MVT::i64))) {
8900 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8901 // Do an any-extend to 32-bits if this is a half-word input.
8902 if (BSwapOp.getValueType() == MVT::i16)
8903 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8906 N->getOperand(0), BSwapOp, N->getOperand(2),
8907 DAG.getValueType(N->getOperand(1).getValueType())
8910 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8911 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8912 cast<StoreSDNode>(N)->getMemOperand());
8915 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8916 EVT VT = N->getOperand(1).getValueType();
8917 if (VT.isSimple()) {
8918 MVT StoreVT = VT.getSimpleVT();
8919 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8920 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8921 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8922 return expandVSXStoreForLE(N, DCI);
8927 LoadSDNode *LD = cast<LoadSDNode>(N);
8928 EVT VT = LD->getValueType(0);
8930 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8931 if (VT.isSimple()) {
8932 MVT LoadVT = VT.getSimpleVT();
8933 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8934 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8935 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8936 return expandVSXLoadForLE(N, DCI);
8939 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8940 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8941 if (ISD::isNON_EXTLoad(N) && VT.isVector() && Subtarget.hasAltivec() &&
8942 // P8 and later hardware should just use LOAD.
8943 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8944 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8945 LD->getAlignment() < ABIAlignment) {
8946 // This is a type-legal unaligned Altivec load.
8947 SDValue Chain = LD->getChain();
8948 SDValue Ptr = LD->getBasePtr();
8949 bool isLittleEndian = Subtarget.isLittleEndian();
8951 // This implements the loading of unaligned vectors as described in
8952 // the venerable Apple Velocity Engine overview. Specifically:
8953 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8954 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8956 // The general idea is to expand a sequence of one or more unaligned
8957 // loads into an alignment-based permutation-control instruction (lvsl
8958 // or lvsr), a series of regular vector loads (which always truncate
8959 // their input address to an aligned address), and a series of
8960 // permutations. The results of these permutations are the requested
8961 // loaded values. The trick is that the last "extra" load is not taken
8962 // from the address you might suspect (sizeof(vector) bytes after the
8963 // last requested load), but rather sizeof(vector) - 1 bytes after the
8964 // last requested vector. The point of this is to avoid a page fault if
8965 // the base address happened to be aligned. This works because if the
8966 // base address is aligned, then adding less than a full vector length
8967 // will cause the last vector in the sequence to be (re)loaded.
8968 // Otherwise, the next vector will be fetched as you might suspect was
8971 // We might be able to reuse the permutation generation from
8972 // a different base address offset from this one by an aligned amount.
8973 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8974 // optimization later.
8975 Intrinsic::ID Intr = (isLittleEndian ?
8976 Intrinsic::ppc_altivec_lvsr :
8977 Intrinsic::ppc_altivec_lvsl);
8978 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8980 // Create the new MMO for the new base load. It is like the original MMO,
8981 // but represents an area in memory almost twice the vector size centered
8982 // on the original address. If the address is unaligned, we might start
8983 // reading up to (sizeof(vector)-1) bytes below the address of the
8984 // original unaligned load.
8985 MachineFunction &MF = DAG.getMachineFunction();
8986 MachineMemOperand *BaseMMO =
8987 MF.getMachineMemOperand(LD->getMemOperand(),
8988 -LD->getMemoryVT().getStoreSize()+1,
8989 2*LD->getMemoryVT().getStoreSize()-1);
8991 // Create the new base load.
8992 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8994 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8996 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8997 DAG.getVTList(MVT::v4i32, MVT::Other),
8998 BaseLoadOps, MVT::v4i32, BaseMMO);
9000 // Note that the value of IncOffset (which is provided to the next
9001 // load's pointer info offset value, and thus used to calculate the
9002 // alignment), and the value of IncValue (which is actually used to
9003 // increment the pointer value) are different! This is because we
9004 // require the next load to appear to be aligned, even though it
9005 // is actually offset from the base pointer by a lesser amount.
9006 int IncOffset = VT.getSizeInBits() / 8;
9007 int IncValue = IncOffset;
9009 // Walk (both up and down) the chain looking for another load at the real
9010 // (aligned) offset (the alignment of the other load does not matter in
9011 // this case). If found, then do not use the offset reduction trick, as
9012 // that will prevent the loads from being later combined (as they would
9013 // otherwise be duplicates).
9014 if (!findConsecutiveLoad(LD, DAG))
9017 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9018 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9020 MachineMemOperand *ExtraMMO =
9021 MF.getMachineMemOperand(LD->getMemOperand(),
9022 1, 2*LD->getMemoryVT().getStoreSize()-1);
9023 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9025 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9026 DAG.getVTList(MVT::v4i32, MVT::Other),
9027 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9029 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9030 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9032 // Because vperm has a big-endian bias, we must reverse the order
9033 // of the input vectors and complement the permute control vector
9034 // when generating little endian code. We have already handled the
9035 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9036 // and ExtraLoad here.
9039 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9040 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9042 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9043 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9045 if (VT != MVT::v4i32)
9046 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9048 // The output of the permutation is our loaded result, the TokenFactor is
9050 DCI.CombineTo(N, Perm, TF);
9051 return SDValue(N, 0);
9055 case ISD::INTRINSIC_WO_CHAIN: {
9056 bool isLittleEndian = Subtarget.isLittleEndian();
9057 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
9058 : Intrinsic::ppc_altivec_lvsl);
9059 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9060 N->getOperand(1)->getOpcode() == ISD::ADD) {
9061 SDValue Add = N->getOperand(1);
9063 if (DAG.MaskedValueIsZero(
9065 APInt::getAllOnesValue(4 /* 16 byte alignment */)
9067 Add.getValueType().getScalarType().getSizeInBits()))) {
9068 SDNode *BasePtr = Add->getOperand(0).getNode();
9069 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9070 UE = BasePtr->use_end();
9072 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9073 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9075 // We've found another LVSL/LVSR, and this address is an aligned
9076 // multiple of that one. The results will be the same, so use the
9077 // one we've just found instead.
9079 return SDValue(*UI, 0);
9087 case ISD::INTRINSIC_W_CHAIN: {
9088 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9089 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9090 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9093 case Intrinsic::ppc_vsx_lxvw4x:
9094 case Intrinsic::ppc_vsx_lxvd2x:
9095 return expandVSXLoadForLE(N, DCI);
9100 case ISD::INTRINSIC_VOID: {
9101 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9102 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9103 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9106 case Intrinsic::ppc_vsx_stxvw4x:
9107 case Intrinsic::ppc_vsx_stxvd2x:
9108 return expandVSXStoreForLE(N, DCI);
9114 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9115 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9116 N->getOperand(0).hasOneUse() &&
9117 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9118 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9119 N->getValueType(0) == MVT::i64))) {
9120 SDValue Load = N->getOperand(0);
9121 LoadSDNode *LD = cast<LoadSDNode>(Load);
9122 // Create the byte-swapping load.
9124 LD->getChain(), // Chain
9125 LD->getBasePtr(), // Ptr
9126 DAG.getValueType(N->getValueType(0)) // VT
9129 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9130 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9131 MVT::i64 : MVT::i32, MVT::Other),
9132 Ops, LD->getMemoryVT(), LD->getMemOperand());
9134 // If this is an i16 load, insert the truncate.
9135 SDValue ResVal = BSLoad;
9136 if (N->getValueType(0) == MVT::i16)
9137 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9139 // First, combine the bswap away. This makes the value produced by the
9141 DCI.CombineTo(N, ResVal);
9143 // Next, combine the load away, we give it a bogus result value but a real
9144 // chain result. The result value is dead because the bswap is dead.
9145 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9147 // Return N so it doesn't get rechecked!
9148 return SDValue(N, 0);
9152 case PPCISD::VCMP: {
9153 // If a VCMPo node already exists with exactly the same operands as this
9154 // node, use its result instead of this node (VCMPo computes both a CR6 and
9155 // a normal output).
9157 if (!N->getOperand(0).hasOneUse() &&
9158 !N->getOperand(1).hasOneUse() &&
9159 !N->getOperand(2).hasOneUse()) {
9161 // Scan all of the users of the LHS, looking for VCMPo's that match.
9162 SDNode *VCMPoNode = nullptr;
9164 SDNode *LHSN = N->getOperand(0).getNode();
9165 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9167 if (UI->getOpcode() == PPCISD::VCMPo &&
9168 UI->getOperand(1) == N->getOperand(1) &&
9169 UI->getOperand(2) == N->getOperand(2) &&
9170 UI->getOperand(0) == N->getOperand(0)) {
9175 // If there is no VCMPo node, or if the flag value has a single use, don't
9177 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9180 // Look at the (necessarily single) use of the flag value. If it has a
9181 // chain, this transformation is more complex. Note that multiple things
9182 // could use the value result, which we should ignore.
9183 SDNode *FlagUser = nullptr;
9184 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9185 FlagUser == nullptr; ++UI) {
9186 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9188 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9189 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9196 // If the user is a MFOCRF instruction, we know this is safe.
9197 // Otherwise we give up for right now.
9198 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9199 return SDValue(VCMPoNode, 0);
9204 SDValue Cond = N->getOperand(1);
9205 SDValue Target = N->getOperand(2);
9207 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9208 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9209 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9211 // We now need to make the intrinsic dead (it cannot be instruction
9213 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9214 assert(Cond.getNode()->hasOneUse() &&
9215 "Counter decrement has more than one use");
9217 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9218 N->getOperand(0), Target);
9223 // If this is a branch on an altivec predicate comparison, lower this so
9224 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9225 // lowering is done pre-legalize, because the legalizer lowers the predicate
9226 // compare down to code that is difficult to reassemble.
9227 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9228 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9230 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9231 // value. If so, pass-through the AND to get to the intrinsic.
9232 if (LHS.getOpcode() == ISD::AND &&
9233 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9234 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9235 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9236 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9237 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9239 LHS = LHS.getOperand(0);
9241 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9242 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9243 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9244 isa<ConstantSDNode>(RHS)) {
9245 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9246 "Counter decrement comparison is not EQ or NE");
9248 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9249 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9250 (CC == ISD::SETNE && !Val);
9252 // We now need to make the intrinsic dead (it cannot be instruction
9254 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9255 assert(LHS.getNode()->hasOneUse() &&
9256 "Counter decrement has more than one use");
9258 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9259 N->getOperand(0), N->getOperand(4));
9265 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9266 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9267 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9268 assert(isDot && "Can't compare against a vector result!");
9270 // If this is a comparison against something other than 0/1, then we know
9271 // that the condition is never/always true.
9272 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9273 if (Val != 0 && Val != 1) {
9274 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9275 return N->getOperand(0);
9276 // Always !=, turn it into an unconditional branch.
9277 return DAG.getNode(ISD::BR, dl, MVT::Other,
9278 N->getOperand(0), N->getOperand(4));
9281 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9283 // Create the PPCISD altivec 'dot' comparison node.
9285 LHS.getOperand(2), // LHS of compare
9286 LHS.getOperand(3), // RHS of compare
9287 DAG.getConstant(CompareOpc, MVT::i32)
9289 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9290 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9292 // Unpack the result based on how the target uses it.
9293 PPC::Predicate CompOpc;
9294 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9295 default: // Can't happen, don't crash on invalid number though.
9296 case 0: // Branch on the value of the EQ bit of CR6.
9297 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9299 case 1: // Branch on the inverted value of the EQ bit of CR6.
9300 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9302 case 2: // Branch on the value of the LT bit of CR6.
9303 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9305 case 3: // Branch on the inverted value of the LT bit of CR6.
9306 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9310 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9311 DAG.getConstant(CompOpc, MVT::i32),
9312 DAG.getRegister(PPC::CR6, MVT::i32),
9313 N->getOperand(4), CompNode.getValue(1));
9323 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9325 std::vector<SDNode *> *Created) const {
9326 // fold (sdiv X, pow2)
9327 EVT VT = N->getValueType(0);
9328 if (VT == MVT::i64 && !Subtarget.isPPC64())
9330 if ((VT != MVT::i32 && VT != MVT::i64) ||
9331 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9335 SDValue N0 = N->getOperand(0);
9337 bool IsNegPow2 = (-Divisor).isPowerOf2();
9338 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9339 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9341 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9343 Created->push_back(Op.getNode());
9346 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9348 Created->push_back(Op.getNode());
9354 //===----------------------------------------------------------------------===//
9355 // Inline Assembly Support
9356 //===----------------------------------------------------------------------===//
9358 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9361 const SelectionDAG &DAG,
9362 unsigned Depth) const {
9363 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9364 switch (Op.getOpcode()) {
9366 case PPCISD::LBRX: {
9367 // lhbrx is known to have the top bits cleared out.
9368 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9369 KnownZero = 0xFFFF0000;
9372 case ISD::INTRINSIC_WO_CHAIN: {
9373 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9375 case Intrinsic::ppc_altivec_vcmpbfp_p:
9376 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9377 case Intrinsic::ppc_altivec_vcmpequb_p:
9378 case Intrinsic::ppc_altivec_vcmpequh_p:
9379 case Intrinsic::ppc_altivec_vcmpequw_p:
9380 case Intrinsic::ppc_altivec_vcmpgefp_p:
9381 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9382 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9383 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9384 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9385 case Intrinsic::ppc_altivec_vcmpgtub_p:
9386 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9387 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9388 KnownZero = ~1U; // All bits but the low one are known to be zero.
9395 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9396 switch (Subtarget.getDarwinDirective()) {
9401 case PPC::DIR_PWR5X:
9403 case PPC::DIR_PWR6X:
9405 case PPC::DIR_PWR8: {
9409 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
9411 // For small loops (between 5 and 8 instructions), align to a 32-byte
9412 // boundary so that the entire loop fits in one instruction-cache line.
9413 uint64_t LoopSize = 0;
9414 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9415 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9416 LoopSize += TII->GetInstSizeInBytes(J);
9418 if (LoopSize > 16 && LoopSize <= 32)
9425 return TargetLowering::getPrefLoopAlignment(ML);
9428 /// getConstraintType - Given a constraint, return the type of
9429 /// constraint it is for this target.
9430 PPCTargetLowering::ConstraintType
9431 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9432 if (Constraint.size() == 1) {
9433 switch (Constraint[0]) {
9440 return C_RegisterClass;
9442 // FIXME: While Z does indicate a memory constraint, it specifically
9443 // indicates an r+r address (used in conjunction with the 'y' modifier
9444 // in the replacement string). Currently, we're forcing the base
9445 // register to be r0 in the asm printer (which is interpreted as zero)
9446 // and forming the complete address in the second register. This is
9450 } else if (Constraint == "wc") { // individual CR bits.
9451 return C_RegisterClass;
9452 } else if (Constraint == "wa" || Constraint == "wd" ||
9453 Constraint == "wf" || Constraint == "ws") {
9454 return C_RegisterClass; // VSX registers.
9456 return TargetLowering::getConstraintType(Constraint);
9459 /// Examine constraint type and operand type and determine a weight value.
9460 /// This object must already have been set up with the operand type
9461 /// and the current alternative constraint selected.
9462 TargetLowering::ConstraintWeight
9463 PPCTargetLowering::getSingleConstraintMatchWeight(
9464 AsmOperandInfo &info, const char *constraint) const {
9465 ConstraintWeight weight = CW_Invalid;
9466 Value *CallOperandVal = info.CallOperandVal;
9467 // If we don't have a value, we can't do a match,
9468 // but allow it at the lowest weight.
9469 if (!CallOperandVal)
9471 Type *type = CallOperandVal->getType();
9473 // Look at the constraint type.
9474 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9475 return CW_Register; // an individual CR bit.
9476 else if ((StringRef(constraint) == "wa" ||
9477 StringRef(constraint) == "wd" ||
9478 StringRef(constraint) == "wf") &&
9481 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9484 switch (*constraint) {
9486 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9489 if (type->isIntegerTy())
9490 weight = CW_Register;
9493 if (type->isFloatTy())
9494 weight = CW_Register;
9497 if (type->isDoubleTy())
9498 weight = CW_Register;
9501 if (type->isVectorTy())
9502 weight = CW_Register;
9505 weight = CW_Register;
9514 std::pair<unsigned, const TargetRegisterClass*>
9515 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9517 if (Constraint.size() == 1) {
9518 // GCC RS6000 Constraint Letters
9519 switch (Constraint[0]) {
9521 if (VT == MVT::i64 && Subtarget.isPPC64())
9522 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9523 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9525 if (VT == MVT::i64 && Subtarget.isPPC64())
9526 return std::make_pair(0U, &PPC::G8RCRegClass);
9527 return std::make_pair(0U, &PPC::GPRCRegClass);
9529 if (VT == MVT::f32 || VT == MVT::i32)
9530 return std::make_pair(0U, &PPC::F4RCRegClass);
9531 if (VT == MVT::f64 || VT == MVT::i64)
9532 return std::make_pair(0U, &PPC::F8RCRegClass);
9535 return std::make_pair(0U, &PPC::VRRCRegClass);
9537 return std::make_pair(0U, &PPC::CRRCRegClass);
9539 } else if (Constraint == "wc") { // an individual CR bit.
9540 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9541 } else if (Constraint == "wa" || Constraint == "wd" ||
9542 Constraint == "wf") {
9543 return std::make_pair(0U, &PPC::VSRCRegClass);
9544 } else if (Constraint == "ws") {
9545 return std::make_pair(0U, &PPC::VSFRCRegClass);
9548 std::pair<unsigned, const TargetRegisterClass*> R =
9549 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9551 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9552 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9553 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9555 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9556 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9557 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9558 PPC::GPRCRegClass.contains(R.first)) {
9559 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
9560 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9561 PPC::sub_32, &PPC::G8RCRegClass),
9562 &PPC::G8RCRegClass);
9565 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9566 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9568 R.second = &PPC::CRRCRegClass;
9575 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9576 /// vector. If it is invalid, don't add anything to Ops.
9577 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9578 std::string &Constraint,
9579 std::vector<SDValue>&Ops,
9580 SelectionDAG &DAG) const {
9583 // Only support length 1 constraints.
9584 if (Constraint.length() > 1) return;
9586 char Letter = Constraint[0];
9597 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9598 if (!CST) return; // Must be an immediate to match.
9599 int64_t Value = CST->getSExtValue();
9600 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9601 // numbers are printed as such.
9603 default: llvm_unreachable("Unknown constraint letter!");
9604 case 'I': // "I" is a signed 16-bit constant.
9605 if (isInt<16>(Value))
9606 Result = DAG.getTargetConstant(Value, TCVT);
9608 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9609 if (isShiftedUInt<16, 16>(Value))
9610 Result = DAG.getTargetConstant(Value, TCVT);
9612 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9613 if (isShiftedInt<16, 16>(Value))
9614 Result = DAG.getTargetConstant(Value, TCVT);
9616 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9617 if (isUInt<16>(Value))
9618 Result = DAG.getTargetConstant(Value, TCVT);
9620 case 'M': // "M" is a constant that is greater than 31.
9622 Result = DAG.getTargetConstant(Value, TCVT);
9624 case 'N': // "N" is a positive constant that is an exact power of two.
9625 if (Value > 0 && isPowerOf2_64(Value))
9626 Result = DAG.getTargetConstant(Value, TCVT);
9628 case 'O': // "O" is the constant zero.
9630 Result = DAG.getTargetConstant(Value, TCVT);
9632 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9633 if (isInt<16>(-Value))
9634 Result = DAG.getTargetConstant(Value, TCVT);
9641 if (Result.getNode()) {
9642 Ops.push_back(Result);
9646 // Handle standard constraint letters.
9647 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9650 // isLegalAddressingMode - Return true if the addressing mode represented
9651 // by AM is legal for this target, for a load/store of the specified type.
9652 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9654 // FIXME: PPC does not allow r+i addressing modes for vectors!
9656 // PPC allows a sign-extended 16-bit immediate field.
9657 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9660 // No global is ever allowed as a base.
9664 // PPC only support r+r,
9666 case 0: // "r+i" or just "i", depending on HasBaseReg.
9669 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9671 // Otherwise we have r+r or r+i.
9674 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9676 // Allow 2*r as r+r.
9679 // No other scales are supported.
9686 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9687 SelectionDAG &DAG) const {
9688 MachineFunction &MF = DAG.getMachineFunction();
9689 MachineFrameInfo *MFI = MF.getFrameInfo();
9690 MFI->setReturnAddressIsTaken(true);
9692 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9696 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9698 // Make sure the function does not optimize away the store of the RA to
9700 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9701 FuncInfo->setLRStoreRequired();
9702 bool isPPC64 = Subtarget.isPPC64();
9705 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9707 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(),
9708 isPPC64 ? MVT::i64 : MVT::i32);
9709 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9710 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9712 MachinePointerInfo(), false, false, false, 0);
9715 // Just load the return address off the stack.
9716 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9717 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9718 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9721 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9722 SelectionDAG &DAG) const {
9724 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9726 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9727 bool isPPC64 = PtrVT == MVT::i64;
9729 MachineFunction &MF = DAG.getMachineFunction();
9730 MachineFrameInfo *MFI = MF.getFrameInfo();
9731 MFI->setFrameAddressIsTaken(true);
9733 // Naked functions never have a frame pointer, and so we use r1. For all
9734 // other functions, this decision must be delayed until during PEI.
9736 if (MF.getFunction()->getAttributes().hasAttribute(
9737 AttributeSet::FunctionIndex, Attribute::Naked))
9738 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9740 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9742 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9745 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9746 FrameAddr, MachinePointerInfo(), false, false,
9751 // FIXME? Maybe this could be a TableGen attribute on some registers and
9752 // this table could be generated automatically from RegInfo.
9753 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9755 bool isPPC64 = Subtarget.isPPC64();
9756 bool isDarwinABI = Subtarget.isDarwinABI();
9758 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9759 (!isPPC64 && VT != MVT::i32))
9760 report_fatal_error("Invalid register global variable type");
9762 bool is64Bit = isPPC64 && VT == MVT::i64;
9763 unsigned Reg = StringSwitch<unsigned>(RegName)
9764 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9765 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
9766 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9767 (is64Bit ? PPC::X13 : PPC::R13))
9772 report_fatal_error("Invalid register name global variable");
9776 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9777 // The PowerPC target isn't yet aware of offsets.
9781 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9783 unsigned Intrinsic) const {
9785 switch (Intrinsic) {
9786 case Intrinsic::ppc_altivec_lvx:
9787 case Intrinsic::ppc_altivec_lvxl:
9788 case Intrinsic::ppc_altivec_lvebx:
9789 case Intrinsic::ppc_altivec_lvehx:
9790 case Intrinsic::ppc_altivec_lvewx:
9791 case Intrinsic::ppc_vsx_lxvd2x:
9792 case Intrinsic::ppc_vsx_lxvw4x: {
9794 switch (Intrinsic) {
9795 case Intrinsic::ppc_altivec_lvebx:
9798 case Intrinsic::ppc_altivec_lvehx:
9801 case Intrinsic::ppc_altivec_lvewx:
9804 case Intrinsic::ppc_vsx_lxvd2x:
9812 Info.opc = ISD::INTRINSIC_W_CHAIN;
9814 Info.ptrVal = I.getArgOperand(0);
9815 Info.offset = -VT.getStoreSize()+1;
9816 Info.size = 2*VT.getStoreSize()-1;
9819 Info.readMem = true;
9820 Info.writeMem = false;
9823 case Intrinsic::ppc_altivec_stvx:
9824 case Intrinsic::ppc_altivec_stvxl:
9825 case Intrinsic::ppc_altivec_stvebx:
9826 case Intrinsic::ppc_altivec_stvehx:
9827 case Intrinsic::ppc_altivec_stvewx:
9828 case Intrinsic::ppc_vsx_stxvd2x:
9829 case Intrinsic::ppc_vsx_stxvw4x: {
9831 switch (Intrinsic) {
9832 case Intrinsic::ppc_altivec_stvebx:
9835 case Intrinsic::ppc_altivec_stvehx:
9838 case Intrinsic::ppc_altivec_stvewx:
9841 case Intrinsic::ppc_vsx_stxvd2x:
9849 Info.opc = ISD::INTRINSIC_VOID;
9851 Info.ptrVal = I.getArgOperand(1);
9852 Info.offset = -VT.getStoreSize()+1;
9853 Info.size = 2*VT.getStoreSize()-1;
9856 Info.readMem = false;
9857 Info.writeMem = true;
9867 /// getOptimalMemOpType - Returns the target specific optimal type for load
9868 /// and store operations as a result of memset, memcpy, and memmove
9869 /// lowering. If DstAlign is zero that means it's safe to destination
9870 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9871 /// means there isn't a need to check it against alignment requirement,
9872 /// probably because the source does not need to be loaded. If 'IsMemset' is
9873 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9874 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9875 /// source is constant so it does not need to be loaded.
9876 /// It returns EVT::Other if the type should be determined using generic
9877 /// target-independent logic.
9878 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9879 unsigned DstAlign, unsigned SrcAlign,
9880 bool IsMemset, bool ZeroMemset,
9882 MachineFunction &MF) const {
9883 if (Subtarget.isPPC64()) {
9890 /// \brief Returns true if it is beneficial to convert a load of a constant
9891 /// to just the constant itself.
9892 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9894 assert(Ty->isIntegerTy());
9896 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9897 if (BitSize == 0 || BitSize > 64)
9902 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9903 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9905 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9906 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9907 return NumBits1 == 64 && NumBits2 == 32;
9910 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9911 if (!VT1.isInteger() || !VT2.isInteger())
9913 unsigned NumBits1 = VT1.getSizeInBits();
9914 unsigned NumBits2 = VT2.getSizeInBits();
9915 return NumBits1 == 64 && NumBits2 == 32;
9918 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9919 // Generally speaking, zexts are not free, but they are free when they can be
9920 // folded with other operations.
9921 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9922 EVT MemVT = LD->getMemoryVT();
9923 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9924 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9925 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9926 LD->getExtensionType() == ISD::ZEXTLOAD))
9930 // FIXME: Add other cases...
9931 // - 32-bit shifts with a zext to i64
9932 // - zext after ctlz, bswap, etc.
9933 // - zext after and by a constant mask
9935 return TargetLowering::isZExtFree(Val, VT2);
9938 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9939 assert(VT.isFloatingPoint());
9943 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9944 return isInt<16>(Imm) || isUInt<16>(Imm);
9947 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9948 return isInt<16>(Imm) || isUInt<16>(Imm);
9951 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9955 if (DisablePPCUnaligned)
9958 // PowerPC supports unaligned memory access for simple non-vector types.
9959 // Although accessing unaligned addresses is not as efficient as accessing
9960 // aligned addresses, it is generally more efficient than manual expansion,
9961 // and generally only traps for software emulation when crossing page
9967 if (VT.getSimpleVT().isVector()) {
9968 if (Subtarget.hasVSX()) {
9969 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9970 VT != MVT::v4f32 && VT != MVT::v4i32)
9977 if (VT == MVT::ppcf128)
9986 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9987 VT = VT.getScalarType();
9992 switch (VT.getSimpleVT().SimpleTy) {
10004 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
10005 // LR is a callee-save register, but we must treat it as clobbered by any call
10006 // site. Hence we include LR in the scratch registers, which are in turn added
10007 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
10008 // to CTR, which is used by any indirect call.
10009 static const MCPhysReg ScratchRegs[] = {
10010 PPC::X12, PPC::LR8, PPC::CTR8, 0
10013 return ScratchRegs;
10017 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10018 EVT VT , unsigned DefinedValues) const {
10019 if (VT == MVT::v2i64)
10022 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10025 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10026 if (DisableILPPref || Subtarget.enableMachineScheduler())
10027 return TargetLowering::getSchedulingPreference(N);
10032 // Create a fast isel object.
10034 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10035 const TargetLibraryInfo *LibInfo) const {
10036 return PPC::createFastISel(FuncInfo, LibInfo);