1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
62 Subtarget(*TM.getSubtargetImpl()) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 if (Subtarget.useCRBits()) {
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
100 if (isPPC64 || Subtarget.hasFPCVT()) {
101 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
112 // PowerPC does not support direct load / store of condition registers
113 setOperationAction(ISD::LOAD, MVT::i1, Custom);
114 setOperationAction(ISD::STORE, MVT::i1, Custom);
116 // FIXME: Remove this once the ANDI glue bug is fixed:
118 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
120 for (MVT VT : MVT::integer_valuetypes()) {
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
123 setTruncStoreAction(VT, MVT::i1, Expand);
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
129 // This is used in the ppcf128->int sequence. Note it has different semantics
130 // from FP_ROUND: that rounds to nearest, this rounds to zero.
131 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
133 // We do not currently implement these libm ops for PowerPC.
134 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
141 // PowerPC has no SREM/UREM instructions
142 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::UREM, MVT::i32, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
148 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
157 // We don't support sin/cos/sqrt/fmod/pow
158 setOperationAction(ISD::FSIN , MVT::f64, Expand);
159 setOperationAction(ISD::FCOS , MVT::f64, Expand);
160 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
161 setOperationAction(ISD::FREM , MVT::f64, Expand);
162 setOperationAction(ISD::FPOW , MVT::f64, Expand);
163 setOperationAction(ISD::FMA , MVT::f64, Legal);
164 setOperationAction(ISD::FSIN , MVT::f32, Expand);
165 setOperationAction(ISD::FCOS , MVT::f32, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FREM , MVT::f32, Expand);
168 setOperationAction(ISD::FPOW , MVT::f32, Expand);
169 setOperationAction(ISD::FMA , MVT::f32, Legal);
171 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
173 // If we're enabling GP optimizations, use hardware square root
174 if (!Subtarget.hasFSQRT() &&
175 !(TM.Options.UnsafeFPMath &&
176 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
177 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath &&
181 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
182 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
184 if (Subtarget.hasFCPSGN()) {
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
192 if (Subtarget.hasFPRND()) {
193 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
194 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
195 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
196 setOperationAction(ISD::FROUND, MVT::f64, Legal);
198 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
201 setOperationAction(ISD::FROUND, MVT::f32, Legal);
204 // PowerPC does not have BSWAP, CTPOP or CTTZ
205 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
207 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
209 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
214 if (Subtarget.hasPOPCNTD()) {
215 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
218 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
222 // PowerPC does not have ROTR
223 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
224 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
226 if (!Subtarget.useCRBits()) {
227 // PowerPC does not have Select
228 setOperationAction(ISD::SELECT, MVT::i32, Expand);
229 setOperationAction(ISD::SELECT, MVT::i64, Expand);
230 setOperationAction(ISD::SELECT, MVT::f32, Expand);
231 setOperationAction(ISD::SELECT, MVT::f64, Expand);
234 // PowerPC wants to turn select_cc of FP into fsel when possible.
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
238 // PowerPC wants to optimize integer setcc a bit
239 if (!Subtarget.useCRBits())
240 setOperationAction(ISD::SETCC, MVT::i32, Custom);
242 // PowerPC does not have BRCOND which requires SetCC
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
246 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
248 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
251 // PowerPC does not have [U|S]INT_TO_FP
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
257 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
260 // We cannot sextinreg(i1). Expand to shifts.
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
263 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
264 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
265 // support continuation, user-level threading, and etc.. As a result, no
266 // other SjLj exception interfaces are implemented and please don't build
267 // your own exception handling based on them.
268 // LLVM/Clang supports zero-cost DWARF exception handling.
269 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
270 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
272 // We want to legalize GlobalAddress and ConstantPool nodes into the
273 // appropriate instructions to materialize the address.
274 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
277 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
278 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
286 setOperationAction(ISD::TRAP, MVT::Other, Legal);
288 // TRAMPOLINE is custom lowered.
289 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
290 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
292 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
293 setOperationAction(ISD::VASTART , MVT::Other, Custom);
295 if (Subtarget.isSVR4ABI()) {
297 // VAARG always uses double-word chunks, so promote anything smaller.
298 setOperationAction(ISD::VAARG, MVT::i1, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i8, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i16, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i32, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::Other, Expand);
308 // VAARG is custom lowered with the 32-bit SVR4 ABI.
309 setOperationAction(ISD::VAARG, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::i64, Custom);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
315 if (Subtarget.isSVR4ABI() && !isPPC64)
316 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
319 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
321 // Use the default implementation.
322 setOperationAction(ISD::VAEND , MVT::Other, Expand);
323 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
324 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
326 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
328 // We want to custom lower some of our intrinsics.
329 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
331 // To handle counter-based loop conditions.
332 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
334 // Comparisons that require checking two conditions.
335 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
348 if (Subtarget.has64BitSupport()) {
349 // They also have instructions for converting between i64 and fp.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
354 // This is just the low 32 bits of a (signed) fp->i64 conversion.
355 // We cannot do this with Promote because i64 is not a legal type.
356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
361 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
362 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
365 // With the instructions enabled under FPCVT, we can do everything.
366 if (Subtarget.hasFPCVT()) {
367 if (Subtarget.has64BitSupport()) {
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
369 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
380 if (Subtarget.use64BitRegs()) {
381 // 64-bit PowerPC implementations can support i64 types directly
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
383 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
384 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
385 // 64-bit PowerPC wants to expand i128 shifts itself.
386 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
388 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
390 // 32-bit PowerPC wants to expand i64 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
396 if (Subtarget.hasAltivec()) {
397 // First set operation action for all vector types to expand. Then we
398 // will selectively turn on ones that can be effectively codegen'd.
399 for (MVT VT : MVT::vector_valuetypes()) {
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (MVT InnerVT : MVT::vector_valuetypes()) {
467 setTruncStoreAction(VT, InnerVT, Expand);
468 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
470 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
474 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
475 // with merges, splats, etc.
476 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
478 setOperationAction(ISD::AND , MVT::v4i32, Legal);
479 setOperationAction(ISD::OR , MVT::v4i32, Legal);
480 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
481 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
482 setOperationAction(ISD::SELECT, MVT::v4i32,
483 Subtarget.useCRBits() ? Legal : Expand);
484 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
487 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
489 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
490 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
491 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
499 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
502 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
503 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
504 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
507 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
508 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
509 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
512 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
519 // Altivec does not contain unordered floating-point compare instructions
520 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
525 if (Subtarget.hasVSX()) {
526 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
529 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
537 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
538 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
540 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
541 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
549 // Share the Altivec comparison restrictions.
550 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
555 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
556 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
558 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
562 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
563 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
565 // VSX v2i64 only supports non-arithmetic operations.
566 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
567 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
569 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
571 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
575 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
582 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
585 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
587 // Vector operation legalization checks the result type of
588 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
594 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
598 if (Subtarget.has64BitSupport())
599 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
604 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
608 setBooleanContents(ZeroOrOneBooleanContent);
609 // Altivec instructions set fields to all zeros or all ones.
610 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
613 // These libcalls are not available in 32-bit.
614 setLibcallName(RTLIB::SHL_I128, nullptr);
615 setLibcallName(RTLIB::SRL_I128, nullptr);
616 setLibcallName(RTLIB::SRA_I128, nullptr);
620 setStackPointerRegisterToSaveRestore(PPC::X1);
621 setExceptionPointerRegister(PPC::X3);
622 setExceptionSelectorRegister(PPC::X4);
624 setStackPointerRegisterToSaveRestore(PPC::R1);
625 setExceptionPointerRegister(PPC::R3);
626 setExceptionSelectorRegister(PPC::R4);
629 // We have target-specific dag combine patterns for the following nodes:
630 setTargetDAGCombine(ISD::SINT_TO_FP);
631 if (Subtarget.hasFPCVT())
632 setTargetDAGCombine(ISD::UINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 switch (Subtarget.getDarwinDirective()) {
686 case PPC::DIR_E500mc:
695 setPrefFunctionAlignment(4);
696 setPrefLoopAlignment(4);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores do better with aggressive inlining of memcpy and
710 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
722 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
723 /// the desired ByVal argument alignment.
724 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
725 unsigned MaxMaxAlign) {
726 if (MaxAlign == MaxMaxAlign)
728 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
729 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
731 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
733 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
739 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
742 if (EltAlign > MaxAlign)
744 if (MaxAlign == MaxMaxAlign)
750 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
751 /// function arguments in the caller parameter area.
752 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
753 // Darwin passes everything on 4 byte boundary.
754 if (Subtarget.isDarwin())
757 // 16byte and wider vectors are passed on 16byte boundary.
758 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
759 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
760 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
761 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
765 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
767 default: return nullptr;
768 case PPCISD::FSEL: return "PPCISD::FSEL";
769 case PPCISD::FCFID: return "PPCISD::FCFID";
770 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
771 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
772 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
776 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
777 case PPCISD::FRE: return "PPCISD::FRE";
778 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
779 case PPCISD::STFIWX: return "PPCISD::STFIWX";
780 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
781 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
782 case PPCISD::VPERM: return "PPCISD::VPERM";
783 case PPCISD::CMPB: return "PPCISD::CMPB";
784 case PPCISD::Hi: return "PPCISD::Hi";
785 case PPCISD::Lo: return "PPCISD::Lo";
786 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
795 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
796 case PPCISD::MTCTR: return "PPCISD::MTCTR";
797 case PPCISD::BCTRL: return "PPCISD::BCTRL";
798 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
799 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
800 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
801 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
802 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
803 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
804 case PPCISD::VCMP: return "PPCISD::VCMP";
805 case PPCISD::VCMPo: return "PPCISD::VCMPo";
806 case PPCISD::LBRX: return "PPCISD::LBRX";
807 case PPCISD::STBRX: return "PPCISD::STBRX";
808 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
809 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
810 case PPCISD::LARX: return "PPCISD::LARX";
811 case PPCISD::STCX: return "PPCISD::STCX";
812 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
813 case PPCISD::BDNZ: return "PPCISD::BDNZ";
814 case PPCISD::BDZ: return "PPCISD::BDZ";
815 case PPCISD::MFFS: return "PPCISD::MFFS";
816 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
817 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
818 case PPCISD::CR6SET: return "PPCISD::CR6SET";
819 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
820 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
821 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
822 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
823 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
824 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
825 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
826 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
827 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
828 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
829 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
830 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
831 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
832 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
833 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
834 case PPCISD::SC: return "PPCISD::SC";
838 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
841 return VT.changeVectorElementTypeToInteger();
844 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
845 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
849 //===----------------------------------------------------------------------===//
850 // Node matching predicates, for use by the tblgen matching code.
851 //===----------------------------------------------------------------------===//
853 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
854 static bool isFloatingPointZero(SDValue Op) {
855 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
856 return CFP->getValueAPF().isZero();
857 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
858 // Maybe this has already been legalized into the constant pool?
859 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
860 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
861 return CFP->getValueAPF().isZero();
866 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
867 /// true if Op is undef or if it matches the specified value.
868 static bool isConstantOrUndef(int Op, int Val) {
869 return Op < 0 || Op == Val;
872 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUHUM instruction.
874 /// The ShuffleKind distinguishes between big-endian operations with
875 /// two different inputs (0), either-endian operations with two identical
876 /// inputs (1), and little-endian operantion with two different inputs (2).
877 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
878 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
880 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
881 if (ShuffleKind == 0) {
884 for (unsigned i = 0; i != 16; ++i)
885 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
887 } else if (ShuffleKind == 2) {
890 for (unsigned i = 0; i != 16; ++i)
891 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
893 } else if (ShuffleKind == 1) {
894 unsigned j = IsLE ? 0 : 1;
895 for (unsigned i = 0; i != 8; ++i)
896 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
903 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
904 /// VPKUWUM instruction.
905 /// The ShuffleKind distinguishes between big-endian operations with
906 /// two different inputs (0), either-endian operations with two identical
907 /// inputs (1), and little-endian operantion with two different inputs (2).
908 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
909 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
911 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
912 if (ShuffleKind == 0) {
915 for (unsigned i = 0; i != 16; i += 2)
916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
919 } else if (ShuffleKind == 2) {
922 for (unsigned i = 0; i != 16; i += 2)
923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
926 } else if (ShuffleKind == 1) {
927 unsigned j = IsLE ? 0 : 2;
928 for (unsigned i = 0; i != 8; i += 2)
929 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
931 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
932 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
938 /// isVMerge - Common function, used to match vmrg* shuffles.
940 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned LHSStart, unsigned RHSStart) {
942 if (N->getValueType(0) != MVT::v16i8)
944 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
945 "Unsupported merge size!");
947 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
948 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
949 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
950 LHSStart+j+i*UnitSize) ||
951 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
952 RHSStart+j+i*UnitSize))
958 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
959 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
960 /// The ShuffleKind distinguishes between big-endian merges with two
961 /// different inputs (0), either-endian merges with two identical inputs (1),
962 /// and little-endian merges with two different inputs (2). For the latter,
963 /// the input operands are swapped (see PPCInstrAltivec.td).
964 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
965 unsigned ShuffleKind, SelectionDAG &DAG) {
966 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
967 if (ShuffleKind == 1) // unary
968 return isVMerge(N, UnitSize, 0, 0);
969 else if (ShuffleKind == 2) // swapped
970 return isVMerge(N, UnitSize, 0, 16);
974 if (ShuffleKind == 1) // unary
975 return isVMerge(N, UnitSize, 8, 8);
976 else if (ShuffleKind == 0) // normal
977 return isVMerge(N, UnitSize, 8, 24);
983 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
984 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
985 /// The ShuffleKind distinguishes between big-endian merges with two
986 /// different inputs (0), either-endian merges with two identical inputs (1),
987 /// and little-endian merges with two different inputs (2). For the latter,
988 /// the input operands are swapped (see PPCInstrAltivec.td).
989 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
990 unsigned ShuffleKind, SelectionDAG &DAG) {
991 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
992 if (ShuffleKind == 1) // unary
993 return isVMerge(N, UnitSize, 8, 8);
994 else if (ShuffleKind == 2) // swapped
995 return isVMerge(N, UnitSize, 8, 24);
999 if (ShuffleKind == 1) // unary
1000 return isVMerge(N, UnitSize, 0, 0);
1001 else if (ShuffleKind == 0) // normal
1002 return isVMerge(N, UnitSize, 0, 16);
1009 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1010 /// amount, otherwise return -1.
1011 /// The ShuffleKind distinguishes between big-endian operations with two
1012 /// different inputs (0), either-endian operations with two identical inputs
1013 /// (1), and little-endian operations with two different inputs (2). For the
1014 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1015 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1016 SelectionDAG &DAG) {
1017 if (N->getValueType(0) != MVT::v16i8)
1020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1022 // Find the first non-undef value in the shuffle mask.
1024 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1027 if (i == 16) return -1; // all undef.
1029 // Otherwise, check to see if the rest of the elements are consecutively
1030 // numbered from this value.
1031 unsigned ShiftAmt = SVOp->getMaskElt(i);
1032 if (ShiftAmt < i) return -1;
1035 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1038 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1039 // Check the rest of the elements to see if they are consecutive.
1040 for (++i; i != 16; ++i)
1041 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1043 } else if (ShuffleKind == 1) {
1044 // Check the rest of the elements to see if they are consecutive.
1045 for (++i; i != 16; ++i)
1046 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1051 if (ShuffleKind == 2 && isLE)
1052 ShiftAmt = 16 - ShiftAmt;
1057 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1058 /// specifies a splat of a single element that is suitable for input to
1059 /// VSPLTB/VSPLTH/VSPLTW.
1060 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1061 assert(N->getValueType(0) == MVT::v16i8 &&
1062 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1064 // This is a splat operation if each element of the permute is the same, and
1065 // if the value doesn't reference the second vector.
1066 unsigned ElementBase = N->getMaskElt(0);
1068 // FIXME: Handle UNDEF elements too!
1069 if (ElementBase >= 16)
1072 // Check that the indices are consecutive, in the case of a multi-byte element
1073 // splatted with a v16i8 mask.
1074 for (unsigned i = 1; i != EltSize; ++i)
1075 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1078 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1079 if (N->getMaskElt(i) < 0) continue;
1080 for (unsigned j = 0; j != EltSize; ++j)
1081 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1087 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1089 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1090 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1092 APInt APVal, APUndef;
1096 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1098 return CFP->getValueAPF().isNegZero();
1103 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1104 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1105 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1106 SelectionDAG &DAG) {
1107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1108 assert(isSplatShuffleMask(SVOp, EltSize));
1109 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1110 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1112 return SVOp->getMaskElt(0) / EltSize;
1115 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1116 /// by using a vspltis[bhw] instruction of the specified element size, return
1117 /// the constant being splatted. The ByteSize field indicates the number of
1118 /// bytes of each element [124] -> [bhw].
1119 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1120 SDValue OpVal(nullptr, 0);
1122 // If ByteSize of the splat is bigger than the element size of the
1123 // build_vector, then we have a case where we are checking for a splat where
1124 // multiple elements of the buildvector are folded together into a single
1125 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1126 unsigned EltSize = 16/N->getNumOperands();
1127 if (EltSize < ByteSize) {
1128 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1129 SDValue UniquedVals[4];
1130 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1132 // See if all of the elements in the buildvector agree across.
1133 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1134 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1135 // If the element isn't a constant, bail fully out.
1136 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1139 if (!UniquedVals[i&(Multiple-1)].getNode())
1140 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1141 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1142 return SDValue(); // no match.
1145 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1146 // either constant or undef values that are identical for each chunk. See
1147 // if these chunks can form into a larger vspltis*.
1149 // Check to see if all of the leading entries are either 0 or -1. If
1150 // neither, then this won't fit into the immediate field.
1151 bool LeadingZero = true;
1152 bool LeadingOnes = true;
1153 for (unsigned i = 0; i != Multiple-1; ++i) {
1154 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1156 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1157 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1159 // Finally, check the least significant entry.
1161 if (!UniquedVals[Multiple-1].getNode())
1162 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1163 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1165 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1168 if (!UniquedVals[Multiple-1].getNode())
1169 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1170 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1171 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1172 return DAG.getTargetConstant(Val, MVT::i32);
1178 // Check to see if this buildvec has a single non-undef value in its elements.
1179 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1180 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1181 if (!OpVal.getNode())
1182 OpVal = N->getOperand(i);
1183 else if (OpVal != N->getOperand(i))
1187 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1189 unsigned ValSizeInBytes = EltSize;
1191 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1192 Value = CN->getZExtValue();
1193 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1194 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1195 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1198 // If the splat value is larger than the element value, then we can never do
1199 // this splat. The only case that we could fit the replicated bits into our
1200 // immediate field for would be zero, and we prefer to use vxor for it.
1201 if (ValSizeInBytes < ByteSize) return SDValue();
1203 // If the element value is larger than the splat value, cut it in half and
1204 // check to see if the two halves are equal. Continue doing this until we
1205 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1206 while (ValSizeInBytes > ByteSize) {
1207 ValSizeInBytes >>= 1;
1209 // If the top half equals the bottom half, we're still ok.
1210 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1211 (Value & ((1 << (8*ValSizeInBytes))-1)))
1215 // Properly sign extend the value.
1216 int MaskVal = SignExtend32(Value, ByteSize * 8);
1218 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1219 if (MaskVal == 0) return SDValue();
1221 // Finally, if this value fits in a 5 bit sext field, return it
1222 if (SignExtend32<5>(MaskVal) == MaskVal)
1223 return DAG.getTargetConstant(MaskVal, MVT::i32);
1227 //===----------------------------------------------------------------------===//
1228 // Addressing Mode Selection
1229 //===----------------------------------------------------------------------===//
1231 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1232 /// or 64-bit immediate, and if the value can be accurately represented as a
1233 /// sign extension from a 16-bit value. If so, this returns true and the
1235 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1236 if (!isa<ConstantSDNode>(N))
1239 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1240 if (N->getValueType(0) == MVT::i32)
1241 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1243 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1245 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1246 return isIntS16Immediate(Op.getNode(), Imm);
1250 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1251 /// can be represented as an indexed [r+r] operation. Returns false if it
1252 /// can be more efficiently represented with [r+imm].
1253 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1255 SelectionDAG &DAG) const {
1257 if (N.getOpcode() == ISD::ADD) {
1258 if (isIntS16Immediate(N.getOperand(1), imm))
1259 return false; // r+i
1260 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1261 return false; // r+i
1263 Base = N.getOperand(0);
1264 Index = N.getOperand(1);
1266 } else if (N.getOpcode() == ISD::OR) {
1267 if (isIntS16Immediate(N.getOperand(1), imm))
1268 return false; // r+i can fold it if we can.
1270 // If this is an or of disjoint bitfields, we can codegen this as an add
1271 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1273 APInt LHSKnownZero, LHSKnownOne;
1274 APInt RHSKnownZero, RHSKnownOne;
1275 DAG.computeKnownBits(N.getOperand(0),
1276 LHSKnownZero, LHSKnownOne);
1278 if (LHSKnownZero.getBoolValue()) {
1279 DAG.computeKnownBits(N.getOperand(1),
1280 RHSKnownZero, RHSKnownOne);
1281 // If all of the bits are known zero on the LHS or RHS, the add won't
1283 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1284 Base = N.getOperand(0);
1285 Index = N.getOperand(1);
1294 // If we happen to be doing an i64 load or store into a stack slot that has
1295 // less than a 4-byte alignment, then the frame-index elimination may need to
1296 // use an indexed load or store instruction (because the offset may not be a
1297 // multiple of 4). The extra register needed to hold the offset comes from the
1298 // register scavenger, and it is possible that the scavenger will need to use
1299 // an emergency spill slot. As a result, we need to make sure that a spill slot
1300 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1302 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1303 // FIXME: This does not handle the LWA case.
1307 // NOTE: We'll exclude negative FIs here, which come from argument
1308 // lowering, because there are no known test cases triggering this problem
1309 // using packed structures (or similar). We can remove this exclusion if
1310 // we find such a test case. The reason why this is so test-case driven is
1311 // because this entire 'fixup' is only to prevent crashes (from the
1312 // register scavenger) on not-really-valid inputs. For example, if we have:
1314 // %b = bitcast i1* %a to i64*
1315 // store i64* a, i64 b
1316 // then the store should really be marked as 'align 1', but is not. If it
1317 // were marked as 'align 1' then the indexed form would have been
1318 // instruction-selected initially, and the problem this 'fixup' is preventing
1319 // won't happen regardless.
1323 MachineFunction &MF = DAG.getMachineFunction();
1324 MachineFrameInfo *MFI = MF.getFrameInfo();
1326 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1330 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1331 FuncInfo->setHasNonRISpills();
1334 /// Returns true if the address N can be represented by a base register plus
1335 /// a signed 16-bit displacement [r+imm], and if it is not better
1336 /// represented as reg+reg. If Aligned is true, only accept displacements
1337 /// suitable for STD and friends, i.e. multiples of 4.
1338 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1341 bool Aligned) const {
1342 // FIXME dl should come from parent load or store, not from address
1344 // If this can be more profitably realized as r+r, fail.
1345 if (SelectAddressRegReg(N, Disp, Base, DAG))
1348 if (N.getOpcode() == ISD::ADD) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 Disp = DAG.getTargetConstant(imm, N.getValueType());
1353 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1354 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1355 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1357 Base = N.getOperand(0);
1359 return true; // [r+i]
1360 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1361 // Match LOAD (ADD (X, Lo(G))).
1362 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1363 && "Cannot handle constant offsets yet!");
1364 Disp = N.getOperand(1).getOperand(0); // The global address.
1365 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1366 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1367 Disp.getOpcode() == ISD::TargetConstantPool ||
1368 Disp.getOpcode() == ISD::TargetJumpTable);
1369 Base = N.getOperand(0);
1370 return true; // [&g+r]
1372 } else if (N.getOpcode() == ISD::OR) {
1374 if (isIntS16Immediate(N.getOperand(1), imm) &&
1375 (!Aligned || (imm & 3) == 0)) {
1376 // If this is an or of disjoint bitfields, we can codegen this as an add
1377 // (for better address arithmetic) if the LHS and RHS of the OR are
1378 // provably disjoint.
1379 APInt LHSKnownZero, LHSKnownOne;
1380 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1382 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1383 // If all of the bits are known zero on the LHS or RHS, the add won't
1385 if (FrameIndexSDNode *FI =
1386 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1387 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1388 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1390 Base = N.getOperand(0);
1392 Disp = DAG.getTargetConstant(imm, N.getValueType());
1396 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1397 // Loading from a constant address.
1399 // If this address fits entirely in a 16-bit sext immediate field, codegen
1402 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1403 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1404 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1405 CN->getValueType(0));
1409 // Handle 32-bit sext immediates with LIS + addr mode.
1410 if ((CN->getValueType(0) == MVT::i32 ||
1411 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1412 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1413 int Addr = (int)CN->getZExtValue();
1415 // Otherwise, break this down into an LIS + disp.
1416 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1418 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1419 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1420 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1425 Disp = DAG.getTargetConstant(0, getPointerTy());
1426 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1427 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1428 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1431 return true; // [r+0]
1434 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1435 /// represented as an indexed [r+r] operation.
1436 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1438 SelectionDAG &DAG) const {
1439 // Check to see if we can easily represent this as an [r+r] address. This
1440 // will fail if it thinks that the address is more profitably represented as
1441 // reg+imm, e.g. where imm = 0.
1442 if (SelectAddressRegReg(N, Base, Index, DAG))
1445 // If the operand is an addition, always emit this as [r+r], since this is
1446 // better (for code size, and execution, as the memop does the add for free)
1447 // than emitting an explicit add.
1448 if (N.getOpcode() == ISD::ADD) {
1449 Base = N.getOperand(0);
1450 Index = N.getOperand(1);
1454 // Otherwise, do it the hard way, using R0 as the base register.
1455 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1461 /// getPreIndexedAddressParts - returns true by value, base pointer and
1462 /// offset pointer and addressing mode by reference if the node's address
1463 /// can be legally represented as pre-indexed load / store address.
1464 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1466 ISD::MemIndexedMode &AM,
1467 SelectionDAG &DAG) const {
1468 if (DisablePPCPreinc) return false;
1474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1475 Ptr = LD->getBasePtr();
1476 VT = LD->getMemoryVT();
1477 Alignment = LD->getAlignment();
1478 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1479 Ptr = ST->getBasePtr();
1480 VT = ST->getMemoryVT();
1481 Alignment = ST->getAlignment();
1486 // PowerPC doesn't have preinc load/store instructions for vectors.
1490 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1492 // Common code will reject creating a pre-inc form if the base pointer
1493 // is a frame index, or if N is a store and the base pointer is either
1494 // the same as or a predecessor of the value being stored. Check for
1495 // those situations here, and try with swapped Base/Offset instead.
1498 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1501 SDValue Val = cast<StoreSDNode>(N)->getValue();
1502 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1507 std::swap(Base, Offset);
1513 // LDU/STU can only handle immediates that are a multiple of 4.
1514 if (VT != MVT::i64) {
1515 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1518 // LDU/STU need an address with at least 4-byte alignment.
1522 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1526 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1527 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1528 // sext i32 to i64 when addr mode is r+i.
1529 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1530 LD->getExtensionType() == ISD::SEXTLOAD &&
1531 isa<ConstantSDNode>(Offset))
1539 //===----------------------------------------------------------------------===//
1540 // LowerOperation implementation
1541 //===----------------------------------------------------------------------===//
1543 /// GetLabelAccessInfo - Return true if we should reference labels using a
1544 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1545 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1546 unsigned &LoOpFlags,
1547 const GlobalValue *GV = nullptr) {
1548 HiOpFlags = PPCII::MO_HA;
1549 LoOpFlags = PPCII::MO_LO;
1551 // Don't use the pic base if not in PIC relocation model.
1552 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1555 HiOpFlags |= PPCII::MO_PIC_FLAG;
1556 LoOpFlags |= PPCII::MO_PIC_FLAG;
1559 // If this is a reference to a global value that requires a non-lazy-ptr, make
1560 // sure that instruction lowering adds it.
1561 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1562 HiOpFlags |= PPCII::MO_NLP_FLAG;
1563 LoOpFlags |= PPCII::MO_NLP_FLAG;
1565 if (GV->hasHiddenVisibility()) {
1566 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1567 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1574 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1575 SelectionDAG &DAG) {
1576 EVT PtrVT = HiPart.getValueType();
1577 SDValue Zero = DAG.getConstant(0, PtrVT);
1580 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1581 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1583 // With PIC, the first instruction is actually "GR+hi(&G)".
1585 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1586 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1588 // Generate non-pic code that has direct accesses to the constant pool.
1589 // The address of the global is just (hi(&g)+lo(&g)).
1590 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1593 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1594 SelectionDAG &DAG) const {
1595 EVT PtrVT = Op.getValueType();
1596 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1597 const Constant *C = CP->getConstVal();
1599 // 64-bit SVR4 ABI code is always position-independent.
1600 // The actual address of the GlobalValue is stored in the TOC.
1601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1602 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1603 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1604 DAG.getRegister(PPC::X2, MVT::i64));
1607 unsigned MOHiFlag, MOLoFlag;
1608 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 if (isPIC && Subtarget.isSVR4ABI()) {
1611 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1612 PPCII::MO_PIC_FLAG);
1614 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1615 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1619 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1621 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1622 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1625 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1626 EVT PtrVT = Op.getValueType();
1627 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1629 // 64-bit SVR4 ABI code is always position-independent.
1630 // The actual address of the GlobalValue is stored in the TOC.
1631 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1632 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1633 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1634 DAG.getRegister(PPC::X2, MVT::i64));
1637 unsigned MOHiFlag, MOLoFlag;
1638 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1640 if (isPIC && Subtarget.isSVR4ABI()) {
1641 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1642 PPCII::MO_PIC_FLAG);
1644 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1645 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1648 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1649 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1650 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1653 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1654 SelectionDAG &DAG) const {
1655 EVT PtrVT = Op.getValueType();
1656 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1657 const BlockAddress *BA = BASDN->getBlockAddress();
1659 // 64-bit SVR4 ABI code is always position-independent.
1660 // The actual BlockAddress is stored in the TOC.
1661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1662 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1663 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1664 DAG.getRegister(PPC::X2, MVT::i64));
1667 unsigned MOHiFlag, MOLoFlag;
1668 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1669 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1670 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1671 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1674 // Generate a call to __tls_get_addr for the given GOT entry Op.
1675 std::pair<SDValue,SDValue>
1676 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1677 SelectionDAG &DAG) const {
1679 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1680 TargetLowering::ArgListTy Args;
1681 TargetLowering::ArgListEntry Entry;
1683 Entry.Ty = IntPtrTy;
1684 Args.push_back(Entry);
1686 TargetLowering::CallLoweringInfo CLI(DAG);
1687 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1688 .setCallee(CallingConv::C, IntPtrTy,
1689 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1690 std::move(Args), 0);
1692 return LowerCallTo(CLI);
1695 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1696 SelectionDAG &DAG) const {
1698 // FIXME: TLS addresses currently use medium model code sequences,
1699 // which is the most useful form. Eventually support for small and
1700 // large models could be added if users need it, at the cost of
1701 // additional complexity.
1702 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1704 const GlobalValue *GV = GA->getGlobal();
1705 EVT PtrVT = getPointerTy();
1706 bool is64bit = Subtarget.isPPC64();
1707 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1708 PICLevel::Level picLevel = M->getPICLevel();
1710 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1712 if (Model == TLSModel::LocalExec) {
1713 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1714 PPCII::MO_TPREL_HA);
1715 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1716 PPCII::MO_TPREL_LO);
1717 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1718 is64bit ? MVT::i64 : MVT::i32);
1719 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1720 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1723 if (Model == TLSModel::InitialExec) {
1724 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1725 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1730 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1731 PtrVT, GOTReg, TGA);
1733 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1734 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1735 PtrVT, TGA, GOTPtr);
1736 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1739 if (Model == TLSModel::GeneralDynamic) {
1740 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1744 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1745 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1748 if (picLevel == PICLevel::Small)
1749 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1751 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1753 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1755 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1756 return CallResult.first;
1759 if (Model == TLSModel::LocalDynamic) {
1760 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1764 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1765 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1768 if (picLevel == PICLevel::Small)
1769 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1771 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1773 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1775 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1776 SDValue TLSAddr = CallResult.first;
1777 SDValue Chain = CallResult.second;
1778 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1779 Chain, TLSAddr, TGA);
1780 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1783 llvm_unreachable("Unknown TLS model!");
1786 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1787 SelectionDAG &DAG) const {
1788 EVT PtrVT = Op.getValueType();
1789 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1791 const GlobalValue *GV = GSDN->getGlobal();
1793 // 64-bit SVR4 ABI code is always position-independent.
1794 // The actual address of the GlobalValue is stored in the TOC.
1795 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1796 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1797 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1798 DAG.getRegister(PPC::X2, MVT::i64));
1801 unsigned MOHiFlag, MOLoFlag;
1802 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1804 if (isPIC && Subtarget.isSVR4ABI()) {
1805 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1807 PPCII::MO_PIC_FLAG);
1808 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1809 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1813 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1815 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1817 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1819 // If the global reference is actually to a non-lazy-pointer, we have to do an
1820 // extra load to get the address of the global.
1821 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1822 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1823 false, false, false, 0);
1827 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1828 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1831 if (Op.getValueType() == MVT::v2i64) {
1832 // When the operands themselves are v2i64 values, we need to do something
1833 // special because VSX has no underlying comparison operations for these.
1834 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1835 // Equality can be handled by casting to the legal type for Altivec
1836 // comparisons, everything else needs to be expanded.
1837 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1838 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1839 DAG.getSetCC(dl, MVT::v4i32,
1840 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1841 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1848 // We handle most of these in the usual way.
1852 // If we're comparing for equality to zero, expose the fact that this is
1853 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1854 // fold the new nodes.
1855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1856 if (C->isNullValue() && CC == ISD::SETEQ) {
1857 EVT VT = Op.getOperand(0).getValueType();
1858 SDValue Zext = Op.getOperand(0);
1859 if (VT.bitsLT(MVT::i32)) {
1861 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1863 unsigned Log2b = Log2_32(VT.getSizeInBits());
1864 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1865 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1866 DAG.getConstant(Log2b, MVT::i32));
1867 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1869 // Leave comparisons against 0 and -1 alone for now, since they're usually
1870 // optimized. FIXME: revisit this when we can custom lower all setcc
1872 if (C->isAllOnesValue() || C->isNullValue())
1876 // If we have an integer seteq/setne, turn it into a compare against zero
1877 // by xor'ing the rhs with the lhs, which is faster than setting a
1878 // condition register, reading it back out, and masking the correct bit. The
1879 // normal approach here uses sub to do this instead of xor. Using xor exposes
1880 // the result to other bit-twiddling opportunities.
1881 EVT LHSVT = Op.getOperand(0).getValueType();
1882 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1883 EVT VT = Op.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1886 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1891 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1892 const PPCSubtarget &Subtarget) const {
1893 SDNode *Node = Op.getNode();
1894 EVT VT = Node->getValueType(0);
1895 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1896 SDValue InChain = Node->getOperand(0);
1897 SDValue VAListPtr = Node->getOperand(1);
1898 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1901 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1904 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1905 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1906 false, false, false, 0);
1907 InChain = GprIndex.getValue(1);
1909 if (VT == MVT::i64) {
1910 // Check if GprIndex is even
1911 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1912 DAG.getConstant(1, MVT::i32));
1913 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1914 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1915 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1916 DAG.getConstant(1, MVT::i32));
1917 // Align GprIndex to be even if it isn't
1918 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1922 // fpr index is 1 byte after gpr
1923 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1924 DAG.getConstant(1, MVT::i32));
1927 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1928 FprPtr, MachinePointerInfo(SV), MVT::i8,
1929 false, false, false, 0);
1930 InChain = FprIndex.getValue(1);
1932 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1933 DAG.getConstant(8, MVT::i32));
1935 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1936 DAG.getConstant(4, MVT::i32));
1939 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1940 MachinePointerInfo(), false, false,
1942 InChain = OverflowArea.getValue(1);
1944 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1945 MachinePointerInfo(), false, false,
1947 InChain = RegSaveArea.getValue(1);
1949 // select overflow_area if index > 8
1950 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1951 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1953 // adjustment constant gpr_index * 4/8
1954 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1955 VT.isInteger() ? GprIndex : FprIndex,
1956 DAG.getConstant(VT.isInteger() ? 4 : 8,
1959 // OurReg = RegSaveArea + RegConstant
1960 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1963 // Floating types are 32 bytes into RegSaveArea
1964 if (VT.isFloatingPoint())
1965 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1966 DAG.getConstant(32, MVT::i32));
1968 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1969 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1970 VT.isInteger() ? GprIndex : FprIndex,
1971 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1974 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1975 VT.isInteger() ? VAListPtr : FprPtr,
1976 MachinePointerInfo(SV),
1977 MVT::i8, false, false, 0);
1979 // determine if we should load from reg_save_area or overflow_area
1980 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1982 // increase overflow_area by 4/8 if gpr/fpr > 8
1983 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1984 DAG.getConstant(VT.isInteger() ? 4 : 8,
1987 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1990 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1992 MachinePointerInfo(),
1993 MVT::i32, false, false, 0);
1995 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1996 false, false, false, 0);
1999 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2000 const PPCSubtarget &Subtarget) const {
2001 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2003 // We have to copy the entire va_list struct:
2004 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2005 return DAG.getMemcpy(Op.getOperand(0), Op,
2006 Op.getOperand(1), Op.getOperand(2),
2007 DAG.getConstant(12, MVT::i32), 8, false, true,
2008 MachinePointerInfo(), MachinePointerInfo());
2011 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2012 SelectionDAG &DAG) const {
2013 return Op.getOperand(0);
2016 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2017 SelectionDAG &DAG) const {
2018 SDValue Chain = Op.getOperand(0);
2019 SDValue Trmp = Op.getOperand(1); // trampoline
2020 SDValue FPtr = Op.getOperand(2); // nested function
2021 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2025 bool isPPC64 = (PtrVT == MVT::i64);
2027 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2030 TargetLowering::ArgListTy Args;
2031 TargetLowering::ArgListEntry Entry;
2033 Entry.Ty = IntPtrTy;
2034 Entry.Node = Trmp; Args.push_back(Entry);
2036 // TrampSize == (isPPC64 ? 48 : 40);
2037 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2038 isPPC64 ? MVT::i64 : MVT::i32);
2039 Args.push_back(Entry);
2041 Entry.Node = FPtr; Args.push_back(Entry);
2042 Entry.Node = Nest; Args.push_back(Entry);
2044 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2045 TargetLowering::CallLoweringInfo CLI(DAG);
2046 CLI.setDebugLoc(dl).setChain(Chain)
2047 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2048 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2049 std::move(Args), 0);
2051 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2052 return CallResult.second;
2055 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2056 const PPCSubtarget &Subtarget) const {
2057 MachineFunction &MF = DAG.getMachineFunction();
2058 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2062 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2063 // vastart just stores the address of the VarArgsFrameIndex slot into the
2064 // memory location argument.
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2066 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2068 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2069 MachinePointerInfo(SV),
2073 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2074 // We suppose the given va_list is already allocated.
2077 // char gpr; /* index into the array of 8 GPRs
2078 // * stored in the register save area
2079 // * gpr=0 corresponds to r3,
2080 // * gpr=1 to r4, etc.
2082 // char fpr; /* index into the array of 8 FPRs
2083 // * stored in the register save area
2084 // * fpr=0 corresponds to f1,
2085 // * fpr=1 to f2, etc.
2087 // char *overflow_arg_area;
2088 // /* location on stack that holds
2089 // * the next overflow argument
2091 // char *reg_save_area;
2092 // /* where r3:r10 and f1:f8 (if saved)
2098 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2099 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2102 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2104 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2106 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2109 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2110 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2112 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2113 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2115 uint64_t FPROffset = 1;
2116 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2118 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2120 // Store first byte : number of int regs
2121 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2123 MachinePointerInfo(SV),
2124 MVT::i8, false, false, 0);
2125 uint64_t nextOffset = FPROffset;
2126 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2129 // Store second byte : number of float regs
2130 SDValue secondStore =
2131 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2132 MachinePointerInfo(SV, nextOffset), MVT::i8,
2134 nextOffset += StackOffset;
2135 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2137 // Store second word : arguments given on stack
2138 SDValue thirdStore =
2139 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2140 MachinePointerInfo(SV, nextOffset),
2142 nextOffset += FrameOffset;
2143 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2145 // Store third word : arguments given in registers
2146 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2147 MachinePointerInfo(SV, nextOffset),
2152 #include "PPCGenCallingConv.inc"
2154 // Function whose sole purpose is to kill compiler warnings
2155 // stemming from unused functions included from PPCGenCallingConv.inc.
2156 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2157 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2160 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2161 CCValAssign::LocInfo &LocInfo,
2162 ISD::ArgFlagsTy &ArgFlags,
2167 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2169 CCValAssign::LocInfo &LocInfo,
2170 ISD::ArgFlagsTy &ArgFlags,
2172 static const MCPhysReg ArgRegs[] = {
2173 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2174 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2176 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2178 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2180 // Skip one register if the first unallocated register has an even register
2181 // number and there are still argument registers available which have not been
2182 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2183 // need to skip a register if RegNum is odd.
2184 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2185 State.AllocateReg(ArgRegs[RegNum]);
2188 // Always return false here, as this function only makes sure that the first
2189 // unallocated register has an odd register number and does not actually
2190 // allocate a register for the current argument.
2194 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2196 CCValAssign::LocInfo &LocInfo,
2197 ISD::ArgFlagsTy &ArgFlags,
2199 static const MCPhysReg ArgRegs[] = {
2200 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2204 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2206 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2208 // If there is only one Floating-point register left we need to put both f64
2209 // values of a split ppc_fp128 value on the stack.
2210 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2211 State.AllocateReg(ArgRegs[RegNum]);
2214 // Always return false here, as this function only makes sure that the two f64
2215 // values a ppc_fp128 value is split into are both passed in registers or both
2216 // passed on the stack and does not actually allocate a register for the
2217 // current argument.
2221 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2223 static const MCPhysReg *GetFPR() {
2224 static const MCPhysReg FPR[] = {
2225 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2226 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2232 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2234 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2235 unsigned PtrByteSize) {
2236 unsigned ArgSize = ArgVT.getStoreSize();
2237 if (Flags.isByVal())
2238 ArgSize = Flags.getByValSize();
2240 // Round up to multiples of the pointer size, except for array members,
2241 // which are always packed.
2242 if (!Flags.isInConsecutiveRegs())
2243 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2248 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2250 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2251 ISD::ArgFlagsTy Flags,
2252 unsigned PtrByteSize) {
2253 unsigned Align = PtrByteSize;
2255 // Altivec parameters are padded to a 16 byte boundary.
2256 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2257 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2258 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2261 // ByVal parameters are aligned as requested.
2262 if (Flags.isByVal()) {
2263 unsigned BVAlign = Flags.getByValAlign();
2264 if (BVAlign > PtrByteSize) {
2265 if (BVAlign % PtrByteSize != 0)
2267 "ByVal alignment is not a multiple of the pointer size");
2273 // Array members are always packed to their original alignment.
2274 if (Flags.isInConsecutiveRegs()) {
2275 // If the array member was split into multiple registers, the first
2276 // needs to be aligned to the size of the full type. (Except for
2277 // ppcf128, which is only aligned as its f64 components.)
2278 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2279 Align = OrigVT.getStoreSize();
2281 Align = ArgVT.getStoreSize();
2287 /// CalculateStackSlotUsed - Return whether this argument will use its
2288 /// stack slot (instead of being passed in registers). ArgOffset,
2289 /// AvailableFPRs, and AvailableVRs must hold the current argument
2290 /// position, and will be updated to account for this argument.
2291 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2292 ISD::ArgFlagsTy Flags,
2293 unsigned PtrByteSize,
2294 unsigned LinkageSize,
2295 unsigned ParamAreaSize,
2296 unsigned &ArgOffset,
2297 unsigned &AvailableFPRs,
2298 unsigned &AvailableVRs) {
2299 bool UseMemory = false;
2301 // Respect alignment of argument on the stack.
2303 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2304 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2305 // If there's no space left in the argument save area, we must
2306 // use memory (this check also catches zero-sized arguments).
2307 if (ArgOffset >= LinkageSize + ParamAreaSize)
2310 // Allocate argument on the stack.
2311 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2312 if (Flags.isInConsecutiveRegsLast())
2313 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2314 // If we overran the argument save area, we must use memory
2315 // (this check catches arguments passed partially in memory)
2316 if (ArgOffset > LinkageSize + ParamAreaSize)
2319 // However, if the argument is actually passed in an FPR or a VR,
2320 // we don't use memory after all.
2321 if (!Flags.isByVal()) {
2322 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2323 if (AvailableFPRs > 0) {
2327 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2328 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2329 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2330 if (AvailableVRs > 0) {
2339 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2340 /// ensure minimum alignment required for target.
2341 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2342 unsigned NumBytes) {
2343 unsigned TargetAlign =
2344 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2345 unsigned AlignMask = TargetAlign - 1;
2346 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2351 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2352 CallingConv::ID CallConv, bool isVarArg,
2353 const SmallVectorImpl<ISD::InputArg>
2355 SDLoc dl, SelectionDAG &DAG,
2356 SmallVectorImpl<SDValue> &InVals)
2358 if (Subtarget.isSVR4ABI()) {
2359 if (Subtarget.isPPC64())
2360 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2363 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2366 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2372 PPCTargetLowering::LowerFormalArguments_32SVR4(
2374 CallingConv::ID CallConv, bool isVarArg,
2375 const SmallVectorImpl<ISD::InputArg>
2377 SDLoc dl, SelectionDAG &DAG,
2378 SmallVectorImpl<SDValue> &InVals) const {
2380 // 32-bit SVR4 ABI Stack Frame Layout:
2381 // +-----------------------------------+
2382 // +--> | Back chain |
2383 // | +-----------------------------------+
2384 // | | Floating-point register save area |
2385 // | +-----------------------------------+
2386 // | | General register save area |
2387 // | +-----------------------------------+
2388 // | | CR save word |
2389 // | +-----------------------------------+
2390 // | | VRSAVE save word |
2391 // | +-----------------------------------+
2392 // | | Alignment padding |
2393 // | +-----------------------------------+
2394 // | | Vector register save area |
2395 // | +-----------------------------------+
2396 // | | Local variable space |
2397 // | +-----------------------------------+
2398 // | | Parameter list area |
2399 // | +-----------------------------------+
2400 // | | LR save word |
2401 // | +-----------------------------------+
2402 // SP--> +--- | Back chain |
2403 // +-----------------------------------+
2406 // System V Application Binary Interface PowerPC Processor Supplement
2407 // AltiVec Technology Programming Interface Manual
2409 MachineFunction &MF = DAG.getMachineFunction();
2410 MachineFrameInfo *MFI = MF.getFrameInfo();
2411 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2413 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2414 // Potential tail calls could cause overwriting of argument stack slots.
2415 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2416 (CallConv == CallingConv::Fast));
2417 unsigned PtrByteSize = 4;
2419 // Assign locations to all of the incoming arguments.
2420 SmallVector<CCValAssign, 16> ArgLocs;
2421 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2424 // Reserve space for the linkage area on the stack.
2425 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2426 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2428 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2431 CCValAssign &VA = ArgLocs[i];
2433 // Arguments stored in registers.
2434 if (VA.isRegLoc()) {
2435 const TargetRegisterClass *RC;
2436 EVT ValVT = VA.getValVT();
2438 switch (ValVT.getSimpleVT().SimpleTy) {
2440 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2443 RC = &PPC::GPRCRegClass;
2446 RC = &PPC::F4RCRegClass;
2449 if (Subtarget.hasVSX())
2450 RC = &PPC::VSFRCRegClass;
2452 RC = &PPC::F8RCRegClass;
2458 RC = &PPC::VRRCRegClass;
2462 RC = &PPC::VSHRCRegClass;
2466 // Transform the arguments stored in physical registers into virtual ones.
2467 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2468 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2469 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2471 if (ValVT == MVT::i1)
2472 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2474 InVals.push_back(ArgValue);
2476 // Argument stored in memory.
2477 assert(VA.isMemLoc());
2479 unsigned ArgSize = VA.getLocVT().getStoreSize();
2480 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2483 // Create load nodes to retrieve arguments from the stack.
2484 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2485 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2486 MachinePointerInfo(),
2487 false, false, false, 0));
2491 // Assign locations to all of the incoming aggregate by value arguments.
2492 // Aggregates passed by value are stored in the local variable space of the
2493 // caller's stack frame, right above the parameter list area.
2494 SmallVector<CCValAssign, 16> ByValArgLocs;
2495 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2496 ByValArgLocs, *DAG.getContext());
2498 // Reserve stack space for the allocations in CCInfo.
2499 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2501 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2503 // Area that is at least reserved in the caller of this function.
2504 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2505 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2507 // Set the size that is at least reserved in caller of this function. Tail
2508 // call optimized function's reserved stack space needs to be aligned so that
2509 // taking the difference between two stack areas will result in an aligned
2511 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2512 FuncInfo->setMinReservedArea(MinReservedArea);
2514 SmallVector<SDValue, 8> MemOps;
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start.
2519 static const MCPhysReg GPArgRegs[] = {
2520 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2521 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2523 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2525 static const MCPhysReg FPArgRegs[] = {
2526 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2529 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2530 if (DisablePPCFloatInVariadic)
2533 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2535 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2538 // Make room for NumGPArgRegs and NumFPArgRegs.
2539 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2540 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2542 FuncInfo->setVarArgsStackOffset(
2543 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2544 CCInfo.getNextStackOffset(), true));
2546 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2547 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2549 // The fixed integer arguments of a variadic function are stored to the
2550 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2551 // the result of va_next.
2552 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2553 // Get an existing live-in vreg, or add a new one.
2554 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2556 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2558 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2559 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2560 MachinePointerInfo(), false, false, 0);
2561 MemOps.push_back(Store);
2562 // Increment the address by four for the next argument to store
2563 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2564 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2567 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2569 // The double arguments are stored to the VarArgsFrameIndex
2571 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2572 // Get an existing live-in vreg, or add a new one.
2573 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2575 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2577 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2578 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2579 MachinePointerInfo(), false, false, 0);
2580 MemOps.push_back(Store);
2581 // Increment the address by eight for the next argument to store
2582 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2584 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2588 if (!MemOps.empty())
2589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2594 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2595 // value to MVT::i64 and then truncate to the correct register size.
2597 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2598 SelectionDAG &DAG, SDValue ArgVal,
2601 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2602 DAG.getValueType(ObjectVT));
2603 else if (Flags.isZExt())
2604 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2605 DAG.getValueType(ObjectVT));
2607 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2611 PPCTargetLowering::LowerFormalArguments_64SVR4(
2613 CallingConv::ID CallConv, bool isVarArg,
2614 const SmallVectorImpl<ISD::InputArg>
2616 SDLoc dl, SelectionDAG &DAG,
2617 SmallVectorImpl<SDValue> &InVals) const {
2618 // TODO: add description of PPC stack frame format, or at least some docs.
2620 bool isELFv2ABI = Subtarget.isELFv2ABI();
2621 bool isLittleEndian = Subtarget.isLittleEndian();
2622 MachineFunction &MF = DAG.getMachineFunction();
2623 MachineFrameInfo *MFI = MF.getFrameInfo();
2624 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2626 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2627 "fastcc not supported on varargs functions");
2629 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2630 // Potential tail calls could cause overwriting of argument stack slots.
2631 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2632 (CallConv == CallingConv::Fast));
2633 unsigned PtrByteSize = 8;
2635 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2638 static const MCPhysReg GPR[] = {
2639 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2640 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2643 static const MCPhysReg *FPR = GetFPR();
2645 static const MCPhysReg VR[] = {
2646 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2647 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2649 static const MCPhysReg VSRH[] = {
2650 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2651 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2654 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2655 const unsigned Num_FPR_Regs = 13;
2656 const unsigned Num_VR_Regs = array_lengthof(VR);
2658 // Do a first pass over the arguments to determine whether the ABI
2659 // guarantees that our caller has allocated the parameter save area
2660 // on its stack frame. In the ELFv1 ABI, this is always the case;
2661 // in the ELFv2 ABI, it is true if this is a vararg function or if
2662 // any parameter is located in a stack slot.
2664 bool HasParameterArea = !isELFv2ABI || isVarArg;
2665 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2666 unsigned NumBytes = LinkageSize;
2667 unsigned AvailableFPRs = Num_FPR_Regs;
2668 unsigned AvailableVRs = Num_VR_Regs;
2669 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2670 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2671 PtrByteSize, LinkageSize, ParamAreaSize,
2672 NumBytes, AvailableFPRs, AvailableVRs))
2673 HasParameterArea = true;
2675 // Add DAG nodes to load the arguments or copy them out of registers. On
2676 // entry to a function on PPC, the arguments start after the linkage area,
2677 // although the first ones are often in registers.
2679 unsigned ArgOffset = LinkageSize;
2680 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2681 SmallVector<SDValue, 8> MemOps;
2682 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2683 unsigned CurArgIdx = 0;
2684 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2686 bool needsLoad = false;
2687 EVT ObjectVT = Ins[ArgNo].VT;
2688 EVT OrigVT = Ins[ArgNo].ArgVT;
2689 unsigned ObjSize = ObjectVT.getStoreSize();
2690 unsigned ArgSize = ObjSize;
2691 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2692 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2693 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2695 // We re-align the argument offset for each argument, except when using the
2696 // fast calling convention, when we need to make sure we do that only when
2697 // we'll actually use a stack slot.
2698 unsigned CurArgOffset, Align;
2699 auto ComputeArgOffset = [&]() {
2700 /* Respect alignment of argument on the stack. */
2701 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2702 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2703 CurArgOffset = ArgOffset;
2706 if (CallConv != CallingConv::Fast) {
2709 /* Compute GPR index associated with argument offset. */
2710 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2711 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2714 // FIXME the codegen can be much improved in some cases.
2715 // We do not have to keep everything in memory.
2716 if (Flags.isByVal()) {
2717 if (CallConv == CallingConv::Fast)
2720 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2721 ObjSize = Flags.getByValSize();
2722 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2723 // Empty aggregate parameters do not take up registers. Examples:
2727 // etc. However, we have to provide a place-holder in InVals, so
2728 // pretend we have an 8-byte item at the current address for that
2731 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2732 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2733 InVals.push_back(FIN);
2737 // Create a stack object covering all stack doublewords occupied
2738 // by the argument. If the argument is (fully or partially) on
2739 // the stack, or if the argument is fully in registers but the
2740 // caller has allocated the parameter save anyway, we can refer
2741 // directly to the caller's stack frame. Otherwise, create a
2742 // local copy in our own frame.
2744 if (HasParameterArea ||
2745 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2746 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2748 FI = MFI->CreateStackObject(ArgSize, Align, false);
2749 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2751 // Handle aggregates smaller than 8 bytes.
2752 if (ObjSize < PtrByteSize) {
2753 // The value of the object is its address, which differs from the
2754 // address of the enclosing doubleword on big-endian systems.
2756 if (!isLittleEndian) {
2757 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2758 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2760 InVals.push_back(Arg);
2762 if (GPR_idx != Num_GPR_Regs) {
2763 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2767 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2768 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2769 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2770 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2771 MachinePointerInfo(FuncArg),
2772 ObjType, false, false, 0);
2774 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2775 // store the whole register as-is to the parameter save area
2777 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2778 MachinePointerInfo(FuncArg),
2782 MemOps.push_back(Store);
2784 // Whether we copied from a register or not, advance the offset
2785 // into the parameter save area by a full doubleword.
2786 ArgOffset += PtrByteSize;
2790 // The value of the object is its address, which is the address of
2791 // its first stack doubleword.
2792 InVals.push_back(FIN);
2794 // Store whatever pieces of the object are in registers to memory.
2795 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2796 if (GPR_idx == Num_GPR_Regs)
2799 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2800 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2803 SDValue Off = DAG.getConstant(j, PtrVT);
2804 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2806 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2807 MachinePointerInfo(FuncArg, j),
2809 MemOps.push_back(Store);
2812 ArgOffset += ArgSize;
2816 switch (ObjectVT.getSimpleVT().SimpleTy) {
2817 default: llvm_unreachable("Unhandled argument type!");
2821 // These can be scalar arguments or elements of an integer array type
2822 // passed directly. Clang may use those instead of "byval" aggregate
2823 // types to avoid forcing arguments to memory unnecessarily.
2824 if (GPR_idx != Num_GPR_Regs) {
2825 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2826 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2828 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2829 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2830 // value to MVT::i64 and then truncate to the correct register size.
2831 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2833 if (CallConv == CallingConv::Fast)
2837 ArgSize = PtrByteSize;
2839 if (CallConv != CallingConv::Fast || needsLoad)
2845 // These can be scalar arguments or elements of a float array type
2846 // passed directly. The latter are used to implement ELFv2 homogenous
2847 // float aggregates.
2848 if (FPR_idx != Num_FPR_Regs) {
2851 if (ObjectVT == MVT::f32)
2852 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2854 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2855 &PPC::VSFRCRegClass :
2856 &PPC::F8RCRegClass);
2858 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2860 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2861 // This can only ever happen in the presence of f32 array types,
2862 // since otherwise we never run out of FPRs before running out
2864 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2865 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2867 if (ObjectVT == MVT::f32) {
2868 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2869 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2870 DAG.getConstant(32, MVT::i32));
2871 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2874 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2876 if (CallConv == CallingConv::Fast)
2882 // When passing an array of floats, the array occupies consecutive
2883 // space in the argument area; only round up to the next doubleword
2884 // at the end of the array. Otherwise, each float takes 8 bytes.
2885 if (CallConv != CallingConv::Fast || needsLoad) {
2886 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2887 ArgOffset += ArgSize;
2888 if (Flags.isInConsecutiveRegsLast())
2889 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2898 // These can be scalar arguments or elements of a vector array type
2899 // passed directly. The latter are used to implement ELFv2 homogenous
2900 // vector aggregates.
2901 if (VR_idx != Num_VR_Regs) {
2902 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2903 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2904 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2905 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2908 if (CallConv == CallingConv::Fast)
2913 if (CallConv != CallingConv::Fast || needsLoad)
2918 // We need to load the argument to a virtual register if we determined
2919 // above that we ran out of physical registers of the appropriate type.
2921 if (ObjSize < ArgSize && !isLittleEndian)
2922 CurArgOffset += ArgSize - ObjSize;
2923 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2924 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2925 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2926 false, false, false, 0);
2929 InVals.push_back(ArgVal);
2932 // Area that is at least reserved in the caller of this function.
2933 unsigned MinReservedArea;
2934 if (HasParameterArea)
2935 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2937 MinReservedArea = LinkageSize;
2939 // Set the size that is at least reserved in caller of this function. Tail
2940 // call optimized functions' reserved stack space needs to be aligned so that
2941 // taking the difference between two stack areas will result in an aligned
2943 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2944 FuncInfo->setMinReservedArea(MinReservedArea);
2946 // If the function takes variable number of arguments, make a frame index for
2947 // the start of the first vararg value... for expansion of llvm.va_start.
2949 int Depth = ArgOffset;
2951 FuncInfo->setVarArgsFrameIndex(
2952 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2953 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2955 // If this function is vararg, store any remaining integer argument regs
2956 // to their spots on the stack so that they may be loaded by deferencing the
2957 // result of va_next.
2958 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2959 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2960 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2961 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2962 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2963 MachinePointerInfo(), false, false, 0);
2964 MemOps.push_back(Store);
2965 // Increment the address by four for the next argument to store
2966 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2967 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2971 if (!MemOps.empty())
2972 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2978 PPCTargetLowering::LowerFormalArguments_Darwin(
2980 CallingConv::ID CallConv, bool isVarArg,
2981 const SmallVectorImpl<ISD::InputArg>
2983 SDLoc dl, SelectionDAG &DAG,
2984 SmallVectorImpl<SDValue> &InVals) const {
2985 // TODO: add description of PPC stack frame format, or at least some docs.
2987 MachineFunction &MF = DAG.getMachineFunction();
2988 MachineFrameInfo *MFI = MF.getFrameInfo();
2989 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2991 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2992 bool isPPC64 = PtrVT == MVT::i64;
2993 // Potential tail calls could cause overwriting of argument stack slots.
2994 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2995 (CallConv == CallingConv::Fast));
2996 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2998 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
3000 unsigned ArgOffset = LinkageSize;
3001 // Area that is at least reserved in caller of this function.
3002 unsigned MinReservedArea = ArgOffset;
3004 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3005 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3006 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3008 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3009 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3010 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3013 static const MCPhysReg *FPR = GetFPR();
3015 static const MCPhysReg VR[] = {
3016 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3017 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3020 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3021 const unsigned Num_FPR_Regs = 13;
3022 const unsigned Num_VR_Regs = array_lengthof( VR);
3024 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3026 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3028 // In 32-bit non-varargs functions, the stack space for vectors is after the
3029 // stack space for non-vectors. We do not use this space unless we have
3030 // too many vectors to fit in registers, something that only occurs in
3031 // constructed examples:), but we have to walk the arglist to figure
3032 // that out...for the pathological case, compute VecArgOffset as the
3033 // start of the vector parameter area. Computing VecArgOffset is the
3034 // entire point of the following loop.
3035 unsigned VecArgOffset = ArgOffset;
3036 if (!isVarArg && !isPPC64) {
3037 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3039 EVT ObjectVT = Ins[ArgNo].VT;
3040 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3042 if (Flags.isByVal()) {
3043 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3044 unsigned ObjSize = Flags.getByValSize();
3046 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3047 VecArgOffset += ArgSize;
3051 switch(ObjectVT.getSimpleVT().SimpleTy) {
3052 default: llvm_unreachable("Unhandled argument type!");
3058 case MVT::i64: // PPC64
3060 // FIXME: We are guaranteed to be !isPPC64 at this point.
3061 // Does MVT::i64 apply?
3068 // Nothing to do, we're only looking at Nonvector args here.
3073 // We've found where the vector parameter area in memory is. Skip the
3074 // first 12 parameters; these don't use that memory.
3075 VecArgOffset = ((VecArgOffset+15)/16)*16;
3076 VecArgOffset += 12*16;
3078 // Add DAG nodes to load the arguments or copy them out of registers. On
3079 // entry to a function on PPC, the arguments start after the linkage area,
3080 // although the first ones are often in registers.
3082 SmallVector<SDValue, 8> MemOps;
3083 unsigned nAltivecParamsAtEnd = 0;
3084 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3085 unsigned CurArgIdx = 0;
3086 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3088 bool needsLoad = false;
3089 EVT ObjectVT = Ins[ArgNo].VT;
3090 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3091 unsigned ArgSize = ObjSize;
3092 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3093 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3094 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3096 unsigned CurArgOffset = ArgOffset;
3098 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3099 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3100 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3101 if (isVarArg || isPPC64) {
3102 MinReservedArea = ((MinReservedArea+15)/16)*16;
3103 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3106 } else nAltivecParamsAtEnd++;
3108 // Calculate min reserved area.
3109 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3113 // FIXME the codegen can be much improved in some cases.
3114 // We do not have to keep everything in memory.
3115 if (Flags.isByVal()) {
3116 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3117 ObjSize = Flags.getByValSize();
3118 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3119 // Objects of size 1 and 2 are right justified, everything else is
3120 // left justified. This means the memory address is adjusted forwards.
3121 if (ObjSize==1 || ObjSize==2) {
3122 CurArgOffset = CurArgOffset + (4 - ObjSize);
3124 // The value of the object is its address.
3125 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3126 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3127 InVals.push_back(FIN);
3128 if (ObjSize==1 || ObjSize==2) {
3129 if (GPR_idx != Num_GPR_Regs) {
3132 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3134 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3135 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3136 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3137 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3138 MachinePointerInfo(FuncArg),
3139 ObjType, false, false, 0);
3140 MemOps.push_back(Store);
3144 ArgOffset += PtrByteSize;
3148 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3149 // Store whatever pieces of the object are in registers
3150 // to memory. ArgOffset will be the address of the beginning
3152 if (GPR_idx != Num_GPR_Regs) {
3155 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3157 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3158 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3159 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3160 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3161 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3162 MachinePointerInfo(FuncArg, j),
3164 MemOps.push_back(Store);
3166 ArgOffset += PtrByteSize;
3168 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3175 switch (ObjectVT.getSimpleVT().SimpleTy) {
3176 default: llvm_unreachable("Unhandled argument type!");
3180 if (GPR_idx != Num_GPR_Regs) {
3181 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3182 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3184 if (ObjectVT == MVT::i1)
3185 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3190 ArgSize = PtrByteSize;
3192 // All int arguments reserve stack space in the Darwin ABI.
3193 ArgOffset += PtrByteSize;
3197 case MVT::i64: // PPC64
3198 if (GPR_idx != Num_GPR_Regs) {
3199 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3200 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3202 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3203 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3204 // value to MVT::i64 and then truncate to the correct register size.
3205 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3210 ArgSize = PtrByteSize;
3212 // All int arguments reserve stack space in the Darwin ABI.
3218 // Every 4 bytes of argument space consumes one of the GPRs available for
3219 // argument passing.
3220 if (GPR_idx != Num_GPR_Regs) {
3222 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3225 if (FPR_idx != Num_FPR_Regs) {
3228 if (ObjectVT == MVT::f32)
3229 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3231 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3233 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3239 // All FP arguments reserve stack space in the Darwin ABI.
3240 ArgOffset += isPPC64 ? 8 : ObjSize;
3246 // Note that vector arguments in registers don't reserve stack space,
3247 // except in varargs functions.
3248 if (VR_idx != Num_VR_Regs) {
3249 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3250 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3252 while ((ArgOffset % 16) != 0) {
3253 ArgOffset += PtrByteSize;
3254 if (GPR_idx != Num_GPR_Regs)
3258 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3262 if (!isVarArg && !isPPC64) {
3263 // Vectors go after all the nonvectors.
3264 CurArgOffset = VecArgOffset;
3267 // Vectors are aligned.
3268 ArgOffset = ((ArgOffset+15)/16)*16;
3269 CurArgOffset = ArgOffset;
3277 // We need to load the argument to a virtual register if we determined above
3278 // that we ran out of physical registers of the appropriate type.
3280 int FI = MFI->CreateFixedObject(ObjSize,
3281 CurArgOffset + (ArgSize - ObjSize),
3283 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3284 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3285 false, false, false, 0);
3288 InVals.push_back(ArgVal);
3291 // Allow for Altivec parameters at the end, if needed.
3292 if (nAltivecParamsAtEnd) {
3293 MinReservedArea = ((MinReservedArea+15)/16)*16;
3294 MinReservedArea += 16*nAltivecParamsAtEnd;
3297 // Area that is at least reserved in the caller of this function.
3298 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3300 // Set the size that is at least reserved in caller of this function. Tail
3301 // call optimized functions' reserved stack space needs to be aligned so that
3302 // taking the difference between two stack areas will result in an aligned
3304 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3305 FuncInfo->setMinReservedArea(MinReservedArea);
3307 // If the function takes variable number of arguments, make a frame index for
3308 // the start of the first vararg value... for expansion of llvm.va_start.
3310 int Depth = ArgOffset;
3312 FuncInfo->setVarArgsFrameIndex(
3313 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3315 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3317 // If this function is vararg, store any remaining integer argument regs
3318 // to their spots on the stack so that they may be loaded by deferencing the
3319 // result of va_next.
3320 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3324 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3326 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3328 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3329 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3330 MachinePointerInfo(), false, false, 0);
3331 MemOps.push_back(Store);
3332 // Increment the address by four for the next argument to store
3333 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3334 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3338 if (!MemOps.empty())
3339 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3344 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3345 /// adjusted to accommodate the arguments for the tailcall.
3346 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3347 unsigned ParamSize) {
3349 if (!isTailCall) return 0;
3351 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3352 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3353 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3354 // Remember only if the new adjustement is bigger.
3355 if (SPDiff < FI->getTailCallSPDelta())
3356 FI->setTailCallSPDelta(SPDiff);
3361 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3362 /// for tail call optimization. Targets which want to do tail call
3363 /// optimization should implement this function.
3365 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3366 CallingConv::ID CalleeCC,
3368 const SmallVectorImpl<ISD::InputArg> &Ins,
3369 SelectionDAG& DAG) const {
3370 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3373 // Variable argument functions are not supported.
3377 MachineFunction &MF = DAG.getMachineFunction();
3378 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3379 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3380 // Functions containing by val parameters are not supported.
3381 for (unsigned i = 0; i != Ins.size(); i++) {
3382 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3383 if (Flags.isByVal()) return false;
3386 // Non-PIC/GOT tail calls are supported.
3387 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3390 // At the moment we can only do local tail calls (in same module, hidden
3391 // or protected) if we are generating PIC.
3392 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3393 return G->getGlobal()->hasHiddenVisibility()
3394 || G->getGlobal()->hasProtectedVisibility();
3400 /// isCallCompatibleAddress - Return the immediate to use if the specified
3401 /// 32-bit value is representable in the immediate field of a BxA instruction.
3402 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3404 if (!C) return nullptr;
3406 int Addr = C->getZExtValue();
3407 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3408 SignExtend32<26>(Addr) != Addr)
3409 return nullptr; // Top 6 bits have to be sext of immediate.
3411 return DAG.getConstant((int)C->getZExtValue() >> 2,
3412 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3417 struct TailCallArgumentInfo {
3422 TailCallArgumentInfo() : FrameIdx(0) {}
3427 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3429 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3431 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3432 SmallVectorImpl<SDValue> &MemOpChains,
3434 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3435 SDValue Arg = TailCallArgs[i].Arg;
3436 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3437 int FI = TailCallArgs[i].FrameIdx;
3438 // Store relative to framepointer.
3439 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3440 MachinePointerInfo::getFixedStack(FI),
3445 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3446 /// the appropriate stack slot for the tail call optimized function call.
3447 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3448 MachineFunction &MF,
3457 // Calculate the new stack slot for the return address.
3458 int SlotSize = isPPC64 ? 8 : 4;
3459 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3461 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3462 NewRetAddrLoc, true);
3463 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3464 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3465 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3466 MachinePointerInfo::getFixedStack(NewRetAddr),
3469 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3470 // slot as the FP is never overwritten.
3473 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3474 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3476 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3477 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3478 MachinePointerInfo::getFixedStack(NewFPIdx),
3485 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3486 /// the position of the argument.
3488 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3489 SDValue Arg, int SPDiff, unsigned ArgOffset,
3490 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3491 int Offset = ArgOffset + SPDiff;
3492 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3493 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3494 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3495 SDValue FIN = DAG.getFrameIndex(FI, VT);
3496 TailCallArgumentInfo Info;
3498 Info.FrameIdxOp = FIN;
3500 TailCallArguments.push_back(Info);
3503 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3504 /// stack slot. Returns the chain as result and the loaded frame pointers in
3505 /// LROpOut/FPOpout. Used when tail calling.
3506 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3514 // Load the LR and FP stack slot for later adjusting.
3515 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3516 LROpOut = getReturnAddrFrameIndex(DAG);
3517 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3518 false, false, false, 0);
3519 Chain = SDValue(LROpOut.getNode(), 1);
3521 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3522 // slot as the FP is never overwritten.
3524 FPOpOut = getFramePointerFrameIndex(DAG);
3525 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3526 false, false, false, 0);
3527 Chain = SDValue(FPOpOut.getNode(), 1);
3533 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3534 /// by "Src" to address "Dst" of size "Size". Alignment information is
3535 /// specified by the specific parameter attribute. The copy will be passed as
3536 /// a byval function parameter.
3537 /// Sometimes what we are copying is the end of a larger object, the part that
3538 /// does not fit in registers.
3540 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3541 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3543 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3544 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3545 false, false, MachinePointerInfo(),
3546 MachinePointerInfo());
3549 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3552 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3553 SDValue Arg, SDValue PtrOff, int SPDiff,
3554 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3555 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3556 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3558 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3563 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3565 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3566 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3567 DAG.getConstant(ArgOffset, PtrVT));
3569 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3570 MachinePointerInfo(), false, false, 0));
3571 // Calculate and remember argument location.
3572 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3577 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3578 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3579 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3580 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3581 MachineFunction &MF = DAG.getMachineFunction();
3583 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3584 // might overwrite each other in case of tail call optimization.
3585 SmallVector<SDValue, 8> MemOpChains2;
3586 // Do not flag preceding copytoreg stuff together with the following stuff.
3588 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3590 if (!MemOpChains2.empty())
3591 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3593 // Store the return address to the appropriate stack slot.
3594 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3595 isPPC64, isDarwinABI, dl);
3597 // Emit callseq_end just before tailcall node.
3598 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3599 DAG.getIntPtrConstant(0, true), InFlag, dl);
3600 InFlag = Chain.getValue(1);
3603 // Is this global address that of a function that can be called by name? (as
3604 // opposed to something that must hold a descriptor for an indirect call).
3605 static bool isFunctionGlobalAddress(SDValue Callee) {
3606 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3607 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3608 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3611 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3618 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3619 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3620 bool isTailCall, bool IsPatchPoint,
3621 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3622 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3623 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3625 bool isPPC64 = Subtarget.isPPC64();
3626 bool isSVR4ABI = Subtarget.isSVR4ABI();
3627 bool isELFv2ABI = Subtarget.isELFv2ABI();
3629 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3630 NodeTys.push_back(MVT::Other); // Returns a chain
3631 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3633 unsigned CallOpc = PPCISD::CALL;
3635 bool needIndirectCall = true;
3636 if (!isSVR4ABI || !isPPC64)
3637 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3638 // If this is an absolute destination address, use the munged value.
3639 Callee = SDValue(Dest, 0);
3640 needIndirectCall = false;
3643 if (isFunctionGlobalAddress(Callee)) {
3644 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3645 // A call to a TLS address is actually an indirect call to a
3646 // thread-specific pointer.
3647 unsigned OpFlags = 0;
3648 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3649 (Subtarget.getTargetTriple().isMacOSX() &&
3650 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3651 (G->getGlobal()->isDeclaration() ||
3652 G->getGlobal()->isWeakForLinker())) ||
3653 (Subtarget.isTargetELF() && !isPPC64 &&
3654 !G->getGlobal()->hasLocalLinkage() &&
3655 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3656 // PC-relative references to external symbols should go through $stub,
3657 // unless we're building with the leopard linker or later, which
3658 // automatically synthesizes these stubs.
3659 OpFlags = PPCII::MO_PLT_OR_STUB;
3662 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3663 // every direct call is) turn it into a TargetGlobalAddress /
3664 // TargetExternalSymbol node so that legalize doesn't hack it.
3665 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3666 Callee.getValueType(), 0, OpFlags);
3667 needIndirectCall = false;
3670 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3671 unsigned char OpFlags = 0;
3673 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3674 (Subtarget.getTargetTriple().isMacOSX() &&
3675 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3676 (Subtarget.isTargetELF() && !isPPC64 &&
3677 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3678 // PC-relative references to external symbols should go through $stub,
3679 // unless we're building with the leopard linker or later, which
3680 // automatically synthesizes these stubs.
3681 OpFlags = PPCII::MO_PLT_OR_STUB;
3684 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3686 needIndirectCall = false;
3690 // We'll form an invalid direct call when lowering a patchpoint; the full
3691 // sequence for an indirect call is complicated, and many of the
3692 // instructions introduced might have side effects (and, thus, can't be
3693 // removed later). The call itself will be removed as soon as the
3694 // argument/return lowering is complete, so the fact that it has the wrong
3695 // kind of operands should not really matter.
3696 needIndirectCall = false;
3699 if (needIndirectCall) {
3700 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3701 // to do the call, we can't use PPCISD::CALL.
3702 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3704 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3705 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3706 // entry point, but to the function descriptor (the function entry point
3707 // address is part of the function descriptor though).
3708 // The function descriptor is a three doubleword structure with the
3709 // following fields: function entry point, TOC base address and
3710 // environment pointer.
3711 // Thus for a call through a function pointer, the following actions need
3713 // 1. Save the TOC of the caller in the TOC save area of its stack
3714 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3715 // 2. Load the address of the function entry point from the function
3717 // 3. Load the TOC of the callee from the function descriptor into r2.
3718 // 4. Load the environment pointer from the function descriptor into
3720 // 5. Branch to the function entry point address.
3721 // 6. On return of the callee, the TOC of the caller needs to be
3722 // restored (this is done in FinishCall()).
3724 // The loads are scheduled at the beginning of the call sequence, and the
3725 // register copies are flagged together to ensure that no other
3726 // operations can be scheduled in between. E.g. without flagging the
3727 // copies together, a TOC access in the caller could be scheduled between
3728 // the assignment of the callee TOC and the branch to the callee, which
3729 // results in the TOC access going through the TOC of the callee instead
3730 // of going through the TOC of the caller, which leads to incorrect code.
3732 // Load the address of the function entry point from the function
3734 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3735 if (LDChain.getValueType() == MVT::Glue)
3736 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3738 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3740 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3741 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3742 false, false, LoadsInv, 8);
3744 // Load environment pointer into r11.
3745 SDValue PtrOff = DAG.getIntPtrConstant(16);
3746 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3747 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3748 MPI.getWithOffset(16), false, false,
3751 SDValue TOCOff = DAG.getIntPtrConstant(8);
3752 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3753 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3754 MPI.getWithOffset(8), false, false,
3757 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3759 Chain = TOCVal.getValue(0);
3760 InFlag = TOCVal.getValue(1);
3762 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3765 Chain = EnvVal.getValue(0);
3766 InFlag = EnvVal.getValue(1);
3768 MTCTROps[0] = Chain;
3769 MTCTROps[1] = LoadFuncPtr;
3770 MTCTROps[2] = InFlag;
3773 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3774 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3775 InFlag = Chain.getValue(1);
3778 NodeTys.push_back(MVT::Other);
3779 NodeTys.push_back(MVT::Glue);
3780 Ops.push_back(Chain);
3781 CallOpc = PPCISD::BCTRL;
3782 Callee.setNode(nullptr);
3783 // Add use of X11 (holding environment pointer)
3784 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3785 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3786 // Add CTR register as callee so a bctr can be emitted later.
3788 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3791 // If this is a direct call, pass the chain and the callee.
3792 if (Callee.getNode()) {
3793 Ops.push_back(Chain);
3794 Ops.push_back(Callee);
3796 // If this is a call to __tls_get_addr, find the symbol whose address
3797 // is to be taken and add it to the list. This will be used to
3798 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3799 // We find the symbol by walking the chain to the CopyFromReg, walking
3800 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3801 // pulling the symbol from that node.
3802 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3803 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3804 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3805 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3806 SDValue TGTAddr = AddI->getOperand(1);
3807 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3808 "Didn't find target global TLS address where we expected one");
3809 Ops.push_back(TGTAddr);
3810 CallOpc = PPCISD::CALL_TLS;
3813 // If this is a tail call add stack pointer delta.
3815 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3817 // Add argument registers to the end of the list so that they are known live
3819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3820 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3821 RegsToPass[i].second.getValueType()));
3823 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3824 if (Callee.getNode() && isELFv2ABI && !IsPatchPoint)
3825 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3831 bool isLocalCall(const SDValue &Callee)
3833 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3834 return !G->getGlobal()->isDeclaration() &&
3835 !G->getGlobal()->isWeakForLinker();
3840 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3841 CallingConv::ID CallConv, bool isVarArg,
3842 const SmallVectorImpl<ISD::InputArg> &Ins,
3843 SDLoc dl, SelectionDAG &DAG,
3844 SmallVectorImpl<SDValue> &InVals) const {
3846 SmallVector<CCValAssign, 16> RVLocs;
3847 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3849 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3851 // Copy all of the result registers out of their specified physreg.
3852 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3853 CCValAssign &VA = RVLocs[i];
3854 assert(VA.isRegLoc() && "Can only return in registers!");
3856 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3857 VA.getLocReg(), VA.getLocVT(), InFlag);
3858 Chain = Val.getValue(1);
3859 InFlag = Val.getValue(2);
3861 switch (VA.getLocInfo()) {
3862 default: llvm_unreachable("Unknown loc info!");
3863 case CCValAssign::Full: break;
3864 case CCValAssign::AExt:
3865 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3867 case CCValAssign::ZExt:
3868 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3869 DAG.getValueType(VA.getValVT()));
3870 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3872 case CCValAssign::SExt:
3873 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3874 DAG.getValueType(VA.getValVT()));
3875 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3879 InVals.push_back(Val);
3886 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3887 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3889 SmallVector<std::pair<unsigned, SDValue>, 8>
3891 SDValue InFlag, SDValue Chain,
3892 SDValue CallSeqStart, SDValue &Callee,
3893 int SPDiff, unsigned NumBytes,
3894 const SmallVectorImpl<ISD::InputArg> &Ins,
3895 SmallVectorImpl<SDValue> &InVals,
3896 ImmutableCallSite *CS) const {
3898 bool isELFv2ABI = Subtarget.isELFv2ABI();
3899 std::vector<EVT> NodeTys;
3900 SmallVector<SDValue, 8> Ops;
3901 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3902 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3903 Ops, NodeTys, CS, Subtarget);
3905 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3906 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3907 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3909 // When performing tail call optimization the callee pops its arguments off
3910 // the stack. Account for this here so these bytes can be pushed back on in
3911 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3912 int BytesCalleePops =
3913 (CallConv == CallingConv::Fast &&
3914 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3916 // Add a register mask operand representing the call-preserved registers.
3917 const TargetRegisterInfo *TRI =
3918 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3919 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3920 assert(Mask && "Missing call preserved mask for calling convention");
3921 Ops.push_back(DAG.getRegisterMask(Mask));
3923 if (InFlag.getNode())
3924 Ops.push_back(InFlag);
3928 assert(((Callee.getOpcode() == ISD::Register &&
3929 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3930 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3931 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3932 isa<ConstantSDNode>(Callee)) &&
3933 "Expecting an global address, external symbol, absolute value or register");
3935 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3938 // Add a NOP immediately after the branch instruction when using the 64-bit
3939 // SVR4 ABI. At link time, if caller and callee are in a different module and
3940 // thus have a different TOC, the call will be replaced with a call to a stub
3941 // function which saves the current TOC, loads the TOC of the callee and
3942 // branches to the callee. The NOP will be replaced with a load instruction
3943 // which restores the TOC of the caller from the TOC save slot of the current
3944 // stack frame. If caller and callee belong to the same module (and have the
3945 // same TOC), the NOP will remain unchanged.
3947 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3949 if (CallOpc == PPCISD::BCTRL) {
3950 // This is a call through a function pointer.
3951 // Restore the caller TOC from the save area into R2.
3952 // See PrepareCall() for more information about calls through function
3953 // pointers in the 64-bit SVR4 ABI.
3954 // We are using a target-specific load with r2 hard coded, because the
3955 // result of a target-independent load would never go directly into r2,
3956 // since r2 is a reserved register (which prevents the register allocator
3957 // from allocating it), resulting in an additional register being
3958 // allocated and an unnecessary move instruction being generated.
3959 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3961 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3962 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3963 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3964 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3965 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3967 // The address needs to go after the chain input but before the flag (or
3968 // any other variadic arguments).
3969 Ops.insert(std::next(Ops.begin()), AddTOC);
3970 } else if ((CallOpc == PPCISD::CALL) &&
3971 (!isLocalCall(Callee) ||
3972 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3973 // Otherwise insert NOP for non-local calls.
3974 CallOpc = PPCISD::CALL_NOP;
3975 } else if (CallOpc == PPCISD::CALL_TLS)
3976 // For 64-bit SVR4, TLS calls are always non-local.
3977 CallOpc = PPCISD::CALL_NOP_TLS;
3980 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3981 InFlag = Chain.getValue(1);
3983 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3984 DAG.getIntPtrConstant(BytesCalleePops, true),
3987 InFlag = Chain.getValue(1);
3989 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3990 Ins, dl, DAG, InVals);
3994 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3995 SmallVectorImpl<SDValue> &InVals) const {
3996 SelectionDAG &DAG = CLI.DAG;
3998 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3999 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4000 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4001 SDValue Chain = CLI.Chain;
4002 SDValue Callee = CLI.Callee;
4003 bool &isTailCall = CLI.IsTailCall;
4004 CallingConv::ID CallConv = CLI.CallConv;
4005 bool isVarArg = CLI.IsVarArg;
4006 bool IsPatchPoint = CLI.IsPatchPoint;
4007 ImmutableCallSite *CS = CLI.CS;
4010 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4013 if (!isTailCall && CS && CS->isMustTailCall())
4014 report_fatal_error("failed to perform tail call elimination on a call "
4015 "site marked musttail");
4017 if (Subtarget.isSVR4ABI()) {
4018 if (Subtarget.isPPC64())
4019 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4020 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4021 dl, DAG, InVals, CS);
4023 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4024 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4025 dl, DAG, InVals, CS);
4028 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4029 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4030 dl, DAG, InVals, CS);
4034 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4035 CallingConv::ID CallConv, bool isVarArg,
4036 bool isTailCall, bool IsPatchPoint,
4037 const SmallVectorImpl<ISD::OutputArg> &Outs,
4038 const SmallVectorImpl<SDValue> &OutVals,
4039 const SmallVectorImpl<ISD::InputArg> &Ins,
4040 SDLoc dl, SelectionDAG &DAG,
4041 SmallVectorImpl<SDValue> &InVals,
4042 ImmutableCallSite *CS) const {
4043 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4044 // of the 32-bit SVR4 ABI stack frame layout.
4046 assert((CallConv == CallingConv::C ||
4047 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4049 unsigned PtrByteSize = 4;
4051 MachineFunction &MF = DAG.getMachineFunction();
4053 // Mark this function as potentially containing a function that contains a
4054 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4055 // and restoring the callers stack pointer in this functions epilog. This is
4056 // done because by tail calling the called function might overwrite the value
4057 // in this function's (MF) stack pointer stack slot 0(SP).
4058 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4059 CallConv == CallingConv::Fast)
4060 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4062 // Count how many bytes are to be pushed on the stack, including the linkage
4063 // area, parameter list area and the part of the local variable space which
4064 // contains copies of aggregates which are passed by value.
4066 // Assign locations to all of the outgoing arguments.
4067 SmallVector<CCValAssign, 16> ArgLocs;
4068 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4071 // Reserve space for the linkage area on the stack.
4072 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4076 // Handle fixed and variable vector arguments differently.
4077 // Fixed vector arguments go into registers as long as registers are
4078 // available. Variable vector arguments always go into memory.
4079 unsigned NumArgs = Outs.size();
4081 for (unsigned i = 0; i != NumArgs; ++i) {
4082 MVT ArgVT = Outs[i].VT;
4083 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4086 if (Outs[i].IsFixed) {
4087 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4090 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4096 errs() << "Call operand #" << i << " has unhandled type "
4097 << EVT(ArgVT).getEVTString() << "\n";
4099 llvm_unreachable(nullptr);
4103 // All arguments are treated the same.
4104 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4107 // Assign locations to all of the outgoing aggregate by value arguments.
4108 SmallVector<CCValAssign, 16> ByValArgLocs;
4109 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4110 ByValArgLocs, *DAG.getContext());
4112 // Reserve stack space for the allocations in CCInfo.
4113 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4115 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4117 // Size of the linkage area, parameter list area and the part of the local
4118 // space variable where copies of aggregates which are passed by value are
4120 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4122 // Calculate by how many bytes the stack has to be adjusted in case of tail
4123 // call optimization.
4124 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4126 // Adjust the stack pointer for the new arguments...
4127 // These operations are automatically eliminated by the prolog/epilog pass
4128 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4130 SDValue CallSeqStart = Chain;
4132 // Load the return address and frame pointer so it can be moved somewhere else
4135 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4138 // Set up a copy of the stack pointer for use loading and storing any
4139 // arguments that may not fit in the registers available for argument
4141 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4143 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4144 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4145 SmallVector<SDValue, 8> MemOpChains;
4147 bool seenFloatArg = false;
4148 // Walk the register/memloc assignments, inserting copies/loads.
4149 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4152 CCValAssign &VA = ArgLocs[i];
4153 SDValue Arg = OutVals[i];
4154 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4156 if (Flags.isByVal()) {
4157 // Argument is an aggregate which is passed by value, thus we need to
4158 // create a copy of it in the local variable space of the current stack
4159 // frame (which is the stack frame of the caller) and pass the address of
4160 // this copy to the callee.
4161 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4162 CCValAssign &ByValVA = ByValArgLocs[j++];
4163 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4165 // Memory reserved in the local variable space of the callers stack frame.
4166 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4168 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4169 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4171 // Create a copy of the argument in the local area of the current
4173 SDValue MemcpyCall =
4174 CreateCopyOfByValArgument(Arg, PtrOff,
4175 CallSeqStart.getNode()->getOperand(0),
4178 // This must go outside the CALLSEQ_START..END.
4179 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4180 CallSeqStart.getNode()->getOperand(1),
4182 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4183 NewCallSeqStart.getNode());
4184 Chain = CallSeqStart = NewCallSeqStart;
4186 // Pass the address of the aggregate copy on the stack either in a
4187 // physical register or in the parameter list area of the current stack
4188 // frame to the callee.
4192 if (VA.isRegLoc()) {
4193 if (Arg.getValueType() == MVT::i1)
4194 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4196 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4197 // Put argument in a physical register.
4198 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4200 // Put argument in the parameter list area of the current stack frame.
4201 assert(VA.isMemLoc());
4202 unsigned LocMemOffset = VA.getLocMemOffset();
4205 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4206 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4208 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4209 MachinePointerInfo(),
4212 // Calculate and remember argument location.
4213 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4219 if (!MemOpChains.empty())
4220 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4222 // Build a sequence of copy-to-reg nodes chained together with token chain
4223 // and flag operands which copy the outgoing args into the appropriate regs.
4225 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4226 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4227 RegsToPass[i].second, InFlag);
4228 InFlag = Chain.getValue(1);
4231 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4234 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4235 SDValue Ops[] = { Chain, InFlag };
4237 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4238 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4240 InFlag = Chain.getValue(1);
4244 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4245 false, TailCallArguments);
4247 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4248 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4249 NumBytes, Ins, InVals, CS);
4252 // Copy an argument into memory, being careful to do this outside the
4253 // call sequence for the call to which the argument belongs.
4255 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4256 SDValue CallSeqStart,
4257 ISD::ArgFlagsTy Flags,
4260 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4261 CallSeqStart.getNode()->getOperand(0),
4263 // The MEMCPY must go outside the CALLSEQ_START..END.
4264 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4265 CallSeqStart.getNode()->getOperand(1),
4267 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4268 NewCallSeqStart.getNode());
4269 return NewCallSeqStart;
4273 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4274 CallingConv::ID CallConv, bool isVarArg,
4275 bool isTailCall, bool IsPatchPoint,
4276 const SmallVectorImpl<ISD::OutputArg> &Outs,
4277 const SmallVectorImpl<SDValue> &OutVals,
4278 const SmallVectorImpl<ISD::InputArg> &Ins,
4279 SDLoc dl, SelectionDAG &DAG,
4280 SmallVectorImpl<SDValue> &InVals,
4281 ImmutableCallSite *CS) const {
4283 bool isELFv2ABI = Subtarget.isELFv2ABI();
4284 bool isLittleEndian = Subtarget.isLittleEndian();
4285 unsigned NumOps = Outs.size();
4287 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4288 unsigned PtrByteSize = 8;
4290 MachineFunction &MF = DAG.getMachineFunction();
4292 // Mark this function as potentially containing a function that contains a
4293 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4294 // and restoring the callers stack pointer in this functions epilog. This is
4295 // done because by tail calling the called function might overwrite the value
4296 // in this function's (MF) stack pointer stack slot 0(SP).
4297 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4298 CallConv == CallingConv::Fast)
4299 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4301 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4302 "fastcc not supported on varargs functions");
4304 // Count how many bytes are to be pushed on the stack, including the linkage
4305 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4306 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4307 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4308 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4310 unsigned NumBytes = LinkageSize;
4311 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4313 static const MCPhysReg GPR[] = {
4314 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4315 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4317 static const MCPhysReg *FPR = GetFPR();
4319 static const MCPhysReg VR[] = {
4320 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4321 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4323 static const MCPhysReg VSRH[] = {
4324 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4325 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4328 const unsigned NumGPRs = array_lengthof(GPR);
4329 const unsigned NumFPRs = 13;
4330 const unsigned NumVRs = array_lengthof(VR);
4332 // When using the fast calling convention, we don't provide backing for
4333 // arguments that will be in registers.
4334 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4336 // Add up all the space actually used.
4337 for (unsigned i = 0; i != NumOps; ++i) {
4338 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4339 EVT ArgVT = Outs[i].VT;
4340 EVT OrigVT = Outs[i].ArgVT;
4342 if (CallConv == CallingConv::Fast) {
4343 if (Flags.isByVal())
4344 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4346 switch (ArgVT.getSimpleVT().SimpleTy) {
4347 default: llvm_unreachable("Unexpected ValueType for argument!");
4351 if (++NumGPRsUsed <= NumGPRs)
4356 if (++NumFPRsUsed <= NumFPRs)
4365 if (++NumVRsUsed <= NumVRs)
4371 /* Respect alignment of argument on the stack. */
4373 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4374 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4376 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4377 if (Flags.isInConsecutiveRegsLast())
4378 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4381 unsigned NumBytesActuallyUsed = NumBytes;
4383 // The prolog code of the callee may store up to 8 GPR argument registers to
4384 // the stack, allowing va_start to index over them in memory if its varargs.
4385 // Because we cannot tell if this is needed on the caller side, we have to
4386 // conservatively assume that it is needed. As such, make sure we have at
4387 // least enough stack space for the caller to store the 8 GPRs.
4388 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4389 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4391 // Tail call needs the stack to be aligned.
4392 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4393 CallConv == CallingConv::Fast)
4394 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4396 // Calculate by how many bytes the stack has to be adjusted in case of tail
4397 // call optimization.
4398 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4400 // To protect arguments on the stack from being clobbered in a tail call,
4401 // force all the loads to happen before doing any other lowering.
4403 Chain = DAG.getStackArgumentTokenFactor(Chain);
4405 // Adjust the stack pointer for the new arguments...
4406 // These operations are automatically eliminated by the prolog/epilog pass
4407 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4409 SDValue CallSeqStart = Chain;
4411 // Load the return address and frame pointer so it can be move somewhere else
4414 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4417 // Set up a copy of the stack pointer for use loading and storing any
4418 // arguments that may not fit in the registers available for argument
4420 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4422 // Figure out which arguments are going to go in registers, and which in
4423 // memory. Also, if this is a vararg function, floating point operations
4424 // must be stored to our stack, and loaded into integer regs as well, if
4425 // any integer regs are available for argument passing.
4426 unsigned ArgOffset = LinkageSize;
4428 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4429 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4431 SmallVector<SDValue, 8> MemOpChains;
4432 for (unsigned i = 0; i != NumOps; ++i) {
4433 SDValue Arg = OutVals[i];
4434 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4435 EVT ArgVT = Outs[i].VT;
4436 EVT OrigVT = Outs[i].ArgVT;
4438 // PtrOff will be used to store the current argument to the stack if a
4439 // register cannot be found for it.
4442 // We re-align the argument offset for each argument, except when using the
4443 // fast calling convention, when we need to make sure we do that only when
4444 // we'll actually use a stack slot.
4445 auto ComputePtrOff = [&]() {
4446 /* Respect alignment of argument on the stack. */
4448 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4449 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4451 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4453 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4456 if (CallConv != CallingConv::Fast) {
4459 /* Compute GPR index associated with argument offset. */
4460 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4461 GPR_idx = std::min(GPR_idx, NumGPRs);
4464 // Promote integers to 64-bit values.
4465 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4466 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4467 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4468 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4471 // FIXME memcpy is used way more than necessary. Correctness first.
4472 // Note: "by value" is code for passing a structure by value, not
4474 if (Flags.isByVal()) {
4475 // Note: Size includes alignment padding, so
4476 // struct x { short a; char b; }
4477 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4478 // These are the proper values we need for right-justifying the
4479 // aggregate in a parameter register.
4480 unsigned Size = Flags.getByValSize();
4482 // An empty aggregate parameter takes up no storage and no
4487 if (CallConv == CallingConv::Fast)
4490 // All aggregates smaller than 8 bytes must be passed right-justified.
4491 if (Size==1 || Size==2 || Size==4) {
4492 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4493 if (GPR_idx != NumGPRs) {
4494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4495 MachinePointerInfo(), VT,
4496 false, false, false, 0);
4497 MemOpChains.push_back(Load.getValue(1));
4498 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4500 ArgOffset += PtrByteSize;
4505 if (GPR_idx == NumGPRs && Size < 8) {
4506 SDValue AddPtr = PtrOff;
4507 if (!isLittleEndian) {
4508 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4509 PtrOff.getValueType());
4510 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4512 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4515 ArgOffset += PtrByteSize;
4518 // Copy entire object into memory. There are cases where gcc-generated
4519 // code assumes it is there, even if it could be put entirely into
4520 // registers. (This is not what the doc says.)
4522 // FIXME: The above statement is likely due to a misunderstanding of the
4523 // documents. All arguments must be copied into the parameter area BY
4524 // THE CALLEE in the event that the callee takes the address of any
4525 // formal argument. That has not yet been implemented. However, it is
4526 // reasonable to use the stack area as a staging area for the register
4529 // Skip this for small aggregates, as we will use the same slot for a
4530 // right-justified copy, below.
4532 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4536 // When a register is available, pass a small aggregate right-justified.
4537 if (Size < 8 && GPR_idx != NumGPRs) {
4538 // The easiest way to get this right-justified in a register
4539 // is to copy the structure into the rightmost portion of a
4540 // local variable slot, then load the whole slot into the
4542 // FIXME: The memcpy seems to produce pretty awful code for
4543 // small aggregates, particularly for packed ones.
4544 // FIXME: It would be preferable to use the slot in the
4545 // parameter save area instead of a new local variable.
4546 SDValue AddPtr = PtrOff;
4547 if (!isLittleEndian) {
4548 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4549 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4551 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4555 // Load the slot into the register.
4556 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4557 MachinePointerInfo(),
4558 false, false, false, 0);
4559 MemOpChains.push_back(Load.getValue(1));
4560 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4562 // Done with this argument.
4563 ArgOffset += PtrByteSize;
4567 // For aggregates larger than PtrByteSize, copy the pieces of the
4568 // object that fit into registers from the parameter save area.
4569 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4570 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4571 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4572 if (GPR_idx != NumGPRs) {
4573 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4574 MachinePointerInfo(),
4575 false, false, false, 0);
4576 MemOpChains.push_back(Load.getValue(1));
4577 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4578 ArgOffset += PtrByteSize;
4580 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4587 switch (Arg.getSimpleValueType().SimpleTy) {
4588 default: llvm_unreachable("Unexpected ValueType for argument!");
4592 // These can be scalar arguments or elements of an integer array type
4593 // passed directly. Clang may use those instead of "byval" aggregate
4594 // types to avoid forcing arguments to memory unnecessarily.
4595 if (GPR_idx != NumGPRs) {
4596 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4598 if (CallConv == CallingConv::Fast)
4601 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4602 true, isTailCall, false, MemOpChains,
4603 TailCallArguments, dl);
4604 if (CallConv == CallingConv::Fast)
4605 ArgOffset += PtrByteSize;
4607 if (CallConv != CallingConv::Fast)
4608 ArgOffset += PtrByteSize;
4612 // These can be scalar arguments or elements of a float array type
4613 // passed directly. The latter are used to implement ELFv2 homogenous
4614 // float aggregates.
4616 // Named arguments go into FPRs first, and once they overflow, the
4617 // remaining arguments go into GPRs and then the parameter save area.
4618 // Unnamed arguments for vararg functions always go to GPRs and
4619 // then the parameter save area. For now, put all arguments to vararg
4620 // routines always in both locations (FPR *and* GPR or stack slot).
4621 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4622 bool NeededLoad = false;
4624 // First load the argument into the next available FPR.
4625 if (FPR_idx != NumFPRs)
4626 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4628 // Next, load the argument into GPR or stack slot if needed.
4629 if (!NeedGPROrStack)
4631 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4632 // In the non-vararg case, this can only ever happen in the
4633 // presence of f32 array types, since otherwise we never run
4634 // out of FPRs before running out of GPRs.
4637 // Double values are always passed in a single GPR.
4638 if (Arg.getValueType() != MVT::f32) {
4639 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4641 // Non-array float values are extended and passed in a GPR.
4642 } else if (!Flags.isInConsecutiveRegs()) {
4643 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4644 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4646 // If we have an array of floats, we collect every odd element
4647 // together with its predecessor into one GPR.
4648 } else if (ArgOffset % PtrByteSize != 0) {
4650 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4651 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4652 if (!isLittleEndian)
4654 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4656 // The final element, if even, goes into the first half of a GPR.
4657 } else if (Flags.isInConsecutiveRegsLast()) {
4658 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4659 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4660 if (!isLittleEndian)
4661 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4662 DAG.getConstant(32, MVT::i32));
4664 // Non-final even elements are skipped; they will be handled
4665 // together the with subsequent argument on the next go-around.
4669 if (ArgVal.getNode())
4670 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4672 if (CallConv == CallingConv::Fast)
4675 // Single-precision floating-point values are mapped to the
4676 // second (rightmost) word of the stack doubleword.
4677 if (Arg.getValueType() == MVT::f32 &&
4678 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4679 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4680 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4683 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4684 true, isTailCall, false, MemOpChains,
4685 TailCallArguments, dl);
4689 // When passing an array of floats, the array occupies consecutive
4690 // space in the argument area; only round up to the next doubleword
4691 // at the end of the array. Otherwise, each float takes 8 bytes.
4692 if (CallConv != CallingConv::Fast || NeededLoad) {
4693 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4694 Flags.isInConsecutiveRegs()) ? 4 : 8;
4695 if (Flags.isInConsecutiveRegsLast())
4696 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4706 // These can be scalar arguments or elements of a vector array type
4707 // passed directly. The latter are used to implement ELFv2 homogenous
4708 // vector aggregates.
4710 // For a varargs call, named arguments go into VRs or on the stack as
4711 // usual; unnamed arguments always go to the stack or the corresponding
4712 // GPRs when within range. For now, we always put the value in both
4713 // locations (or even all three).
4715 // We could elide this store in the case where the object fits
4716 // entirely in R registers. Maybe later.
4717 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4718 MachinePointerInfo(), false, false, 0);
4719 MemOpChains.push_back(Store);
4720 if (VR_idx != NumVRs) {
4721 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4722 MachinePointerInfo(),
4723 false, false, false, 0);
4724 MemOpChains.push_back(Load.getValue(1));
4726 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4727 Arg.getSimpleValueType() == MVT::v2i64) ?
4728 VSRH[VR_idx] : VR[VR_idx];
4731 RegsToPass.push_back(std::make_pair(VReg, Load));
4734 for (unsigned i=0; i<16; i+=PtrByteSize) {
4735 if (GPR_idx == NumGPRs)
4737 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4738 DAG.getConstant(i, PtrVT));
4739 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4740 false, false, false, 0);
4741 MemOpChains.push_back(Load.getValue(1));
4742 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4747 // Non-varargs Altivec params go into VRs or on the stack.
4748 if (VR_idx != NumVRs) {
4749 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4750 Arg.getSimpleValueType() == MVT::v2i64) ?
4751 VSRH[VR_idx] : VR[VR_idx];
4754 RegsToPass.push_back(std::make_pair(VReg, Arg));
4756 if (CallConv == CallingConv::Fast)
4759 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4760 true, isTailCall, true, MemOpChains,
4761 TailCallArguments, dl);
4762 if (CallConv == CallingConv::Fast)
4766 if (CallConv != CallingConv::Fast)
4772 assert(NumBytesActuallyUsed == ArgOffset);
4773 (void)NumBytesActuallyUsed;
4775 if (!MemOpChains.empty())
4776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4778 // Check if this is an indirect call (MTCTR/BCTRL).
4779 // See PrepareCall() for more information about calls through function
4780 // pointers in the 64-bit SVR4 ABI.
4781 if (!isTailCall && !IsPatchPoint &&
4782 !isFunctionGlobalAddress(Callee) &&
4783 !isa<ExternalSymbolSDNode>(Callee)) {
4784 // Load r2 into a virtual register and store it to the TOC save area.
4785 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4786 // TOC save area offset.
4787 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4788 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4789 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4790 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4791 MachinePointerInfo::getStack(TOCSaveOffset),
4793 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4794 // This does not mean the MTCTR instruction must use R12; it's easier
4795 // to model this as an extra parameter, so do that.
4796 if (isELFv2ABI && !IsPatchPoint)
4797 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4800 // Build a sequence of copy-to-reg nodes chained together with token chain
4801 // and flag operands which copy the outgoing args into the appropriate regs.
4803 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4804 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4805 RegsToPass[i].second, InFlag);
4806 InFlag = Chain.getValue(1);
4810 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4811 FPOp, true, TailCallArguments);
4813 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4814 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4815 NumBytes, Ins, InVals, CS);
4819 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4820 CallingConv::ID CallConv, bool isVarArg,
4821 bool isTailCall, bool IsPatchPoint,
4822 const SmallVectorImpl<ISD::OutputArg> &Outs,
4823 const SmallVectorImpl<SDValue> &OutVals,
4824 const SmallVectorImpl<ISD::InputArg> &Ins,
4825 SDLoc dl, SelectionDAG &DAG,
4826 SmallVectorImpl<SDValue> &InVals,
4827 ImmutableCallSite *CS) const {
4829 unsigned NumOps = Outs.size();
4831 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4832 bool isPPC64 = PtrVT == MVT::i64;
4833 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4835 MachineFunction &MF = DAG.getMachineFunction();
4837 // Mark this function as potentially containing a function that contains a
4838 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4839 // and restoring the callers stack pointer in this functions epilog. This is
4840 // done because by tail calling the called function might overwrite the value
4841 // in this function's (MF) stack pointer stack slot 0(SP).
4842 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4843 CallConv == CallingConv::Fast)
4844 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4846 // Count how many bytes are to be pushed on the stack, including the linkage
4847 // area, and parameter passing area. We start with 24/48 bytes, which is
4848 // prereserved space for [SP][CR][LR][3 x unused].
4849 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4851 unsigned NumBytes = LinkageSize;
4853 // Add up all the space actually used.
4854 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4855 // they all go in registers, but we must reserve stack space for them for
4856 // possible use by the caller. In varargs or 64-bit calls, parameters are
4857 // assigned stack space in order, with padding so Altivec parameters are
4859 unsigned nAltivecParamsAtEnd = 0;
4860 for (unsigned i = 0; i != NumOps; ++i) {
4861 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4862 EVT ArgVT = Outs[i].VT;
4863 // Varargs Altivec parameters are padded to a 16 byte boundary.
4864 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4865 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4866 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4867 if (!isVarArg && !isPPC64) {
4868 // Non-varargs Altivec parameters go after all the non-Altivec
4869 // parameters; handle those later so we know how much padding we need.
4870 nAltivecParamsAtEnd++;
4873 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4874 NumBytes = ((NumBytes+15)/16)*16;
4876 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4879 // Allow for Altivec parameters at the end, if needed.
4880 if (nAltivecParamsAtEnd) {
4881 NumBytes = ((NumBytes+15)/16)*16;
4882 NumBytes += 16*nAltivecParamsAtEnd;
4885 // The prolog code of the callee may store up to 8 GPR argument registers to
4886 // the stack, allowing va_start to index over them in memory if its varargs.
4887 // Because we cannot tell if this is needed on the caller side, we have to
4888 // conservatively assume that it is needed. As such, make sure we have at
4889 // least enough stack space for the caller to store the 8 GPRs.
4890 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4892 // Tail call needs the stack to be aligned.
4893 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4894 CallConv == CallingConv::Fast)
4895 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4897 // Calculate by how many bytes the stack has to be adjusted in case of tail
4898 // call optimization.
4899 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4901 // To protect arguments on the stack from being clobbered in a tail call,
4902 // force all the loads to happen before doing any other lowering.
4904 Chain = DAG.getStackArgumentTokenFactor(Chain);
4906 // Adjust the stack pointer for the new arguments...
4907 // These operations are automatically eliminated by the prolog/epilog pass
4908 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4910 SDValue CallSeqStart = Chain;
4912 // Load the return address and frame pointer so it can be move somewhere else
4915 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4918 // Set up a copy of the stack pointer for use loading and storing any
4919 // arguments that may not fit in the registers available for argument
4923 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4925 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4927 // Figure out which arguments are going to go in registers, and which in
4928 // memory. Also, if this is a vararg function, floating point operations
4929 // must be stored to our stack, and loaded into integer regs as well, if
4930 // any integer regs are available for argument passing.
4931 unsigned ArgOffset = LinkageSize;
4932 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4934 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4935 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4936 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4938 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4939 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4940 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4942 static const MCPhysReg *FPR = GetFPR();
4944 static const MCPhysReg VR[] = {
4945 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4946 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4948 const unsigned NumGPRs = array_lengthof(GPR_32);
4949 const unsigned NumFPRs = 13;
4950 const unsigned NumVRs = array_lengthof(VR);
4952 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4954 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4955 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4957 SmallVector<SDValue, 8> MemOpChains;
4958 for (unsigned i = 0; i != NumOps; ++i) {
4959 SDValue Arg = OutVals[i];
4960 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4962 // PtrOff will be used to store the current argument to the stack if a
4963 // register cannot be found for it.
4966 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4968 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4970 // On PPC64, promote integers to 64-bit values.
4971 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4972 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4973 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4974 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4977 // FIXME memcpy is used way more than necessary. Correctness first.
4978 // Note: "by value" is code for passing a structure by value, not
4980 if (Flags.isByVal()) {
4981 unsigned Size = Flags.getByValSize();
4982 // Very small objects are passed right-justified. Everything else is
4983 // passed left-justified.
4984 if (Size==1 || Size==2) {
4985 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4986 if (GPR_idx != NumGPRs) {
4987 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4988 MachinePointerInfo(), VT,
4989 false, false, false, 0);
4990 MemOpChains.push_back(Load.getValue(1));
4991 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4993 ArgOffset += PtrByteSize;
4995 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4996 PtrOff.getValueType());
4997 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4998 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5001 ArgOffset += PtrByteSize;
5005 // Copy entire object into memory. There are cases where gcc-generated
5006 // code assumes it is there, even if it could be put entirely into
5007 // registers. (This is not what the doc says.)
5008 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5012 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5013 // copy the pieces of the object that fit into registers from the
5014 // parameter save area.
5015 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5016 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5017 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5018 if (GPR_idx != NumGPRs) {
5019 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5020 MachinePointerInfo(),
5021 false, false, false, 0);
5022 MemOpChains.push_back(Load.getValue(1));
5023 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5024 ArgOffset += PtrByteSize;
5026 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5033 switch (Arg.getSimpleValueType().SimpleTy) {
5034 default: llvm_unreachable("Unexpected ValueType for argument!");
5038 if (GPR_idx != NumGPRs) {
5039 if (Arg.getValueType() == MVT::i1)
5040 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5042 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5044 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5045 isPPC64, isTailCall, false, MemOpChains,
5046 TailCallArguments, dl);
5048 ArgOffset += PtrByteSize;
5052 if (FPR_idx != NumFPRs) {
5053 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5056 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5057 MachinePointerInfo(), false, false, 0);
5058 MemOpChains.push_back(Store);
5060 // Float varargs are always shadowed in available integer registers
5061 if (GPR_idx != NumGPRs) {
5062 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5063 MachinePointerInfo(), false, false,
5065 MemOpChains.push_back(Load.getValue(1));
5066 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5068 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5069 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5070 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5071 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5072 MachinePointerInfo(),
5073 false, false, false, 0);
5074 MemOpChains.push_back(Load.getValue(1));
5075 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5078 // If we have any FPRs remaining, we may also have GPRs remaining.
5079 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5081 if (GPR_idx != NumGPRs)
5083 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5084 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5088 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5089 isPPC64, isTailCall, false, MemOpChains,
5090 TailCallArguments, dl);
5094 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5101 // These go aligned on the stack, or in the corresponding R registers
5102 // when within range. The Darwin PPC ABI doc claims they also go in
5103 // V registers; in fact gcc does this only for arguments that are
5104 // prototyped, not for those that match the ... We do it for all
5105 // arguments, seems to work.
5106 while (ArgOffset % 16 !=0) {
5107 ArgOffset += PtrByteSize;
5108 if (GPR_idx != NumGPRs)
5111 // We could elide this store in the case where the object fits
5112 // entirely in R registers. Maybe later.
5113 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5114 DAG.getConstant(ArgOffset, PtrVT));
5115 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5116 MachinePointerInfo(), false, false, 0);
5117 MemOpChains.push_back(Store);
5118 if (VR_idx != NumVRs) {
5119 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5120 MachinePointerInfo(),
5121 false, false, false, 0);
5122 MemOpChains.push_back(Load.getValue(1));
5123 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5126 for (unsigned i=0; i<16; i+=PtrByteSize) {
5127 if (GPR_idx == NumGPRs)
5129 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5130 DAG.getConstant(i, PtrVT));
5131 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5132 false, false, false, 0);
5133 MemOpChains.push_back(Load.getValue(1));
5134 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5139 // Non-varargs Altivec params generally go in registers, but have
5140 // stack space allocated at the end.
5141 if (VR_idx != NumVRs) {
5142 // Doesn't have GPR space allocated.
5143 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5144 } else if (nAltivecParamsAtEnd==0) {
5145 // We are emitting Altivec params in order.
5146 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5147 isPPC64, isTailCall, true, MemOpChains,
5148 TailCallArguments, dl);
5154 // If all Altivec parameters fit in registers, as they usually do,
5155 // they get stack space following the non-Altivec parameters. We
5156 // don't track this here because nobody below needs it.
5157 // If there are more Altivec parameters than fit in registers emit
5159 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5161 // Offset is aligned; skip 1st 12 params which go in V registers.
5162 ArgOffset = ((ArgOffset+15)/16)*16;
5164 for (unsigned i = 0; i != NumOps; ++i) {
5165 SDValue Arg = OutVals[i];
5166 EVT ArgType = Outs[i].VT;
5167 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5168 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5171 // We are emitting Altivec params in order.
5172 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5173 isPPC64, isTailCall, true, MemOpChains,
5174 TailCallArguments, dl);
5181 if (!MemOpChains.empty())
5182 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5184 // On Darwin, R12 must contain the address of an indirect callee. This does
5185 // not mean the MTCTR instruction must use R12; it's easier to model this as
5186 // an extra parameter, so do that.
5188 !isFunctionGlobalAddress(Callee) &&
5189 !isa<ExternalSymbolSDNode>(Callee) &&
5190 !isBLACompatibleAddress(Callee, DAG))
5191 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5192 PPC::R12), Callee));
5194 // Build a sequence of copy-to-reg nodes chained together with token chain
5195 // and flag operands which copy the outgoing args into the appropriate regs.
5197 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5198 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5199 RegsToPass[i].second, InFlag);
5200 InFlag = Chain.getValue(1);
5204 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5205 FPOp, true, TailCallArguments);
5207 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5208 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5209 NumBytes, Ins, InVals, CS);
5213 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5214 MachineFunction &MF, bool isVarArg,
5215 const SmallVectorImpl<ISD::OutputArg> &Outs,
5216 LLVMContext &Context) const {
5217 SmallVector<CCValAssign, 16> RVLocs;
5218 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5219 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5223 PPCTargetLowering::LowerReturn(SDValue Chain,
5224 CallingConv::ID CallConv, bool isVarArg,
5225 const SmallVectorImpl<ISD::OutputArg> &Outs,
5226 const SmallVectorImpl<SDValue> &OutVals,
5227 SDLoc dl, SelectionDAG &DAG) const {
5229 SmallVector<CCValAssign, 16> RVLocs;
5230 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5232 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5235 SmallVector<SDValue, 4> RetOps(1, Chain);
5237 // Copy the result values into the output registers.
5238 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5239 CCValAssign &VA = RVLocs[i];
5240 assert(VA.isRegLoc() && "Can only return in registers!");
5242 SDValue Arg = OutVals[i];
5244 switch (VA.getLocInfo()) {
5245 default: llvm_unreachable("Unknown loc info!");
5246 case CCValAssign::Full: break;
5247 case CCValAssign::AExt:
5248 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5250 case CCValAssign::ZExt:
5251 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5253 case CCValAssign::SExt:
5254 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5258 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5259 Flag = Chain.getValue(1);
5260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5263 RetOps[0] = Chain; // Update chain.
5265 // Add the flag if we have it.
5267 RetOps.push_back(Flag);
5269 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5272 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5273 const PPCSubtarget &Subtarget) const {
5274 // When we pop the dynamic allocation we need to restore the SP link.
5277 // Get the corect type for pointers.
5278 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5280 // Construct the stack pointer operand.
5281 bool isPPC64 = Subtarget.isPPC64();
5282 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5283 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5285 // Get the operands for the STACKRESTORE.
5286 SDValue Chain = Op.getOperand(0);
5287 SDValue SaveSP = Op.getOperand(1);
5289 // Load the old link SP.
5290 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5291 MachinePointerInfo(),
5292 false, false, false, 0);
5294 // Restore the stack pointer.
5295 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5297 // Store the old link SP.
5298 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5305 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5306 MachineFunction &MF = DAG.getMachineFunction();
5307 bool isPPC64 = Subtarget.isPPC64();
5308 bool isDarwinABI = Subtarget.isDarwinABI();
5309 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5311 // Get current frame pointer save index. The users of this index will be
5312 // primarily DYNALLOC instructions.
5313 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5314 int RASI = FI->getReturnAddrSaveIndex();
5316 // If the frame pointer save index hasn't been defined yet.
5318 // Find out what the fix offset of the frame pointer save area.
5319 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5320 // Allocate the frame index for frame pointer save area.
5321 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5323 FI->setReturnAddrSaveIndex(RASI);
5325 return DAG.getFrameIndex(RASI, PtrVT);
5329 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5330 MachineFunction &MF = DAG.getMachineFunction();
5331 bool isPPC64 = Subtarget.isPPC64();
5332 bool isDarwinABI = Subtarget.isDarwinABI();
5333 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5335 // Get current frame pointer save index. The users of this index will be
5336 // primarily DYNALLOC instructions.
5337 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5338 int FPSI = FI->getFramePointerSaveIndex();
5340 // If the frame pointer save index hasn't been defined yet.
5342 // Find out what the fix offset of the frame pointer save area.
5343 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5346 // Allocate the frame index for frame pointer save area.
5347 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5349 FI->setFramePointerSaveIndex(FPSI);
5351 return DAG.getFrameIndex(FPSI, PtrVT);
5354 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5356 const PPCSubtarget &Subtarget) const {
5358 SDValue Chain = Op.getOperand(0);
5359 SDValue Size = Op.getOperand(1);
5362 // Get the corect type for pointers.
5363 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5365 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5366 DAG.getConstant(0, PtrVT), Size);
5367 // Construct a node for the frame pointer save index.
5368 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5369 // Build a DYNALLOC node.
5370 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5371 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5372 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5375 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5376 SelectionDAG &DAG) const {
5378 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5379 DAG.getVTList(MVT::i32, MVT::Other),
5380 Op.getOperand(0), Op.getOperand(1));
5383 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5384 SelectionDAG &DAG) const {
5386 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5387 Op.getOperand(0), Op.getOperand(1));
5390 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5391 assert(Op.getValueType() == MVT::i1 &&
5392 "Custom lowering only for i1 loads");
5394 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5397 LoadSDNode *LD = cast<LoadSDNode>(Op);
5399 SDValue Chain = LD->getChain();
5400 SDValue BasePtr = LD->getBasePtr();
5401 MachineMemOperand *MMO = LD->getMemOperand();
5403 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5404 BasePtr, MVT::i8, MMO);
5405 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5407 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5408 return DAG.getMergeValues(Ops, dl);
5411 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5412 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5413 "Custom lowering only for i1 stores");
5415 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5418 StoreSDNode *ST = cast<StoreSDNode>(Op);
5420 SDValue Chain = ST->getChain();
5421 SDValue BasePtr = ST->getBasePtr();
5422 SDValue Value = ST->getValue();
5423 MachineMemOperand *MMO = ST->getMemOperand();
5425 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5426 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5429 // FIXME: Remove this once the ANDI glue bug is fixed:
5430 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5431 assert(Op.getValueType() == MVT::i1 &&
5432 "Custom lowering only for i1 results");
5435 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5439 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5441 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5442 // Not FP? Not a fsel.
5443 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5444 !Op.getOperand(2).getValueType().isFloatingPoint())
5447 // We might be able to do better than this under some circumstances, but in
5448 // general, fsel-based lowering of select is a finite-math-only optimization.
5449 // For more information, see section F.3 of the 2.06 ISA specification.
5450 if (!DAG.getTarget().Options.NoInfsFPMath ||
5451 !DAG.getTarget().Options.NoNaNsFPMath)
5454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5456 EVT ResVT = Op.getValueType();
5457 EVT CmpVT = Op.getOperand(0).getValueType();
5458 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5459 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5462 // If the RHS of the comparison is a 0.0, we don't need to do the
5463 // subtraction at all.
5465 if (isFloatingPointZero(RHS))
5467 default: break; // SETUO etc aren't handled by fsel.
5471 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5472 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5473 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5474 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5475 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5476 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5477 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5480 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5483 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5484 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5485 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5488 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5491 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5492 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5493 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5494 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5499 default: break; // SETUO etc aren't handled by fsel.
5503 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5504 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5505 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5506 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5507 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5508 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5509 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5510 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5513 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5514 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5515 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5516 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5519 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5520 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5521 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5522 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5525 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5526 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5527 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5528 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5531 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5532 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5533 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5534 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5539 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5542 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5543 SDValue Src = Op.getOperand(0);
5544 if (Src.getValueType() == MVT::f32)
5545 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5548 switch (Op.getSimpleValueType().SimpleTy) {
5549 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5551 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5552 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5557 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5558 "i64 FP_TO_UINT is supported only with FPCVT");
5559 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5565 // Convert the FP value to an int value through memory.
5566 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5567 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5568 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5569 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5570 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5572 // Emit a store to the stack slot.
5575 MachineFunction &MF = DAG.getMachineFunction();
5576 MachineMemOperand *MMO =
5577 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5578 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5579 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5580 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5582 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5583 MPI, false, false, 0);
5585 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5587 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5588 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5589 DAG.getConstant(4, FIPtr.getValueType()));
5590 MPI = MPI.getWithOffset(4);
5598 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5601 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5603 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5604 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5608 // We're trying to insert a regular store, S, and then a load, L. If the
5609 // incoming value, O, is a load, we might just be able to have our load use the
5610 // address used by O. However, we don't know if anything else will store to
5611 // that address before we can load from it. To prevent this situation, we need
5612 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5613 // the same chain operand as O, we create a token factor from the chain results
5614 // of O and L, and we replace all uses of O's chain result with that token
5615 // factor (see spliceIntoChain below for this last part).
5616 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5619 ISD::LoadExtType ET) const {
5621 if (ET == ISD::NON_EXTLOAD &&
5622 (Op.getOpcode() == ISD::FP_TO_UINT ||
5623 Op.getOpcode() == ISD::FP_TO_SINT) &&
5624 isOperationLegalOrCustom(Op.getOpcode(),
5625 Op.getOperand(0).getValueType())) {
5627 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5631 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5632 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5633 LD->isNonTemporal())
5635 if (LD->getMemoryVT() != MemVT)
5638 RLI.Ptr = LD->getBasePtr();
5639 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5640 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5641 "Non-pre-inc AM on PPC?");
5642 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5646 RLI.Chain = LD->getChain();
5647 RLI.MPI = LD->getPointerInfo();
5648 RLI.IsInvariant = LD->isInvariant();
5649 RLI.Alignment = LD->getAlignment();
5650 RLI.AAInfo = LD->getAAInfo();
5651 RLI.Ranges = LD->getRanges();
5653 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5657 // Given the head of the old chain, ResChain, insert a token factor containing
5658 // it and NewResChain, and make users of ResChain now be users of that token
5660 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5661 SDValue NewResChain,
5662 SelectionDAG &DAG) const {
5666 SDLoc dl(NewResChain);
5668 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5669 NewResChain, DAG.getUNDEF(MVT::Other));
5670 assert(TF.getNode() != NewResChain.getNode() &&
5671 "A new TF really is required here");
5673 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5674 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5677 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5678 SelectionDAG &DAG) const {
5680 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5681 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5684 if (Op.getOperand(0).getValueType() == MVT::i1)
5685 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5686 DAG.getConstantFP(1.0, Op.getValueType()),
5687 DAG.getConstantFP(0.0, Op.getValueType()));
5689 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5690 "UINT_TO_FP is supported only with FPCVT");
5692 // If we have FCFIDS, then use it when converting to single-precision.
5693 // Otherwise, convert to double-precision and then round.
5694 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5695 (Op.getOpcode() == ISD::UINT_TO_FP ?
5696 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5697 (Op.getOpcode() == ISD::UINT_TO_FP ?
5698 PPCISD::FCFIDU : PPCISD::FCFID);
5699 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5700 MVT::f32 : MVT::f64;
5702 if (Op.getOperand(0).getValueType() == MVT::i64) {
5703 SDValue SINT = Op.getOperand(0);
5704 // When converting to single-precision, we actually need to convert
5705 // to double-precision first and then round to single-precision.
5706 // To avoid double-rounding effects during that operation, we have
5707 // to prepare the input operand. Bits that might be truncated when
5708 // converting to double-precision are replaced by a bit that won't
5709 // be lost at this stage, but is below the single-precision rounding
5712 // However, if -enable-unsafe-fp-math is in effect, accept double
5713 // rounding to avoid the extra overhead.
5714 if (Op.getValueType() == MVT::f32 &&
5715 !Subtarget.hasFPCVT() &&
5716 !DAG.getTarget().Options.UnsafeFPMath) {
5718 // Twiddle input to make sure the low 11 bits are zero. (If this
5719 // is the case, we are guaranteed the value will fit into the 53 bit
5720 // mantissa of an IEEE double-precision value without rounding.)
5721 // If any of those low 11 bits were not zero originally, make sure
5722 // bit 12 (value 2048) is set instead, so that the final rounding
5723 // to single-precision gets the correct result.
5724 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5725 SINT, DAG.getConstant(2047, MVT::i64));
5726 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5727 Round, DAG.getConstant(2047, MVT::i64));
5728 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5729 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5730 Round, DAG.getConstant(-2048, MVT::i64));
5732 // However, we cannot use that value unconditionally: if the magnitude
5733 // of the input value is small, the bit-twiddling we did above might
5734 // end up visibly changing the output. Fortunately, in that case, we
5735 // don't need to twiddle bits since the original input will convert
5736 // exactly to double-precision floating-point already. Therefore,
5737 // construct a conditional to use the original value if the top 11
5738 // bits are all sign-bit copies, and use the rounded value computed
5740 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5741 SINT, DAG.getConstant(53, MVT::i32));
5742 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5743 Cond, DAG.getConstant(1, MVT::i64));
5744 Cond = DAG.getSetCC(dl, MVT::i32,
5745 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5747 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5753 MachineFunction &MF = DAG.getMachineFunction();
5754 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5755 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5756 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5758 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5759 } else if (Subtarget.hasLFIWAX() &&
5760 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5761 MachineMemOperand *MMO =
5762 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5763 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5764 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5765 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5766 DAG.getVTList(MVT::f64, MVT::Other),
5767 Ops, MVT::i32, MMO);
5768 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5769 } else if (Subtarget.hasFPCVT() &&
5770 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5771 MachineMemOperand *MMO =
5772 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5773 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5774 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5775 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5776 DAG.getVTList(MVT::f64, MVT::Other),
5777 Ops, MVT::i32, MMO);
5778 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5779 } else if (((Subtarget.hasLFIWAX() &&
5780 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5781 (Subtarget.hasFPCVT() &&
5782 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5783 SINT.getOperand(0).getValueType() == MVT::i32) {
5784 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5785 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5787 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5788 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5791 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5792 MachinePointerInfo::getFixedStack(FrameIdx),
5795 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5796 "Expected an i32 store");
5800 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5803 MachineMemOperand *MMO =
5804 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5805 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5806 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5807 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5808 PPCISD::LFIWZX : PPCISD::LFIWAX,
5809 dl, DAG.getVTList(MVT::f64, MVT::Other),
5810 Ops, MVT::i32, MMO);
5812 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5814 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5816 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5817 FP = DAG.getNode(ISD::FP_ROUND, dl,
5818 MVT::f32, FP, DAG.getIntPtrConstant(0));
5822 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5823 "Unhandled INT_TO_FP type in custom expander!");
5824 // Since we only generate this in 64-bit mode, we can take advantage of
5825 // 64-bit registers. In particular, sign extend the input value into the
5826 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5827 // then lfd it and fcfid it.
5828 MachineFunction &MF = DAG.getMachineFunction();
5829 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5830 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5833 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5836 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5838 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5839 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5841 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5842 MachinePointerInfo::getFixedStack(FrameIdx),
5845 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5846 "Expected an i32 store");
5850 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5854 MachineMemOperand *MMO =
5855 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5856 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5857 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5858 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5859 PPCISD::LFIWZX : PPCISD::LFIWAX,
5860 dl, DAG.getVTList(MVT::f64, MVT::Other),
5861 Ops, MVT::i32, MMO);
5863 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5865 assert(Subtarget.isPPC64() &&
5866 "i32->FP without LFIWAX supported only on PPC64");
5868 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5869 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5871 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5874 // STD the extended value into the stack slot.
5875 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5876 MachinePointerInfo::getFixedStack(FrameIdx),
5879 // Load the value as a double.
5880 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5881 MachinePointerInfo::getFixedStack(FrameIdx),
5882 false, false, false, 0);
5885 // FCFID it and return it.
5886 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5887 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5888 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5892 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5893 SelectionDAG &DAG) const {
5896 The rounding mode is in bits 30:31 of FPSR, and has the following
5903 FLT_ROUNDS, on the other hand, expects the following:
5910 To perform the conversion, we do:
5911 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5914 MachineFunction &MF = DAG.getMachineFunction();
5915 EVT VT = Op.getValueType();
5916 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5918 // Save FP Control Word to register
5920 MVT::f64, // return register
5921 MVT::Glue // unused in this context
5923 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5925 // Save FP register to stack slot
5926 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5927 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5928 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5929 StackSlot, MachinePointerInfo(), false, false,0);
5931 // Load FP Control Word from low 32 bits of stack slot.
5932 SDValue Four = DAG.getConstant(4, PtrVT);
5933 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5934 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5935 false, false, false, 0);
5937 // Transform as necessary
5939 DAG.getNode(ISD::AND, dl, MVT::i32,
5940 CWD, DAG.getConstant(3, MVT::i32));
5942 DAG.getNode(ISD::SRL, dl, MVT::i32,
5943 DAG.getNode(ISD::AND, dl, MVT::i32,
5944 DAG.getNode(ISD::XOR, dl, MVT::i32,
5945 CWD, DAG.getConstant(3, MVT::i32)),
5946 DAG.getConstant(3, MVT::i32)),
5947 DAG.getConstant(1, MVT::i32));
5950 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5952 return DAG.getNode((VT.getSizeInBits() < 16 ?
5953 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5956 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5957 EVT VT = Op.getValueType();
5958 unsigned BitWidth = VT.getSizeInBits();
5960 assert(Op.getNumOperands() == 3 &&
5961 VT == Op.getOperand(1).getValueType() &&
5964 // Expand into a bunch of logical ops. Note that these ops
5965 // depend on the PPC behavior for oversized shift amounts.
5966 SDValue Lo = Op.getOperand(0);
5967 SDValue Hi = Op.getOperand(1);
5968 SDValue Amt = Op.getOperand(2);
5969 EVT AmtVT = Amt.getValueType();
5971 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5972 DAG.getConstant(BitWidth, AmtVT), Amt);
5973 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5974 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5975 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5976 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5977 DAG.getConstant(-BitWidth, AmtVT));
5978 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5979 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5980 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5981 SDValue OutOps[] = { OutLo, OutHi };
5982 return DAG.getMergeValues(OutOps, dl);
5985 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5986 EVT VT = Op.getValueType();
5988 unsigned BitWidth = VT.getSizeInBits();
5989 assert(Op.getNumOperands() == 3 &&
5990 VT == Op.getOperand(1).getValueType() &&
5993 // Expand into a bunch of logical ops. Note that these ops
5994 // depend on the PPC behavior for oversized shift amounts.
5995 SDValue Lo = Op.getOperand(0);
5996 SDValue Hi = Op.getOperand(1);
5997 SDValue Amt = Op.getOperand(2);
5998 EVT AmtVT = Amt.getValueType();
6000 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6001 DAG.getConstant(BitWidth, AmtVT), Amt);
6002 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6003 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6004 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6005 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6006 DAG.getConstant(-BitWidth, AmtVT));
6007 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6008 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6009 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6010 SDValue OutOps[] = { OutLo, OutHi };
6011 return DAG.getMergeValues(OutOps, dl);
6014 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6016 EVT VT = Op.getValueType();
6017 unsigned BitWidth = VT.getSizeInBits();
6018 assert(Op.getNumOperands() == 3 &&
6019 VT == Op.getOperand(1).getValueType() &&
6022 // Expand into a bunch of logical ops, followed by a select_cc.
6023 SDValue Lo = Op.getOperand(0);
6024 SDValue Hi = Op.getOperand(1);
6025 SDValue Amt = Op.getOperand(2);
6026 EVT AmtVT = Amt.getValueType();
6028 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6029 DAG.getConstant(BitWidth, AmtVT), Amt);
6030 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6031 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6032 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6033 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6034 DAG.getConstant(-BitWidth, AmtVT));
6035 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6036 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6037 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6038 Tmp4, Tmp6, ISD::SETLE);
6039 SDValue OutOps[] = { OutLo, OutHi };
6040 return DAG.getMergeValues(OutOps, dl);
6043 //===----------------------------------------------------------------------===//
6044 // Vector related lowering.
6047 /// BuildSplatI - Build a canonical splati of Val with an element size of
6048 /// SplatSize. Cast the result to VT.
6049 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6050 SelectionDAG &DAG, SDLoc dl) {
6051 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6053 static const EVT VTys[] = { // canonical VT to use for each size.
6054 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6057 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6059 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6063 EVT CanonicalVT = VTys[SplatSize-1];
6065 // Build a canonical splat for this value.
6066 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6067 SmallVector<SDValue, 8> Ops;
6068 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6069 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6070 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6073 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6074 /// specified intrinsic ID.
6075 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6076 SelectionDAG &DAG, SDLoc dl,
6077 EVT DestVT = MVT::Other) {
6078 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6079 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6080 DAG.getConstant(IID, MVT::i32), Op);
6083 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6084 /// specified intrinsic ID.
6085 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6086 SelectionDAG &DAG, SDLoc dl,
6087 EVT DestVT = MVT::Other) {
6088 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6089 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6090 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6093 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6094 /// specified intrinsic ID.
6095 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6096 SDValue Op2, SelectionDAG &DAG,
6097 SDLoc dl, EVT DestVT = MVT::Other) {
6098 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6099 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6100 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6104 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6105 /// amount. The result has the specified value type.
6106 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6107 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6108 // Force LHS/RHS to be the right type.
6109 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6110 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6113 for (unsigned i = 0; i != 16; ++i)
6115 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6116 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6119 // If this is a case we can't handle, return null and let the default
6120 // expansion code take care of it. If we CAN select this case, and if it
6121 // selects to a single instruction, return Op. Otherwise, if we can codegen
6122 // this case more efficiently than a constant pool load, lower it to the
6123 // sequence of ops that should be used.
6124 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6125 SelectionDAG &DAG) const {
6127 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6128 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6130 // Check if this is a splat of a constant value.
6131 APInt APSplatBits, APSplatUndef;
6132 unsigned SplatBitSize;
6134 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6135 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6138 unsigned SplatBits = APSplatBits.getZExtValue();
6139 unsigned SplatUndef = APSplatUndef.getZExtValue();
6140 unsigned SplatSize = SplatBitSize / 8;
6142 // First, handle single instruction cases.
6145 if (SplatBits == 0) {
6146 // Canonicalize all zero vectors to be v4i32.
6147 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6148 SDValue Z = DAG.getConstant(0, MVT::i32);
6149 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6150 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6155 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6156 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6158 if (SextVal >= -16 && SextVal <= 15)
6159 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6162 // Two instruction sequences.
6164 // If this value is in the range [-32,30] and is even, use:
6165 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6166 // If this value is in the range [17,31] and is odd, use:
6167 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6168 // If this value is in the range [-31,-17] and is odd, use:
6169 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6170 // Note the last two are three-instruction sequences.
6171 if (SextVal >= -32 && SextVal <= 31) {
6172 // To avoid having these optimizations undone by constant folding,
6173 // we convert to a pseudo that will be expanded later into one of
6175 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6176 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6177 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6178 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6179 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6180 if (VT == Op.getValueType())
6183 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6186 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6187 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6189 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6190 // Make -1 and vspltisw -1:
6191 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6193 // Make the VSLW intrinsic, computing 0x8000_0000.
6194 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6197 // xor by OnesV to invert it.
6198 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6199 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6202 // The remaining cases assume either big endian element order or
6203 // a splat-size that equates to the element size of the vector
6204 // to be built. An example that doesn't work for little endian is
6205 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6206 // and a vector element size of 16 bits. The code below will
6207 // produce the vector in big endian element order, which for little
6208 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6210 // For now, just avoid these optimizations in that case.
6211 // FIXME: Develop correct optimizations for LE with mismatched
6212 // splat and element sizes.
6214 if (Subtarget.isLittleEndian() &&
6215 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6218 // Check to see if this is a wide variety of vsplti*, binop self cases.
6219 static const signed char SplatCsts[] = {
6220 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6221 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6224 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6225 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6226 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6227 int i = SplatCsts[idx];
6229 // Figure out what shift amount will be used by altivec if shifted by i in
6231 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6233 // vsplti + shl self.
6234 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6235 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6236 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6237 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6238 Intrinsic::ppc_altivec_vslw
6240 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6241 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6244 // vsplti + srl self.
6245 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6246 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6247 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6248 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6249 Intrinsic::ppc_altivec_vsrw
6251 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6252 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6255 // vsplti + sra self.
6256 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6257 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6258 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6259 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6260 Intrinsic::ppc_altivec_vsraw
6262 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6263 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6266 // vsplti + rol self.
6267 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6268 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6269 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6270 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6271 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6272 Intrinsic::ppc_altivec_vrlw
6274 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6275 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6278 // t = vsplti c, result = vsldoi t, t, 1
6279 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6280 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6281 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6283 // t = vsplti c, result = vsldoi t, t, 2
6284 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6285 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6286 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6288 // t = vsplti c, result = vsldoi t, t, 3
6289 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6290 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6291 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6298 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6299 /// the specified operations to build the shuffle.
6300 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6301 SDValue RHS, SelectionDAG &DAG,
6303 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6304 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6305 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6308 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6320 if (OpNum == OP_COPY) {
6321 if (LHSID == (1*9+2)*9+3) return LHS;
6322 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6326 SDValue OpLHS, OpRHS;
6327 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6328 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6332 default: llvm_unreachable("Unknown i32 permute!");
6334 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6335 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6336 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6337 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6340 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6341 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6342 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6343 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6346 for (unsigned i = 0; i != 16; ++i)
6347 ShufIdxs[i] = (i&3)+0;
6350 for (unsigned i = 0; i != 16; ++i)
6351 ShufIdxs[i] = (i&3)+4;
6354 for (unsigned i = 0; i != 16; ++i)
6355 ShufIdxs[i] = (i&3)+8;
6358 for (unsigned i = 0; i != 16; ++i)
6359 ShufIdxs[i] = (i&3)+12;
6362 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6364 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6366 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6368 EVT VT = OpLHS.getValueType();
6369 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6370 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6371 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6372 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6375 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6376 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6377 /// return the code it can be lowered into. Worst case, it can always be
6378 /// lowered into a vperm.
6379 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6380 SelectionDAG &DAG) const {
6382 SDValue V1 = Op.getOperand(0);
6383 SDValue V2 = Op.getOperand(1);
6384 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6385 EVT VT = Op.getValueType();
6386 bool isLittleEndian = Subtarget.isLittleEndian();
6388 // Cases that are handled by instructions that take permute immediates
6389 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6390 // selected by the instruction selector.
6391 if (V2.getOpcode() == ISD::UNDEF) {
6392 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6393 PPC::isSplatShuffleMask(SVOp, 2) ||
6394 PPC::isSplatShuffleMask(SVOp, 4) ||
6395 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6396 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6397 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6398 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6399 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6400 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6401 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6402 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6403 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6408 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6409 // and produce a fixed permutation. If any of these match, do not lower to
6411 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6412 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6413 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6414 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6415 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6416 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6417 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6418 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6419 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6420 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6423 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6424 // perfect shuffle table to emit an optimal matching sequence.
6425 ArrayRef<int> PermMask = SVOp->getMask();
6427 unsigned PFIndexes[4];
6428 bool isFourElementShuffle = true;
6429 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6430 unsigned EltNo = 8; // Start out undef.
6431 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6432 if (PermMask[i*4+j] < 0)
6433 continue; // Undef, ignore it.
6435 unsigned ByteSource = PermMask[i*4+j];
6436 if ((ByteSource & 3) != j) {
6437 isFourElementShuffle = false;
6442 EltNo = ByteSource/4;
6443 } else if (EltNo != ByteSource/4) {
6444 isFourElementShuffle = false;
6448 PFIndexes[i] = EltNo;
6451 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6452 // perfect shuffle vector to determine if it is cost effective to do this as
6453 // discrete instructions, or whether we should use a vperm.
6454 // For now, we skip this for little endian until such time as we have a
6455 // little-endian perfect shuffle table.
6456 if (isFourElementShuffle && !isLittleEndian) {
6457 // Compute the index in the perfect shuffle table.
6458 unsigned PFTableIndex =
6459 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6461 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6462 unsigned Cost = (PFEntry >> 30);
6464 // Determining when to avoid vperm is tricky. Many things affect the cost
6465 // of vperm, particularly how many times the perm mask needs to be computed.
6466 // For example, if the perm mask can be hoisted out of a loop or is already
6467 // used (perhaps because there are multiple permutes with the same shuffle
6468 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6469 // the loop requires an extra register.
6471 // As a compromise, we only emit discrete instructions if the shuffle can be
6472 // generated in 3 or fewer operations. When we have loop information
6473 // available, if this block is within a loop, we should avoid using vperm
6474 // for 3-operation perms and use a constant pool load instead.
6476 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6479 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6480 // vector that will get spilled to the constant pool.
6481 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6483 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6484 // that it is in input element units, not in bytes. Convert now.
6486 // For little endian, the order of the input vectors is reversed, and
6487 // the permutation mask is complemented with respect to 31. This is
6488 // necessary to produce proper semantics with the big-endian-biased vperm
6490 EVT EltVT = V1.getValueType().getVectorElementType();
6491 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6493 SmallVector<SDValue, 16> ResultMask;
6494 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6495 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6497 for (unsigned j = 0; j != BytesPerElement; ++j)
6499 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6502 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6506 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6509 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6512 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6516 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6517 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6518 /// information about the intrinsic.
6519 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6521 unsigned IntrinsicID =
6522 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6525 switch (IntrinsicID) {
6526 default: return false;
6527 // Comparison predicates.
6528 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6529 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6530 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6531 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6532 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6533 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6534 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6535 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6536 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6537 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6538 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6539 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6540 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6542 // Normal Comparisons.
6543 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6544 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6545 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6546 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6547 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6548 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6549 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6550 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6551 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6552 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6553 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6554 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6555 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6560 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6561 /// lower, do it, otherwise return null.
6562 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6563 SelectionDAG &DAG) const {
6564 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6565 // opcode number of the comparison.
6569 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6570 return SDValue(); // Don't custom lower most intrinsics.
6572 // If this is a non-dot comparison, make the VCMP node and we are done.
6574 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6575 Op.getOperand(1), Op.getOperand(2),
6576 DAG.getConstant(CompareOpc, MVT::i32));
6577 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6580 // Create the PPCISD altivec 'dot' comparison node.
6582 Op.getOperand(2), // LHS
6583 Op.getOperand(3), // RHS
6584 DAG.getConstant(CompareOpc, MVT::i32)
6586 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6587 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6589 // Now that we have the comparison, emit a copy from the CR to a GPR.
6590 // This is flagged to the above dot comparison.
6591 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6592 DAG.getRegister(PPC::CR6, MVT::i32),
6593 CompNode.getValue(1));
6595 // Unpack the result based on how the target uses it.
6596 unsigned BitNo; // Bit # of CR6.
6597 bool InvertBit; // Invert result?
6598 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6599 default: // Can't happen, don't crash on invalid number though.
6600 case 0: // Return the value of the EQ bit of CR6.
6601 BitNo = 0; InvertBit = false;
6603 case 1: // Return the inverted value of the EQ bit of CR6.
6604 BitNo = 0; InvertBit = true;
6606 case 2: // Return the value of the LT bit of CR6.
6607 BitNo = 2; InvertBit = false;
6609 case 3: // Return the inverted value of the LT bit of CR6.
6610 BitNo = 2; InvertBit = true;
6614 // Shift the bit into the low position.
6615 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6616 DAG.getConstant(8-(3-BitNo), MVT::i32));
6618 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6619 DAG.getConstant(1, MVT::i32));
6621 // If we are supposed to, toggle the bit.
6623 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6624 DAG.getConstant(1, MVT::i32));
6628 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6629 SelectionDAG &DAG) const {
6631 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6632 // instructions), but for smaller types, we need to first extend up to v2i32
6633 // before doing going farther.
6634 if (Op.getValueType() == MVT::v2i64) {
6635 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6636 if (ExtVT != MVT::v2i32) {
6637 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6638 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6639 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6640 ExtVT.getVectorElementType(), 4)));
6641 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6642 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6643 DAG.getValueType(MVT::v2i32));
6652 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6653 SelectionDAG &DAG) const {
6655 // Create a stack slot that is 16-byte aligned.
6656 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6657 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6658 EVT PtrVT = getPointerTy();
6659 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6661 // Store the input value into Value#0 of the stack slot.
6662 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6663 Op.getOperand(0), FIdx, MachinePointerInfo(),
6666 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6667 false, false, false, 0);
6670 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6672 if (Op.getValueType() == MVT::v4i32) {
6673 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6675 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6676 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6678 SDValue RHSSwap = // = vrlw RHS, 16
6679 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6681 // Shrinkify inputs to v8i16.
6682 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6683 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6684 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6686 // Low parts multiplied together, generating 32-bit results (we ignore the
6688 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6689 LHS, RHS, DAG, dl, MVT::v4i32);
6691 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6692 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6693 // Shift the high parts up 16 bits.
6694 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6696 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6697 } else if (Op.getValueType() == MVT::v8i16) {
6698 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6700 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6702 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6703 LHS, RHS, Zero, DAG, dl);
6704 } else if (Op.getValueType() == MVT::v16i8) {
6705 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6706 bool isLittleEndian = Subtarget.isLittleEndian();
6708 // Multiply the even 8-bit parts, producing 16-bit sums.
6709 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6710 LHS, RHS, DAG, dl, MVT::v8i16);
6711 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6713 // Multiply the odd 8-bit parts, producing 16-bit sums.
6714 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6715 LHS, RHS, DAG, dl, MVT::v8i16);
6716 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6718 // Merge the results together. Because vmuleub and vmuloub are
6719 // instructions with a big-endian bias, we must reverse the
6720 // element numbering and reverse the meaning of "odd" and "even"
6721 // when generating little endian code.
6723 for (unsigned i = 0; i != 8; ++i) {
6724 if (isLittleEndian) {
6726 Ops[i*2+1] = 2*i+16;
6729 Ops[i*2+1] = 2*i+1+16;
6733 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6735 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6737 llvm_unreachable("Unknown mul to lower!");
6741 /// LowerOperation - Provide custom lowering hooks for some operations.
6743 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6744 switch (Op.getOpcode()) {
6745 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6746 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6747 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6748 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6749 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6750 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6751 case ISD::SETCC: return LowerSETCC(Op, DAG);
6752 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6753 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6755 return LowerVASTART(Op, DAG, Subtarget);
6758 return LowerVAARG(Op, DAG, Subtarget);
6761 return LowerVACOPY(Op, DAG, Subtarget);
6763 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6764 case ISD::DYNAMIC_STACKALLOC:
6765 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6767 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6768 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6770 case ISD::LOAD: return LowerLOAD(Op, DAG);
6771 case ISD::STORE: return LowerSTORE(Op, DAG);
6772 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6773 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6774 case ISD::FP_TO_UINT:
6775 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6777 case ISD::UINT_TO_FP:
6778 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6779 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6781 // Lower 64-bit shifts.
6782 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6783 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6784 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6786 // Vector-related lowering.
6787 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6788 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6789 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6790 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6791 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6792 case ISD::MUL: return LowerMUL(Op, DAG);
6794 // For counter-based loop handling.
6795 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6797 // Frame & Return address.
6798 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6799 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6803 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6804 SmallVectorImpl<SDValue>&Results,
6805 SelectionDAG &DAG) const {
6806 const TargetMachine &TM = getTargetMachine();
6808 switch (N->getOpcode()) {
6810 llvm_unreachable("Do not know how to custom type legalize this operation!");
6811 case ISD::READCYCLECOUNTER: {
6812 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6813 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6815 Results.push_back(RTB);
6816 Results.push_back(RTB.getValue(1));
6817 Results.push_back(RTB.getValue(2));
6820 case ISD::INTRINSIC_W_CHAIN: {
6821 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6822 Intrinsic::ppc_is_decremented_ctr_nonzero)
6825 assert(N->getValueType(0) == MVT::i1 &&
6826 "Unexpected result type for CTR decrement intrinsic");
6827 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6828 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6829 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6832 Results.push_back(NewInt);
6833 Results.push_back(NewInt.getValue(1));
6837 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6838 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6841 EVT VT = N->getValueType(0);
6843 if (VT == MVT::i64) {
6844 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6846 Results.push_back(NewNode);
6847 Results.push_back(NewNode.getValue(1));
6851 case ISD::FP_ROUND_INREG: {
6852 assert(N->getValueType(0) == MVT::ppcf128);
6853 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6854 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6855 MVT::f64, N->getOperand(0),
6856 DAG.getIntPtrConstant(0));
6857 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6858 MVT::f64, N->getOperand(0),
6859 DAG.getIntPtrConstant(1));
6861 // Add the two halves of the long double in round-to-zero mode.
6862 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6864 // We know the low half is about to be thrown away, so just use something
6866 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6870 case ISD::FP_TO_SINT:
6871 // LowerFP_TO_INT() can only handle f32 and f64.
6872 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6874 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6880 //===----------------------------------------------------------------------===//
6881 // Other Lowering Code
6882 //===----------------------------------------------------------------------===//
6884 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6885 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6886 Function *Func = Intrinsic::getDeclaration(M, Id);
6887 return Builder.CreateCall(Func);
6890 // The mappings for emitLeading/TrailingFence is taken from
6891 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6892 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6893 AtomicOrdering Ord, bool IsStore,
6894 bool IsLoad) const {
6895 if (Ord == SequentiallyConsistent)
6896 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6897 else if (isAtLeastRelease(Ord))
6898 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6903 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6904 AtomicOrdering Ord, bool IsStore,
6905 bool IsLoad) const {
6906 if (IsLoad && isAtLeastAcquire(Ord))
6907 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6908 // FIXME: this is too conservative, a dependent branch + isync is enough.
6909 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6910 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6911 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6917 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6918 bool is64bit, unsigned BinOpcode) const {
6919 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6920 const TargetInstrInfo *TII =
6921 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6923 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6924 MachineFunction *F = BB->getParent();
6925 MachineFunction::iterator It = BB;
6928 unsigned dest = MI->getOperand(0).getReg();
6929 unsigned ptrA = MI->getOperand(1).getReg();
6930 unsigned ptrB = MI->getOperand(2).getReg();
6931 unsigned incr = MI->getOperand(3).getReg();
6932 DebugLoc dl = MI->getDebugLoc();
6934 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6935 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6936 F->insert(It, loopMBB);
6937 F->insert(It, exitMBB);
6938 exitMBB->splice(exitMBB->begin(), BB,
6939 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6940 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6942 MachineRegisterInfo &RegInfo = F->getRegInfo();
6943 unsigned TmpReg = (!BinOpcode) ? incr :
6944 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6945 : &PPC::GPRCRegClass);
6949 // fallthrough --> loopMBB
6950 BB->addSuccessor(loopMBB);
6953 // l[wd]arx dest, ptr
6954 // add r0, dest, incr
6955 // st[wd]cx. r0, ptr
6957 // fallthrough --> exitMBB
6959 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6960 .addReg(ptrA).addReg(ptrB);
6962 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6963 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6964 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6965 BuildMI(BB, dl, TII->get(PPC::BCC))
6966 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6967 BB->addSuccessor(loopMBB);
6968 BB->addSuccessor(exitMBB);
6977 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6978 MachineBasicBlock *BB,
6979 bool is8bit, // operation
6980 unsigned BinOpcode) const {
6981 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6982 const TargetInstrInfo *TII =
6983 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6984 // In 64 bit mode we have to use 64 bits for addresses, even though the
6985 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6986 // registers without caring whether they're 32 or 64, but here we're
6987 // doing actual arithmetic on the addresses.
6988 bool is64bit = Subtarget.isPPC64();
6989 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6991 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6992 MachineFunction *F = BB->getParent();
6993 MachineFunction::iterator It = BB;
6996 unsigned dest = MI->getOperand(0).getReg();
6997 unsigned ptrA = MI->getOperand(1).getReg();
6998 unsigned ptrB = MI->getOperand(2).getReg();
6999 unsigned incr = MI->getOperand(3).getReg();
7000 DebugLoc dl = MI->getDebugLoc();
7002 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7003 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7004 F->insert(It, loopMBB);
7005 F->insert(It, exitMBB);
7006 exitMBB->splice(exitMBB->begin(), BB,
7007 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7008 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7010 MachineRegisterInfo &RegInfo = F->getRegInfo();
7011 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7012 : &PPC::GPRCRegClass;
7013 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7014 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7015 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7016 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7017 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7018 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7019 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7020 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7021 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7022 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7023 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7025 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7029 // fallthrough --> loopMBB
7030 BB->addSuccessor(loopMBB);
7032 // The 4-byte load must be aligned, while a char or short may be
7033 // anywhere in the word. Hence all this nasty bookkeeping code.
7034 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7035 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7036 // xori shift, shift1, 24 [16]
7037 // rlwinm ptr, ptr1, 0, 0, 29
7038 // slw incr2, incr, shift
7039 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7040 // slw mask, mask2, shift
7042 // lwarx tmpDest, ptr
7043 // add tmp, tmpDest, incr2
7044 // andc tmp2, tmpDest, mask
7045 // and tmp3, tmp, mask
7046 // or tmp4, tmp3, tmp2
7049 // fallthrough --> exitMBB
7050 // srw dest, tmpDest, shift
7051 if (ptrA != ZeroReg) {
7052 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7053 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7054 .addReg(ptrA).addReg(ptrB);
7058 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7059 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7060 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7061 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7063 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7064 .addReg(Ptr1Reg).addImm(0).addImm(61);
7066 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7067 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7068 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7069 .addReg(incr).addReg(ShiftReg);
7071 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7073 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7074 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7076 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7077 .addReg(Mask2Reg).addReg(ShiftReg);
7080 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7081 .addReg(ZeroReg).addReg(PtrReg);
7083 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7084 .addReg(Incr2Reg).addReg(TmpDestReg);
7085 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7086 .addReg(TmpDestReg).addReg(MaskReg);
7087 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7088 .addReg(TmpReg).addReg(MaskReg);
7089 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7090 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7091 BuildMI(BB, dl, TII->get(PPC::STWCX))
7092 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7093 BuildMI(BB, dl, TII->get(PPC::BCC))
7094 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7095 BB->addSuccessor(loopMBB);
7096 BB->addSuccessor(exitMBB);
7101 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7106 llvm::MachineBasicBlock*
7107 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7108 MachineBasicBlock *MBB) const {
7109 DebugLoc DL = MI->getDebugLoc();
7110 const TargetInstrInfo *TII =
7111 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7113 MachineFunction *MF = MBB->getParent();
7114 MachineRegisterInfo &MRI = MF->getRegInfo();
7116 const BasicBlock *BB = MBB->getBasicBlock();
7117 MachineFunction::iterator I = MBB;
7121 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7122 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7124 unsigned DstReg = MI->getOperand(0).getReg();
7125 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7126 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7127 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7128 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7130 MVT PVT = getPointerTy();
7131 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7132 "Invalid Pointer Size!");
7133 // For v = setjmp(buf), we generate
7136 // SjLjSetup mainMBB
7142 // buf[LabelOffset] = LR
7146 // v = phi(main, restore)
7149 MachineBasicBlock *thisMBB = MBB;
7150 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7151 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7152 MF->insert(I, mainMBB);
7153 MF->insert(I, sinkMBB);
7155 MachineInstrBuilder MIB;
7157 // Transfer the remainder of BB and its successor edges to sinkMBB.
7158 sinkMBB->splice(sinkMBB->begin(), MBB,
7159 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7160 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7162 // Note that the structure of the jmp_buf used here is not compatible
7163 // with that used by libc, and is not designed to be. Specifically, it
7164 // stores only those 'reserved' registers that LLVM does not otherwise
7165 // understand how to spill. Also, by convention, by the time this
7166 // intrinsic is called, Clang has already stored the frame address in the
7167 // first slot of the buffer and stack address in the third. Following the
7168 // X86 target code, we'll store the jump address in the second slot. We also
7169 // need to save the TOC pointer (R2) to handle jumps between shared
7170 // libraries, and that will be stored in the fourth slot. The thread
7171 // identifier (R13) is not affected.
7174 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7175 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7176 const int64_t BPOffset = 4 * PVT.getStoreSize();
7178 // Prepare IP either in reg.
7179 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7180 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7181 unsigned BufReg = MI->getOperand(1).getReg();
7183 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7184 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7188 MIB.setMemRefs(MMOBegin, MMOEnd);
7191 // Naked functions never have a base pointer, and so we use r1. For all
7192 // other functions, this decision must be delayed until during PEI.
7194 if (MF->getFunction()->getAttributes().hasAttribute(
7195 AttributeSet::FunctionIndex, Attribute::Naked))
7196 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7198 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7200 MIB = BuildMI(*thisMBB, MI, DL,
7201 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7205 MIB.setMemRefs(MMOBegin, MMOEnd);
7208 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7209 const PPCRegisterInfo *TRI =
7210 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
7211 MIB.addRegMask(TRI->getNoPreservedMask());
7213 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7215 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7217 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7219 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7220 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7224 MIB = BuildMI(mainMBB, DL,
7225 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7228 if (Subtarget.isPPC64()) {
7229 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7231 .addImm(LabelOffset)
7234 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7236 .addImm(LabelOffset)
7240 MIB.setMemRefs(MMOBegin, MMOEnd);
7242 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7243 mainMBB->addSuccessor(sinkMBB);
7246 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7247 TII->get(PPC::PHI), DstReg)
7248 .addReg(mainDstReg).addMBB(mainMBB)
7249 .addReg(restoreDstReg).addMBB(thisMBB);
7251 MI->eraseFromParent();
7256 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7257 MachineBasicBlock *MBB) const {
7258 DebugLoc DL = MI->getDebugLoc();
7259 const TargetInstrInfo *TII =
7260 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7262 MachineFunction *MF = MBB->getParent();
7263 MachineRegisterInfo &MRI = MF->getRegInfo();
7266 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7267 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7269 MVT PVT = getPointerTy();
7270 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7271 "Invalid Pointer Size!");
7273 const TargetRegisterClass *RC =
7274 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7275 unsigned Tmp = MRI.createVirtualRegister(RC);
7276 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7277 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7278 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7279 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
7280 (Subtarget.isSVR4ABI() &&
7281 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
7282 PPC::R29 : PPC::R30);
7284 MachineInstrBuilder MIB;
7286 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7287 const int64_t SPOffset = 2 * PVT.getStoreSize();
7288 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7289 const int64_t BPOffset = 4 * PVT.getStoreSize();
7291 unsigned BufReg = MI->getOperand(0).getReg();
7293 // Reload FP (the jumped-to function may not have had a
7294 // frame pointer, and if so, then its r31 will be restored
7296 if (PVT == MVT::i64) {
7297 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7301 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7305 MIB.setMemRefs(MMOBegin, MMOEnd);
7308 if (PVT == MVT::i64) {
7309 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7310 .addImm(LabelOffset)
7313 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7314 .addImm(LabelOffset)
7317 MIB.setMemRefs(MMOBegin, MMOEnd);
7320 if (PVT == MVT::i64) {
7321 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7325 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7329 MIB.setMemRefs(MMOBegin, MMOEnd);
7332 if (PVT == MVT::i64) {
7333 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7337 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7341 MIB.setMemRefs(MMOBegin, MMOEnd);
7344 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7345 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7349 MIB.setMemRefs(MMOBegin, MMOEnd);
7353 BuildMI(*MBB, MI, DL,
7354 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7355 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7357 MI->eraseFromParent();
7362 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7363 MachineBasicBlock *BB) const {
7364 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7365 MI->getOpcode() == TargetOpcode::PATCHPOINT)
7366 return emitPatchPoint(MI, BB);
7368 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7369 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7370 return emitEHSjLjSetJmp(MI, BB);
7371 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7372 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7373 return emitEHSjLjLongJmp(MI, BB);
7376 const TargetInstrInfo *TII =
7377 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7379 // To "insert" these instructions we actually have to insert their
7380 // control-flow patterns.
7381 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7382 MachineFunction::iterator It = BB;
7385 MachineFunction *F = BB->getParent();
7387 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7388 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7389 MI->getOpcode() == PPC::SELECT_I4 ||
7390 MI->getOpcode() == PPC::SELECT_I8)) {
7391 SmallVector<MachineOperand, 2> Cond;
7392 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7393 MI->getOpcode() == PPC::SELECT_CC_I8)
7394 Cond.push_back(MI->getOperand(4));
7396 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7397 Cond.push_back(MI->getOperand(1));
7399 DebugLoc dl = MI->getDebugLoc();
7400 const TargetInstrInfo *TII =
7401 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7402 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7403 Cond, MI->getOperand(2).getReg(),
7404 MI->getOperand(3).getReg());
7405 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7406 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7407 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7408 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7409 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7410 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7411 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7412 MI->getOpcode() == PPC::SELECT_I4 ||
7413 MI->getOpcode() == PPC::SELECT_I8 ||
7414 MI->getOpcode() == PPC::SELECT_F4 ||
7415 MI->getOpcode() == PPC::SELECT_F8 ||
7416 MI->getOpcode() == PPC::SELECT_VRRC ||
7417 MI->getOpcode() == PPC::SELECT_VSFRC ||
7418 MI->getOpcode() == PPC::SELECT_VSRC) {
7419 // The incoming instruction knows the destination vreg to set, the
7420 // condition code register to branch on, the true/false values to
7421 // select between, and a branch opcode to use.
7426 // cmpTY ccX, r1, r2
7428 // fallthrough --> copy0MBB
7429 MachineBasicBlock *thisMBB = BB;
7430 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7431 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7432 DebugLoc dl = MI->getDebugLoc();
7433 F->insert(It, copy0MBB);
7434 F->insert(It, sinkMBB);
7436 // Transfer the remainder of BB and its successor edges to sinkMBB.
7437 sinkMBB->splice(sinkMBB->begin(), BB,
7438 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7439 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7441 // Next, add the true and fallthrough blocks as its successors.
7442 BB->addSuccessor(copy0MBB);
7443 BB->addSuccessor(sinkMBB);
7445 if (MI->getOpcode() == PPC::SELECT_I4 ||
7446 MI->getOpcode() == PPC::SELECT_I8 ||
7447 MI->getOpcode() == PPC::SELECT_F4 ||
7448 MI->getOpcode() == PPC::SELECT_F8 ||
7449 MI->getOpcode() == PPC::SELECT_VRRC ||
7450 MI->getOpcode() == PPC::SELECT_VSFRC ||
7451 MI->getOpcode() == PPC::SELECT_VSRC) {
7452 BuildMI(BB, dl, TII->get(PPC::BC))
7453 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7455 unsigned SelectPred = MI->getOperand(4).getImm();
7456 BuildMI(BB, dl, TII->get(PPC::BCC))
7457 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7461 // %FalseValue = ...
7462 // # fallthrough to sinkMBB
7465 // Update machine-CFG edges
7466 BB->addSuccessor(sinkMBB);
7469 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7472 BuildMI(*BB, BB->begin(), dl,
7473 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7474 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7475 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7476 } else if (MI->getOpcode() == PPC::ReadTB) {
7477 // To read the 64-bit time-base register on a 32-bit target, we read the
7478 // two halves. Should the counter have wrapped while it was being read, we
7479 // need to try again.
7482 // mfspr Rx,TBU # load from TBU
7483 // mfspr Ry,TB # load from TB
7484 // mfspr Rz,TBU # load from TBU
7485 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7486 // bne readLoop # branch if they're not equal
7489 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7490 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7491 DebugLoc dl = MI->getDebugLoc();
7492 F->insert(It, readMBB);
7493 F->insert(It, sinkMBB);
7495 // Transfer the remainder of BB and its successor edges to sinkMBB.
7496 sinkMBB->splice(sinkMBB->begin(), BB,
7497 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7498 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7500 BB->addSuccessor(readMBB);
7503 MachineRegisterInfo &RegInfo = F->getRegInfo();
7504 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7505 unsigned LoReg = MI->getOperand(0).getReg();
7506 unsigned HiReg = MI->getOperand(1).getReg();
7508 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7509 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7510 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7512 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7514 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7515 .addReg(HiReg).addReg(ReadAgainReg);
7516 BuildMI(BB, dl, TII->get(PPC::BCC))
7517 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7519 BB->addSuccessor(readMBB);
7520 BB->addSuccessor(sinkMBB);
7522 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7523 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7524 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7525 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7526 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7527 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7528 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7529 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7531 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7532 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7533 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7534 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7535 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7536 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7537 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7538 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7540 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7541 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7542 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7543 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7544 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7545 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7546 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7547 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7549 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7550 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7551 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7552 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7553 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7554 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7555 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7556 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7558 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7559 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7560 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7561 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7562 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7563 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7564 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7565 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7567 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7568 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7569 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7570 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7571 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7572 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7573 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7574 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7576 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7577 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7578 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7579 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7580 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7581 BB = EmitAtomicBinary(MI, BB, false, 0);
7582 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7583 BB = EmitAtomicBinary(MI, BB, true, 0);
7585 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7586 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7587 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7589 unsigned dest = MI->getOperand(0).getReg();
7590 unsigned ptrA = MI->getOperand(1).getReg();
7591 unsigned ptrB = MI->getOperand(2).getReg();
7592 unsigned oldval = MI->getOperand(3).getReg();
7593 unsigned newval = MI->getOperand(4).getReg();
7594 DebugLoc dl = MI->getDebugLoc();
7596 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7597 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7598 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7599 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7600 F->insert(It, loop1MBB);
7601 F->insert(It, loop2MBB);
7602 F->insert(It, midMBB);
7603 F->insert(It, exitMBB);
7604 exitMBB->splice(exitMBB->begin(), BB,
7605 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7606 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7610 // fallthrough --> loopMBB
7611 BB->addSuccessor(loop1MBB);
7614 // l[wd]arx dest, ptr
7615 // cmp[wd] dest, oldval
7618 // st[wd]cx. newval, ptr
7622 // st[wd]cx. dest, ptr
7625 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7626 .addReg(ptrA).addReg(ptrB);
7627 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7628 .addReg(oldval).addReg(dest);
7629 BuildMI(BB, dl, TII->get(PPC::BCC))
7630 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7631 BB->addSuccessor(loop2MBB);
7632 BB->addSuccessor(midMBB);
7635 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7636 .addReg(newval).addReg(ptrA).addReg(ptrB);
7637 BuildMI(BB, dl, TII->get(PPC::BCC))
7638 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7639 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7640 BB->addSuccessor(loop1MBB);
7641 BB->addSuccessor(exitMBB);
7644 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7645 .addReg(dest).addReg(ptrA).addReg(ptrB);
7646 BB->addSuccessor(exitMBB);
7651 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7652 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7653 // We must use 64-bit registers for addresses when targeting 64-bit,
7654 // since we're actually doing arithmetic on them. Other registers
7656 bool is64bit = Subtarget.isPPC64();
7657 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7659 unsigned dest = MI->getOperand(0).getReg();
7660 unsigned ptrA = MI->getOperand(1).getReg();
7661 unsigned ptrB = MI->getOperand(2).getReg();
7662 unsigned oldval = MI->getOperand(3).getReg();
7663 unsigned newval = MI->getOperand(4).getReg();
7664 DebugLoc dl = MI->getDebugLoc();
7666 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7667 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7668 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7669 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7670 F->insert(It, loop1MBB);
7671 F->insert(It, loop2MBB);
7672 F->insert(It, midMBB);
7673 F->insert(It, exitMBB);
7674 exitMBB->splice(exitMBB->begin(), BB,
7675 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7676 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7678 MachineRegisterInfo &RegInfo = F->getRegInfo();
7679 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7680 : &PPC::GPRCRegClass;
7681 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7682 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7683 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7684 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7685 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7686 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7687 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7688 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7689 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7690 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7691 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7692 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7693 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7695 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7696 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7699 // fallthrough --> loopMBB
7700 BB->addSuccessor(loop1MBB);
7702 // The 4-byte load must be aligned, while a char or short may be
7703 // anywhere in the word. Hence all this nasty bookkeeping code.
7704 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7705 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7706 // xori shift, shift1, 24 [16]
7707 // rlwinm ptr, ptr1, 0, 0, 29
7708 // slw newval2, newval, shift
7709 // slw oldval2, oldval,shift
7710 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7711 // slw mask, mask2, shift
7712 // and newval3, newval2, mask
7713 // and oldval3, oldval2, mask
7715 // lwarx tmpDest, ptr
7716 // and tmp, tmpDest, mask
7717 // cmpw tmp, oldval3
7720 // andc tmp2, tmpDest, mask
7721 // or tmp4, tmp2, newval3
7726 // stwcx. tmpDest, ptr
7728 // srw dest, tmpDest, shift
7729 if (ptrA != ZeroReg) {
7730 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7731 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7732 .addReg(ptrA).addReg(ptrB);
7736 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7737 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7738 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7739 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7741 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7742 .addReg(Ptr1Reg).addImm(0).addImm(61);
7744 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7745 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7746 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7747 .addReg(newval).addReg(ShiftReg);
7748 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7749 .addReg(oldval).addReg(ShiftReg);
7751 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7753 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7754 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7755 .addReg(Mask3Reg).addImm(65535);
7757 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7758 .addReg(Mask2Reg).addReg(ShiftReg);
7759 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7760 .addReg(NewVal2Reg).addReg(MaskReg);
7761 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7762 .addReg(OldVal2Reg).addReg(MaskReg);
7765 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7766 .addReg(ZeroReg).addReg(PtrReg);
7767 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7768 .addReg(TmpDestReg).addReg(MaskReg);
7769 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7770 .addReg(TmpReg).addReg(OldVal3Reg);
7771 BuildMI(BB, dl, TII->get(PPC::BCC))
7772 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7773 BB->addSuccessor(loop2MBB);
7774 BB->addSuccessor(midMBB);
7777 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7778 .addReg(TmpDestReg).addReg(MaskReg);
7779 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7780 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7781 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7782 .addReg(ZeroReg).addReg(PtrReg);
7783 BuildMI(BB, dl, TII->get(PPC::BCC))
7784 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7785 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7786 BB->addSuccessor(loop1MBB);
7787 BB->addSuccessor(exitMBB);
7790 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7791 .addReg(ZeroReg).addReg(PtrReg);
7792 BB->addSuccessor(exitMBB);
7797 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7799 } else if (MI->getOpcode() == PPC::FADDrtz) {
7800 // This pseudo performs an FADD with rounding mode temporarily forced
7801 // to round-to-zero. We emit this via custom inserter since the FPSCR
7802 // is not modeled at the SelectionDAG level.
7803 unsigned Dest = MI->getOperand(0).getReg();
7804 unsigned Src1 = MI->getOperand(1).getReg();
7805 unsigned Src2 = MI->getOperand(2).getReg();
7806 DebugLoc dl = MI->getDebugLoc();
7808 MachineRegisterInfo &RegInfo = F->getRegInfo();
7809 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7811 // Save FPSCR value.
7812 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7814 // Set rounding mode to round-to-zero.
7815 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7816 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7818 // Perform addition.
7819 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7821 // Restore FPSCR value.
7822 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7823 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7824 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7825 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7826 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7827 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7828 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7829 PPC::ANDIo8 : PPC::ANDIo;
7830 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7831 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7833 MachineRegisterInfo &RegInfo = F->getRegInfo();
7834 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7835 &PPC::GPRCRegClass :
7836 &PPC::G8RCRegClass);
7838 DebugLoc dl = MI->getDebugLoc();
7839 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7840 .addReg(MI->getOperand(1).getReg()).addImm(1);
7841 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7842 MI->getOperand(0).getReg())
7843 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7845 llvm_unreachable("Unexpected instr type to insert");
7848 MI->eraseFromParent(); // The pseudo instruction is gone now.
7852 //===----------------------------------------------------------------------===//
7853 // Target Optimization Hooks
7854 //===----------------------------------------------------------------------===//
7856 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7857 DAGCombinerInfo &DCI,
7858 unsigned &RefinementSteps,
7859 bool &UseOneConstNR) const {
7860 EVT VT = Operand.getValueType();
7861 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7862 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7863 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7864 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7865 // Convergence is quadratic, so we essentially double the number of digits
7866 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7867 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7868 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7869 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7870 if (VT.getScalarType() == MVT::f64)
7872 UseOneConstNR = true;
7873 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7878 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7879 DAGCombinerInfo &DCI,
7880 unsigned &RefinementSteps) const {
7881 EVT VT = Operand.getValueType();
7882 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7883 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7884 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7885 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7886 // Convergence is quadratic, so we essentially double the number of digits
7887 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7888 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7889 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7890 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7891 if (VT.getScalarType() == MVT::f64)
7893 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7898 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7899 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7900 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7901 // enabled for division), this functionality is redundant with the default
7902 // combiner logic (once the division -> reciprocal/multiply transformation
7903 // has taken place). As a result, this matters more for older cores than for
7906 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7907 // reciprocal if there are two or more FDIVs (for embedded cores with only
7908 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7909 switch (Subtarget.getDarwinDirective()) {
7911 return NumUsers > 2;
7914 case PPC::DIR_E500mc:
7915 case PPC::DIR_E5500:
7916 return NumUsers > 1;
7920 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7921 unsigned Bytes, int Dist,
7922 SelectionDAG &DAG) {
7923 if (VT.getSizeInBits() / 8 != Bytes)
7926 SDValue BaseLoc = Base->getBasePtr();
7927 if (Loc.getOpcode() == ISD::FrameIndex) {
7928 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7930 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7931 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7932 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7933 int FS = MFI->getObjectSize(FI);
7934 int BFS = MFI->getObjectSize(BFI);
7935 if (FS != BFS || FS != (int)Bytes) return false;
7936 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7940 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7941 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7944 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7945 const GlobalValue *GV1 = nullptr;
7946 const GlobalValue *GV2 = nullptr;
7947 int64_t Offset1 = 0;
7948 int64_t Offset2 = 0;
7949 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7950 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7951 if (isGA1 && isGA2 && GV1 == GV2)
7952 return Offset1 == (Offset2 + Dist*Bytes);
7956 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7957 // not enforce equality of the chain operands.
7958 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7959 unsigned Bytes, int Dist,
7960 SelectionDAG &DAG) {
7961 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7962 EVT VT = LS->getMemoryVT();
7963 SDValue Loc = LS->getBasePtr();
7964 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7967 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7969 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7970 default: return false;
7971 case Intrinsic::ppc_altivec_lvx:
7972 case Intrinsic::ppc_altivec_lvxl:
7973 case Intrinsic::ppc_vsx_lxvw4x:
7976 case Intrinsic::ppc_vsx_lxvd2x:
7979 case Intrinsic::ppc_altivec_lvebx:
7982 case Intrinsic::ppc_altivec_lvehx:
7985 case Intrinsic::ppc_altivec_lvewx:
7990 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7993 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7995 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7996 default: return false;
7997 case Intrinsic::ppc_altivec_stvx:
7998 case Intrinsic::ppc_altivec_stvxl:
7999 case Intrinsic::ppc_vsx_stxvw4x:
8002 case Intrinsic::ppc_vsx_stxvd2x:
8005 case Intrinsic::ppc_altivec_stvebx:
8008 case Intrinsic::ppc_altivec_stvehx:
8011 case Intrinsic::ppc_altivec_stvewx:
8016 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8022 // Return true is there is a nearyby consecutive load to the one provided
8023 // (regardless of alignment). We search up and down the chain, looking though
8024 // token factors and other loads (but nothing else). As a result, a true result
8025 // indicates that it is safe to create a new consecutive load adjacent to the
8027 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8028 SDValue Chain = LD->getChain();
8029 EVT VT = LD->getMemoryVT();
8031 SmallSet<SDNode *, 16> LoadRoots;
8032 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8033 SmallSet<SDNode *, 16> Visited;
8035 // First, search up the chain, branching to follow all token-factor operands.
8036 // If we find a consecutive load, then we're done, otherwise, record all
8037 // nodes just above the top-level loads and token factors.
8038 while (!Queue.empty()) {
8039 SDNode *ChainNext = Queue.pop_back_val();
8040 if (!Visited.insert(ChainNext).second)
8043 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8044 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8047 if (!Visited.count(ChainLD->getChain().getNode()))
8048 Queue.push_back(ChainLD->getChain().getNode());
8049 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8050 for (const SDUse &O : ChainNext->ops())
8051 if (!Visited.count(O.getNode()))
8052 Queue.push_back(O.getNode());
8054 LoadRoots.insert(ChainNext);
8057 // Second, search down the chain, starting from the top-level nodes recorded
8058 // in the first phase. These top-level nodes are the nodes just above all
8059 // loads and token factors. Starting with their uses, recursively look though
8060 // all loads (just the chain uses) and token factors to find a consecutive
8065 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8066 IE = LoadRoots.end(); I != IE; ++I) {
8067 Queue.push_back(*I);
8069 while (!Queue.empty()) {
8070 SDNode *LoadRoot = Queue.pop_back_val();
8071 if (!Visited.insert(LoadRoot).second)
8074 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8075 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8078 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8079 UE = LoadRoot->use_end(); UI != UE; ++UI)
8080 if (((isa<MemSDNode>(*UI) &&
8081 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8082 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8083 Queue.push_back(*UI);
8090 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8091 DAGCombinerInfo &DCI) const {
8092 SelectionDAG &DAG = DCI.DAG;
8095 assert(Subtarget.useCRBits() &&
8096 "Expecting to be tracking CR bits");
8097 // If we're tracking CR bits, we need to be careful that we don't have:
8098 // trunc(binary-ops(zext(x), zext(y)))
8100 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8101 // such that we're unnecessarily moving things into GPRs when it would be
8102 // better to keep them in CR bits.
8104 // Note that trunc here can be an actual i1 trunc, or can be the effective
8105 // truncation that comes from a setcc or select_cc.
8106 if (N->getOpcode() == ISD::TRUNCATE &&
8107 N->getValueType(0) != MVT::i1)
8110 if (N->getOperand(0).getValueType() != MVT::i32 &&
8111 N->getOperand(0).getValueType() != MVT::i64)
8114 if (N->getOpcode() == ISD::SETCC ||
8115 N->getOpcode() == ISD::SELECT_CC) {
8116 // If we're looking at a comparison, then we need to make sure that the
8117 // high bits (all except for the first) don't matter the result.
8119 cast<CondCodeSDNode>(N->getOperand(
8120 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8121 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8123 if (ISD::isSignedIntSetCC(CC)) {
8124 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8125 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8127 } else if (ISD::isUnsignedIntSetCC(CC)) {
8128 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8129 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8130 !DAG.MaskedValueIsZero(N->getOperand(1),
8131 APInt::getHighBitsSet(OpBits, OpBits-1)))
8134 // This is neither a signed nor an unsigned comparison, just make sure
8135 // that the high bits are equal.
8136 APInt Op1Zero, Op1One;
8137 APInt Op2Zero, Op2One;
8138 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8139 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8141 // We don't really care about what is known about the first bit (if
8142 // anything), so clear it in all masks prior to comparing them.
8143 Op1Zero.clearBit(0); Op1One.clearBit(0);
8144 Op2Zero.clearBit(0); Op2One.clearBit(0);
8146 if (Op1Zero != Op2Zero || Op1One != Op2One)
8151 // We now know that the higher-order bits are irrelevant, we just need to
8152 // make sure that all of the intermediate operations are bit operations, and
8153 // all inputs are extensions.
8154 if (N->getOperand(0).getOpcode() != ISD::AND &&
8155 N->getOperand(0).getOpcode() != ISD::OR &&
8156 N->getOperand(0).getOpcode() != ISD::XOR &&
8157 N->getOperand(0).getOpcode() != ISD::SELECT &&
8158 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8159 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8160 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8161 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8162 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8165 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8166 N->getOperand(1).getOpcode() != ISD::AND &&
8167 N->getOperand(1).getOpcode() != ISD::OR &&
8168 N->getOperand(1).getOpcode() != ISD::XOR &&
8169 N->getOperand(1).getOpcode() != ISD::SELECT &&
8170 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8171 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8172 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8173 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8174 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8177 SmallVector<SDValue, 4> Inputs;
8178 SmallVector<SDValue, 8> BinOps, PromOps;
8179 SmallPtrSet<SDNode *, 16> Visited;
8181 for (unsigned i = 0; i < 2; ++i) {
8182 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8183 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8184 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8185 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8186 isa<ConstantSDNode>(N->getOperand(i)))
8187 Inputs.push_back(N->getOperand(i));
8189 BinOps.push_back(N->getOperand(i));
8191 if (N->getOpcode() == ISD::TRUNCATE)
8195 // Visit all inputs, collect all binary operations (and, or, xor and
8196 // select) that are all fed by extensions.
8197 while (!BinOps.empty()) {
8198 SDValue BinOp = BinOps.back();
8201 if (!Visited.insert(BinOp.getNode()).second)
8204 PromOps.push_back(BinOp);
8206 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8207 // The condition of the select is not promoted.
8208 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8210 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8213 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8214 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8215 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8216 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8217 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8218 Inputs.push_back(BinOp.getOperand(i));
8219 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8220 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8221 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8222 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8223 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8224 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8225 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8226 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8227 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8228 BinOps.push_back(BinOp.getOperand(i));
8230 // We have an input that is not an extension or another binary
8231 // operation; we'll abort this transformation.
8237 // Make sure that this is a self-contained cluster of operations (which
8238 // is not quite the same thing as saying that everything has only one
8240 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8241 if (isa<ConstantSDNode>(Inputs[i]))
8244 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8245 UE = Inputs[i].getNode()->use_end();
8248 if (User != N && !Visited.count(User))
8251 // Make sure that we're not going to promote the non-output-value
8252 // operand(s) or SELECT or SELECT_CC.
8253 // FIXME: Although we could sometimes handle this, and it does occur in
8254 // practice that one of the condition inputs to the select is also one of
8255 // the outputs, we currently can't deal with this.
8256 if (User->getOpcode() == ISD::SELECT) {
8257 if (User->getOperand(0) == Inputs[i])
8259 } else if (User->getOpcode() == ISD::SELECT_CC) {
8260 if (User->getOperand(0) == Inputs[i] ||
8261 User->getOperand(1) == Inputs[i])
8267 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8268 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8269 UE = PromOps[i].getNode()->use_end();
8272 if (User != N && !Visited.count(User))
8275 // Make sure that we're not going to promote the non-output-value
8276 // operand(s) or SELECT or SELECT_CC.
8277 // FIXME: Although we could sometimes handle this, and it does occur in
8278 // practice that one of the condition inputs to the select is also one of
8279 // the outputs, we currently can't deal with this.
8280 if (User->getOpcode() == ISD::SELECT) {
8281 if (User->getOperand(0) == PromOps[i])
8283 } else if (User->getOpcode() == ISD::SELECT_CC) {
8284 if (User->getOperand(0) == PromOps[i] ||
8285 User->getOperand(1) == PromOps[i])
8291 // Replace all inputs with the extension operand.
8292 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8293 // Constants may have users outside the cluster of to-be-promoted nodes,
8294 // and so we need to replace those as we do the promotions.
8295 if (isa<ConstantSDNode>(Inputs[i]))
8298 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8301 // Replace all operations (these are all the same, but have a different
8302 // (i1) return type). DAG.getNode will validate that the types of
8303 // a binary operator match, so go through the list in reverse so that
8304 // we've likely promoted both operands first. Any intermediate truncations or
8305 // extensions disappear.
8306 while (!PromOps.empty()) {
8307 SDValue PromOp = PromOps.back();
8310 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8311 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8312 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8313 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8314 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8315 PromOp.getOperand(0).getValueType() != MVT::i1) {
8316 // The operand is not yet ready (see comment below).
8317 PromOps.insert(PromOps.begin(), PromOp);
8321 SDValue RepValue = PromOp.getOperand(0);
8322 if (isa<ConstantSDNode>(RepValue))
8323 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8325 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8330 switch (PromOp.getOpcode()) {
8331 default: C = 0; break;
8332 case ISD::SELECT: C = 1; break;
8333 case ISD::SELECT_CC: C = 2; break;
8336 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8337 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8338 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8339 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8340 // The to-be-promoted operands of this node have not yet been
8341 // promoted (this should be rare because we're going through the
8342 // list backward, but if one of the operands has several users in
8343 // this cluster of to-be-promoted nodes, it is possible).
8344 PromOps.insert(PromOps.begin(), PromOp);
8348 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8349 PromOp.getNode()->op_end());
8351 // If there are any constant inputs, make sure they're replaced now.
8352 for (unsigned i = 0; i < 2; ++i)
8353 if (isa<ConstantSDNode>(Ops[C+i]))
8354 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8356 DAG.ReplaceAllUsesOfValueWith(PromOp,
8357 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8360 // Now we're left with the initial truncation itself.
8361 if (N->getOpcode() == ISD::TRUNCATE)
8362 return N->getOperand(0);
8364 // Otherwise, this is a comparison. The operands to be compared have just
8365 // changed type (to i1), but everything else is the same.
8366 return SDValue(N, 0);
8369 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8370 DAGCombinerInfo &DCI) const {
8371 SelectionDAG &DAG = DCI.DAG;
8374 // If we're tracking CR bits, we need to be careful that we don't have:
8375 // zext(binary-ops(trunc(x), trunc(y)))
8377 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8378 // such that we're unnecessarily moving things into CR bits that can more
8379 // efficiently stay in GPRs. Note that if we're not certain that the high
8380 // bits are set as required by the final extension, we still may need to do
8381 // some masking to get the proper behavior.
8383 // This same functionality is important on PPC64 when dealing with
8384 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8385 // the return values of functions. Because it is so similar, it is handled
8388 if (N->getValueType(0) != MVT::i32 &&
8389 N->getValueType(0) != MVT::i64)
8392 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8393 Subtarget.useCRBits()) ||
8394 (N->getOperand(0).getValueType() == MVT::i32 &&
8395 Subtarget.isPPC64())))
8398 if (N->getOperand(0).getOpcode() != ISD::AND &&
8399 N->getOperand(0).getOpcode() != ISD::OR &&
8400 N->getOperand(0).getOpcode() != ISD::XOR &&
8401 N->getOperand(0).getOpcode() != ISD::SELECT &&
8402 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8405 SmallVector<SDValue, 4> Inputs;
8406 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8407 SmallPtrSet<SDNode *, 16> Visited;
8409 // Visit all inputs, collect all binary operations (and, or, xor and
8410 // select) that are all fed by truncations.
8411 while (!BinOps.empty()) {
8412 SDValue BinOp = BinOps.back();
8415 if (!Visited.insert(BinOp.getNode()).second)
8418 PromOps.push_back(BinOp);
8420 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8421 // The condition of the select is not promoted.
8422 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8424 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8427 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8428 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8429 Inputs.push_back(BinOp.getOperand(i));
8430 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8431 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8432 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8433 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8434 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8435 BinOps.push_back(BinOp.getOperand(i));
8437 // We have an input that is not a truncation or another binary
8438 // operation; we'll abort this transformation.
8444 // The operands of a select that must be truncated when the select is
8445 // promoted because the operand is actually part of the to-be-promoted set.
8446 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8448 // Make sure that this is a self-contained cluster of operations (which
8449 // is not quite the same thing as saying that everything has only one
8451 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8452 if (isa<ConstantSDNode>(Inputs[i]))
8455 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8456 UE = Inputs[i].getNode()->use_end();
8459 if (User != N && !Visited.count(User))
8462 // If we're going to promote the non-output-value operand(s) or SELECT or
8463 // SELECT_CC, record them for truncation.
8464 if (User->getOpcode() == ISD::SELECT) {
8465 if (User->getOperand(0) == Inputs[i])
8466 SelectTruncOp[0].insert(std::make_pair(User,
8467 User->getOperand(0).getValueType()));
8468 } else if (User->getOpcode() == ISD::SELECT_CC) {
8469 if (User->getOperand(0) == Inputs[i])
8470 SelectTruncOp[0].insert(std::make_pair(User,
8471 User->getOperand(0).getValueType()));
8472 if (User->getOperand(1) == Inputs[i])
8473 SelectTruncOp[1].insert(std::make_pair(User,
8474 User->getOperand(1).getValueType()));
8479 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8480 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8481 UE = PromOps[i].getNode()->use_end();
8484 if (User != N && !Visited.count(User))
8487 // If we're going to promote the non-output-value operand(s) or SELECT or
8488 // SELECT_CC, record them for truncation.
8489 if (User->getOpcode() == ISD::SELECT) {
8490 if (User->getOperand(0) == PromOps[i])
8491 SelectTruncOp[0].insert(std::make_pair(User,
8492 User->getOperand(0).getValueType()));
8493 } else if (User->getOpcode() == ISD::SELECT_CC) {
8494 if (User->getOperand(0) == PromOps[i])
8495 SelectTruncOp[0].insert(std::make_pair(User,
8496 User->getOperand(0).getValueType()));
8497 if (User->getOperand(1) == PromOps[i])
8498 SelectTruncOp[1].insert(std::make_pair(User,
8499 User->getOperand(1).getValueType()));
8504 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8505 bool ReallyNeedsExt = false;
8506 if (N->getOpcode() != ISD::ANY_EXTEND) {
8507 // If all of the inputs are not already sign/zero extended, then
8508 // we'll still need to do that at the end.
8509 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8510 if (isa<ConstantSDNode>(Inputs[i]))
8514 Inputs[i].getOperand(0).getValueSizeInBits();
8515 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8517 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8518 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8519 APInt::getHighBitsSet(OpBits,
8520 OpBits-PromBits))) ||
8521 (N->getOpcode() == ISD::SIGN_EXTEND &&
8522 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8523 (OpBits-(PromBits-1)))) {
8524 ReallyNeedsExt = true;
8530 // Replace all inputs, either with the truncation operand, or a
8531 // truncation or extension to the final output type.
8532 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8533 // Constant inputs need to be replaced with the to-be-promoted nodes that
8534 // use them because they might have users outside of the cluster of
8536 if (isa<ConstantSDNode>(Inputs[i]))
8539 SDValue InSrc = Inputs[i].getOperand(0);
8540 if (Inputs[i].getValueType() == N->getValueType(0))
8541 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8542 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8543 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8544 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8545 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8546 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8547 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8549 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8550 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8553 // Replace all operations (these are all the same, but have a different
8554 // (promoted) return type). DAG.getNode will validate that the types of
8555 // a binary operator match, so go through the list in reverse so that
8556 // we've likely promoted both operands first.
8557 while (!PromOps.empty()) {
8558 SDValue PromOp = PromOps.back();
8562 switch (PromOp.getOpcode()) {
8563 default: C = 0; break;
8564 case ISD::SELECT: C = 1; break;
8565 case ISD::SELECT_CC: C = 2; break;
8568 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8569 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8570 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8571 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8572 // The to-be-promoted operands of this node have not yet been
8573 // promoted (this should be rare because we're going through the
8574 // list backward, but if one of the operands has several users in
8575 // this cluster of to-be-promoted nodes, it is possible).
8576 PromOps.insert(PromOps.begin(), PromOp);
8580 // For SELECT and SELECT_CC nodes, we do a similar check for any
8581 // to-be-promoted comparison inputs.
8582 if (PromOp.getOpcode() == ISD::SELECT ||
8583 PromOp.getOpcode() == ISD::SELECT_CC) {
8584 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8585 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8586 (SelectTruncOp[1].count(PromOp.getNode()) &&
8587 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8588 PromOps.insert(PromOps.begin(), PromOp);
8593 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8594 PromOp.getNode()->op_end());
8596 // If this node has constant inputs, then they'll need to be promoted here.
8597 for (unsigned i = 0; i < 2; ++i) {
8598 if (!isa<ConstantSDNode>(Ops[C+i]))
8600 if (Ops[C+i].getValueType() == N->getValueType(0))
8603 if (N->getOpcode() == ISD::SIGN_EXTEND)
8604 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8605 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8606 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8608 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8611 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8612 // truncate them again to the original value type.
8613 if (PromOp.getOpcode() == ISD::SELECT ||
8614 PromOp.getOpcode() == ISD::SELECT_CC) {
8615 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8616 if (SI0 != SelectTruncOp[0].end())
8617 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8618 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8619 if (SI1 != SelectTruncOp[1].end())
8620 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8623 DAG.ReplaceAllUsesOfValueWith(PromOp,
8624 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8627 // Now we're left with the initial extension itself.
8628 if (!ReallyNeedsExt)
8629 return N->getOperand(0);
8631 // To zero extend, just mask off everything except for the first bit (in the
8633 if (N->getOpcode() == ISD::ZERO_EXTEND)
8634 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8635 DAG.getConstant(APInt::getLowBitsSet(
8636 N->getValueSizeInBits(0), PromBits),
8637 N->getValueType(0)));
8639 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8640 "Invalid extension type");
8641 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8643 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8644 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8645 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8646 N->getOperand(0), ShiftCst), ShiftCst);
8649 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8650 DAGCombinerInfo &DCI) const {
8651 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8652 N->getOpcode() == ISD::UINT_TO_FP) &&
8653 "Need an int -> FP conversion node here");
8655 if (!Subtarget.has64BitSupport())
8658 SelectionDAG &DAG = DCI.DAG;
8662 // Don't handle ppc_fp128 here or i1 conversions.
8663 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8665 if (Op.getOperand(0).getValueType() == MVT::i1)
8668 // For i32 intermediate values, unfortunately, the conversion functions
8669 // leave the upper 32 bits of the value are undefined. Within the set of
8670 // scalar instructions, we have no method for zero- or sign-extending the
8671 // value. Thus, we cannot handle i32 intermediate values here.
8672 if (Op.getOperand(0).getValueType() == MVT::i32)
8675 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8676 "UINT_TO_FP is supported only with FPCVT");
8678 // If we have FCFIDS, then use it when converting to single-precision.
8679 // Otherwise, convert to double-precision and then round.
8680 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8681 (Op.getOpcode() == ISD::UINT_TO_FP ?
8682 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8683 (Op.getOpcode() == ISD::UINT_TO_FP ?
8684 PPCISD::FCFIDU : PPCISD::FCFID);
8685 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8686 MVT::f32 : MVT::f64;
8688 // If we're converting from a float, to an int, and back to a float again,
8689 // then we don't need the store/load pair at all.
8690 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8691 Subtarget.hasFPCVT()) ||
8692 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8693 SDValue Src = Op.getOperand(0).getOperand(0);
8694 if (Src.getValueType() == MVT::f32) {
8695 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8696 DCI.AddToWorklist(Src.getNode());
8700 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8703 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8704 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8706 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8707 FP = DAG.getNode(ISD::FP_ROUND, dl,
8708 MVT::f32, FP, DAG.getIntPtrConstant(0));
8709 DCI.AddToWorklist(FP.getNode());
8718 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8719 // builtins) into loads with swaps.
8720 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8721 DAGCombinerInfo &DCI) const {
8722 SelectionDAG &DAG = DCI.DAG;
8726 MachineMemOperand *MMO;
8728 switch (N->getOpcode()) {
8730 llvm_unreachable("Unexpected opcode for little endian VSX load");
8732 LoadSDNode *LD = cast<LoadSDNode>(N);
8733 Chain = LD->getChain();
8734 Base = LD->getBasePtr();
8735 MMO = LD->getMemOperand();
8736 // If the MMO suggests this isn't a load of a full vector, leave
8737 // things alone. For a built-in, we have to make the change for
8738 // correctness, so if there is a size problem that will be a bug.
8739 if (MMO->getSize() < 16)
8743 case ISD::INTRINSIC_W_CHAIN: {
8744 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8745 Chain = Intrin->getChain();
8746 Base = Intrin->getBasePtr();
8747 MMO = Intrin->getMemOperand();
8752 MVT VecTy = N->getValueType(0).getSimpleVT();
8753 SDValue LoadOps[] = { Chain, Base };
8754 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8755 DAG.getVTList(VecTy, MVT::Other),
8756 LoadOps, VecTy, MMO);
8757 DCI.AddToWorklist(Load.getNode());
8758 Chain = Load.getValue(1);
8759 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8760 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8761 DCI.AddToWorklist(Swap.getNode());
8765 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8766 // builtins) into stores with swaps.
8767 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8768 DAGCombinerInfo &DCI) const {
8769 SelectionDAG &DAG = DCI.DAG;
8774 MachineMemOperand *MMO;
8776 switch (N->getOpcode()) {
8778 llvm_unreachable("Unexpected opcode for little endian VSX store");
8780 StoreSDNode *ST = cast<StoreSDNode>(N);
8781 Chain = ST->getChain();
8782 Base = ST->getBasePtr();
8783 MMO = ST->getMemOperand();
8785 // If the MMO suggests this isn't a store of a full vector, leave
8786 // things alone. For a built-in, we have to make the change for
8787 // correctness, so if there is a size problem that will be a bug.
8788 if (MMO->getSize() < 16)
8792 case ISD::INTRINSIC_VOID: {
8793 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8794 Chain = Intrin->getChain();
8795 // Intrin->getBasePtr() oddly does not get what we want.
8796 Base = Intrin->getOperand(3);
8797 MMO = Intrin->getMemOperand();
8803 SDValue Src = N->getOperand(SrcOpnd);
8804 MVT VecTy = Src.getValueType().getSimpleVT();
8805 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8806 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8807 DCI.AddToWorklist(Swap.getNode());
8808 Chain = Swap.getValue(1);
8809 SDValue StoreOps[] = { Chain, Swap, Base };
8810 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8811 DAG.getVTList(MVT::Other),
8812 StoreOps, VecTy, MMO);
8813 DCI.AddToWorklist(Store.getNode());
8817 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8818 DAGCombinerInfo &DCI) const {
8819 const TargetMachine &TM = getTargetMachine();
8820 SelectionDAG &DAG = DCI.DAG;
8822 switch (N->getOpcode()) {
8825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8826 if (C->isNullValue()) // 0 << V -> 0.
8827 return N->getOperand(0);
8831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8832 if (C->isNullValue()) // 0 >>u V -> 0.
8833 return N->getOperand(0);
8837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8838 if (C->isNullValue() || // 0 >>s V -> 0.
8839 C->isAllOnesValue()) // -1 >>s V -> -1.
8840 return N->getOperand(0);
8843 case ISD::SIGN_EXTEND:
8844 case ISD::ZERO_EXTEND:
8845 case ISD::ANY_EXTEND:
8846 return DAGCombineExtBoolTrunc(N, DCI);
8849 case ISD::SELECT_CC:
8850 return DAGCombineTruncBoolExt(N, DCI);
8851 case ISD::SINT_TO_FP:
8852 case ISD::UINT_TO_FP:
8853 return combineFPToIntToFP(N, DCI);
8855 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8856 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8857 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8858 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8859 N->getOperand(1).getValueType() == MVT::i32 &&
8860 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8861 SDValue Val = N->getOperand(1).getOperand(0);
8862 if (Val.getValueType() == MVT::f32) {
8863 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8864 DCI.AddToWorklist(Val.getNode());
8866 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8867 DCI.AddToWorklist(Val.getNode());
8870 N->getOperand(0), Val, N->getOperand(2),
8871 DAG.getValueType(N->getOperand(1).getValueType())
8874 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8875 DAG.getVTList(MVT::Other), Ops,
8876 cast<StoreSDNode>(N)->getMemoryVT(),
8877 cast<StoreSDNode>(N)->getMemOperand());
8878 DCI.AddToWorklist(Val.getNode());
8882 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8883 if (cast<StoreSDNode>(N)->isUnindexed() &&
8884 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8885 N->getOperand(1).getNode()->hasOneUse() &&
8886 (N->getOperand(1).getValueType() == MVT::i32 ||
8887 N->getOperand(1).getValueType() == MVT::i16 ||
8888 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8889 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8890 N->getOperand(1).getValueType() == MVT::i64))) {
8891 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8892 // Do an any-extend to 32-bits if this is a half-word input.
8893 if (BSwapOp.getValueType() == MVT::i16)
8894 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8897 N->getOperand(0), BSwapOp, N->getOperand(2),
8898 DAG.getValueType(N->getOperand(1).getValueType())
8901 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8902 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8903 cast<StoreSDNode>(N)->getMemOperand());
8906 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8907 EVT VT = N->getOperand(1).getValueType();
8908 if (VT.isSimple()) {
8909 MVT StoreVT = VT.getSimpleVT();
8910 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8911 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8912 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8913 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8914 return expandVSXStoreForLE(N, DCI);
8919 LoadSDNode *LD = cast<LoadSDNode>(N);
8920 EVT VT = LD->getValueType(0);
8922 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8923 if (VT.isSimple()) {
8924 MVT LoadVT = VT.getSimpleVT();
8925 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8926 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8927 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8928 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8929 return expandVSXLoadForLE(N, DCI);
8932 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8933 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8934 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8935 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8936 // P8 and later hardware should just use LOAD.
8937 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8938 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8939 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8940 LD->getAlignment() < ABIAlignment) {
8941 // This is a type-legal unaligned Altivec load.
8942 SDValue Chain = LD->getChain();
8943 SDValue Ptr = LD->getBasePtr();
8944 bool isLittleEndian = Subtarget.isLittleEndian();
8946 // This implements the loading of unaligned vectors as described in
8947 // the venerable Apple Velocity Engine overview. Specifically:
8948 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8949 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8951 // The general idea is to expand a sequence of one or more unaligned
8952 // loads into an alignment-based permutation-control instruction (lvsl
8953 // or lvsr), a series of regular vector loads (which always truncate
8954 // their input address to an aligned address), and a series of
8955 // permutations. The results of these permutations are the requested
8956 // loaded values. The trick is that the last "extra" load is not taken
8957 // from the address you might suspect (sizeof(vector) bytes after the
8958 // last requested load), but rather sizeof(vector) - 1 bytes after the
8959 // last requested vector. The point of this is to avoid a page fault if
8960 // the base address happened to be aligned. This works because if the
8961 // base address is aligned, then adding less than a full vector length
8962 // will cause the last vector in the sequence to be (re)loaded.
8963 // Otherwise, the next vector will be fetched as you might suspect was
8966 // We might be able to reuse the permutation generation from
8967 // a different base address offset from this one by an aligned amount.
8968 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8969 // optimization later.
8970 Intrinsic::ID Intr = (isLittleEndian ?
8971 Intrinsic::ppc_altivec_lvsr :
8972 Intrinsic::ppc_altivec_lvsl);
8973 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8975 // Create the new MMO for the new base load. It is like the original MMO,
8976 // but represents an area in memory almost twice the vector size centered
8977 // on the original address. If the address is unaligned, we might start
8978 // reading up to (sizeof(vector)-1) bytes below the address of the
8979 // original unaligned load.
8980 MachineFunction &MF = DAG.getMachineFunction();
8981 MachineMemOperand *BaseMMO =
8982 MF.getMachineMemOperand(LD->getMemOperand(),
8983 -LD->getMemoryVT().getStoreSize()+1,
8984 2*LD->getMemoryVT().getStoreSize()-1);
8986 // Create the new base load.
8987 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8989 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8991 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8992 DAG.getVTList(MVT::v4i32, MVT::Other),
8993 BaseLoadOps, MVT::v4i32, BaseMMO);
8995 // Note that the value of IncOffset (which is provided to the next
8996 // load's pointer info offset value, and thus used to calculate the
8997 // alignment), and the value of IncValue (which is actually used to
8998 // increment the pointer value) are different! This is because we
8999 // require the next load to appear to be aligned, even though it
9000 // is actually offset from the base pointer by a lesser amount.
9001 int IncOffset = VT.getSizeInBits() / 8;
9002 int IncValue = IncOffset;
9004 // Walk (both up and down) the chain looking for another load at the real
9005 // (aligned) offset (the alignment of the other load does not matter in
9006 // this case). If found, then do not use the offset reduction trick, as
9007 // that will prevent the loads from being later combined (as they would
9008 // otherwise be duplicates).
9009 if (!findConsecutiveLoad(LD, DAG))
9012 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9013 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9015 MachineMemOperand *ExtraMMO =
9016 MF.getMachineMemOperand(LD->getMemOperand(),
9017 1, 2*LD->getMemoryVT().getStoreSize()-1);
9018 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9020 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9021 DAG.getVTList(MVT::v4i32, MVT::Other),
9022 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9024 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9025 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9027 // Because vperm has a big-endian bias, we must reverse the order
9028 // of the input vectors and complement the permute control vector
9029 // when generating little endian code. We have already handled the
9030 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9031 // and ExtraLoad here.
9034 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9035 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9037 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9038 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9040 if (VT != MVT::v4i32)
9041 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9043 // The output of the permutation is our loaded result, the TokenFactor is
9045 DCI.CombineTo(N, Perm, TF);
9046 return SDValue(N, 0);
9050 case ISD::INTRINSIC_WO_CHAIN: {
9051 bool isLittleEndian = Subtarget.isLittleEndian();
9052 Intrinsic::ID Intr = (isLittleEndian ?
9053 Intrinsic::ppc_altivec_lvsr :
9054 Intrinsic::ppc_altivec_lvsl);
9055 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9056 N->getOperand(1)->getOpcode() == ISD::ADD) {
9057 SDValue Add = N->getOperand(1);
9059 if (DAG.MaskedValueIsZero(Add->getOperand(1),
9060 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
9061 Add.getValueType().getScalarType().getSizeInBits()))) {
9062 SDNode *BasePtr = Add->getOperand(0).getNode();
9063 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9064 UE = BasePtr->use_end(); UI != UE; ++UI) {
9065 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9066 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9068 // We've found another LVSL/LVSR, and this address is an aligned
9069 // multiple of that one. The results will be the same, so use the
9070 // one we've just found instead.
9072 return SDValue(*UI, 0);
9080 case ISD::INTRINSIC_W_CHAIN: {
9081 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9082 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
9083 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
9084 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9087 case Intrinsic::ppc_vsx_lxvw4x:
9088 case Intrinsic::ppc_vsx_lxvd2x:
9089 return expandVSXLoadForLE(N, DCI);
9094 case ISD::INTRINSIC_VOID: {
9095 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9096 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
9097 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
9098 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9101 case Intrinsic::ppc_vsx_stxvw4x:
9102 case Intrinsic::ppc_vsx_stxvd2x:
9103 return expandVSXStoreForLE(N, DCI);
9109 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9110 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9111 N->getOperand(0).hasOneUse() &&
9112 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9113 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
9114 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
9115 N->getValueType(0) == MVT::i64))) {
9116 SDValue Load = N->getOperand(0);
9117 LoadSDNode *LD = cast<LoadSDNode>(Load);
9118 // Create the byte-swapping load.
9120 LD->getChain(), // Chain
9121 LD->getBasePtr(), // Ptr
9122 DAG.getValueType(N->getValueType(0)) // VT
9125 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9126 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9127 MVT::i64 : MVT::i32, MVT::Other),
9128 Ops, LD->getMemoryVT(), LD->getMemOperand());
9130 // If this is an i16 load, insert the truncate.
9131 SDValue ResVal = BSLoad;
9132 if (N->getValueType(0) == MVT::i16)
9133 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9135 // First, combine the bswap away. This makes the value produced by the
9137 DCI.CombineTo(N, ResVal);
9139 // Next, combine the load away, we give it a bogus result value but a real
9140 // chain result. The result value is dead because the bswap is dead.
9141 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9143 // Return N so it doesn't get rechecked!
9144 return SDValue(N, 0);
9148 case PPCISD::VCMP: {
9149 // If a VCMPo node already exists with exactly the same operands as this
9150 // node, use its result instead of this node (VCMPo computes both a CR6 and
9151 // a normal output).
9153 if (!N->getOperand(0).hasOneUse() &&
9154 !N->getOperand(1).hasOneUse() &&
9155 !N->getOperand(2).hasOneUse()) {
9157 // Scan all of the users of the LHS, looking for VCMPo's that match.
9158 SDNode *VCMPoNode = nullptr;
9160 SDNode *LHSN = N->getOperand(0).getNode();
9161 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9163 if (UI->getOpcode() == PPCISD::VCMPo &&
9164 UI->getOperand(1) == N->getOperand(1) &&
9165 UI->getOperand(2) == N->getOperand(2) &&
9166 UI->getOperand(0) == N->getOperand(0)) {
9171 // If there is no VCMPo node, or if the flag value has a single use, don't
9173 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9176 // Look at the (necessarily single) use of the flag value. If it has a
9177 // chain, this transformation is more complex. Note that multiple things
9178 // could use the value result, which we should ignore.
9179 SDNode *FlagUser = nullptr;
9180 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9181 FlagUser == nullptr; ++UI) {
9182 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9184 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9185 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9192 // If the user is a MFOCRF instruction, we know this is safe.
9193 // Otherwise we give up for right now.
9194 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9195 return SDValue(VCMPoNode, 0);
9200 SDValue Cond = N->getOperand(1);
9201 SDValue Target = N->getOperand(2);
9203 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9204 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9205 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9207 // We now need to make the intrinsic dead (it cannot be instruction
9209 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9210 assert(Cond.getNode()->hasOneUse() &&
9211 "Counter decrement has more than one use");
9213 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9214 N->getOperand(0), Target);
9219 // If this is a branch on an altivec predicate comparison, lower this so
9220 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9221 // lowering is done pre-legalize, because the legalizer lowers the predicate
9222 // compare down to code that is difficult to reassemble.
9223 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9224 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9226 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9227 // value. If so, pass-through the AND to get to the intrinsic.
9228 if (LHS.getOpcode() == ISD::AND &&
9229 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9230 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9231 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9232 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9233 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9235 LHS = LHS.getOperand(0);
9237 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9238 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9239 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9240 isa<ConstantSDNode>(RHS)) {
9241 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9242 "Counter decrement comparison is not EQ or NE");
9244 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9245 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9246 (CC == ISD::SETNE && !Val);
9248 // We now need to make the intrinsic dead (it cannot be instruction
9250 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9251 assert(LHS.getNode()->hasOneUse() &&
9252 "Counter decrement has more than one use");
9254 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9255 N->getOperand(0), N->getOperand(4));
9261 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9262 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9263 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9264 assert(isDot && "Can't compare against a vector result!");
9266 // If this is a comparison against something other than 0/1, then we know
9267 // that the condition is never/always true.
9268 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9269 if (Val != 0 && Val != 1) {
9270 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9271 return N->getOperand(0);
9272 // Always !=, turn it into an unconditional branch.
9273 return DAG.getNode(ISD::BR, dl, MVT::Other,
9274 N->getOperand(0), N->getOperand(4));
9277 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9279 // Create the PPCISD altivec 'dot' comparison node.
9281 LHS.getOperand(2), // LHS of compare
9282 LHS.getOperand(3), // RHS of compare
9283 DAG.getConstant(CompareOpc, MVT::i32)
9285 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9286 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9288 // Unpack the result based on how the target uses it.
9289 PPC::Predicate CompOpc;
9290 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9291 default: // Can't happen, don't crash on invalid number though.
9292 case 0: // Branch on the value of the EQ bit of CR6.
9293 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9295 case 1: // Branch on the inverted value of the EQ bit of CR6.
9296 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9298 case 2: // Branch on the value of the LT bit of CR6.
9299 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9301 case 3: // Branch on the inverted value of the LT bit of CR6.
9302 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9306 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9307 DAG.getConstant(CompOpc, MVT::i32),
9308 DAG.getRegister(PPC::CR6, MVT::i32),
9309 N->getOperand(4), CompNode.getValue(1));
9319 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9321 std::vector<SDNode *> *Created) const {
9322 // fold (sdiv X, pow2)
9323 EVT VT = N->getValueType(0);
9324 if (VT == MVT::i64 && !Subtarget.isPPC64())
9326 if ((VT != MVT::i32 && VT != MVT::i64) ||
9327 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9331 SDValue N0 = N->getOperand(0);
9333 bool IsNegPow2 = (-Divisor).isPowerOf2();
9334 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9335 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9337 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9339 Created->push_back(Op.getNode());
9342 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9344 Created->push_back(Op.getNode());
9350 //===----------------------------------------------------------------------===//
9351 // Inline Assembly Support
9352 //===----------------------------------------------------------------------===//
9354 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9357 const SelectionDAG &DAG,
9358 unsigned Depth) const {
9359 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9360 switch (Op.getOpcode()) {
9362 case PPCISD::LBRX: {
9363 // lhbrx is known to have the top bits cleared out.
9364 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9365 KnownZero = 0xFFFF0000;
9368 case ISD::INTRINSIC_WO_CHAIN: {
9369 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9371 case Intrinsic::ppc_altivec_vcmpbfp_p:
9372 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9373 case Intrinsic::ppc_altivec_vcmpequb_p:
9374 case Intrinsic::ppc_altivec_vcmpequh_p:
9375 case Intrinsic::ppc_altivec_vcmpequw_p:
9376 case Intrinsic::ppc_altivec_vcmpgefp_p:
9377 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9378 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9379 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9380 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9381 case Intrinsic::ppc_altivec_vcmpgtub_p:
9382 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9383 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9384 KnownZero = ~1U; // All bits but the low one are known to be zero.
9391 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9392 switch (Subtarget.getDarwinDirective()) {
9397 case PPC::DIR_PWR5X:
9399 case PPC::DIR_PWR6X:
9401 case PPC::DIR_PWR8: {
9405 const PPCInstrInfo *TII =
9406 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9409 // For small loops (between 5 and 8 instructions), align to a 32-byte
9410 // boundary so that the entire loop fits in one instruction-cache line.
9411 uint64_t LoopSize = 0;
9412 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9413 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9414 LoopSize += TII->GetInstSizeInBytes(J);
9416 if (LoopSize > 16 && LoopSize <= 32)
9423 return TargetLowering::getPrefLoopAlignment(ML);
9426 /// getConstraintType - Given a constraint, return the type of
9427 /// constraint it is for this target.
9428 PPCTargetLowering::ConstraintType
9429 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9430 if (Constraint.size() == 1) {
9431 switch (Constraint[0]) {
9438 return C_RegisterClass;
9440 // FIXME: While Z does indicate a memory constraint, it specifically
9441 // indicates an r+r address (used in conjunction with the 'y' modifier
9442 // in the replacement string). Currently, we're forcing the base
9443 // register to be r0 in the asm printer (which is interpreted as zero)
9444 // and forming the complete address in the second register. This is
9448 } else if (Constraint == "wc") { // individual CR bits.
9449 return C_RegisterClass;
9450 } else if (Constraint == "wa" || Constraint == "wd" ||
9451 Constraint == "wf" || Constraint == "ws") {
9452 return C_RegisterClass; // VSX registers.
9454 return TargetLowering::getConstraintType(Constraint);
9457 /// Examine constraint type and operand type and determine a weight value.
9458 /// This object must already have been set up with the operand type
9459 /// and the current alternative constraint selected.
9460 TargetLowering::ConstraintWeight
9461 PPCTargetLowering::getSingleConstraintMatchWeight(
9462 AsmOperandInfo &info, const char *constraint) const {
9463 ConstraintWeight weight = CW_Invalid;
9464 Value *CallOperandVal = info.CallOperandVal;
9465 // If we don't have a value, we can't do a match,
9466 // but allow it at the lowest weight.
9467 if (!CallOperandVal)
9469 Type *type = CallOperandVal->getType();
9471 // Look at the constraint type.
9472 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9473 return CW_Register; // an individual CR bit.
9474 else if ((StringRef(constraint) == "wa" ||
9475 StringRef(constraint) == "wd" ||
9476 StringRef(constraint) == "wf") &&
9479 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9482 switch (*constraint) {
9484 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9487 if (type->isIntegerTy())
9488 weight = CW_Register;
9491 if (type->isFloatTy())
9492 weight = CW_Register;
9495 if (type->isDoubleTy())
9496 weight = CW_Register;
9499 if (type->isVectorTy())
9500 weight = CW_Register;
9503 weight = CW_Register;
9512 std::pair<unsigned, const TargetRegisterClass*>
9513 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9515 if (Constraint.size() == 1) {
9516 // GCC RS6000 Constraint Letters
9517 switch (Constraint[0]) {
9519 if (VT == MVT::i64 && Subtarget.isPPC64())
9520 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9521 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9523 if (VT == MVT::i64 && Subtarget.isPPC64())
9524 return std::make_pair(0U, &PPC::G8RCRegClass);
9525 return std::make_pair(0U, &PPC::GPRCRegClass);
9527 if (VT == MVT::f32 || VT == MVT::i32)
9528 return std::make_pair(0U, &PPC::F4RCRegClass);
9529 if (VT == MVT::f64 || VT == MVT::i64)
9530 return std::make_pair(0U, &PPC::F8RCRegClass);
9533 return std::make_pair(0U, &PPC::VRRCRegClass);
9535 return std::make_pair(0U, &PPC::CRRCRegClass);
9537 } else if (Constraint == "wc") { // an individual CR bit.
9538 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9539 } else if (Constraint == "wa" || Constraint == "wd" ||
9540 Constraint == "wf") {
9541 return std::make_pair(0U, &PPC::VSRCRegClass);
9542 } else if (Constraint == "ws") {
9543 return std::make_pair(0U, &PPC::VSFRCRegClass);
9546 std::pair<unsigned, const TargetRegisterClass*> R =
9547 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9549 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9550 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9551 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9553 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9554 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9555 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9556 PPC::GPRCRegClass.contains(R.first)) {
9557 const TargetRegisterInfo *TRI =
9558 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9559 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9560 PPC::sub_32, &PPC::G8RCRegClass),
9561 &PPC::G8RCRegClass);
9564 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9565 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9567 R.second = &PPC::CRRCRegClass;
9574 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9575 /// vector. If it is invalid, don't add anything to Ops.
9576 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9577 std::string &Constraint,
9578 std::vector<SDValue>&Ops,
9579 SelectionDAG &DAG) const {
9582 // Only support length 1 constraints.
9583 if (Constraint.length() > 1) return;
9585 char Letter = Constraint[0];
9596 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9597 if (!CST) return; // Must be an immediate to match.
9598 int64_t Value = CST->getSExtValue();
9599 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9600 // numbers are printed as such.
9602 default: llvm_unreachable("Unknown constraint letter!");
9603 case 'I': // "I" is a signed 16-bit constant.
9604 if (isInt<16>(Value))
9605 Result = DAG.getTargetConstant(Value, TCVT);
9607 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9608 if (isShiftedUInt<16, 16>(Value))
9609 Result = DAG.getTargetConstant(Value, TCVT);
9611 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9612 if (isShiftedInt<16, 16>(Value))
9613 Result = DAG.getTargetConstant(Value, TCVT);
9615 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9616 if (isUInt<16>(Value))
9617 Result = DAG.getTargetConstant(Value, TCVT);
9619 case 'M': // "M" is a constant that is greater than 31.
9621 Result = DAG.getTargetConstant(Value, TCVT);
9623 case 'N': // "N" is a positive constant that is an exact power of two.
9624 if (Value > 0 && isPowerOf2_64(Value))
9625 Result = DAG.getTargetConstant(Value, TCVT);
9627 case 'O': // "O" is the constant zero.
9629 Result = DAG.getTargetConstant(Value, TCVT);
9631 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9632 if (isInt<16>(-Value))
9633 Result = DAG.getTargetConstant(Value, TCVT);
9640 if (Result.getNode()) {
9641 Ops.push_back(Result);
9645 // Handle standard constraint letters.
9646 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9649 // isLegalAddressingMode - Return true if the addressing mode represented
9650 // by AM is legal for this target, for a load/store of the specified type.
9651 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9653 // FIXME: PPC does not allow r+i addressing modes for vectors!
9655 // PPC allows a sign-extended 16-bit immediate field.
9656 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9659 // No global is ever allowed as a base.
9663 // PPC only support r+r,
9665 case 0: // "r+i" or just "i", depending on HasBaseReg.
9668 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9670 // Otherwise we have r+r or r+i.
9673 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9675 // Allow 2*r as r+r.
9678 // No other scales are supported.
9685 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9686 SelectionDAG &DAG) const {
9687 MachineFunction &MF = DAG.getMachineFunction();
9688 MachineFrameInfo *MFI = MF.getFrameInfo();
9689 MFI->setReturnAddressIsTaken(true);
9691 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9695 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9697 // Make sure the function does not optimize away the store of the RA to
9699 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9700 FuncInfo->setLRStoreRequired();
9701 bool isPPC64 = Subtarget.isPPC64();
9702 bool isDarwinABI = Subtarget.isDarwinABI();
9705 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9708 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9709 isPPC64? MVT::i64 : MVT::i32);
9710 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9711 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9713 MachinePointerInfo(), false, false, false, 0);
9716 // Just load the return address off the stack.
9717 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9718 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9719 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9722 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9723 SelectionDAG &DAG) const {
9725 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9727 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9728 bool isPPC64 = PtrVT == MVT::i64;
9730 MachineFunction &MF = DAG.getMachineFunction();
9731 MachineFrameInfo *MFI = MF.getFrameInfo();
9732 MFI->setFrameAddressIsTaken(true);
9734 // Naked functions never have a frame pointer, and so we use r1. For all
9735 // other functions, this decision must be delayed until during PEI.
9737 if (MF.getFunction()->getAttributes().hasAttribute(
9738 AttributeSet::FunctionIndex, Attribute::Naked))
9739 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9741 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9743 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9746 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9747 FrameAddr, MachinePointerInfo(), false, false,
9752 // FIXME? Maybe this could be a TableGen attribute on some registers and
9753 // this table could be generated automatically from RegInfo.
9754 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9756 bool isPPC64 = Subtarget.isPPC64();
9757 bool isDarwinABI = Subtarget.isDarwinABI();
9759 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9760 (!isPPC64 && VT != MVT::i32))
9761 report_fatal_error("Invalid register global variable type");
9763 bool is64Bit = isPPC64 && VT == MVT::i64;
9764 unsigned Reg = StringSwitch<unsigned>(RegName)
9765 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9766 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9767 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9768 (is64Bit ? PPC::X13 : PPC::R13))
9773 report_fatal_error("Invalid register name global variable");
9777 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9778 // The PowerPC target isn't yet aware of offsets.
9782 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9784 unsigned Intrinsic) const {
9786 switch (Intrinsic) {
9787 case Intrinsic::ppc_altivec_lvx:
9788 case Intrinsic::ppc_altivec_lvxl:
9789 case Intrinsic::ppc_altivec_lvebx:
9790 case Intrinsic::ppc_altivec_lvehx:
9791 case Intrinsic::ppc_altivec_lvewx:
9792 case Intrinsic::ppc_vsx_lxvd2x:
9793 case Intrinsic::ppc_vsx_lxvw4x: {
9795 switch (Intrinsic) {
9796 case Intrinsic::ppc_altivec_lvebx:
9799 case Intrinsic::ppc_altivec_lvehx:
9802 case Intrinsic::ppc_altivec_lvewx:
9805 case Intrinsic::ppc_vsx_lxvd2x:
9813 Info.opc = ISD::INTRINSIC_W_CHAIN;
9815 Info.ptrVal = I.getArgOperand(0);
9816 Info.offset = -VT.getStoreSize()+1;
9817 Info.size = 2*VT.getStoreSize()-1;
9820 Info.readMem = true;
9821 Info.writeMem = false;
9824 case Intrinsic::ppc_altivec_stvx:
9825 case Intrinsic::ppc_altivec_stvxl:
9826 case Intrinsic::ppc_altivec_stvebx:
9827 case Intrinsic::ppc_altivec_stvehx:
9828 case Intrinsic::ppc_altivec_stvewx:
9829 case Intrinsic::ppc_vsx_stxvd2x:
9830 case Intrinsic::ppc_vsx_stxvw4x: {
9832 switch (Intrinsic) {
9833 case Intrinsic::ppc_altivec_stvebx:
9836 case Intrinsic::ppc_altivec_stvehx:
9839 case Intrinsic::ppc_altivec_stvewx:
9842 case Intrinsic::ppc_vsx_stxvd2x:
9850 Info.opc = ISD::INTRINSIC_VOID;
9852 Info.ptrVal = I.getArgOperand(1);
9853 Info.offset = -VT.getStoreSize()+1;
9854 Info.size = 2*VT.getStoreSize()-1;
9857 Info.readMem = false;
9858 Info.writeMem = true;
9868 /// getOptimalMemOpType - Returns the target specific optimal type for load
9869 /// and store operations as a result of memset, memcpy, and memmove
9870 /// lowering. If DstAlign is zero that means it's safe to destination
9871 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9872 /// means there isn't a need to check it against alignment requirement,
9873 /// probably because the source does not need to be loaded. If 'IsMemset' is
9874 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9875 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9876 /// source is constant so it does not need to be loaded.
9877 /// It returns EVT::Other if the type should be determined using generic
9878 /// target-independent logic.
9879 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9880 unsigned DstAlign, unsigned SrcAlign,
9881 bool IsMemset, bool ZeroMemset,
9883 MachineFunction &MF) const {
9884 if (Subtarget.isPPC64()) {
9891 /// \brief Returns true if it is beneficial to convert a load of a constant
9892 /// to just the constant itself.
9893 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9895 assert(Ty->isIntegerTy());
9897 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9898 if (BitSize == 0 || BitSize > 64)
9903 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9904 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9906 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9907 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9908 return NumBits1 == 64 && NumBits2 == 32;
9911 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9912 if (!VT1.isInteger() || !VT2.isInteger())
9914 unsigned NumBits1 = VT1.getSizeInBits();
9915 unsigned NumBits2 = VT2.getSizeInBits();
9916 return NumBits1 == 64 && NumBits2 == 32;
9919 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9920 // Generally speaking, zexts are not free, but they are free when they can be
9921 // folded with other operations.
9922 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9923 EVT MemVT = LD->getMemoryVT();
9924 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9925 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9926 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9927 LD->getExtensionType() == ISD::ZEXTLOAD))
9931 // FIXME: Add other cases...
9932 // - 32-bit shifts with a zext to i64
9933 // - zext after ctlz, bswap, etc.
9934 // - zext after and by a constant mask
9936 return TargetLowering::isZExtFree(Val, VT2);
9939 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9940 assert(VT.isFloatingPoint());
9944 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9945 return isInt<16>(Imm) || isUInt<16>(Imm);
9948 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9949 return isInt<16>(Imm) || isUInt<16>(Imm);
9952 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9956 if (DisablePPCUnaligned)
9959 // PowerPC supports unaligned memory access for simple non-vector types.
9960 // Although accessing unaligned addresses is not as efficient as accessing
9961 // aligned addresses, it is generally more efficient than manual expansion,
9962 // and generally only traps for software emulation when crossing page
9968 if (VT.getSimpleVT().isVector()) {
9969 if (Subtarget.hasVSX()) {
9970 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9971 VT != MVT::v4f32 && VT != MVT::v4i32)
9978 if (VT == MVT::ppcf128)
9987 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9988 VT = VT.getScalarType();
9993 switch (VT.getSimpleVT().SimpleTy) {
10005 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
10006 // LR is a callee-save register, but we must treat it as clobbered by any call
10007 // site. Hence we include LR in the scratch registers, which are in turn added
10008 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
10009 // to CTR, which is used by any indirect call.
10010 static const MCPhysReg ScratchRegs[] = {
10011 PPC::X12, PPC::LR8, PPC::CTR8, 0
10014 return ScratchRegs;
10018 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10019 EVT VT , unsigned DefinedValues) const {
10020 if (VT == MVT::v2i64)
10023 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10026 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10027 if (DisableILPPref || Subtarget.enableMachineScheduler())
10028 return TargetLowering::getSchedulingPreference(N);
10033 // Create a fast isel object.
10035 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10036 const TargetLibraryInfo *LibInfo) const {
10037 return PPC::createFastISel(FuncInfo, LibInfo);