1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAG.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Intrinsics.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
43 // FIXME: Remove this once soft-float is supported.
44 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
45 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
47 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
48 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
50 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
51 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
53 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
54 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
56 // FIXME: Remove this once the bug has been fixed!
57 extern cl::opt<bool> ANDIGlueBug;
59 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
61 Subtarget(*TM.getSubtargetImpl()) {
62 // Use _setjmp/_longjmp instead of setjmp/longjmp.
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(true);
66 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
67 // arguments are at least 4/8 bytes aligned.
68 bool isPPC64 = Subtarget.isPPC64();
69 setMinStackArgumentAlignment(isPPC64 ? 8:4);
71 // Set up the register classes.
72 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
73 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
74 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
76 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
77 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
80 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
82 // PowerPC has pre-inc load and store's.
83 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
88 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
94 if (Subtarget.useCRBits()) {
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
97 if (isPPC64 || Subtarget.hasFPCVT()) {
98 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
99 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
100 isPPC64 ? MVT::i64 : MVT::i32);
101 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
106 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
109 // PowerPC does not support direct load / store of condition registers
110 setOperationAction(ISD::LOAD, MVT::i1, Custom);
111 setOperationAction(ISD::STORE, MVT::i1, Custom);
113 // FIXME: Remove this once the ANDI glue bug is fixed:
115 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
117 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
119 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
120 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
121 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
122 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
124 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
127 // This is used in the ppcf128->int sequence. Note it has different semantics
128 // from FP_ROUND: that rounds to nearest, this rounds to zero.
129 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
131 // We do not currently implement these libm ops for PowerPC.
132 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
133 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
134 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
139 // PowerPC has no SREM/UREM instructions
140 setOperationAction(ISD::SREM, MVT::i32, Expand);
141 setOperationAction(ISD::UREM, MVT::i32, Expand);
142 setOperationAction(ISD::SREM, MVT::i64, Expand);
143 setOperationAction(ISD::UREM, MVT::i64, Expand);
145 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
146 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
147 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
148 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
150 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
151 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
155 // We don't support sin/cos/sqrt/fmod/pow
156 setOperationAction(ISD::FSIN , MVT::f64, Expand);
157 setOperationAction(ISD::FCOS , MVT::f64, Expand);
158 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
159 setOperationAction(ISD::FREM , MVT::f64, Expand);
160 setOperationAction(ISD::FPOW , MVT::f64, Expand);
161 setOperationAction(ISD::FMA , MVT::f64, Legal);
162 setOperationAction(ISD::FSIN , MVT::f32, Expand);
163 setOperationAction(ISD::FCOS , MVT::f32, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
165 setOperationAction(ISD::FREM , MVT::f32, Expand);
166 setOperationAction(ISD::FPOW , MVT::f32, Expand);
167 setOperationAction(ISD::FMA , MVT::f32, Legal);
169 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
171 // If we're enabling GP optimizations, use hardware square root
172 if (!Subtarget.hasFSQRT() &&
173 !(TM.Options.UnsafeFPMath &&
174 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
175 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
177 if (!Subtarget.hasFSQRT() &&
178 !(TM.Options.UnsafeFPMath &&
179 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
180 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
182 if (Subtarget.hasFCPSGN()) {
183 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
184 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
187 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
190 if (Subtarget.hasFPRND()) {
191 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
192 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
193 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
194 setOperationAction(ISD::FROUND, MVT::f64, Legal);
196 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
197 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
198 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
199 setOperationAction(ISD::FROUND, MVT::f32, Legal);
202 // PowerPC does not have BSWAP, CTPOP or CTTZ
203 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
204 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
205 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
206 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
207 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
208 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
209 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
210 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
212 if (Subtarget.hasPOPCNTD()) {
213 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
214 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
217 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
220 // PowerPC does not have ROTR
221 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
222 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
224 if (!Subtarget.useCRBits()) {
225 // PowerPC does not have Select
226 setOperationAction(ISD::SELECT, MVT::i32, Expand);
227 setOperationAction(ISD::SELECT, MVT::i64, Expand);
228 setOperationAction(ISD::SELECT, MVT::f32, Expand);
229 setOperationAction(ISD::SELECT, MVT::f64, Expand);
232 // PowerPC wants to turn select_cc of FP into fsel when possible.
233 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
234 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
236 // PowerPC wants to optimize integer setcc a bit
237 if (!Subtarget.useCRBits())
238 setOperationAction(ISD::SETCC, MVT::i32, Custom);
240 // PowerPC does not have BRCOND which requires SetCC
241 if (!Subtarget.useCRBits())
242 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
244 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
246 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
247 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
249 // PowerPC does not have [U|S]INT_TO_FP
250 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
254 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
256 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
258 // We cannot sextinreg(i1). Expand to shifts.
259 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
261 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
262 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
263 // support continuation, user-level threading, and etc.. As a result, no
264 // other SjLj exception interfaces are implemented and please don't build
265 // your own exception handling based on them.
266 // LLVM/Clang supports zero-cost DWARF exception handling.
267 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
268 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
270 // We want to legalize GlobalAddress and ConstantPool nodes into the
271 // appropriate instructions to materialize the address.
272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
273 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
274 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
275 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
276 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
277 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
278 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
279 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
280 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
281 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
284 setOperationAction(ISD::TRAP, MVT::Other, Legal);
286 // TRAMPOLINE is custom lowered.
287 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
288 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
290 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
291 setOperationAction(ISD::VASTART , MVT::Other, Custom);
293 if (Subtarget.isSVR4ABI()) {
295 // VAARG always uses double-word chunks, so promote anything smaller.
296 setOperationAction(ISD::VAARG, MVT::i1, Promote);
297 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
298 setOperationAction(ISD::VAARG, MVT::i8, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i16, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i32, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::Other, Expand);
306 // VAARG is custom lowered with the 32-bit SVR4 ABI.
307 setOperationAction(ISD::VAARG, MVT::Other, Custom);
308 setOperationAction(ISD::VAARG, MVT::i64, Custom);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 if (Subtarget.isSVR4ABI() && !isPPC64)
314 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
315 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
317 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
319 // Use the default implementation.
320 setOperationAction(ISD::VAEND , MVT::Other, Expand);
321 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
322 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
323 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
324 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
326 // We want to custom lower some of our intrinsics.
327 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
329 // To handle counter-based loop conditions.
330 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
332 // Comparisons that require checking two conditions.
333 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
334 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
335 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
346 if (Subtarget.has64BitSupport()) {
347 // They also have instructions for converting between i64 and fp.
348 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
349 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
352 // This is just the low 32 bits of a (signed) fp->i64 conversion.
353 // We cannot do this with Promote because i64 is not a legal type.
354 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
356 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
357 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
359 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
363 // With the instructions enabled under FPCVT, we can do everything.
364 if (Subtarget.hasFPCVT()) {
365 if (Subtarget.has64BitSupport()) {
366 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
367 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
368 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
369 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
372 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
378 if (Subtarget.use64BitRegs()) {
379 // 64-bit PowerPC implementations can support i64 types directly
380 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
381 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
382 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
383 // 64-bit PowerPC wants to expand i128 shifts itself.
384 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
385 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
386 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
388 // 32-bit PowerPC wants to expand i64 shifts itself.
389 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
390 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
391 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
394 if (Subtarget.hasAltivec()) {
395 // First set operation action for all vector types to expand. Then we
396 // will selectively turn on ones that can be effectively codegen'd.
397 for (MVT VT : MVT::vector_valuetypes()) {
398 // add/sub are legal for all supported vector VT's.
399 setOperationAction(ISD::ADD , VT, Legal);
400 setOperationAction(ISD::SUB , VT, Legal);
402 // We promote all shuffles to v16i8.
403 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
404 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
406 // We promote all non-typed operations to v4i32.
407 setOperationAction(ISD::AND , VT, Promote);
408 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
409 setOperationAction(ISD::OR , VT, Promote);
410 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
411 setOperationAction(ISD::XOR , VT, Promote);
412 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
413 setOperationAction(ISD::LOAD , VT, Promote);
414 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
415 setOperationAction(ISD::SELECT, VT, Promote);
416 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
417 setOperationAction(ISD::STORE, VT, Promote);
418 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
420 // No other operations are legal.
421 setOperationAction(ISD::MUL , VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UDIV, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
426 setOperationAction(ISD::FDIV, VT, Expand);
427 setOperationAction(ISD::FREM, VT, Expand);
428 setOperationAction(ISD::FNEG, VT, Expand);
429 setOperationAction(ISD::FSQRT, VT, Expand);
430 setOperationAction(ISD::FLOG, VT, Expand);
431 setOperationAction(ISD::FLOG10, VT, Expand);
432 setOperationAction(ISD::FLOG2, VT, Expand);
433 setOperationAction(ISD::FEXP, VT, Expand);
434 setOperationAction(ISD::FEXP2, VT, Expand);
435 setOperationAction(ISD::FSIN, VT, Expand);
436 setOperationAction(ISD::FCOS, VT, Expand);
437 setOperationAction(ISD::FABS, VT, Expand);
438 setOperationAction(ISD::FPOWI, VT, Expand);
439 setOperationAction(ISD::FFLOOR, VT, Expand);
440 setOperationAction(ISD::FCEIL, VT, Expand);
441 setOperationAction(ISD::FTRUNC, VT, Expand);
442 setOperationAction(ISD::FRINT, VT, Expand);
443 setOperationAction(ISD::FNEARBYINT, VT, Expand);
444 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
445 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
446 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
447 setOperationAction(ISD::MULHU, VT, Expand);
448 setOperationAction(ISD::MULHS, VT, Expand);
449 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
450 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
451 setOperationAction(ISD::UDIVREM, VT, Expand);
452 setOperationAction(ISD::SDIVREM, VT, Expand);
453 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
454 setOperationAction(ISD::FPOW, VT, Expand);
455 setOperationAction(ISD::BSWAP, VT, Expand);
456 setOperationAction(ISD::CTPOP, VT, Expand);
457 setOperationAction(ISD::CTLZ, VT, Expand);
458 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
459 setOperationAction(ISD::CTTZ, VT, Expand);
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::VSELECT, VT, Expand);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
464 for (MVT InnerVT : MVT::vector_valuetypes())
465 setTruncStoreAction(VT, InnerVT, Expand);
466 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
467 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
468 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
471 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
472 // with merges, splats, etc.
473 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
475 setOperationAction(ISD::AND , MVT::v4i32, Legal);
476 setOperationAction(ISD::OR , MVT::v4i32, Legal);
477 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
478 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
479 setOperationAction(ISD::SELECT, MVT::v4i32,
480 Subtarget.useCRBits() ? Legal : Expand);
481 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
482 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
483 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
484 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
485 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
486 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
487 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
488 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
489 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
491 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
492 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
493 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
494 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
496 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
497 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
499 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
500 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
501 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
504 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
505 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
506 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
508 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
509 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
511 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
512 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
513 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
516 // Altivec does not contain unordered floating-point compare instructions
517 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
518 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
519 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
520 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
522 if (Subtarget.hasVSX()) {
523 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
524 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
526 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
528 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
529 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
530 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
532 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
534 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
535 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
537 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
538 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
540 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
541 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
542 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
546 // Share the Altivec comparison restrictions.
547 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
548 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
549 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
550 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
552 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
553 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
555 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
557 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
559 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
560 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
562 // VSX v2i64 only supports non-arithmetic operations.
563 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
564 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
566 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
567 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
568 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
572 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
573 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
574 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
575 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
579 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
580 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
581 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
582 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
584 // Vector operation legalization checks the result type of
585 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
586 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
587 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
588 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
591 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
595 if (Subtarget.has64BitSupport())
596 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
598 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
601 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
602 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
605 setBooleanContents(ZeroOrOneBooleanContent);
606 // Altivec instructions set fields to all zeros or all ones.
607 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
610 // These libcalls are not available in 32-bit.
611 setLibcallName(RTLIB::SHL_I128, nullptr);
612 setLibcallName(RTLIB::SRL_I128, nullptr);
613 setLibcallName(RTLIB::SRA_I128, nullptr);
617 setStackPointerRegisterToSaveRestore(PPC::X1);
618 setExceptionPointerRegister(PPC::X3);
619 setExceptionSelectorRegister(PPC::X4);
621 setStackPointerRegisterToSaveRestore(PPC::R1);
622 setExceptionPointerRegister(PPC::R3);
623 setExceptionSelectorRegister(PPC::R4);
626 // We have target-specific dag combine patterns for the following nodes:
627 setTargetDAGCombine(ISD::SINT_TO_FP);
628 if (Subtarget.hasFPCVT())
629 setTargetDAGCombine(ISD::UINT_TO_FP);
630 setTargetDAGCombine(ISD::LOAD);
631 setTargetDAGCombine(ISD::STORE);
632 setTargetDAGCombine(ISD::BR_CC);
633 if (Subtarget.useCRBits())
634 setTargetDAGCombine(ISD::BRCOND);
635 setTargetDAGCombine(ISD::BSWAP);
636 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
637 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
638 setTargetDAGCombine(ISD::INTRINSIC_VOID);
640 setTargetDAGCombine(ISD::SIGN_EXTEND);
641 setTargetDAGCombine(ISD::ZERO_EXTEND);
642 setTargetDAGCombine(ISD::ANY_EXTEND);
644 if (Subtarget.useCRBits()) {
645 setTargetDAGCombine(ISD::TRUNCATE);
646 setTargetDAGCombine(ISD::SETCC);
647 setTargetDAGCombine(ISD::SELECT_CC);
650 // Use reciprocal estimates.
651 if (TM.Options.UnsafeFPMath) {
652 setTargetDAGCombine(ISD::FDIV);
653 setTargetDAGCombine(ISD::FSQRT);
656 // Darwin long double math library functions have $LDBL128 appended.
657 if (Subtarget.isDarwin()) {
658 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
659 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
660 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
661 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
662 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
663 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
664 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
665 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
666 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
667 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
670 // With 32 condition bits, we don't need to sink (and duplicate) compares
671 // aggressively in CodeGenPrep.
672 if (Subtarget.useCRBits())
673 setHasMultipleConditionRegisters();
675 setMinFunctionAlignment(2);
676 if (Subtarget.isDarwin())
677 setPrefFunctionAlignment(4);
679 switch (Subtarget.getDarwinDirective()) {
683 case PPC::DIR_E500mc:
692 setPrefFunctionAlignment(4);
693 setPrefLoopAlignment(4);
697 setInsertFencesForAtomic(true);
699 if (Subtarget.enableMachineScheduler())
700 setSchedulingPreference(Sched::Source);
702 setSchedulingPreference(Sched::Hybrid);
704 computeRegisterProperties();
706 // The Freescale cores do better with aggressive inlining of memcpy and
707 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
708 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
709 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
710 MaxStoresPerMemset = 32;
711 MaxStoresPerMemsetOptSize = 16;
712 MaxStoresPerMemcpy = 32;
713 MaxStoresPerMemcpyOptSize = 8;
714 MaxStoresPerMemmove = 32;
715 MaxStoresPerMemmoveOptSize = 8;
719 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
720 /// the desired ByVal argument alignment.
721 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
722 unsigned MaxMaxAlign) {
723 if (MaxAlign == MaxMaxAlign)
725 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
726 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
728 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
730 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
731 unsigned EltAlign = 0;
732 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
733 if (EltAlign > MaxAlign)
735 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
736 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
737 unsigned EltAlign = 0;
738 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
739 if (EltAlign > MaxAlign)
741 if (MaxAlign == MaxMaxAlign)
747 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
748 /// function arguments in the caller parameter area.
749 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
750 // Darwin passes everything on 4 byte boundary.
751 if (Subtarget.isDarwin())
754 // 16byte and wider vectors are passed on 16byte boundary.
755 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
756 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
757 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
758 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
762 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
764 default: return nullptr;
765 case PPCISD::FSEL: return "PPCISD::FSEL";
766 case PPCISD::FCFID: return "PPCISD::FCFID";
767 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
768 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
769 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
770 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
771 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
772 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
773 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
774 case PPCISD::FRE: return "PPCISD::FRE";
775 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
776 case PPCISD::STFIWX: return "PPCISD::STFIWX";
777 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
778 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
779 case PPCISD::VPERM: return "PPCISD::VPERM";
780 case PPCISD::CMPB: return "PPCISD::CMPB";
781 case PPCISD::Hi: return "PPCISD::Hi";
782 case PPCISD::Lo: return "PPCISD::Lo";
783 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
784 case PPCISD::LOAD: return "PPCISD::LOAD";
785 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
786 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
787 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
788 case PPCISD::SRL: return "PPCISD::SRL";
789 case PPCISD::SRA: return "PPCISD::SRA";
790 case PPCISD::SHL: return "PPCISD::SHL";
791 case PPCISD::CALL: return "PPCISD::CALL";
792 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
793 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
794 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
795 case PPCISD::MTCTR: return "PPCISD::MTCTR";
796 case PPCISD::BCTRL: return "PPCISD::BCTRL";
797 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
798 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
799 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
800 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
801 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
802 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
803 case PPCISD::VCMP: return "PPCISD::VCMP";
804 case PPCISD::VCMPo: return "PPCISD::VCMPo";
805 case PPCISD::LBRX: return "PPCISD::LBRX";
806 case PPCISD::STBRX: return "PPCISD::STBRX";
807 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
808 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
809 case PPCISD::LARX: return "PPCISD::LARX";
810 case PPCISD::STCX: return "PPCISD::STCX";
811 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
812 case PPCISD::BDNZ: return "PPCISD::BDNZ";
813 case PPCISD::BDZ: return "PPCISD::BDZ";
814 case PPCISD::MFFS: return "PPCISD::MFFS";
815 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
816 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
817 case PPCISD::CR6SET: return "PPCISD::CR6SET";
818 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
819 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
820 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
821 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
822 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
823 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
824 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
825 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
826 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
827 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
828 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
829 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
830 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
831 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
832 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
833 case PPCISD::SC: return "PPCISD::SC";
837 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
839 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
840 return VT.changeVectorElementTypeToInteger();
843 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
844 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
848 //===----------------------------------------------------------------------===//
849 // Node matching predicates, for use by the tblgen matching code.
850 //===----------------------------------------------------------------------===//
852 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
853 static bool isFloatingPointZero(SDValue Op) {
854 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
855 return CFP->getValueAPF().isZero();
856 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
857 // Maybe this has already been legalized into the constant pool?
858 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
859 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
860 return CFP->getValueAPF().isZero();
865 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
866 /// true if Op is undef or if it matches the specified value.
867 static bool isConstantOrUndef(int Op, int Val) {
868 return Op < 0 || Op == Val;
871 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
872 /// VPKUHUM instruction.
873 /// The ShuffleKind distinguishes between big-endian operations with
874 /// two different inputs (0), either-endian operations with two identical
875 /// inputs (1), and little-endian operantion with two different inputs (2).
876 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
877 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
879 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
880 if (ShuffleKind == 0) {
883 for (unsigned i = 0; i != 16; ++i)
884 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
886 } else if (ShuffleKind == 2) {
889 for (unsigned i = 0; i != 16; ++i)
890 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
892 } else if (ShuffleKind == 1) {
893 unsigned j = IsLE ? 0 : 1;
894 for (unsigned i = 0; i != 8; ++i)
895 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
896 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
902 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
903 /// VPKUWUM instruction.
904 /// The ShuffleKind distinguishes between big-endian operations with
905 /// two different inputs (0), either-endian operations with two identical
906 /// inputs (1), and little-endian operantion with two different inputs (2).
907 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
908 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
910 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
911 if (ShuffleKind == 0) {
914 for (unsigned i = 0; i != 16; i += 2)
915 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
916 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
918 } else if (ShuffleKind == 2) {
921 for (unsigned i = 0; i != 16; i += 2)
922 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
923 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
925 } else if (ShuffleKind == 1) {
926 unsigned j = IsLE ? 0 : 2;
927 for (unsigned i = 0; i != 8; i += 2)
928 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
929 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
930 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
931 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
937 /// isVMerge - Common function, used to match vmrg* shuffles.
939 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
940 unsigned LHSStart, unsigned RHSStart) {
941 if (N->getValueType(0) != MVT::v16i8)
943 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
944 "Unsupported merge size!");
946 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
947 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
948 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
949 LHSStart+j+i*UnitSize) ||
950 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
951 RHSStart+j+i*UnitSize))
957 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
958 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
959 /// The ShuffleKind distinguishes between big-endian merges with two
960 /// different inputs (0), either-endian merges with two identical inputs (1),
961 /// and little-endian merges with two different inputs (2). For the latter,
962 /// the input operands are swapped (see PPCInstrAltivec.td).
963 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
964 unsigned ShuffleKind, SelectionDAG &DAG) {
965 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
966 if (ShuffleKind == 1) // unary
967 return isVMerge(N, UnitSize, 0, 0);
968 else if (ShuffleKind == 2) // swapped
969 return isVMerge(N, UnitSize, 0, 16);
973 if (ShuffleKind == 1) // unary
974 return isVMerge(N, UnitSize, 8, 8);
975 else if (ShuffleKind == 0) // normal
976 return isVMerge(N, UnitSize, 8, 24);
982 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
983 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
984 /// The ShuffleKind distinguishes between big-endian merges with two
985 /// different inputs (0), either-endian merges with two identical inputs (1),
986 /// and little-endian merges with two different inputs (2). For the latter,
987 /// the input operands are swapped (see PPCInstrAltivec.td).
988 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
989 unsigned ShuffleKind, SelectionDAG &DAG) {
990 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
991 if (ShuffleKind == 1) // unary
992 return isVMerge(N, UnitSize, 8, 8);
993 else if (ShuffleKind == 2) // swapped
994 return isVMerge(N, UnitSize, 8, 24);
998 if (ShuffleKind == 1) // unary
999 return isVMerge(N, UnitSize, 0, 0);
1000 else if (ShuffleKind == 0) // normal
1001 return isVMerge(N, UnitSize, 0, 16);
1008 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1009 /// amount, otherwise return -1.
1010 /// The ShuffleKind distinguishes between big-endian operations with two
1011 /// different inputs (0), either-endian operations with two identical inputs
1012 /// (1), and little-endian operations with two different inputs (2). For the
1013 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1014 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1015 SelectionDAG &DAG) {
1016 if (N->getValueType(0) != MVT::v16i8)
1019 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1021 // Find the first non-undef value in the shuffle mask.
1023 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1026 if (i == 16) return -1; // all undef.
1028 // Otherwise, check to see if the rest of the elements are consecutively
1029 // numbered from this value.
1030 unsigned ShiftAmt = SVOp->getMaskElt(i);
1031 if (ShiftAmt < i) return -1;
1034 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1037 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1038 // Check the rest of the elements to see if they are consecutive.
1039 for (++i; i != 16; ++i)
1040 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1042 } else if (ShuffleKind == 1) {
1043 // Check the rest of the elements to see if they are consecutive.
1044 for (++i; i != 16; ++i)
1045 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1050 if (ShuffleKind == 2 && isLE)
1051 ShiftAmt = 16 - ShiftAmt;
1056 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1057 /// specifies a splat of a single element that is suitable for input to
1058 /// VSPLTB/VSPLTH/VSPLTW.
1059 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1060 assert(N->getValueType(0) == MVT::v16i8 &&
1061 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1063 // This is a splat operation if each element of the permute is the same, and
1064 // if the value doesn't reference the second vector.
1065 unsigned ElementBase = N->getMaskElt(0);
1067 // FIXME: Handle UNDEF elements too!
1068 if (ElementBase >= 16)
1071 // Check that the indices are consecutive, in the case of a multi-byte element
1072 // splatted with a v16i8 mask.
1073 for (unsigned i = 1; i != EltSize; ++i)
1074 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1077 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1078 if (N->getMaskElt(i) < 0) continue;
1079 for (unsigned j = 0; j != EltSize; ++j)
1080 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1086 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1088 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1089 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1091 APInt APVal, APUndef;
1095 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1096 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1097 return CFP->getValueAPF().isNegZero();
1102 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1103 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1104 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1105 SelectionDAG &DAG) {
1106 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1107 assert(isSplatShuffleMask(SVOp, EltSize));
1108 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1109 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1111 return SVOp->getMaskElt(0) / EltSize;
1114 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1115 /// by using a vspltis[bhw] instruction of the specified element size, return
1116 /// the constant being splatted. The ByteSize field indicates the number of
1117 /// bytes of each element [124] -> [bhw].
1118 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1119 SDValue OpVal(nullptr, 0);
1121 // If ByteSize of the splat is bigger than the element size of the
1122 // build_vector, then we have a case where we are checking for a splat where
1123 // multiple elements of the buildvector are folded together into a single
1124 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1125 unsigned EltSize = 16/N->getNumOperands();
1126 if (EltSize < ByteSize) {
1127 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1128 SDValue UniquedVals[4];
1129 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1131 // See if all of the elements in the buildvector agree across.
1132 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1133 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1134 // If the element isn't a constant, bail fully out.
1135 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1138 if (!UniquedVals[i&(Multiple-1)].getNode())
1139 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1140 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1141 return SDValue(); // no match.
1144 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1145 // either constant or undef values that are identical for each chunk. See
1146 // if these chunks can form into a larger vspltis*.
1148 // Check to see if all of the leading entries are either 0 or -1. If
1149 // neither, then this won't fit into the immediate field.
1150 bool LeadingZero = true;
1151 bool LeadingOnes = true;
1152 for (unsigned i = 0; i != Multiple-1; ++i) {
1153 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1155 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1156 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1158 // Finally, check the least significant entry.
1160 if (!UniquedVals[Multiple-1].getNode())
1161 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1162 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1164 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1167 if (!UniquedVals[Multiple-1].getNode())
1168 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1169 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1170 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1171 return DAG.getTargetConstant(Val, MVT::i32);
1177 // Check to see if this buildvec has a single non-undef value in its elements.
1178 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1179 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1180 if (!OpVal.getNode())
1181 OpVal = N->getOperand(i);
1182 else if (OpVal != N->getOperand(i))
1186 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1188 unsigned ValSizeInBytes = EltSize;
1190 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1191 Value = CN->getZExtValue();
1192 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1193 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1194 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1197 // If the splat value is larger than the element value, then we can never do
1198 // this splat. The only case that we could fit the replicated bits into our
1199 // immediate field for would be zero, and we prefer to use vxor for it.
1200 if (ValSizeInBytes < ByteSize) return SDValue();
1202 // If the element value is larger than the splat value, cut it in half and
1203 // check to see if the two halves are equal. Continue doing this until we
1204 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1205 while (ValSizeInBytes > ByteSize) {
1206 ValSizeInBytes >>= 1;
1208 // If the top half equals the bottom half, we're still ok.
1209 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1210 (Value & ((1 << (8*ValSizeInBytes))-1)))
1214 // Properly sign extend the value.
1215 int MaskVal = SignExtend32(Value, ByteSize * 8);
1217 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1218 if (MaskVal == 0) return SDValue();
1220 // Finally, if this value fits in a 5 bit sext field, return it
1221 if (SignExtend32<5>(MaskVal) == MaskVal)
1222 return DAG.getTargetConstant(MaskVal, MVT::i32);
1226 //===----------------------------------------------------------------------===//
1227 // Addressing Mode Selection
1228 //===----------------------------------------------------------------------===//
1230 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1231 /// or 64-bit immediate, and if the value can be accurately represented as a
1232 /// sign extension from a 16-bit value. If so, this returns true and the
1234 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1235 if (!isa<ConstantSDNode>(N))
1238 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1239 if (N->getValueType(0) == MVT::i32)
1240 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1242 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1244 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1245 return isIntS16Immediate(Op.getNode(), Imm);
1249 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1250 /// can be represented as an indexed [r+r] operation. Returns false if it
1251 /// can be more efficiently represented with [r+imm].
1252 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1254 SelectionDAG &DAG) const {
1256 if (N.getOpcode() == ISD::ADD) {
1257 if (isIntS16Immediate(N.getOperand(1), imm))
1258 return false; // r+i
1259 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1260 return false; // r+i
1262 Base = N.getOperand(0);
1263 Index = N.getOperand(1);
1265 } else if (N.getOpcode() == ISD::OR) {
1266 if (isIntS16Immediate(N.getOperand(1), imm))
1267 return false; // r+i can fold it if we can.
1269 // If this is an or of disjoint bitfields, we can codegen this as an add
1270 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1272 APInt LHSKnownZero, LHSKnownOne;
1273 APInt RHSKnownZero, RHSKnownOne;
1274 DAG.computeKnownBits(N.getOperand(0),
1275 LHSKnownZero, LHSKnownOne);
1277 if (LHSKnownZero.getBoolValue()) {
1278 DAG.computeKnownBits(N.getOperand(1),
1279 RHSKnownZero, RHSKnownOne);
1280 // If all of the bits are known zero on the LHS or RHS, the add won't
1282 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1283 Base = N.getOperand(0);
1284 Index = N.getOperand(1);
1293 // If we happen to be doing an i64 load or store into a stack slot that has
1294 // less than a 4-byte alignment, then the frame-index elimination may need to
1295 // use an indexed load or store instruction (because the offset may not be a
1296 // multiple of 4). The extra register needed to hold the offset comes from the
1297 // register scavenger, and it is possible that the scavenger will need to use
1298 // an emergency spill slot. As a result, we need to make sure that a spill slot
1299 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1301 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1302 // FIXME: This does not handle the LWA case.
1306 // NOTE: We'll exclude negative FIs here, which come from argument
1307 // lowering, because there are no known test cases triggering this problem
1308 // using packed structures (or similar). We can remove this exclusion if
1309 // we find such a test case. The reason why this is so test-case driven is
1310 // because this entire 'fixup' is only to prevent crashes (from the
1311 // register scavenger) on not-really-valid inputs. For example, if we have:
1313 // %b = bitcast i1* %a to i64*
1314 // store i64* a, i64 b
1315 // then the store should really be marked as 'align 1', but is not. If it
1316 // were marked as 'align 1' then the indexed form would have been
1317 // instruction-selected initially, and the problem this 'fixup' is preventing
1318 // won't happen regardless.
1322 MachineFunction &MF = DAG.getMachineFunction();
1323 MachineFrameInfo *MFI = MF.getFrameInfo();
1325 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1329 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1330 FuncInfo->setHasNonRISpills();
1333 /// Returns true if the address N can be represented by a base register plus
1334 /// a signed 16-bit displacement [r+imm], and if it is not better
1335 /// represented as reg+reg. If Aligned is true, only accept displacements
1336 /// suitable for STD and friends, i.e. multiples of 4.
1337 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1340 bool Aligned) const {
1341 // FIXME dl should come from parent load or store, not from address
1343 // If this can be more profitably realized as r+r, fail.
1344 if (SelectAddressRegReg(N, Disp, Base, DAG))
1347 if (N.getOpcode() == ISD::ADD) {
1349 if (isIntS16Immediate(N.getOperand(1), imm) &&
1350 (!Aligned || (imm & 3) == 0)) {
1351 Disp = DAG.getTargetConstant(imm, N.getValueType());
1352 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1353 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1354 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1356 Base = N.getOperand(0);
1358 return true; // [r+i]
1359 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1360 // Match LOAD (ADD (X, Lo(G))).
1361 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1362 && "Cannot handle constant offsets yet!");
1363 Disp = N.getOperand(1).getOperand(0); // The global address.
1364 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1365 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1366 Disp.getOpcode() == ISD::TargetConstantPool ||
1367 Disp.getOpcode() == ISD::TargetJumpTable);
1368 Base = N.getOperand(0);
1369 return true; // [&g+r]
1371 } else if (N.getOpcode() == ISD::OR) {
1373 if (isIntS16Immediate(N.getOperand(1), imm) &&
1374 (!Aligned || (imm & 3) == 0)) {
1375 // If this is an or of disjoint bitfields, we can codegen this as an add
1376 // (for better address arithmetic) if the LHS and RHS of the OR are
1377 // provably disjoint.
1378 APInt LHSKnownZero, LHSKnownOne;
1379 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1381 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1382 // If all of the bits are known zero on the LHS or RHS, the add won't
1384 if (FrameIndexSDNode *FI =
1385 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1386 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1387 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1389 Base = N.getOperand(0);
1391 Disp = DAG.getTargetConstant(imm, N.getValueType());
1395 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1396 // Loading from a constant address.
1398 // If this address fits entirely in a 16-bit sext immediate field, codegen
1401 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1402 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1403 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 CN->getValueType(0));
1408 // Handle 32-bit sext immediates with LIS + addr mode.
1409 if ((CN->getValueType(0) == MVT::i32 ||
1410 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1411 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1412 int Addr = (int)CN->getZExtValue();
1414 // Otherwise, break this down into an LIS + disp.
1415 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1417 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1418 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1419 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1424 Disp = DAG.getTargetConstant(0, getPointerTy());
1425 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1426 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1427 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1430 return true; // [r+0]
1433 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1434 /// represented as an indexed [r+r] operation.
1435 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1437 SelectionDAG &DAG) const {
1438 // Check to see if we can easily represent this as an [r+r] address. This
1439 // will fail if it thinks that the address is more profitably represented as
1440 // reg+imm, e.g. where imm = 0.
1441 if (SelectAddressRegReg(N, Base, Index, DAG))
1444 // If the operand is an addition, always emit this as [r+r], since this is
1445 // better (for code size, and execution, as the memop does the add for free)
1446 // than emitting an explicit add.
1447 if (N.getOpcode() == ISD::ADD) {
1448 Base = N.getOperand(0);
1449 Index = N.getOperand(1);
1453 // Otherwise, do it the hard way, using R0 as the base register.
1454 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1460 /// getPreIndexedAddressParts - returns true by value, base pointer and
1461 /// offset pointer and addressing mode by reference if the node's address
1462 /// can be legally represented as pre-indexed load / store address.
1463 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1465 ISD::MemIndexedMode &AM,
1466 SelectionDAG &DAG) const {
1467 if (DisablePPCPreinc) return false;
1473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1474 Ptr = LD->getBasePtr();
1475 VT = LD->getMemoryVT();
1476 Alignment = LD->getAlignment();
1477 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1478 Ptr = ST->getBasePtr();
1479 VT = ST->getMemoryVT();
1480 Alignment = ST->getAlignment();
1485 // PowerPC doesn't have preinc load/store instructions for vectors.
1489 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1491 // Common code will reject creating a pre-inc form if the base pointer
1492 // is a frame index, or if N is a store and the base pointer is either
1493 // the same as or a predecessor of the value being stored. Check for
1494 // those situations here, and try with swapped Base/Offset instead.
1497 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1500 SDValue Val = cast<StoreSDNode>(N)->getValue();
1501 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1506 std::swap(Base, Offset);
1512 // LDU/STU can only handle immediates that are a multiple of 4.
1513 if (VT != MVT::i64) {
1514 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1517 // LDU/STU need an address with at least 4-byte alignment.
1521 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1525 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1526 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1527 // sext i32 to i64 when addr mode is r+i.
1528 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1529 LD->getExtensionType() == ISD::SEXTLOAD &&
1530 isa<ConstantSDNode>(Offset))
1538 //===----------------------------------------------------------------------===//
1539 // LowerOperation implementation
1540 //===----------------------------------------------------------------------===//
1542 /// GetLabelAccessInfo - Return true if we should reference labels using a
1543 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1544 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1545 unsigned &LoOpFlags,
1546 const GlobalValue *GV = nullptr) {
1547 HiOpFlags = PPCII::MO_HA;
1548 LoOpFlags = PPCII::MO_LO;
1550 // Don't use the pic base if not in PIC relocation model.
1551 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1554 HiOpFlags |= PPCII::MO_PIC_FLAG;
1555 LoOpFlags |= PPCII::MO_PIC_FLAG;
1558 // If this is a reference to a global value that requires a non-lazy-ptr, make
1559 // sure that instruction lowering adds it.
1560 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1561 HiOpFlags |= PPCII::MO_NLP_FLAG;
1562 LoOpFlags |= PPCII::MO_NLP_FLAG;
1564 if (GV->hasHiddenVisibility()) {
1565 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1566 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1573 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1574 SelectionDAG &DAG) {
1575 EVT PtrVT = HiPart.getValueType();
1576 SDValue Zero = DAG.getConstant(0, PtrVT);
1579 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1580 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1582 // With PIC, the first instruction is actually "GR+hi(&G)".
1584 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1585 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1587 // Generate non-pic code that has direct accesses to the constant pool.
1588 // The address of the global is just (hi(&g)+lo(&g)).
1589 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1592 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1593 SelectionDAG &DAG) const {
1594 EVT PtrVT = Op.getValueType();
1595 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1596 const Constant *C = CP->getConstVal();
1598 // 64-bit SVR4 ABI code is always position-independent.
1599 // The actual address of the GlobalValue is stored in the TOC.
1600 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1601 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1602 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1603 DAG.getRegister(PPC::X2, MVT::i64));
1606 unsigned MOHiFlag, MOLoFlag;
1607 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1609 if (isPIC && Subtarget.isSVR4ABI()) {
1610 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1611 PPCII::MO_PIC_FLAG);
1613 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1614 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1618 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1620 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1621 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1624 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1625 EVT PtrVT = Op.getValueType();
1626 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1628 // 64-bit SVR4 ABI code is always position-independent.
1629 // The actual address of the GlobalValue is stored in the TOC.
1630 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1631 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1632 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1633 DAG.getRegister(PPC::X2, MVT::i64));
1636 unsigned MOHiFlag, MOLoFlag;
1637 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1639 if (isPIC && Subtarget.isSVR4ABI()) {
1640 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1641 PPCII::MO_PIC_FLAG);
1643 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1644 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1647 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1648 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1649 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1652 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1653 SelectionDAG &DAG) const {
1654 EVT PtrVT = Op.getValueType();
1655 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1656 const BlockAddress *BA = BASDN->getBlockAddress();
1658 // 64-bit SVR4 ABI code is always position-independent.
1659 // The actual BlockAddress is stored in the TOC.
1660 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1661 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1662 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1663 DAG.getRegister(PPC::X2, MVT::i64));
1666 unsigned MOHiFlag, MOLoFlag;
1667 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1668 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1669 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1670 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1673 // Generate a call to __tls_get_addr for the given GOT entry Op.
1674 std::pair<SDValue,SDValue>
1675 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1676 SelectionDAG &DAG) const {
1678 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1679 TargetLowering::ArgListTy Args;
1680 TargetLowering::ArgListEntry Entry;
1682 Entry.Ty = IntPtrTy;
1683 Args.push_back(Entry);
1685 TargetLowering::CallLoweringInfo CLI(DAG);
1686 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1687 .setCallee(CallingConv::C, IntPtrTy,
1688 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1689 std::move(Args), 0);
1691 return LowerCallTo(CLI);
1694 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1695 SelectionDAG &DAG) const {
1697 // FIXME: TLS addresses currently use medium model code sequences,
1698 // which is the most useful form. Eventually support for small and
1699 // large models could be added if users need it, at the cost of
1700 // additional complexity.
1701 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1703 const GlobalValue *GV = GA->getGlobal();
1704 EVT PtrVT = getPointerTy();
1705 bool is64bit = Subtarget.isPPC64();
1706 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1707 PICLevel::Level picLevel = M->getPICLevel();
1709 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1711 if (Model == TLSModel::LocalExec) {
1712 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1713 PPCII::MO_TPREL_HA);
1714 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1715 PPCII::MO_TPREL_LO);
1716 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1717 is64bit ? MVT::i64 : MVT::i32);
1718 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1719 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1722 if (Model == TLSModel::InitialExec) {
1723 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1724 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1728 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1729 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1730 PtrVT, GOTReg, TGA);
1732 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1733 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1734 PtrVT, TGA, GOTPtr);
1735 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1738 if (Model == TLSModel::GeneralDynamic) {
1739 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1743 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1744 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1747 if (picLevel == PICLevel::Small)
1748 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1750 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1752 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1754 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1755 return CallResult.first;
1758 if (Model == TLSModel::LocalDynamic) {
1759 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1763 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1764 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1767 if (picLevel == PICLevel::Small)
1768 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1770 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1772 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1774 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1775 SDValue TLSAddr = CallResult.first;
1776 SDValue Chain = CallResult.second;
1777 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1778 Chain, TLSAddr, TGA);
1779 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1782 llvm_unreachable("Unknown TLS model!");
1785 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1786 SelectionDAG &DAG) const {
1787 EVT PtrVT = Op.getValueType();
1788 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1790 const GlobalValue *GV = GSDN->getGlobal();
1792 // 64-bit SVR4 ABI code is always position-independent.
1793 // The actual address of the GlobalValue is stored in the TOC.
1794 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1795 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1796 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1797 DAG.getRegister(PPC::X2, MVT::i64));
1800 unsigned MOHiFlag, MOLoFlag;
1801 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1803 if (isPIC && Subtarget.isSVR4ABI()) {
1804 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1806 PPCII::MO_PIC_FLAG);
1807 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1808 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1812 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1814 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1816 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1818 // If the global reference is actually to a non-lazy-pointer, we have to do an
1819 // extra load to get the address of the global.
1820 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1821 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1822 false, false, false, 0);
1826 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1827 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1830 if (Op.getValueType() == MVT::v2i64) {
1831 // When the operands themselves are v2i64 values, we need to do something
1832 // special because VSX has no underlying comparison operations for these.
1833 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1834 // Equality can be handled by casting to the legal type for Altivec
1835 // comparisons, everything else needs to be expanded.
1836 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1837 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1838 DAG.getSetCC(dl, MVT::v4i32,
1839 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1840 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1847 // We handle most of these in the usual way.
1851 // If we're comparing for equality to zero, expose the fact that this is
1852 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1853 // fold the new nodes.
1854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1855 if (C->isNullValue() && CC == ISD::SETEQ) {
1856 EVT VT = Op.getOperand(0).getValueType();
1857 SDValue Zext = Op.getOperand(0);
1858 if (VT.bitsLT(MVT::i32)) {
1860 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1862 unsigned Log2b = Log2_32(VT.getSizeInBits());
1863 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1864 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1865 DAG.getConstant(Log2b, MVT::i32));
1866 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1868 // Leave comparisons against 0 and -1 alone for now, since they're usually
1869 // optimized. FIXME: revisit this when we can custom lower all setcc
1871 if (C->isAllOnesValue() || C->isNullValue())
1875 // If we have an integer seteq/setne, turn it into a compare against zero
1876 // by xor'ing the rhs with the lhs, which is faster than setting a
1877 // condition register, reading it back out, and masking the correct bit. The
1878 // normal approach here uses sub to do this instead of xor. Using xor exposes
1879 // the result to other bit-twiddling opportunities.
1880 EVT LHSVT = Op.getOperand(0).getValueType();
1881 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1882 EVT VT = Op.getValueType();
1883 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1885 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1890 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 SDNode *Node = Op.getNode();
1893 EVT VT = Node->getValueType(0);
1894 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1895 SDValue InChain = Node->getOperand(0);
1896 SDValue VAListPtr = Node->getOperand(1);
1897 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1900 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1903 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1904 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1905 false, false, false, 0);
1906 InChain = GprIndex.getValue(1);
1908 if (VT == MVT::i64) {
1909 // Check if GprIndex is even
1910 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1911 DAG.getConstant(1, MVT::i32));
1912 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1913 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1914 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1915 DAG.getConstant(1, MVT::i32));
1916 // Align GprIndex to be even if it isn't
1917 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1921 // fpr index is 1 byte after gpr
1922 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1923 DAG.getConstant(1, MVT::i32));
1926 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1927 FprPtr, MachinePointerInfo(SV), MVT::i8,
1928 false, false, false, 0);
1929 InChain = FprIndex.getValue(1);
1931 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1932 DAG.getConstant(8, MVT::i32));
1934 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1935 DAG.getConstant(4, MVT::i32));
1938 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1939 MachinePointerInfo(), false, false,
1941 InChain = OverflowArea.getValue(1);
1943 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1944 MachinePointerInfo(), false, false,
1946 InChain = RegSaveArea.getValue(1);
1948 // select overflow_area if index > 8
1949 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1950 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1952 // adjustment constant gpr_index * 4/8
1953 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1954 VT.isInteger() ? GprIndex : FprIndex,
1955 DAG.getConstant(VT.isInteger() ? 4 : 8,
1958 // OurReg = RegSaveArea + RegConstant
1959 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1962 // Floating types are 32 bytes into RegSaveArea
1963 if (VT.isFloatingPoint())
1964 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1965 DAG.getConstant(32, MVT::i32));
1967 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1968 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1969 VT.isInteger() ? GprIndex : FprIndex,
1970 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1973 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1974 VT.isInteger() ? VAListPtr : FprPtr,
1975 MachinePointerInfo(SV),
1976 MVT::i8, false, false, 0);
1978 // determine if we should load from reg_save_area or overflow_area
1979 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1981 // increase overflow_area by 4/8 if gpr/fpr > 8
1982 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1983 DAG.getConstant(VT.isInteger() ? 4 : 8,
1986 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1989 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1991 MachinePointerInfo(),
1992 MVT::i32, false, false, 0);
1994 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1995 false, false, false, 0);
1998 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1999 const PPCSubtarget &Subtarget) const {
2000 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2002 // We have to copy the entire va_list struct:
2003 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2004 return DAG.getMemcpy(Op.getOperand(0), Op,
2005 Op.getOperand(1), Op.getOperand(2),
2006 DAG.getConstant(12, MVT::i32), 8, false, true,
2007 MachinePointerInfo(), MachinePointerInfo());
2010 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2011 SelectionDAG &DAG) const {
2012 return Op.getOperand(0);
2015 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2016 SelectionDAG &DAG) const {
2017 SDValue Chain = Op.getOperand(0);
2018 SDValue Trmp = Op.getOperand(1); // trampoline
2019 SDValue FPtr = Op.getOperand(2); // nested function
2020 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2023 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2024 bool isPPC64 = (PtrVT == MVT::i64);
2026 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2029 TargetLowering::ArgListTy Args;
2030 TargetLowering::ArgListEntry Entry;
2032 Entry.Ty = IntPtrTy;
2033 Entry.Node = Trmp; Args.push_back(Entry);
2035 // TrampSize == (isPPC64 ? 48 : 40);
2036 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2037 isPPC64 ? MVT::i64 : MVT::i32);
2038 Args.push_back(Entry);
2040 Entry.Node = FPtr; Args.push_back(Entry);
2041 Entry.Node = Nest; Args.push_back(Entry);
2043 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2044 TargetLowering::CallLoweringInfo CLI(DAG);
2045 CLI.setDebugLoc(dl).setChain(Chain)
2046 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2047 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2048 std::move(Args), 0);
2050 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2051 return CallResult.second;
2054 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2055 const PPCSubtarget &Subtarget) const {
2056 MachineFunction &MF = DAG.getMachineFunction();
2057 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2061 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2062 // vastart just stores the address of the VarArgsFrameIndex slot into the
2063 // memory location argument.
2064 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2065 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2066 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2067 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2068 MachinePointerInfo(SV),
2072 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2073 // We suppose the given va_list is already allocated.
2076 // char gpr; /* index into the array of 8 GPRs
2077 // * stored in the register save area
2078 // * gpr=0 corresponds to r3,
2079 // * gpr=1 to r4, etc.
2081 // char fpr; /* index into the array of 8 FPRs
2082 // * stored in the register save area
2083 // * fpr=0 corresponds to f1,
2084 // * fpr=1 to f2, etc.
2086 // char *overflow_arg_area;
2087 // /* location on stack that holds
2088 // * the next overflow argument
2090 // char *reg_save_area;
2091 // /* where r3:r10 and f1:f8 (if saved)
2097 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2098 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2101 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2103 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2105 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2108 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2109 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2111 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2112 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2114 uint64_t FPROffset = 1;
2115 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2117 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2119 // Store first byte : number of int regs
2120 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2122 MachinePointerInfo(SV),
2123 MVT::i8, false, false, 0);
2124 uint64_t nextOffset = FPROffset;
2125 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2128 // Store second byte : number of float regs
2129 SDValue secondStore =
2130 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2131 MachinePointerInfo(SV, nextOffset), MVT::i8,
2133 nextOffset += StackOffset;
2134 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2136 // Store second word : arguments given on stack
2137 SDValue thirdStore =
2138 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2139 MachinePointerInfo(SV, nextOffset),
2141 nextOffset += FrameOffset;
2142 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2144 // Store third word : arguments given in registers
2145 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2146 MachinePointerInfo(SV, nextOffset),
2151 #include "PPCGenCallingConv.inc"
2153 // Function whose sole purpose is to kill compiler warnings
2154 // stemming from unused functions included from PPCGenCallingConv.inc.
2155 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2156 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2159 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2160 CCValAssign::LocInfo &LocInfo,
2161 ISD::ArgFlagsTy &ArgFlags,
2166 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2168 CCValAssign::LocInfo &LocInfo,
2169 ISD::ArgFlagsTy &ArgFlags,
2171 static const MCPhysReg ArgRegs[] = {
2172 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2173 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2175 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2177 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2179 // Skip one register if the first unallocated register has an even register
2180 // number and there are still argument registers available which have not been
2181 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2182 // need to skip a register if RegNum is odd.
2183 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2184 State.AllocateReg(ArgRegs[RegNum]);
2187 // Always return false here, as this function only makes sure that the first
2188 // unallocated register has an odd register number and does not actually
2189 // allocate a register for the current argument.
2193 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2195 CCValAssign::LocInfo &LocInfo,
2196 ISD::ArgFlagsTy &ArgFlags,
2198 static const MCPhysReg ArgRegs[] = {
2199 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2203 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2205 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2207 // If there is only one Floating-point register left we need to put both f64
2208 // values of a split ppc_fp128 value on the stack.
2209 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2210 State.AllocateReg(ArgRegs[RegNum]);
2213 // Always return false here, as this function only makes sure that the two f64
2214 // values a ppc_fp128 value is split into are both passed in registers or both
2215 // passed on the stack and does not actually allocate a register for the
2216 // current argument.
2220 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2222 static const MCPhysReg *GetFPR() {
2223 static const MCPhysReg FPR[] = {
2224 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2225 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2231 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2233 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2234 unsigned PtrByteSize) {
2235 unsigned ArgSize = ArgVT.getStoreSize();
2236 if (Flags.isByVal())
2237 ArgSize = Flags.getByValSize();
2239 // Round up to multiples of the pointer size, except for array members,
2240 // which are always packed.
2241 if (!Flags.isInConsecutiveRegs())
2242 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2247 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2249 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2250 ISD::ArgFlagsTy Flags,
2251 unsigned PtrByteSize) {
2252 unsigned Align = PtrByteSize;
2254 // Altivec parameters are padded to a 16 byte boundary.
2255 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2256 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2257 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2260 // ByVal parameters are aligned as requested.
2261 if (Flags.isByVal()) {
2262 unsigned BVAlign = Flags.getByValAlign();
2263 if (BVAlign > PtrByteSize) {
2264 if (BVAlign % PtrByteSize != 0)
2266 "ByVal alignment is not a multiple of the pointer size");
2272 // Array members are always packed to their original alignment.
2273 if (Flags.isInConsecutiveRegs()) {
2274 // If the array member was split into multiple registers, the first
2275 // needs to be aligned to the size of the full type. (Except for
2276 // ppcf128, which is only aligned as its f64 components.)
2277 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2278 Align = OrigVT.getStoreSize();
2280 Align = ArgVT.getStoreSize();
2286 /// CalculateStackSlotUsed - Return whether this argument will use its
2287 /// stack slot (instead of being passed in registers). ArgOffset,
2288 /// AvailableFPRs, and AvailableVRs must hold the current argument
2289 /// position, and will be updated to account for this argument.
2290 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2291 ISD::ArgFlagsTy Flags,
2292 unsigned PtrByteSize,
2293 unsigned LinkageSize,
2294 unsigned ParamAreaSize,
2295 unsigned &ArgOffset,
2296 unsigned &AvailableFPRs,
2297 unsigned &AvailableVRs) {
2298 bool UseMemory = false;
2300 // Respect alignment of argument on the stack.
2302 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2303 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2304 // If there's no space left in the argument save area, we must
2305 // use memory (this check also catches zero-sized arguments).
2306 if (ArgOffset >= LinkageSize + ParamAreaSize)
2309 // Allocate argument on the stack.
2310 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2311 if (Flags.isInConsecutiveRegsLast())
2312 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2313 // If we overran the argument save area, we must use memory
2314 // (this check catches arguments passed partially in memory)
2315 if (ArgOffset > LinkageSize + ParamAreaSize)
2318 // However, if the argument is actually passed in an FPR or a VR,
2319 // we don't use memory after all.
2320 if (!Flags.isByVal()) {
2321 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2322 if (AvailableFPRs > 0) {
2326 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2327 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2328 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2329 if (AvailableVRs > 0) {
2338 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2339 /// ensure minimum alignment required for target.
2340 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2341 unsigned NumBytes) {
2342 unsigned TargetAlign =
2343 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2344 unsigned AlignMask = TargetAlign - 1;
2345 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2350 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2351 CallingConv::ID CallConv, bool isVarArg,
2352 const SmallVectorImpl<ISD::InputArg>
2354 SDLoc dl, SelectionDAG &DAG,
2355 SmallVectorImpl<SDValue> &InVals)
2357 if (Subtarget.isSVR4ABI()) {
2358 if (Subtarget.isPPC64())
2359 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2362 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2365 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2371 PPCTargetLowering::LowerFormalArguments_32SVR4(
2373 CallingConv::ID CallConv, bool isVarArg,
2374 const SmallVectorImpl<ISD::InputArg>
2376 SDLoc dl, SelectionDAG &DAG,
2377 SmallVectorImpl<SDValue> &InVals) const {
2379 // 32-bit SVR4 ABI Stack Frame Layout:
2380 // +-----------------------------------+
2381 // +--> | Back chain |
2382 // | +-----------------------------------+
2383 // | | Floating-point register save area |
2384 // | +-----------------------------------+
2385 // | | General register save area |
2386 // | +-----------------------------------+
2387 // | | CR save word |
2388 // | +-----------------------------------+
2389 // | | VRSAVE save word |
2390 // | +-----------------------------------+
2391 // | | Alignment padding |
2392 // | +-----------------------------------+
2393 // | | Vector register save area |
2394 // | +-----------------------------------+
2395 // | | Local variable space |
2396 // | +-----------------------------------+
2397 // | | Parameter list area |
2398 // | +-----------------------------------+
2399 // | | LR save word |
2400 // | +-----------------------------------+
2401 // SP--> +--- | Back chain |
2402 // +-----------------------------------+
2405 // System V Application Binary Interface PowerPC Processor Supplement
2406 // AltiVec Technology Programming Interface Manual
2408 MachineFunction &MF = DAG.getMachineFunction();
2409 MachineFrameInfo *MFI = MF.getFrameInfo();
2410 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2412 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2413 // Potential tail calls could cause overwriting of argument stack slots.
2414 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2415 (CallConv == CallingConv::Fast));
2416 unsigned PtrByteSize = 4;
2418 // Assign locations to all of the incoming arguments.
2419 SmallVector<CCValAssign, 16> ArgLocs;
2420 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2423 // Reserve space for the linkage area on the stack.
2424 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2425 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2427 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2429 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2430 CCValAssign &VA = ArgLocs[i];
2432 // Arguments stored in registers.
2433 if (VA.isRegLoc()) {
2434 const TargetRegisterClass *RC;
2435 EVT ValVT = VA.getValVT();
2437 switch (ValVT.getSimpleVT().SimpleTy) {
2439 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2442 RC = &PPC::GPRCRegClass;
2445 RC = &PPC::F4RCRegClass;
2448 if (Subtarget.hasVSX())
2449 RC = &PPC::VSFRCRegClass;
2451 RC = &PPC::F8RCRegClass;
2457 RC = &PPC::VRRCRegClass;
2461 RC = &PPC::VSHRCRegClass;
2465 // Transform the arguments stored in physical registers into virtual ones.
2466 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2467 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2468 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2470 if (ValVT == MVT::i1)
2471 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2473 InVals.push_back(ArgValue);
2475 // Argument stored in memory.
2476 assert(VA.isMemLoc());
2478 unsigned ArgSize = VA.getLocVT().getStoreSize();
2479 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2482 // Create load nodes to retrieve arguments from the stack.
2483 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2484 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2485 MachinePointerInfo(),
2486 false, false, false, 0));
2490 // Assign locations to all of the incoming aggregate by value arguments.
2491 // Aggregates passed by value are stored in the local variable space of the
2492 // caller's stack frame, right above the parameter list area.
2493 SmallVector<CCValAssign, 16> ByValArgLocs;
2494 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2495 ByValArgLocs, *DAG.getContext());
2497 // Reserve stack space for the allocations in CCInfo.
2498 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2500 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2502 // Area that is at least reserved in the caller of this function.
2503 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2504 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2506 // Set the size that is at least reserved in caller of this function. Tail
2507 // call optimized function's reserved stack space needs to be aligned so that
2508 // taking the difference between two stack areas will result in an aligned
2510 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2511 FuncInfo->setMinReservedArea(MinReservedArea);
2513 SmallVector<SDValue, 8> MemOps;
2515 // If the function takes variable number of arguments, make a frame index for
2516 // the start of the first vararg value... for expansion of llvm.va_start.
2518 static const MCPhysReg GPArgRegs[] = {
2519 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2520 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2522 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2524 static const MCPhysReg FPArgRegs[] = {
2525 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2528 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2529 if (DisablePPCFloatInVariadic)
2532 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2534 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2537 // Make room for NumGPArgRegs and NumFPArgRegs.
2538 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2539 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2541 FuncInfo->setVarArgsStackOffset(
2542 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2543 CCInfo.getNextStackOffset(), true));
2545 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2546 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2548 // The fixed integer arguments of a variadic function are stored to the
2549 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2550 // the result of va_next.
2551 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2552 // Get an existing live-in vreg, or add a new one.
2553 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2555 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2557 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2558 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2559 MachinePointerInfo(), false, false, 0);
2560 MemOps.push_back(Store);
2561 // Increment the address by four for the next argument to store
2562 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2563 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2566 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2568 // The double arguments are stored to the VarArgsFrameIndex
2570 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2571 // Get an existing live-in vreg, or add a new one.
2572 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2574 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2576 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2577 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2578 MachinePointerInfo(), false, false, 0);
2579 MemOps.push_back(Store);
2580 // Increment the address by eight for the next argument to store
2581 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2583 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2587 if (!MemOps.empty())
2588 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2593 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2594 // value to MVT::i64 and then truncate to the correct register size.
2596 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2597 SelectionDAG &DAG, SDValue ArgVal,
2600 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2601 DAG.getValueType(ObjectVT));
2602 else if (Flags.isZExt())
2603 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2604 DAG.getValueType(ObjectVT));
2606 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2610 PPCTargetLowering::LowerFormalArguments_64SVR4(
2612 CallingConv::ID CallConv, bool isVarArg,
2613 const SmallVectorImpl<ISD::InputArg>
2615 SDLoc dl, SelectionDAG &DAG,
2616 SmallVectorImpl<SDValue> &InVals) const {
2617 // TODO: add description of PPC stack frame format, or at least some docs.
2619 bool isELFv2ABI = Subtarget.isELFv2ABI();
2620 bool isLittleEndian = Subtarget.isLittleEndian();
2621 MachineFunction &MF = DAG.getMachineFunction();
2622 MachineFrameInfo *MFI = MF.getFrameInfo();
2623 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2625 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2626 // Potential tail calls could cause overwriting of argument stack slots.
2627 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2628 (CallConv == CallingConv::Fast));
2629 unsigned PtrByteSize = 8;
2631 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2634 static const MCPhysReg GPR[] = {
2635 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2636 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2639 static const MCPhysReg *FPR = GetFPR();
2641 static const MCPhysReg VR[] = {
2642 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2643 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2645 static const MCPhysReg VSRH[] = {
2646 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2647 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2650 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2651 const unsigned Num_FPR_Regs = 13;
2652 const unsigned Num_VR_Regs = array_lengthof(VR);
2654 // Do a first pass over the arguments to determine whether the ABI
2655 // guarantees that our caller has allocated the parameter save area
2656 // on its stack frame. In the ELFv1 ABI, this is always the case;
2657 // in the ELFv2 ABI, it is true if this is a vararg function or if
2658 // any parameter is located in a stack slot.
2660 bool HasParameterArea = !isELFv2ABI || isVarArg;
2661 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2662 unsigned NumBytes = LinkageSize;
2663 unsigned AvailableFPRs = Num_FPR_Regs;
2664 unsigned AvailableVRs = Num_VR_Regs;
2665 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2666 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2667 PtrByteSize, LinkageSize, ParamAreaSize,
2668 NumBytes, AvailableFPRs, AvailableVRs))
2669 HasParameterArea = true;
2671 // Add DAG nodes to load the arguments or copy them out of registers. On
2672 // entry to a function on PPC, the arguments start after the linkage area,
2673 // although the first ones are often in registers.
2675 unsigned ArgOffset = LinkageSize;
2676 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2677 SmallVector<SDValue, 8> MemOps;
2678 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2679 unsigned CurArgIdx = 0;
2680 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2682 bool needsLoad = false;
2683 EVT ObjectVT = Ins[ArgNo].VT;
2684 EVT OrigVT = Ins[ArgNo].ArgVT;
2685 unsigned ObjSize = ObjectVT.getStoreSize();
2686 unsigned ArgSize = ObjSize;
2687 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2688 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2689 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2691 /* Respect alignment of argument on the stack. */
2693 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2694 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2695 unsigned CurArgOffset = ArgOffset;
2697 /* Compute GPR index associated with argument offset. */
2698 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2699 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2701 // FIXME the codegen can be much improved in some cases.
2702 // We do not have to keep everything in memory.
2703 if (Flags.isByVal()) {
2704 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2705 ObjSize = Flags.getByValSize();
2706 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2707 // Empty aggregate parameters do not take up registers. Examples:
2711 // etc. However, we have to provide a place-holder in InVals, so
2712 // pretend we have an 8-byte item at the current address for that
2715 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2716 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2717 InVals.push_back(FIN);
2721 // Create a stack object covering all stack doublewords occupied
2722 // by the argument. If the argument is (fully or partially) on
2723 // the stack, or if the argument is fully in registers but the
2724 // caller has allocated the parameter save anyway, we can refer
2725 // directly to the caller's stack frame. Otherwise, create a
2726 // local copy in our own frame.
2728 if (HasParameterArea ||
2729 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2730 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2732 FI = MFI->CreateStackObject(ArgSize, Align, false);
2733 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2735 // Handle aggregates smaller than 8 bytes.
2736 if (ObjSize < PtrByteSize) {
2737 // The value of the object is its address, which differs from the
2738 // address of the enclosing doubleword on big-endian systems.
2740 if (!isLittleEndian) {
2741 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2742 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2744 InVals.push_back(Arg);
2746 if (GPR_idx != Num_GPR_Regs) {
2747 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2748 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2751 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2752 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2753 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2754 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2755 MachinePointerInfo(FuncArg),
2756 ObjType, false, false, 0);
2758 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2759 // store the whole register as-is to the parameter save area
2761 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2762 MachinePointerInfo(FuncArg),
2766 MemOps.push_back(Store);
2768 // Whether we copied from a register or not, advance the offset
2769 // into the parameter save area by a full doubleword.
2770 ArgOffset += PtrByteSize;
2774 // The value of the object is its address, which is the address of
2775 // its first stack doubleword.
2776 InVals.push_back(FIN);
2778 // Store whatever pieces of the object are in registers to memory.
2779 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2780 if (GPR_idx == Num_GPR_Regs)
2783 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2784 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2787 SDValue Off = DAG.getConstant(j, PtrVT);
2788 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2790 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2791 MachinePointerInfo(FuncArg, j),
2793 MemOps.push_back(Store);
2796 ArgOffset += ArgSize;
2800 switch (ObjectVT.getSimpleVT().SimpleTy) {
2801 default: llvm_unreachable("Unhandled argument type!");
2805 // These can be scalar arguments or elements of an integer array type
2806 // passed directly. Clang may use those instead of "byval" aggregate
2807 // types to avoid forcing arguments to memory unnecessarily.
2808 if (GPR_idx != Num_GPR_Regs) {
2809 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2810 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2812 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2813 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2814 // value to MVT::i64 and then truncate to the correct register size.
2815 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2818 ArgSize = PtrByteSize;
2825 // These can be scalar arguments or elements of a float array type
2826 // passed directly. The latter are used to implement ELFv2 homogenous
2827 // float aggregates.
2828 if (FPR_idx != Num_FPR_Regs) {
2831 if (ObjectVT == MVT::f32)
2832 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2834 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2835 &PPC::VSFRCRegClass :
2836 &PPC::F8RCRegClass);
2838 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2840 } else if (GPR_idx != Num_GPR_Regs) {
2841 // This can only ever happen in the presence of f32 array types,
2842 // since otherwise we never run out of FPRs before running out
2844 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2845 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2847 if (ObjectVT == MVT::f32) {
2848 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2849 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2850 DAG.getConstant(32, MVT::i32));
2851 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2854 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2859 // When passing an array of floats, the array occupies consecutive
2860 // space in the argument area; only round up to the next doubleword
2861 // at the end of the array. Otherwise, each float takes 8 bytes.
2862 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2863 ArgOffset += ArgSize;
2864 if (Flags.isInConsecutiveRegsLast())
2865 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2873 // These can be scalar arguments or elements of a vector array type
2874 // passed directly. The latter are used to implement ELFv2 homogenous
2875 // vector aggregates.
2876 if (VR_idx != Num_VR_Regs) {
2877 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2878 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2879 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2880 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2889 // We need to load the argument to a virtual register if we determined
2890 // above that we ran out of physical registers of the appropriate type.
2892 if (ObjSize < ArgSize && !isLittleEndian)
2893 CurArgOffset += ArgSize - ObjSize;
2894 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2895 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2896 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2897 false, false, false, 0);
2900 InVals.push_back(ArgVal);
2903 // Area that is at least reserved in the caller of this function.
2904 unsigned MinReservedArea;
2905 if (HasParameterArea)
2906 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2908 MinReservedArea = LinkageSize;
2910 // Set the size that is at least reserved in caller of this function. Tail
2911 // call optimized functions' reserved stack space needs to be aligned so that
2912 // taking the difference between two stack areas will result in an aligned
2914 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2915 FuncInfo->setMinReservedArea(MinReservedArea);
2917 // If the function takes variable number of arguments, make a frame index for
2918 // the start of the first vararg value... for expansion of llvm.va_start.
2920 int Depth = ArgOffset;
2922 FuncInfo->setVarArgsFrameIndex(
2923 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2924 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2926 // If this function is vararg, store any remaining integer argument regs
2927 // to their spots on the stack so that they may be loaded by deferencing the
2928 // result of va_next.
2929 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2930 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2931 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2932 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2933 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2934 MachinePointerInfo(), false, false, 0);
2935 MemOps.push_back(Store);
2936 // Increment the address by four for the next argument to store
2937 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2938 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2942 if (!MemOps.empty())
2943 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2949 PPCTargetLowering::LowerFormalArguments_Darwin(
2951 CallingConv::ID CallConv, bool isVarArg,
2952 const SmallVectorImpl<ISD::InputArg>
2954 SDLoc dl, SelectionDAG &DAG,
2955 SmallVectorImpl<SDValue> &InVals) const {
2956 // TODO: add description of PPC stack frame format, or at least some docs.
2958 MachineFunction &MF = DAG.getMachineFunction();
2959 MachineFrameInfo *MFI = MF.getFrameInfo();
2960 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2962 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2963 bool isPPC64 = PtrVT == MVT::i64;
2964 // Potential tail calls could cause overwriting of argument stack slots.
2965 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2966 (CallConv == CallingConv::Fast));
2967 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2969 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2971 unsigned ArgOffset = LinkageSize;
2972 // Area that is at least reserved in caller of this function.
2973 unsigned MinReservedArea = ArgOffset;
2975 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2976 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2977 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2979 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2980 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2981 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2984 static const MCPhysReg *FPR = GetFPR();
2986 static const MCPhysReg VR[] = {
2987 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2988 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2991 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2992 const unsigned Num_FPR_Regs = 13;
2993 const unsigned Num_VR_Regs = array_lengthof( VR);
2995 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2997 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2999 // In 32-bit non-varargs functions, the stack space for vectors is after the
3000 // stack space for non-vectors. We do not use this space unless we have
3001 // too many vectors to fit in registers, something that only occurs in
3002 // constructed examples:), but we have to walk the arglist to figure
3003 // that out...for the pathological case, compute VecArgOffset as the
3004 // start of the vector parameter area. Computing VecArgOffset is the
3005 // entire point of the following loop.
3006 unsigned VecArgOffset = ArgOffset;
3007 if (!isVarArg && !isPPC64) {
3008 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3010 EVT ObjectVT = Ins[ArgNo].VT;
3011 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3013 if (Flags.isByVal()) {
3014 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3015 unsigned ObjSize = Flags.getByValSize();
3017 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3018 VecArgOffset += ArgSize;
3022 switch(ObjectVT.getSimpleVT().SimpleTy) {
3023 default: llvm_unreachable("Unhandled argument type!");
3029 case MVT::i64: // PPC64
3031 // FIXME: We are guaranteed to be !isPPC64 at this point.
3032 // Does MVT::i64 apply?
3039 // Nothing to do, we're only looking at Nonvector args here.
3044 // We've found where the vector parameter area in memory is. Skip the
3045 // first 12 parameters; these don't use that memory.
3046 VecArgOffset = ((VecArgOffset+15)/16)*16;
3047 VecArgOffset += 12*16;
3049 // Add DAG nodes to load the arguments or copy them out of registers. On
3050 // entry to a function on PPC, the arguments start after the linkage area,
3051 // although the first ones are often in registers.
3053 SmallVector<SDValue, 8> MemOps;
3054 unsigned nAltivecParamsAtEnd = 0;
3055 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3056 unsigned CurArgIdx = 0;
3057 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3059 bool needsLoad = false;
3060 EVT ObjectVT = Ins[ArgNo].VT;
3061 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3062 unsigned ArgSize = ObjSize;
3063 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3064 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3065 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3067 unsigned CurArgOffset = ArgOffset;
3069 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3070 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3071 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3072 if (isVarArg || isPPC64) {
3073 MinReservedArea = ((MinReservedArea+15)/16)*16;
3074 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3077 } else nAltivecParamsAtEnd++;
3079 // Calculate min reserved area.
3080 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3084 // FIXME the codegen can be much improved in some cases.
3085 // We do not have to keep everything in memory.
3086 if (Flags.isByVal()) {
3087 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3088 ObjSize = Flags.getByValSize();
3089 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3090 // Objects of size 1 and 2 are right justified, everything else is
3091 // left justified. This means the memory address is adjusted forwards.
3092 if (ObjSize==1 || ObjSize==2) {
3093 CurArgOffset = CurArgOffset + (4 - ObjSize);
3095 // The value of the object is its address.
3096 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3097 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3098 InVals.push_back(FIN);
3099 if (ObjSize==1 || ObjSize==2) {
3100 if (GPR_idx != Num_GPR_Regs) {
3103 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3105 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3106 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3107 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3108 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3109 MachinePointerInfo(FuncArg),
3110 ObjType, false, false, 0);
3111 MemOps.push_back(Store);
3115 ArgOffset += PtrByteSize;
3119 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3120 // Store whatever pieces of the object are in registers
3121 // to memory. ArgOffset will be the address of the beginning
3123 if (GPR_idx != Num_GPR_Regs) {
3126 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3128 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3129 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3130 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3131 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3132 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3133 MachinePointerInfo(FuncArg, j),
3135 MemOps.push_back(Store);
3137 ArgOffset += PtrByteSize;
3139 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3146 switch (ObjectVT.getSimpleVT().SimpleTy) {
3147 default: llvm_unreachable("Unhandled argument type!");
3151 if (GPR_idx != Num_GPR_Regs) {
3152 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3153 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3155 if (ObjectVT == MVT::i1)
3156 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3161 ArgSize = PtrByteSize;
3163 // All int arguments reserve stack space in the Darwin ABI.
3164 ArgOffset += PtrByteSize;
3168 case MVT::i64: // PPC64
3169 if (GPR_idx != Num_GPR_Regs) {
3170 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3171 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3173 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3174 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3175 // value to MVT::i64 and then truncate to the correct register size.
3176 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3181 ArgSize = PtrByteSize;
3183 // All int arguments reserve stack space in the Darwin ABI.
3189 // Every 4 bytes of argument space consumes one of the GPRs available for
3190 // argument passing.
3191 if (GPR_idx != Num_GPR_Regs) {
3193 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3196 if (FPR_idx != Num_FPR_Regs) {
3199 if (ObjectVT == MVT::f32)
3200 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3202 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3204 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3210 // All FP arguments reserve stack space in the Darwin ABI.
3211 ArgOffset += isPPC64 ? 8 : ObjSize;
3217 // Note that vector arguments in registers don't reserve stack space,
3218 // except in varargs functions.
3219 if (VR_idx != Num_VR_Regs) {
3220 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3221 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3223 while ((ArgOffset % 16) != 0) {
3224 ArgOffset += PtrByteSize;
3225 if (GPR_idx != Num_GPR_Regs)
3229 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3233 if (!isVarArg && !isPPC64) {
3234 // Vectors go after all the nonvectors.
3235 CurArgOffset = VecArgOffset;
3238 // Vectors are aligned.
3239 ArgOffset = ((ArgOffset+15)/16)*16;
3240 CurArgOffset = ArgOffset;
3248 // We need to load the argument to a virtual register if we determined above
3249 // that we ran out of physical registers of the appropriate type.
3251 int FI = MFI->CreateFixedObject(ObjSize,
3252 CurArgOffset + (ArgSize - ObjSize),
3254 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3255 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3256 false, false, false, 0);
3259 InVals.push_back(ArgVal);
3262 // Allow for Altivec parameters at the end, if needed.
3263 if (nAltivecParamsAtEnd) {
3264 MinReservedArea = ((MinReservedArea+15)/16)*16;
3265 MinReservedArea += 16*nAltivecParamsAtEnd;
3268 // Area that is at least reserved in the caller of this function.
3269 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3271 // Set the size that is at least reserved in caller of this function. Tail
3272 // call optimized functions' reserved stack space needs to be aligned so that
3273 // taking the difference between two stack areas will result in an aligned
3275 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3276 FuncInfo->setMinReservedArea(MinReservedArea);
3278 // If the function takes variable number of arguments, make a frame index for
3279 // the start of the first vararg value... for expansion of llvm.va_start.
3281 int Depth = ArgOffset;
3283 FuncInfo->setVarArgsFrameIndex(
3284 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3286 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3288 // If this function is vararg, store any remaining integer argument regs
3289 // to their spots on the stack so that they may be loaded by deferencing the
3290 // result of va_next.
3291 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3295 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3297 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3299 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3300 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3301 MachinePointerInfo(), false, false, 0);
3302 MemOps.push_back(Store);
3303 // Increment the address by four for the next argument to store
3304 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3305 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3309 if (!MemOps.empty())
3310 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3315 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3316 /// adjusted to accommodate the arguments for the tailcall.
3317 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3318 unsigned ParamSize) {
3320 if (!isTailCall) return 0;
3322 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3323 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3324 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3325 // Remember only if the new adjustement is bigger.
3326 if (SPDiff < FI->getTailCallSPDelta())
3327 FI->setTailCallSPDelta(SPDiff);
3332 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3333 /// for tail call optimization. Targets which want to do tail call
3334 /// optimization should implement this function.
3336 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3337 CallingConv::ID CalleeCC,
3339 const SmallVectorImpl<ISD::InputArg> &Ins,
3340 SelectionDAG& DAG) const {
3341 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3344 // Variable argument functions are not supported.
3348 MachineFunction &MF = DAG.getMachineFunction();
3349 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3350 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3351 // Functions containing by val parameters are not supported.
3352 for (unsigned i = 0; i != Ins.size(); i++) {
3353 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3354 if (Flags.isByVal()) return false;
3357 // Non-PIC/GOT tail calls are supported.
3358 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3361 // At the moment we can only do local tail calls (in same module, hidden
3362 // or protected) if we are generating PIC.
3363 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3364 return G->getGlobal()->hasHiddenVisibility()
3365 || G->getGlobal()->hasProtectedVisibility();
3371 /// isCallCompatibleAddress - Return the immediate to use if the specified
3372 /// 32-bit value is representable in the immediate field of a BxA instruction.
3373 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3374 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3375 if (!C) return nullptr;
3377 int Addr = C->getZExtValue();
3378 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3379 SignExtend32<26>(Addr) != Addr)
3380 return nullptr; // Top 6 bits have to be sext of immediate.
3382 return DAG.getConstant((int)C->getZExtValue() >> 2,
3383 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3388 struct TailCallArgumentInfo {
3393 TailCallArgumentInfo() : FrameIdx(0) {}
3398 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3400 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3402 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3403 SmallVectorImpl<SDValue> &MemOpChains,
3405 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3406 SDValue Arg = TailCallArgs[i].Arg;
3407 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3408 int FI = TailCallArgs[i].FrameIdx;
3409 // Store relative to framepointer.
3410 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3411 MachinePointerInfo::getFixedStack(FI),
3416 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3417 /// the appropriate stack slot for the tail call optimized function call.
3418 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3419 MachineFunction &MF,
3428 // Calculate the new stack slot for the return address.
3429 int SlotSize = isPPC64 ? 8 : 4;
3430 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3432 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3433 NewRetAddrLoc, true);
3434 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3435 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3436 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3437 MachinePointerInfo::getFixedStack(NewRetAddr),
3440 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3441 // slot as the FP is never overwritten.
3444 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3445 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3447 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3448 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3449 MachinePointerInfo::getFixedStack(NewFPIdx),
3456 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3457 /// the position of the argument.
3459 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3460 SDValue Arg, int SPDiff, unsigned ArgOffset,
3461 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3462 int Offset = ArgOffset + SPDiff;
3463 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3464 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3465 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3466 SDValue FIN = DAG.getFrameIndex(FI, VT);
3467 TailCallArgumentInfo Info;
3469 Info.FrameIdxOp = FIN;
3471 TailCallArguments.push_back(Info);
3474 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3475 /// stack slot. Returns the chain as result and the loaded frame pointers in
3476 /// LROpOut/FPOpout. Used when tail calling.
3477 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3485 // Load the LR and FP stack slot for later adjusting.
3486 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3487 LROpOut = getReturnAddrFrameIndex(DAG);
3488 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3489 false, false, false, 0);
3490 Chain = SDValue(LROpOut.getNode(), 1);
3492 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3493 // slot as the FP is never overwritten.
3495 FPOpOut = getFramePointerFrameIndex(DAG);
3496 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3497 false, false, false, 0);
3498 Chain = SDValue(FPOpOut.getNode(), 1);
3504 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3505 /// by "Src" to address "Dst" of size "Size". Alignment information is
3506 /// specified by the specific parameter attribute. The copy will be passed as
3507 /// a byval function parameter.
3508 /// Sometimes what we are copying is the end of a larger object, the part that
3509 /// does not fit in registers.
3511 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3512 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3514 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3515 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3516 false, false, MachinePointerInfo(),
3517 MachinePointerInfo());
3520 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3523 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3524 SDValue Arg, SDValue PtrOff, int SPDiff,
3525 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3526 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3527 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3529 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3534 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3536 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3537 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3538 DAG.getConstant(ArgOffset, PtrVT));
3540 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3541 MachinePointerInfo(), false, false, 0));
3542 // Calculate and remember argument location.
3543 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3548 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3549 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3550 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3551 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3552 MachineFunction &MF = DAG.getMachineFunction();
3554 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3555 // might overwrite each other in case of tail call optimization.
3556 SmallVector<SDValue, 8> MemOpChains2;
3557 // Do not flag preceding copytoreg stuff together with the following stuff.
3559 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3561 if (!MemOpChains2.empty())
3562 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3564 // Store the return address to the appropriate stack slot.
3565 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3566 isPPC64, isDarwinABI, dl);
3568 // Emit callseq_end just before tailcall node.
3569 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3570 DAG.getIntPtrConstant(0, true), InFlag, dl);
3571 InFlag = Chain.getValue(1);
3575 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3576 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3577 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3578 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3579 const PPCSubtarget &Subtarget) {
3581 bool isPPC64 = Subtarget.isPPC64();
3582 bool isSVR4ABI = Subtarget.isSVR4ABI();
3583 bool isELFv2ABI = Subtarget.isELFv2ABI();
3585 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3586 NodeTys.push_back(MVT::Other); // Returns a chain
3587 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3589 unsigned CallOpc = PPCISD::CALL;
3591 bool needIndirectCall = true;
3592 if (!isSVR4ABI || !isPPC64)
3593 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3594 // If this is an absolute destination address, use the munged value.
3595 Callee = SDValue(Dest, 0);
3596 needIndirectCall = false;
3599 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3600 unsigned OpFlags = 0;
3601 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3602 (Subtarget.getTargetTriple().isMacOSX() &&
3603 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3604 (G->getGlobal()->isDeclaration() ||
3605 G->getGlobal()->isWeakForLinker())) ||
3606 (Subtarget.isTargetELF() && !isPPC64 &&
3607 !G->getGlobal()->hasLocalLinkage() &&
3608 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3609 // PC-relative references to external symbols should go through $stub,
3610 // unless we're building with the leopard linker or later, which
3611 // automatically synthesizes these stubs.
3612 OpFlags = PPCII::MO_PLT_OR_STUB;
3615 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3616 // every direct call is) turn it into a TargetGlobalAddress /
3617 // TargetExternalSymbol node so that legalize doesn't hack it.
3618 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3619 Callee.getValueType(), 0, OpFlags);
3620 needIndirectCall = false;
3623 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3624 unsigned char OpFlags = 0;
3626 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3627 (Subtarget.getTargetTriple().isMacOSX() &&
3628 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3629 (Subtarget.isTargetELF() && !isPPC64 &&
3630 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3631 // PC-relative references to external symbols should go through $stub,
3632 // unless we're building with the leopard linker or later, which
3633 // automatically synthesizes these stubs.
3634 OpFlags = PPCII::MO_PLT_OR_STUB;
3637 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3639 needIndirectCall = false;
3642 if (needIndirectCall) {
3643 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3644 // to do the call, we can't use PPCISD::CALL.
3645 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3647 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3648 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3649 // entry point, but to the function descriptor (the function entry point
3650 // address is part of the function descriptor though).
3651 // The function descriptor is a three doubleword structure with the
3652 // following fields: function entry point, TOC base address and
3653 // environment pointer.
3654 // Thus for a call through a function pointer, the following actions need
3656 // 1. Save the TOC of the caller in the TOC save area of its stack
3657 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3658 // 2. Load the address of the function entry point from the function
3660 // 3. Load the TOC of the callee from the function descriptor into r2.
3661 // 4. Load the environment pointer from the function descriptor into
3663 // 5. Branch to the function entry point address.
3664 // 6. On return of the callee, the TOC of the caller needs to be
3665 // restored (this is done in FinishCall()).
3667 // All those operations are flagged together to ensure that no other
3668 // operations can be scheduled in between. E.g. without flagging the
3669 // operations together, a TOC access in the caller could be scheduled
3670 // between the load of the callee TOC and the branch to the callee, which
3671 // results in the TOC access going through the TOC of the callee instead
3672 // of going through the TOC of the caller, which leads to incorrect code.
3674 // Load the address of the function entry point from the function
3676 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3677 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3678 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3679 Chain = LoadFuncPtr.getValue(1);
3680 InFlag = LoadFuncPtr.getValue(2);
3682 // Load environment pointer into r11.
3683 // Offset of the environment pointer within the function descriptor.
3684 SDValue PtrOff = DAG.getIntPtrConstant(16);
3686 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3687 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3689 Chain = LoadEnvPtr.getValue(1);
3690 InFlag = LoadEnvPtr.getValue(2);
3692 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3694 Chain = EnvVal.getValue(0);
3695 InFlag = EnvVal.getValue(1);
3697 // Load TOC of the callee into r2. We are using a target-specific load
3698 // with r2 hard coded, because the result of a target-independent load
3699 // would never go directly into r2, since r2 is a reserved register (which
3700 // prevents the register allocator from allocating it), resulting in an
3701 // additional register being allocated and an unnecessary move instruction
3703 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3704 SDValue TOCOff = DAG.getIntPtrConstant(8);
3705 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3706 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3708 Chain = LoadTOCPtr.getValue(0);
3709 InFlag = LoadTOCPtr.getValue(1);
3711 MTCTROps[0] = Chain;
3712 MTCTROps[1] = LoadFuncPtr;
3713 MTCTROps[2] = InFlag;
3716 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3717 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3718 InFlag = Chain.getValue(1);
3721 NodeTys.push_back(MVT::Other);
3722 NodeTys.push_back(MVT::Glue);
3723 Ops.push_back(Chain);
3724 CallOpc = PPCISD::BCTRL;
3725 Callee.setNode(nullptr);
3726 // Add use of X11 (holding environment pointer)
3727 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3728 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3729 // Add CTR register as callee so a bctr can be emitted later.
3731 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3734 // If this is a direct call, pass the chain and the callee.
3735 if (Callee.getNode()) {
3736 Ops.push_back(Chain);
3737 Ops.push_back(Callee);
3739 // If this is a call to __tls_get_addr, find the symbol whose address
3740 // is to be taken and add it to the list. This will be used to
3741 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3742 // We find the symbol by walking the chain to the CopyFromReg, walking
3743 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3744 // pulling the symbol from that node.
3745 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3746 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3747 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3748 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3749 SDValue TGTAddr = AddI->getOperand(1);
3750 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3751 "Didn't find target global TLS address where we expected one");
3752 Ops.push_back(TGTAddr);
3753 CallOpc = PPCISD::CALL_TLS;
3756 // If this is a tail call add stack pointer delta.
3758 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3760 // Add argument registers to the end of the list so that they are known live
3762 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3763 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3764 RegsToPass[i].second.getValueType()));
3766 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3767 if (Callee.getNode() && isELFv2ABI)
3768 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3774 bool isLocalCall(const SDValue &Callee)
3776 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3777 return !G->getGlobal()->isDeclaration() &&
3778 !G->getGlobal()->isWeakForLinker();
3783 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3784 CallingConv::ID CallConv, bool isVarArg,
3785 const SmallVectorImpl<ISD::InputArg> &Ins,
3786 SDLoc dl, SelectionDAG &DAG,
3787 SmallVectorImpl<SDValue> &InVals) const {
3789 SmallVector<CCValAssign, 16> RVLocs;
3790 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3792 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3794 // Copy all of the result registers out of their specified physreg.
3795 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3796 CCValAssign &VA = RVLocs[i];
3797 assert(VA.isRegLoc() && "Can only return in registers!");
3799 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3800 VA.getLocReg(), VA.getLocVT(), InFlag);
3801 Chain = Val.getValue(1);
3802 InFlag = Val.getValue(2);
3804 switch (VA.getLocInfo()) {
3805 default: llvm_unreachable("Unknown loc info!");
3806 case CCValAssign::Full: break;
3807 case CCValAssign::AExt:
3808 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3810 case CCValAssign::ZExt:
3811 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3812 DAG.getValueType(VA.getValVT()));
3813 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3815 case CCValAssign::SExt:
3816 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3817 DAG.getValueType(VA.getValVT()));
3818 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3822 InVals.push_back(Val);
3829 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3830 bool isTailCall, bool isVarArg,
3832 SmallVector<std::pair<unsigned, SDValue>, 8>
3834 SDValue InFlag, SDValue Chain,
3836 int SPDiff, unsigned NumBytes,
3837 const SmallVectorImpl<ISD::InputArg> &Ins,
3838 SmallVectorImpl<SDValue> &InVals) const {
3840 bool isELFv2ABI = Subtarget.isELFv2ABI();
3841 std::vector<EVT> NodeTys;
3842 SmallVector<SDValue, 8> Ops;
3843 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3844 isTailCall, RegsToPass, Ops, NodeTys,
3847 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3848 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3849 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3851 // When performing tail call optimization the callee pops its arguments off
3852 // the stack. Account for this here so these bytes can be pushed back on in
3853 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3854 int BytesCalleePops =
3855 (CallConv == CallingConv::Fast &&
3856 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3858 // Add a register mask operand representing the call-preserved registers.
3859 const TargetRegisterInfo *TRI =
3860 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3861 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3862 assert(Mask && "Missing call preserved mask for calling convention");
3863 Ops.push_back(DAG.getRegisterMask(Mask));
3865 if (InFlag.getNode())
3866 Ops.push_back(InFlag);
3870 assert(((Callee.getOpcode() == ISD::Register &&
3871 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3872 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3873 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3874 isa<ConstantSDNode>(Callee)) &&
3875 "Expecting an global address, external symbol, absolute value or register");
3877 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3880 // Add a NOP immediately after the branch instruction when using the 64-bit
3881 // SVR4 ABI. At link time, if caller and callee are in a different module and
3882 // thus have a different TOC, the call will be replaced with a call to a stub
3883 // function which saves the current TOC, loads the TOC of the callee and
3884 // branches to the callee. The NOP will be replaced with a load instruction
3885 // which restores the TOC of the caller from the TOC save slot of the current
3886 // stack frame. If caller and callee belong to the same module (and have the
3887 // same TOC), the NOP will remain unchanged.
3889 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3890 if (CallOpc == PPCISD::BCTRL) {
3891 // This is a call through a function pointer.
3892 // Restore the caller TOC from the save area into R2.
3893 // See PrepareCall() for more information about calls through function
3894 // pointers in the 64-bit SVR4 ABI.
3895 // We are using a target-specific load with r2 hard coded, because the
3896 // result of a target-independent load would never go directly into r2,
3897 // since r2 is a reserved register (which prevents the register allocator
3898 // from allocating it), resulting in an additional register being
3899 // allocated and an unnecessary move instruction being generated.
3900 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3902 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3903 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3904 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3905 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3906 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3908 // The address needs to go after the chain input but before the flag (or
3909 // any other variadic arguments).
3910 Ops.insert(std::next(Ops.begin()), AddTOC);
3911 } else if ((CallOpc == PPCISD::CALL) &&
3912 (!isLocalCall(Callee) ||
3913 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3914 // Otherwise insert NOP for non-local calls.
3915 CallOpc = PPCISD::CALL_NOP;
3916 } else if (CallOpc == PPCISD::CALL_TLS)
3917 // For 64-bit SVR4, TLS calls are always non-local.
3918 CallOpc = PPCISD::CALL_NOP_TLS;
3921 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3922 InFlag = Chain.getValue(1);
3924 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3925 DAG.getIntPtrConstant(BytesCalleePops, true),
3928 InFlag = Chain.getValue(1);
3930 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3931 Ins, dl, DAG, InVals);
3935 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3936 SmallVectorImpl<SDValue> &InVals) const {
3937 SelectionDAG &DAG = CLI.DAG;
3939 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3940 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3941 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3942 SDValue Chain = CLI.Chain;
3943 SDValue Callee = CLI.Callee;
3944 bool &isTailCall = CLI.IsTailCall;
3945 CallingConv::ID CallConv = CLI.CallConv;
3946 bool isVarArg = CLI.IsVarArg;
3949 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3952 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3953 report_fatal_error("failed to perform tail call elimination on a call "
3954 "site marked musttail");
3956 if (Subtarget.isSVR4ABI()) {
3957 if (Subtarget.isPPC64())
3958 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3959 isTailCall, Outs, OutVals, Ins,
3962 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3963 isTailCall, Outs, OutVals, Ins,
3967 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3968 isTailCall, Outs, OutVals, Ins,
3973 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3974 CallingConv::ID CallConv, bool isVarArg,
3976 const SmallVectorImpl<ISD::OutputArg> &Outs,
3977 const SmallVectorImpl<SDValue> &OutVals,
3978 const SmallVectorImpl<ISD::InputArg> &Ins,
3979 SDLoc dl, SelectionDAG &DAG,
3980 SmallVectorImpl<SDValue> &InVals) const {
3981 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3982 // of the 32-bit SVR4 ABI stack frame layout.
3984 assert((CallConv == CallingConv::C ||
3985 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3987 unsigned PtrByteSize = 4;
3989 MachineFunction &MF = DAG.getMachineFunction();
3991 // Mark this function as potentially containing a function that contains a
3992 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3993 // and restoring the callers stack pointer in this functions epilog. This is
3994 // done because by tail calling the called function might overwrite the value
3995 // in this function's (MF) stack pointer stack slot 0(SP).
3996 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3997 CallConv == CallingConv::Fast)
3998 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4000 // Count how many bytes are to be pushed on the stack, including the linkage
4001 // area, parameter list area and the part of the local variable space which
4002 // contains copies of aggregates which are passed by value.
4004 // Assign locations to all of the outgoing arguments.
4005 SmallVector<CCValAssign, 16> ArgLocs;
4006 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4009 // Reserve space for the linkage area on the stack.
4010 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4014 // Handle fixed and variable vector arguments differently.
4015 // Fixed vector arguments go into registers as long as registers are
4016 // available. Variable vector arguments always go into memory.
4017 unsigned NumArgs = Outs.size();
4019 for (unsigned i = 0; i != NumArgs; ++i) {
4020 MVT ArgVT = Outs[i].VT;
4021 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4024 if (Outs[i].IsFixed) {
4025 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4028 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4034 errs() << "Call operand #" << i << " has unhandled type "
4035 << EVT(ArgVT).getEVTString() << "\n";
4037 llvm_unreachable(nullptr);
4041 // All arguments are treated the same.
4042 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4045 // Assign locations to all of the outgoing aggregate by value arguments.
4046 SmallVector<CCValAssign, 16> ByValArgLocs;
4047 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4048 ByValArgLocs, *DAG.getContext());
4050 // Reserve stack space for the allocations in CCInfo.
4051 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4053 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4055 // Size of the linkage area, parameter list area and the part of the local
4056 // space variable where copies of aggregates which are passed by value are
4058 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4060 // Calculate by how many bytes the stack has to be adjusted in case of tail
4061 // call optimization.
4062 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4064 // Adjust the stack pointer for the new arguments...
4065 // These operations are automatically eliminated by the prolog/epilog pass
4066 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4068 SDValue CallSeqStart = Chain;
4070 // Load the return address and frame pointer so it can be moved somewhere else
4073 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4076 // Set up a copy of the stack pointer for use loading and storing any
4077 // arguments that may not fit in the registers available for argument
4079 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4081 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4082 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4083 SmallVector<SDValue, 8> MemOpChains;
4085 bool seenFloatArg = false;
4086 // Walk the register/memloc assignments, inserting copies/loads.
4087 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4090 CCValAssign &VA = ArgLocs[i];
4091 SDValue Arg = OutVals[i];
4092 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4094 if (Flags.isByVal()) {
4095 // Argument is an aggregate which is passed by value, thus we need to
4096 // create a copy of it in the local variable space of the current stack
4097 // frame (which is the stack frame of the caller) and pass the address of
4098 // this copy to the callee.
4099 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4100 CCValAssign &ByValVA = ByValArgLocs[j++];
4101 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4103 // Memory reserved in the local variable space of the callers stack frame.
4104 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4106 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4107 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4109 // Create a copy of the argument in the local area of the current
4111 SDValue MemcpyCall =
4112 CreateCopyOfByValArgument(Arg, PtrOff,
4113 CallSeqStart.getNode()->getOperand(0),
4116 // This must go outside the CALLSEQ_START..END.
4117 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4118 CallSeqStart.getNode()->getOperand(1),
4120 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4121 NewCallSeqStart.getNode());
4122 Chain = CallSeqStart = NewCallSeqStart;
4124 // Pass the address of the aggregate copy on the stack either in a
4125 // physical register or in the parameter list area of the current stack
4126 // frame to the callee.
4130 if (VA.isRegLoc()) {
4131 if (Arg.getValueType() == MVT::i1)
4132 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4134 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4135 // Put argument in a physical register.
4136 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4138 // Put argument in the parameter list area of the current stack frame.
4139 assert(VA.isMemLoc());
4140 unsigned LocMemOffset = VA.getLocMemOffset();
4143 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4144 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4146 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4147 MachinePointerInfo(),
4150 // Calculate and remember argument location.
4151 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4157 if (!MemOpChains.empty())
4158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4160 // Build a sequence of copy-to-reg nodes chained together with token chain
4161 // and flag operands which copy the outgoing args into the appropriate regs.
4163 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4164 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4165 RegsToPass[i].second, InFlag);
4166 InFlag = Chain.getValue(1);
4169 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4172 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4173 SDValue Ops[] = { Chain, InFlag };
4175 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4176 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4178 InFlag = Chain.getValue(1);
4182 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4183 false, TailCallArguments);
4185 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4186 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4190 // Copy an argument into memory, being careful to do this outside the
4191 // call sequence for the call to which the argument belongs.
4193 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4194 SDValue CallSeqStart,
4195 ISD::ArgFlagsTy Flags,
4198 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4199 CallSeqStart.getNode()->getOperand(0),
4201 // The MEMCPY must go outside the CALLSEQ_START..END.
4202 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4203 CallSeqStart.getNode()->getOperand(1),
4205 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4206 NewCallSeqStart.getNode());
4207 return NewCallSeqStart;
4211 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4212 CallingConv::ID CallConv, bool isVarArg,
4214 const SmallVectorImpl<ISD::OutputArg> &Outs,
4215 const SmallVectorImpl<SDValue> &OutVals,
4216 const SmallVectorImpl<ISD::InputArg> &Ins,
4217 SDLoc dl, SelectionDAG &DAG,
4218 SmallVectorImpl<SDValue> &InVals) const {
4220 bool isELFv2ABI = Subtarget.isELFv2ABI();
4221 bool isLittleEndian = Subtarget.isLittleEndian();
4222 unsigned NumOps = Outs.size();
4224 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4225 unsigned PtrByteSize = 8;
4227 MachineFunction &MF = DAG.getMachineFunction();
4229 // Mark this function as potentially containing a function that contains a
4230 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4231 // and restoring the callers stack pointer in this functions epilog. This is
4232 // done because by tail calling the called function might overwrite the value
4233 // in this function's (MF) stack pointer stack slot 0(SP).
4234 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4235 CallConv == CallingConv::Fast)
4236 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4238 // Count how many bytes are to be pushed on the stack, including the linkage
4239 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4240 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4241 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4242 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4244 unsigned NumBytes = LinkageSize;
4246 // Add up all the space actually used.
4247 for (unsigned i = 0; i != NumOps; ++i) {
4248 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4249 EVT ArgVT = Outs[i].VT;
4250 EVT OrigVT = Outs[i].ArgVT;
4252 /* Respect alignment of argument on the stack. */
4254 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4255 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4257 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4258 if (Flags.isInConsecutiveRegsLast())
4259 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4262 unsigned NumBytesActuallyUsed = NumBytes;
4264 // The prolog code of the callee may store up to 8 GPR argument registers to
4265 // the stack, allowing va_start to index over them in memory if its varargs.
4266 // Because we cannot tell if this is needed on the caller side, we have to
4267 // conservatively assume that it is needed. As such, make sure we have at
4268 // least enough stack space for the caller to store the 8 GPRs.
4269 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4270 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4272 // Tail call needs the stack to be aligned.
4273 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4274 CallConv == CallingConv::Fast)
4275 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4277 // Calculate by how many bytes the stack has to be adjusted in case of tail
4278 // call optimization.
4279 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4281 // To protect arguments on the stack from being clobbered in a tail call,
4282 // force all the loads to happen before doing any other lowering.
4284 Chain = DAG.getStackArgumentTokenFactor(Chain);
4286 // Adjust the stack pointer for the new arguments...
4287 // These operations are automatically eliminated by the prolog/epilog pass
4288 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4290 SDValue CallSeqStart = Chain;
4292 // Load the return address and frame pointer so it can be move somewhere else
4295 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4298 // Set up a copy of the stack pointer for use loading and storing any
4299 // arguments that may not fit in the registers available for argument
4301 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4303 // Figure out which arguments are going to go in registers, and which in
4304 // memory. Also, if this is a vararg function, floating point operations
4305 // must be stored to our stack, and loaded into integer regs as well, if
4306 // any integer regs are available for argument passing.
4307 unsigned ArgOffset = LinkageSize;
4308 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4310 static const MCPhysReg GPR[] = {
4311 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4312 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4314 static const MCPhysReg *FPR = GetFPR();
4316 static const MCPhysReg VR[] = {
4317 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4318 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4320 static const MCPhysReg VSRH[] = {
4321 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4322 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4325 const unsigned NumGPRs = array_lengthof(GPR);
4326 const unsigned NumFPRs = 13;
4327 const unsigned NumVRs = array_lengthof(VR);
4329 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4330 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4332 SmallVector<SDValue, 8> MemOpChains;
4333 for (unsigned i = 0; i != NumOps; ++i) {
4334 SDValue Arg = OutVals[i];
4335 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4336 EVT ArgVT = Outs[i].VT;
4337 EVT OrigVT = Outs[i].ArgVT;
4339 /* Respect alignment of argument on the stack. */
4341 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4342 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4344 /* Compute GPR index associated with argument offset. */
4345 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4346 GPR_idx = std::min(GPR_idx, NumGPRs);
4348 // PtrOff will be used to store the current argument to the stack if a
4349 // register cannot be found for it.
4352 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4354 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4356 // Promote integers to 64-bit values.
4357 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4358 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4359 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4360 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4363 // FIXME memcpy is used way more than necessary. Correctness first.
4364 // Note: "by value" is code for passing a structure by value, not
4366 if (Flags.isByVal()) {
4367 // Note: Size includes alignment padding, so
4368 // struct x { short a; char b; }
4369 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4370 // These are the proper values we need for right-justifying the
4371 // aggregate in a parameter register.
4372 unsigned Size = Flags.getByValSize();
4374 // An empty aggregate parameter takes up no storage and no
4379 // All aggregates smaller than 8 bytes must be passed right-justified.
4380 if (Size==1 || Size==2 || Size==4) {
4381 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4382 if (GPR_idx != NumGPRs) {
4383 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4384 MachinePointerInfo(), VT,
4385 false, false, false, 0);
4386 MemOpChains.push_back(Load.getValue(1));
4387 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4389 ArgOffset += PtrByteSize;
4394 if (GPR_idx == NumGPRs && Size < 8) {
4395 SDValue AddPtr = PtrOff;
4396 if (!isLittleEndian) {
4397 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4398 PtrOff.getValueType());
4399 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4401 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4404 ArgOffset += PtrByteSize;
4407 // Copy entire object into memory. There are cases where gcc-generated
4408 // code assumes it is there, even if it could be put entirely into
4409 // registers. (This is not what the doc says.)
4411 // FIXME: The above statement is likely due to a misunderstanding of the
4412 // documents. All arguments must be copied into the parameter area BY
4413 // THE CALLEE in the event that the callee takes the address of any
4414 // formal argument. That has not yet been implemented. However, it is
4415 // reasonable to use the stack area as a staging area for the register
4418 // Skip this for small aggregates, as we will use the same slot for a
4419 // right-justified copy, below.
4421 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4425 // When a register is available, pass a small aggregate right-justified.
4426 if (Size < 8 && GPR_idx != NumGPRs) {
4427 // The easiest way to get this right-justified in a register
4428 // is to copy the structure into the rightmost portion of a
4429 // local variable slot, then load the whole slot into the
4431 // FIXME: The memcpy seems to produce pretty awful code for
4432 // small aggregates, particularly for packed ones.
4433 // FIXME: It would be preferable to use the slot in the
4434 // parameter save area instead of a new local variable.
4435 SDValue AddPtr = PtrOff;
4436 if (!isLittleEndian) {
4437 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4438 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4440 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4444 // Load the slot into the register.
4445 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4446 MachinePointerInfo(),
4447 false, false, false, 0);
4448 MemOpChains.push_back(Load.getValue(1));
4449 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4451 // Done with this argument.
4452 ArgOffset += PtrByteSize;
4456 // For aggregates larger than PtrByteSize, copy the pieces of the
4457 // object that fit into registers from the parameter save area.
4458 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4459 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4460 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4461 if (GPR_idx != NumGPRs) {
4462 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4463 MachinePointerInfo(),
4464 false, false, false, 0);
4465 MemOpChains.push_back(Load.getValue(1));
4466 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4467 ArgOffset += PtrByteSize;
4469 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4476 switch (Arg.getSimpleValueType().SimpleTy) {
4477 default: llvm_unreachable("Unexpected ValueType for argument!");
4481 // These can be scalar arguments or elements of an integer array type
4482 // passed directly. Clang may use those instead of "byval" aggregate
4483 // types to avoid forcing arguments to memory unnecessarily.
4484 if (GPR_idx != NumGPRs) {
4485 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4487 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4488 true, isTailCall, false, MemOpChains,
4489 TailCallArguments, dl);
4491 ArgOffset += PtrByteSize;
4495 // These can be scalar arguments or elements of a float array type
4496 // passed directly. The latter are used to implement ELFv2 homogenous
4497 // float aggregates.
4499 // Named arguments go into FPRs first, and once they overflow, the
4500 // remaining arguments go into GPRs and then the parameter save area.
4501 // Unnamed arguments for vararg functions always go to GPRs and
4502 // then the parameter save area. For now, put all arguments to vararg
4503 // routines always in both locations (FPR *and* GPR or stack slot).
4504 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4506 // First load the argument into the next available FPR.
4507 if (FPR_idx != NumFPRs)
4508 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4510 // Next, load the argument into GPR or stack slot if needed.
4511 if (!NeedGPROrStack)
4513 else if (GPR_idx != NumGPRs) {
4514 // In the non-vararg case, this can only ever happen in the
4515 // presence of f32 array types, since otherwise we never run
4516 // out of FPRs before running out of GPRs.
4519 // Double values are always passed in a single GPR.
4520 if (Arg.getValueType() != MVT::f32) {
4521 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4523 // Non-array float values are extended and passed in a GPR.
4524 } else if (!Flags.isInConsecutiveRegs()) {
4525 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4526 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4528 // If we have an array of floats, we collect every odd element
4529 // together with its predecessor into one GPR.
4530 } else if (ArgOffset % PtrByteSize != 0) {
4532 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4533 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4534 if (!isLittleEndian)
4536 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4538 // The final element, if even, goes into the first half of a GPR.
4539 } else if (Flags.isInConsecutiveRegsLast()) {
4540 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4541 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4542 if (!isLittleEndian)
4543 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4544 DAG.getConstant(32, MVT::i32));
4546 // Non-final even elements are skipped; they will be handled
4547 // together the with subsequent argument on the next go-around.
4551 if (ArgVal.getNode())
4552 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4554 // Single-precision floating-point values are mapped to the
4555 // second (rightmost) word of the stack doubleword.
4556 if (Arg.getValueType() == MVT::f32 &&
4557 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4558 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4559 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4562 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4563 true, isTailCall, false, MemOpChains,
4564 TailCallArguments, dl);
4566 // When passing an array of floats, the array occupies consecutive
4567 // space in the argument area; only round up to the next doubleword
4568 // at the end of the array. Otherwise, each float takes 8 bytes.
4569 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4570 Flags.isInConsecutiveRegs()) ? 4 : 8;
4571 if (Flags.isInConsecutiveRegsLast())
4572 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4581 // These can be scalar arguments or elements of a vector array type
4582 // passed directly. The latter are used to implement ELFv2 homogenous
4583 // vector aggregates.
4585 // For a varargs call, named arguments go into VRs or on the stack as
4586 // usual; unnamed arguments always go to the stack or the corresponding
4587 // GPRs when within range. For now, we always put the value in both
4588 // locations (or even all three).
4590 // We could elide this store in the case where the object fits
4591 // entirely in R registers. Maybe later.
4592 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4593 MachinePointerInfo(), false, false, 0);
4594 MemOpChains.push_back(Store);
4595 if (VR_idx != NumVRs) {
4596 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4597 MachinePointerInfo(),
4598 false, false, false, 0);
4599 MemOpChains.push_back(Load.getValue(1));
4601 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4602 Arg.getSimpleValueType() == MVT::v2i64) ?
4603 VSRH[VR_idx] : VR[VR_idx];
4606 RegsToPass.push_back(std::make_pair(VReg, Load));
4609 for (unsigned i=0; i<16; i+=PtrByteSize) {
4610 if (GPR_idx == NumGPRs)
4612 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4613 DAG.getConstant(i, PtrVT));
4614 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4615 false, false, false, 0);
4616 MemOpChains.push_back(Load.getValue(1));
4617 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4622 // Non-varargs Altivec params go into VRs or on the stack.
4623 if (VR_idx != NumVRs) {
4624 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4625 Arg.getSimpleValueType() == MVT::v2i64) ?
4626 VSRH[VR_idx] : VR[VR_idx];
4629 RegsToPass.push_back(std::make_pair(VReg, Arg));
4631 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4632 true, isTailCall, true, MemOpChains,
4633 TailCallArguments, dl);
4640 assert(NumBytesActuallyUsed == ArgOffset);
4641 (void)NumBytesActuallyUsed;
4643 if (!MemOpChains.empty())
4644 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4646 // Check if this is an indirect call (MTCTR/BCTRL).
4647 // See PrepareCall() for more information about calls through function
4648 // pointers in the 64-bit SVR4 ABI.
4650 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4651 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4652 // Load r2 into a virtual register and store it to the TOC save area.
4653 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4654 // TOC save area offset.
4655 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4656 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4657 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4658 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4660 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4661 // This does not mean the MTCTR instruction must use R12; it's easier
4662 // to model this as an extra parameter, so do that.
4664 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4667 // Build a sequence of copy-to-reg nodes chained together with token chain
4668 // and flag operands which copy the outgoing args into the appropriate regs.
4670 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4671 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4672 RegsToPass[i].second, InFlag);
4673 InFlag = Chain.getValue(1);
4677 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4678 FPOp, true, TailCallArguments);
4680 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4681 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4686 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4687 CallingConv::ID CallConv, bool isVarArg,
4689 const SmallVectorImpl<ISD::OutputArg> &Outs,
4690 const SmallVectorImpl<SDValue> &OutVals,
4691 const SmallVectorImpl<ISD::InputArg> &Ins,
4692 SDLoc dl, SelectionDAG &DAG,
4693 SmallVectorImpl<SDValue> &InVals) const {
4695 unsigned NumOps = Outs.size();
4697 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4698 bool isPPC64 = PtrVT == MVT::i64;
4699 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4701 MachineFunction &MF = DAG.getMachineFunction();
4703 // Mark this function as potentially containing a function that contains a
4704 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4705 // and restoring the callers stack pointer in this functions epilog. This is
4706 // done because by tail calling the called function might overwrite the value
4707 // in this function's (MF) stack pointer stack slot 0(SP).
4708 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4709 CallConv == CallingConv::Fast)
4710 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4712 // Count how many bytes are to be pushed on the stack, including the linkage
4713 // area, and parameter passing area. We start with 24/48 bytes, which is
4714 // prereserved space for [SP][CR][LR][3 x unused].
4715 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4717 unsigned NumBytes = LinkageSize;
4719 // Add up all the space actually used.
4720 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4721 // they all go in registers, but we must reserve stack space for them for
4722 // possible use by the caller. In varargs or 64-bit calls, parameters are
4723 // assigned stack space in order, with padding so Altivec parameters are
4725 unsigned nAltivecParamsAtEnd = 0;
4726 for (unsigned i = 0; i != NumOps; ++i) {
4727 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4728 EVT ArgVT = Outs[i].VT;
4729 // Varargs Altivec parameters are padded to a 16 byte boundary.
4730 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4731 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4732 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4733 if (!isVarArg && !isPPC64) {
4734 // Non-varargs Altivec parameters go after all the non-Altivec
4735 // parameters; handle those later so we know how much padding we need.
4736 nAltivecParamsAtEnd++;
4739 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4740 NumBytes = ((NumBytes+15)/16)*16;
4742 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4745 // Allow for Altivec parameters at the end, if needed.
4746 if (nAltivecParamsAtEnd) {
4747 NumBytes = ((NumBytes+15)/16)*16;
4748 NumBytes += 16*nAltivecParamsAtEnd;
4751 // The prolog code of the callee may store up to 8 GPR argument registers to
4752 // the stack, allowing va_start to index over them in memory if its varargs.
4753 // Because we cannot tell if this is needed on the caller side, we have to
4754 // conservatively assume that it is needed. As such, make sure we have at
4755 // least enough stack space for the caller to store the 8 GPRs.
4756 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4758 // Tail call needs the stack to be aligned.
4759 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4760 CallConv == CallingConv::Fast)
4761 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4763 // Calculate by how many bytes the stack has to be adjusted in case of tail
4764 // call optimization.
4765 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4767 // To protect arguments on the stack from being clobbered in a tail call,
4768 // force all the loads to happen before doing any other lowering.
4770 Chain = DAG.getStackArgumentTokenFactor(Chain);
4772 // Adjust the stack pointer for the new arguments...
4773 // These operations are automatically eliminated by the prolog/epilog pass
4774 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4776 SDValue CallSeqStart = Chain;
4778 // Load the return address and frame pointer so it can be move somewhere else
4781 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4784 // Set up a copy of the stack pointer for use loading and storing any
4785 // arguments that may not fit in the registers available for argument
4789 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4791 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4793 // Figure out which arguments are going to go in registers, and which in
4794 // memory. Also, if this is a vararg function, floating point operations
4795 // must be stored to our stack, and loaded into integer regs as well, if
4796 // any integer regs are available for argument passing.
4797 unsigned ArgOffset = LinkageSize;
4798 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4800 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4801 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4802 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4804 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4805 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4806 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4808 static const MCPhysReg *FPR = GetFPR();
4810 static const MCPhysReg VR[] = {
4811 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4812 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4814 const unsigned NumGPRs = array_lengthof(GPR_32);
4815 const unsigned NumFPRs = 13;
4816 const unsigned NumVRs = array_lengthof(VR);
4818 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4820 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4821 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4823 SmallVector<SDValue, 8> MemOpChains;
4824 for (unsigned i = 0; i != NumOps; ++i) {
4825 SDValue Arg = OutVals[i];
4826 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4828 // PtrOff will be used to store the current argument to the stack if a
4829 // register cannot be found for it.
4832 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4834 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4836 // On PPC64, promote integers to 64-bit values.
4837 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4838 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4839 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4840 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4843 // FIXME memcpy is used way more than necessary. Correctness first.
4844 // Note: "by value" is code for passing a structure by value, not
4846 if (Flags.isByVal()) {
4847 unsigned Size = Flags.getByValSize();
4848 // Very small objects are passed right-justified. Everything else is
4849 // passed left-justified.
4850 if (Size==1 || Size==2) {
4851 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4852 if (GPR_idx != NumGPRs) {
4853 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4854 MachinePointerInfo(), VT,
4855 false, false, false, 0);
4856 MemOpChains.push_back(Load.getValue(1));
4857 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4859 ArgOffset += PtrByteSize;
4861 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4862 PtrOff.getValueType());
4863 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4864 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4867 ArgOffset += PtrByteSize;
4871 // Copy entire object into memory. There are cases where gcc-generated
4872 // code assumes it is there, even if it could be put entirely into
4873 // registers. (This is not what the doc says.)
4874 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4878 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4879 // copy the pieces of the object that fit into registers from the
4880 // parameter save area.
4881 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4882 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4883 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4884 if (GPR_idx != NumGPRs) {
4885 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4886 MachinePointerInfo(),
4887 false, false, false, 0);
4888 MemOpChains.push_back(Load.getValue(1));
4889 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4890 ArgOffset += PtrByteSize;
4892 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4899 switch (Arg.getSimpleValueType().SimpleTy) {
4900 default: llvm_unreachable("Unexpected ValueType for argument!");
4904 if (GPR_idx != NumGPRs) {
4905 if (Arg.getValueType() == MVT::i1)
4906 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4908 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4910 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4911 isPPC64, isTailCall, false, MemOpChains,
4912 TailCallArguments, dl);
4914 ArgOffset += PtrByteSize;
4918 if (FPR_idx != NumFPRs) {
4919 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4922 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4923 MachinePointerInfo(), false, false, 0);
4924 MemOpChains.push_back(Store);
4926 // Float varargs are always shadowed in available integer registers
4927 if (GPR_idx != NumGPRs) {
4928 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4929 MachinePointerInfo(), false, false,
4931 MemOpChains.push_back(Load.getValue(1));
4932 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4934 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4935 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4936 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4937 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4938 MachinePointerInfo(),
4939 false, false, false, 0);
4940 MemOpChains.push_back(Load.getValue(1));
4941 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4944 // If we have any FPRs remaining, we may also have GPRs remaining.
4945 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4947 if (GPR_idx != NumGPRs)
4949 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4950 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4954 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4955 isPPC64, isTailCall, false, MemOpChains,
4956 TailCallArguments, dl);
4960 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4967 // These go aligned on the stack, or in the corresponding R registers
4968 // when within range. The Darwin PPC ABI doc claims they also go in
4969 // V registers; in fact gcc does this only for arguments that are
4970 // prototyped, not for those that match the ... We do it for all
4971 // arguments, seems to work.
4972 while (ArgOffset % 16 !=0) {
4973 ArgOffset += PtrByteSize;
4974 if (GPR_idx != NumGPRs)
4977 // We could elide this store in the case where the object fits
4978 // entirely in R registers. Maybe later.
4979 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4980 DAG.getConstant(ArgOffset, PtrVT));
4981 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4982 MachinePointerInfo(), false, false, 0);
4983 MemOpChains.push_back(Store);
4984 if (VR_idx != NumVRs) {
4985 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4986 MachinePointerInfo(),
4987 false, false, false, 0);
4988 MemOpChains.push_back(Load.getValue(1));
4989 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4992 for (unsigned i=0; i<16; i+=PtrByteSize) {
4993 if (GPR_idx == NumGPRs)
4995 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4996 DAG.getConstant(i, PtrVT));
4997 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4998 false, false, false, 0);
4999 MemOpChains.push_back(Load.getValue(1));
5000 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5005 // Non-varargs Altivec params generally go in registers, but have
5006 // stack space allocated at the end.
5007 if (VR_idx != NumVRs) {
5008 // Doesn't have GPR space allocated.
5009 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5010 } else if (nAltivecParamsAtEnd==0) {
5011 // We are emitting Altivec params in order.
5012 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5013 isPPC64, isTailCall, true, MemOpChains,
5014 TailCallArguments, dl);
5020 // If all Altivec parameters fit in registers, as they usually do,
5021 // they get stack space following the non-Altivec parameters. We
5022 // don't track this here because nobody below needs it.
5023 // If there are more Altivec parameters than fit in registers emit
5025 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5027 // Offset is aligned; skip 1st 12 params which go in V registers.
5028 ArgOffset = ((ArgOffset+15)/16)*16;
5030 for (unsigned i = 0; i != NumOps; ++i) {
5031 SDValue Arg = OutVals[i];
5032 EVT ArgType = Outs[i].VT;
5033 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5034 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5037 // We are emitting Altivec params in order.
5038 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5039 isPPC64, isTailCall, true, MemOpChains,
5040 TailCallArguments, dl);
5047 if (!MemOpChains.empty())
5048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5050 // On Darwin, R12 must contain the address of an indirect callee. This does
5051 // not mean the MTCTR instruction must use R12; it's easier to model this as
5052 // an extra parameter, so do that.
5054 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5055 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5056 !isBLACompatibleAddress(Callee, DAG))
5057 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5058 PPC::R12), Callee));
5060 // Build a sequence of copy-to-reg nodes chained together with token chain
5061 // and flag operands which copy the outgoing args into the appropriate regs.
5063 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5064 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5065 RegsToPass[i].second, InFlag);
5066 InFlag = Chain.getValue(1);
5070 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5071 FPOp, true, TailCallArguments);
5073 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5074 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5079 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5080 MachineFunction &MF, bool isVarArg,
5081 const SmallVectorImpl<ISD::OutputArg> &Outs,
5082 LLVMContext &Context) const {
5083 SmallVector<CCValAssign, 16> RVLocs;
5084 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5085 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5089 PPCTargetLowering::LowerReturn(SDValue Chain,
5090 CallingConv::ID CallConv, bool isVarArg,
5091 const SmallVectorImpl<ISD::OutputArg> &Outs,
5092 const SmallVectorImpl<SDValue> &OutVals,
5093 SDLoc dl, SelectionDAG &DAG) const {
5095 SmallVector<CCValAssign, 16> RVLocs;
5096 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5098 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5101 SmallVector<SDValue, 4> RetOps(1, Chain);
5103 // Copy the result values into the output registers.
5104 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5105 CCValAssign &VA = RVLocs[i];
5106 assert(VA.isRegLoc() && "Can only return in registers!");
5108 SDValue Arg = OutVals[i];
5110 switch (VA.getLocInfo()) {
5111 default: llvm_unreachable("Unknown loc info!");
5112 case CCValAssign::Full: break;
5113 case CCValAssign::AExt:
5114 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5116 case CCValAssign::ZExt:
5117 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5119 case CCValAssign::SExt:
5120 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5124 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5125 Flag = Chain.getValue(1);
5126 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5129 RetOps[0] = Chain; // Update chain.
5131 // Add the flag if we have it.
5133 RetOps.push_back(Flag);
5135 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5138 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5139 const PPCSubtarget &Subtarget) const {
5140 // When we pop the dynamic allocation we need to restore the SP link.
5143 // Get the corect type for pointers.
5144 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5146 // Construct the stack pointer operand.
5147 bool isPPC64 = Subtarget.isPPC64();
5148 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5149 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5151 // Get the operands for the STACKRESTORE.
5152 SDValue Chain = Op.getOperand(0);
5153 SDValue SaveSP = Op.getOperand(1);
5155 // Load the old link SP.
5156 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5157 MachinePointerInfo(),
5158 false, false, false, 0);
5160 // Restore the stack pointer.
5161 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5163 // Store the old link SP.
5164 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5171 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5172 MachineFunction &MF = DAG.getMachineFunction();
5173 bool isPPC64 = Subtarget.isPPC64();
5174 bool isDarwinABI = Subtarget.isDarwinABI();
5175 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5177 // Get current frame pointer save index. The users of this index will be
5178 // primarily DYNALLOC instructions.
5179 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5180 int RASI = FI->getReturnAddrSaveIndex();
5182 // If the frame pointer save index hasn't been defined yet.
5184 // Find out what the fix offset of the frame pointer save area.
5185 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5186 // Allocate the frame index for frame pointer save area.
5187 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5189 FI->setReturnAddrSaveIndex(RASI);
5191 return DAG.getFrameIndex(RASI, PtrVT);
5195 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5196 MachineFunction &MF = DAG.getMachineFunction();
5197 bool isPPC64 = Subtarget.isPPC64();
5198 bool isDarwinABI = Subtarget.isDarwinABI();
5199 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5201 // Get current frame pointer save index. The users of this index will be
5202 // primarily DYNALLOC instructions.
5203 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5204 int FPSI = FI->getFramePointerSaveIndex();
5206 // If the frame pointer save index hasn't been defined yet.
5208 // Find out what the fix offset of the frame pointer save area.
5209 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5212 // Allocate the frame index for frame pointer save area.
5213 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5215 FI->setFramePointerSaveIndex(FPSI);
5217 return DAG.getFrameIndex(FPSI, PtrVT);
5220 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5222 const PPCSubtarget &Subtarget) const {
5224 SDValue Chain = Op.getOperand(0);
5225 SDValue Size = Op.getOperand(1);
5228 // Get the corect type for pointers.
5229 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5231 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5232 DAG.getConstant(0, PtrVT), Size);
5233 // Construct a node for the frame pointer save index.
5234 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5235 // Build a DYNALLOC node.
5236 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5237 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5238 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5241 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5242 SelectionDAG &DAG) const {
5244 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5245 DAG.getVTList(MVT::i32, MVT::Other),
5246 Op.getOperand(0), Op.getOperand(1));
5249 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5250 SelectionDAG &DAG) const {
5252 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5253 Op.getOperand(0), Op.getOperand(1));
5256 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5257 assert(Op.getValueType() == MVT::i1 &&
5258 "Custom lowering only for i1 loads");
5260 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5263 LoadSDNode *LD = cast<LoadSDNode>(Op);
5265 SDValue Chain = LD->getChain();
5266 SDValue BasePtr = LD->getBasePtr();
5267 MachineMemOperand *MMO = LD->getMemOperand();
5269 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5270 BasePtr, MVT::i8, MMO);
5271 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5273 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5274 return DAG.getMergeValues(Ops, dl);
5277 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5278 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5279 "Custom lowering only for i1 stores");
5281 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5284 StoreSDNode *ST = cast<StoreSDNode>(Op);
5286 SDValue Chain = ST->getChain();
5287 SDValue BasePtr = ST->getBasePtr();
5288 SDValue Value = ST->getValue();
5289 MachineMemOperand *MMO = ST->getMemOperand();
5291 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5292 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5295 // FIXME: Remove this once the ANDI glue bug is fixed:
5296 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5297 assert(Op.getValueType() == MVT::i1 &&
5298 "Custom lowering only for i1 results");
5301 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5305 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5307 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5308 // Not FP? Not a fsel.
5309 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5310 !Op.getOperand(2).getValueType().isFloatingPoint())
5313 // We might be able to do better than this under some circumstances, but in
5314 // general, fsel-based lowering of select is a finite-math-only optimization.
5315 // For more information, see section F.3 of the 2.06 ISA specification.
5316 if (!DAG.getTarget().Options.NoInfsFPMath ||
5317 !DAG.getTarget().Options.NoNaNsFPMath)
5320 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5322 EVT ResVT = Op.getValueType();
5323 EVT CmpVT = Op.getOperand(0).getValueType();
5324 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5325 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5328 // If the RHS of the comparison is a 0.0, we don't need to do the
5329 // subtraction at all.
5331 if (isFloatingPointZero(RHS))
5333 default: break; // SETUO etc aren't handled by fsel.
5337 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5338 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5339 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5340 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5341 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5342 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5343 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5346 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5349 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5350 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5351 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5354 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5357 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5358 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5359 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5360 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5365 default: break; // SETUO etc aren't handled by fsel.
5369 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5370 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5371 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5372 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5373 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5374 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5375 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5376 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5379 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5380 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5381 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5382 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5385 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5386 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5387 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5388 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5391 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5392 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5393 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5394 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5397 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5398 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5399 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5400 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5405 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5408 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5409 SDValue Src = Op.getOperand(0);
5410 if (Src.getValueType() == MVT::f32)
5411 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5414 switch (Op.getSimpleValueType().SimpleTy) {
5415 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5417 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5418 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5423 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5424 "i64 FP_TO_UINT is supported only with FPCVT");
5425 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5431 // Convert the FP value to an int value through memory.
5432 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5433 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5434 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5435 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5436 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5438 // Emit a store to the stack slot.
5441 MachineFunction &MF = DAG.getMachineFunction();
5442 MachineMemOperand *MMO =
5443 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5444 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5445 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5446 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5448 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5449 MPI, false, false, 0);
5451 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5453 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5454 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5455 DAG.getConstant(4, FIPtr.getValueType()));
5456 MPI = MPI.getWithOffset(4);
5464 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5467 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5469 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5470 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5474 // We're trying to insert a regular store, S, and then a load, L. If the
5475 // incoming value, O, is a load, we might just be able to have our load use the
5476 // address used by O. However, we don't know if anything else will store to
5477 // that address before we can load from it. To prevent this situation, we need
5478 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5479 // the same chain operand as O, we create a token factor from the chain results
5480 // of O and L, and we replace all uses of O's chain result with that token
5481 // factor (see spliceIntoChain below for this last part).
5482 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5484 SelectionDAG &DAG) const {
5486 if ((Op.getOpcode() == ISD::FP_TO_UINT ||
5487 Op.getOpcode() == ISD::FP_TO_SINT) &&
5488 isOperationLegalOrCustom(Op.getOpcode(),
5489 Op.getOperand(0).getValueType())) {
5491 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5495 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5496 if (!LD || !ISD::isNON_EXTLoad(LD) || LD->isVolatile() || LD->isNonTemporal())
5498 if (LD->getMemoryVT() != MemVT)
5501 RLI.Ptr = LD->getBasePtr();
5502 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5503 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5504 "Non-pre-inc AM on PPC?");
5505 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5509 RLI.Chain = LD->getChain();
5510 RLI.MPI = LD->getPointerInfo();
5511 RLI.IsInvariant = LD->isInvariant();
5512 RLI.Alignment = LD->getAlignment();
5513 RLI.AAInfo = LD->getAAInfo();
5514 RLI.Ranges = LD->getRanges();
5516 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5520 // Given the head of the old chain, ResChain, insert a token factor containing
5521 // it and NewResChain, and make users of ResChain now be users of that token
5523 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5524 SDValue NewResChain,
5525 SelectionDAG &DAG) const {
5529 SDLoc dl(NewResChain);
5531 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5532 NewResChain, DAG.getUNDEF(MVT::Other));
5533 assert(TF.getNode() != NewResChain.getNode() &&
5534 "A new TF really is required here");
5536 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5537 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5540 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5541 SelectionDAG &DAG) const {
5543 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5544 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5547 if (Op.getOperand(0).getValueType() == MVT::i1)
5548 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5549 DAG.getConstantFP(1.0, Op.getValueType()),
5550 DAG.getConstantFP(0.0, Op.getValueType()));
5552 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5553 "UINT_TO_FP is supported only with FPCVT");
5555 // If we have FCFIDS, then use it when converting to single-precision.
5556 // Otherwise, convert to double-precision and then round.
5557 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5558 (Op.getOpcode() == ISD::UINT_TO_FP ?
5559 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5560 (Op.getOpcode() == ISD::UINT_TO_FP ?
5561 PPCISD::FCFIDU : PPCISD::FCFID);
5562 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5563 MVT::f32 : MVT::f64;
5565 if (Op.getOperand(0).getValueType() == MVT::i64) {
5566 SDValue SINT = Op.getOperand(0);
5567 // When converting to single-precision, we actually need to convert
5568 // to double-precision first and then round to single-precision.
5569 // To avoid double-rounding effects during that operation, we have
5570 // to prepare the input operand. Bits that might be truncated when
5571 // converting to double-precision are replaced by a bit that won't
5572 // be lost at this stage, but is below the single-precision rounding
5575 // However, if -enable-unsafe-fp-math is in effect, accept double
5576 // rounding to avoid the extra overhead.
5577 if (Op.getValueType() == MVT::f32 &&
5578 !Subtarget.hasFPCVT() &&
5579 !DAG.getTarget().Options.UnsafeFPMath) {
5581 // Twiddle input to make sure the low 11 bits are zero. (If this
5582 // is the case, we are guaranteed the value will fit into the 53 bit
5583 // mantissa of an IEEE double-precision value without rounding.)
5584 // If any of those low 11 bits were not zero originally, make sure
5585 // bit 12 (value 2048) is set instead, so that the final rounding
5586 // to single-precision gets the correct result.
5587 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5588 SINT, DAG.getConstant(2047, MVT::i64));
5589 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5590 Round, DAG.getConstant(2047, MVT::i64));
5591 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5592 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5593 Round, DAG.getConstant(-2048, MVT::i64));
5595 // However, we cannot use that value unconditionally: if the magnitude
5596 // of the input value is small, the bit-twiddling we did above might
5597 // end up visibly changing the output. Fortunately, in that case, we
5598 // don't need to twiddle bits since the original input will convert
5599 // exactly to double-precision floating-point already. Therefore,
5600 // construct a conditional to use the original value if the top 11
5601 // bits are all sign-bit copies, and use the rounded value computed
5603 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5604 SINT, DAG.getConstant(53, MVT::i32));
5605 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5606 Cond, DAG.getConstant(1, MVT::i64));
5607 Cond = DAG.getSetCC(dl, MVT::i32,
5608 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5610 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5616 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5617 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5618 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5620 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5622 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5624 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5626 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5627 FP = DAG.getNode(ISD::FP_ROUND, dl,
5628 MVT::f32, FP, DAG.getIntPtrConstant(0));
5632 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5633 "Unhandled INT_TO_FP type in custom expander!");
5634 // Since we only generate this in 64-bit mode, we can take advantage of
5635 // 64-bit registers. In particular, sign extend the input value into the
5636 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5637 // then lfd it and fcfid it.
5638 MachineFunction &MF = DAG.getMachineFunction();
5639 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5643 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5646 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5648 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5649 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5651 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5652 MachinePointerInfo::getFixedStack(FrameIdx),
5655 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5656 "Expected an i32 store");
5660 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5664 MachineMemOperand *MMO =
5665 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5666 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5667 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5668 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5669 PPCISD::LFIWZX : PPCISD::LFIWAX,
5670 dl, DAG.getVTList(MVT::f64, MVT::Other),
5671 Ops, MVT::i32, MMO);
5673 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5675 assert(Subtarget.isPPC64() &&
5676 "i32->FP without LFIWAX supported only on PPC64");
5678 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5679 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5681 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5684 // STD the extended value into the stack slot.
5685 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5686 MachinePointerInfo::getFixedStack(FrameIdx),
5689 // Load the value as a double.
5690 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5691 MachinePointerInfo::getFixedStack(FrameIdx),
5692 false, false, false, 0);
5695 // FCFID it and return it.
5696 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5697 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5698 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5702 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5703 SelectionDAG &DAG) const {
5706 The rounding mode is in bits 30:31 of FPSR, and has the following
5713 FLT_ROUNDS, on the other hand, expects the following:
5720 To perform the conversion, we do:
5721 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5724 MachineFunction &MF = DAG.getMachineFunction();
5725 EVT VT = Op.getValueType();
5726 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5728 // Save FP Control Word to register
5730 MVT::f64, // return register
5731 MVT::Glue // unused in this context
5733 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5735 // Save FP register to stack slot
5736 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5737 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5738 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5739 StackSlot, MachinePointerInfo(), false, false,0);
5741 // Load FP Control Word from low 32 bits of stack slot.
5742 SDValue Four = DAG.getConstant(4, PtrVT);
5743 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5744 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5745 false, false, false, 0);
5747 // Transform as necessary
5749 DAG.getNode(ISD::AND, dl, MVT::i32,
5750 CWD, DAG.getConstant(3, MVT::i32));
5752 DAG.getNode(ISD::SRL, dl, MVT::i32,
5753 DAG.getNode(ISD::AND, dl, MVT::i32,
5754 DAG.getNode(ISD::XOR, dl, MVT::i32,
5755 CWD, DAG.getConstant(3, MVT::i32)),
5756 DAG.getConstant(3, MVT::i32)),
5757 DAG.getConstant(1, MVT::i32));
5760 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5762 return DAG.getNode((VT.getSizeInBits() < 16 ?
5763 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5766 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5767 EVT VT = Op.getValueType();
5768 unsigned BitWidth = VT.getSizeInBits();
5770 assert(Op.getNumOperands() == 3 &&
5771 VT == Op.getOperand(1).getValueType() &&
5774 // Expand into a bunch of logical ops. Note that these ops
5775 // depend on the PPC behavior for oversized shift amounts.
5776 SDValue Lo = Op.getOperand(0);
5777 SDValue Hi = Op.getOperand(1);
5778 SDValue Amt = Op.getOperand(2);
5779 EVT AmtVT = Amt.getValueType();
5781 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5782 DAG.getConstant(BitWidth, AmtVT), Amt);
5783 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5784 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5785 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5786 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5787 DAG.getConstant(-BitWidth, AmtVT));
5788 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5789 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5790 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5791 SDValue OutOps[] = { OutLo, OutHi };
5792 return DAG.getMergeValues(OutOps, dl);
5795 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5796 EVT VT = Op.getValueType();
5798 unsigned BitWidth = VT.getSizeInBits();
5799 assert(Op.getNumOperands() == 3 &&
5800 VT == Op.getOperand(1).getValueType() &&
5803 // Expand into a bunch of logical ops. Note that these ops
5804 // depend on the PPC behavior for oversized shift amounts.
5805 SDValue Lo = Op.getOperand(0);
5806 SDValue Hi = Op.getOperand(1);
5807 SDValue Amt = Op.getOperand(2);
5808 EVT AmtVT = Amt.getValueType();
5810 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5811 DAG.getConstant(BitWidth, AmtVT), Amt);
5812 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5813 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5814 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5815 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5816 DAG.getConstant(-BitWidth, AmtVT));
5817 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5818 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5819 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5820 SDValue OutOps[] = { OutLo, OutHi };
5821 return DAG.getMergeValues(OutOps, dl);
5824 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5826 EVT VT = Op.getValueType();
5827 unsigned BitWidth = VT.getSizeInBits();
5828 assert(Op.getNumOperands() == 3 &&
5829 VT == Op.getOperand(1).getValueType() &&
5832 // Expand into a bunch of logical ops, followed by a select_cc.
5833 SDValue Lo = Op.getOperand(0);
5834 SDValue Hi = Op.getOperand(1);
5835 SDValue Amt = Op.getOperand(2);
5836 EVT AmtVT = Amt.getValueType();
5838 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5839 DAG.getConstant(BitWidth, AmtVT), Amt);
5840 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5841 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5842 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5843 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5844 DAG.getConstant(-BitWidth, AmtVT));
5845 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5846 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5847 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5848 Tmp4, Tmp6, ISD::SETLE);
5849 SDValue OutOps[] = { OutLo, OutHi };
5850 return DAG.getMergeValues(OutOps, dl);
5853 //===----------------------------------------------------------------------===//
5854 // Vector related lowering.
5857 /// BuildSplatI - Build a canonical splati of Val with an element size of
5858 /// SplatSize. Cast the result to VT.
5859 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5860 SelectionDAG &DAG, SDLoc dl) {
5861 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5863 static const EVT VTys[] = { // canonical VT to use for each size.
5864 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5867 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5869 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5873 EVT CanonicalVT = VTys[SplatSize-1];
5875 // Build a canonical splat for this value.
5876 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5877 SmallVector<SDValue, 8> Ops;
5878 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5879 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5880 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5883 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5884 /// specified intrinsic ID.
5885 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5886 SelectionDAG &DAG, SDLoc dl,
5887 EVT DestVT = MVT::Other) {
5888 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5889 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5890 DAG.getConstant(IID, MVT::i32), Op);
5893 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5894 /// specified intrinsic ID.
5895 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5896 SelectionDAG &DAG, SDLoc dl,
5897 EVT DestVT = MVT::Other) {
5898 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5899 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5900 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5903 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5904 /// specified intrinsic ID.
5905 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5906 SDValue Op2, SelectionDAG &DAG,
5907 SDLoc dl, EVT DestVT = MVT::Other) {
5908 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5909 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5910 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5914 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5915 /// amount. The result has the specified value type.
5916 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5917 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5918 // Force LHS/RHS to be the right type.
5919 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5920 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5923 for (unsigned i = 0; i != 16; ++i)
5925 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5926 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5929 // If this is a case we can't handle, return null and let the default
5930 // expansion code take care of it. If we CAN select this case, and if it
5931 // selects to a single instruction, return Op. Otherwise, if we can codegen
5932 // this case more efficiently than a constant pool load, lower it to the
5933 // sequence of ops that should be used.
5934 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5935 SelectionDAG &DAG) const {
5937 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5938 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5940 // Check if this is a splat of a constant value.
5941 APInt APSplatBits, APSplatUndef;
5942 unsigned SplatBitSize;
5944 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5945 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5948 unsigned SplatBits = APSplatBits.getZExtValue();
5949 unsigned SplatUndef = APSplatUndef.getZExtValue();
5950 unsigned SplatSize = SplatBitSize / 8;
5952 // First, handle single instruction cases.
5955 if (SplatBits == 0) {
5956 // Canonicalize all zero vectors to be v4i32.
5957 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5958 SDValue Z = DAG.getConstant(0, MVT::i32);
5959 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5960 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5965 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5966 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5968 if (SextVal >= -16 && SextVal <= 15)
5969 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5972 // Two instruction sequences.
5974 // If this value is in the range [-32,30] and is even, use:
5975 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5976 // If this value is in the range [17,31] and is odd, use:
5977 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5978 // If this value is in the range [-31,-17] and is odd, use:
5979 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5980 // Note the last two are three-instruction sequences.
5981 if (SextVal >= -32 && SextVal <= 31) {
5982 // To avoid having these optimizations undone by constant folding,
5983 // we convert to a pseudo that will be expanded later into one of
5985 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5986 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5987 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5988 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5989 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5990 if (VT == Op.getValueType())
5993 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5996 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5997 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5999 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6000 // Make -1 and vspltisw -1:
6001 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6003 // Make the VSLW intrinsic, computing 0x8000_0000.
6004 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6007 // xor by OnesV to invert it.
6008 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6009 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6012 // The remaining cases assume either big endian element order or
6013 // a splat-size that equates to the element size of the vector
6014 // to be built. An example that doesn't work for little endian is
6015 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6016 // and a vector element size of 16 bits. The code below will
6017 // produce the vector in big endian element order, which for little
6018 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6020 // For now, just avoid these optimizations in that case.
6021 // FIXME: Develop correct optimizations for LE with mismatched
6022 // splat and element sizes.
6024 if (Subtarget.isLittleEndian() &&
6025 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6028 // Check to see if this is a wide variety of vsplti*, binop self cases.
6029 static const signed char SplatCsts[] = {
6030 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6031 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6034 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6035 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6036 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6037 int i = SplatCsts[idx];
6039 // Figure out what shift amount will be used by altivec if shifted by i in
6041 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6043 // vsplti + shl self.
6044 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6045 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6046 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6047 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6048 Intrinsic::ppc_altivec_vslw
6050 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6051 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6054 // vsplti + srl self.
6055 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6056 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6057 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6058 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6059 Intrinsic::ppc_altivec_vsrw
6061 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6062 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6065 // vsplti + sra self.
6066 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6067 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6068 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6069 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6070 Intrinsic::ppc_altivec_vsraw
6072 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6073 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6076 // vsplti + rol self.
6077 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6078 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6079 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6080 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6081 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6082 Intrinsic::ppc_altivec_vrlw
6084 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6085 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6088 // t = vsplti c, result = vsldoi t, t, 1
6089 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6090 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6091 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6093 // t = vsplti c, result = vsldoi t, t, 2
6094 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6095 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6096 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6098 // t = vsplti c, result = vsldoi t, t, 3
6099 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6100 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6101 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6108 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6109 /// the specified operations to build the shuffle.
6110 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6111 SDValue RHS, SelectionDAG &DAG,
6113 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6114 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6115 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6118 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6130 if (OpNum == OP_COPY) {
6131 if (LHSID == (1*9+2)*9+3) return LHS;
6132 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6136 SDValue OpLHS, OpRHS;
6137 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6138 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6142 default: llvm_unreachable("Unknown i32 permute!");
6144 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6145 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6146 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6147 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6150 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6151 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6152 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6153 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6156 for (unsigned i = 0; i != 16; ++i)
6157 ShufIdxs[i] = (i&3)+0;
6160 for (unsigned i = 0; i != 16; ++i)
6161 ShufIdxs[i] = (i&3)+4;
6164 for (unsigned i = 0; i != 16; ++i)
6165 ShufIdxs[i] = (i&3)+8;
6168 for (unsigned i = 0; i != 16; ++i)
6169 ShufIdxs[i] = (i&3)+12;
6172 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6174 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6176 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6178 EVT VT = OpLHS.getValueType();
6179 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6180 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6181 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6182 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6185 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6186 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6187 /// return the code it can be lowered into. Worst case, it can always be
6188 /// lowered into a vperm.
6189 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6190 SelectionDAG &DAG) const {
6192 SDValue V1 = Op.getOperand(0);
6193 SDValue V2 = Op.getOperand(1);
6194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6195 EVT VT = Op.getValueType();
6196 bool isLittleEndian = Subtarget.isLittleEndian();
6198 // Cases that are handled by instructions that take permute immediates
6199 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6200 // selected by the instruction selector.
6201 if (V2.getOpcode() == ISD::UNDEF) {
6202 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6203 PPC::isSplatShuffleMask(SVOp, 2) ||
6204 PPC::isSplatShuffleMask(SVOp, 4) ||
6205 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6206 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6207 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6208 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6209 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6210 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6211 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6212 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6213 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6218 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6219 // and produce a fixed permutation. If any of these match, do not lower to
6221 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6222 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6223 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6224 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6225 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6226 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6227 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6228 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6229 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6230 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6233 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6234 // perfect shuffle table to emit an optimal matching sequence.
6235 ArrayRef<int> PermMask = SVOp->getMask();
6237 unsigned PFIndexes[4];
6238 bool isFourElementShuffle = true;
6239 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6240 unsigned EltNo = 8; // Start out undef.
6241 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6242 if (PermMask[i*4+j] < 0)
6243 continue; // Undef, ignore it.
6245 unsigned ByteSource = PermMask[i*4+j];
6246 if ((ByteSource & 3) != j) {
6247 isFourElementShuffle = false;
6252 EltNo = ByteSource/4;
6253 } else if (EltNo != ByteSource/4) {
6254 isFourElementShuffle = false;
6258 PFIndexes[i] = EltNo;
6261 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6262 // perfect shuffle vector to determine if it is cost effective to do this as
6263 // discrete instructions, or whether we should use a vperm.
6264 // For now, we skip this for little endian until such time as we have a
6265 // little-endian perfect shuffle table.
6266 if (isFourElementShuffle && !isLittleEndian) {
6267 // Compute the index in the perfect shuffle table.
6268 unsigned PFTableIndex =
6269 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6271 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6272 unsigned Cost = (PFEntry >> 30);
6274 // Determining when to avoid vperm is tricky. Many things affect the cost
6275 // of vperm, particularly how many times the perm mask needs to be computed.
6276 // For example, if the perm mask can be hoisted out of a loop or is already
6277 // used (perhaps because there are multiple permutes with the same shuffle
6278 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6279 // the loop requires an extra register.
6281 // As a compromise, we only emit discrete instructions if the shuffle can be
6282 // generated in 3 or fewer operations. When we have loop information
6283 // available, if this block is within a loop, we should avoid using vperm
6284 // for 3-operation perms and use a constant pool load instead.
6286 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6289 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6290 // vector that will get spilled to the constant pool.
6291 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6293 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6294 // that it is in input element units, not in bytes. Convert now.
6296 // For little endian, the order of the input vectors is reversed, and
6297 // the permutation mask is complemented with respect to 31. This is
6298 // necessary to produce proper semantics with the big-endian-biased vperm
6300 EVT EltVT = V1.getValueType().getVectorElementType();
6301 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6303 SmallVector<SDValue, 16> ResultMask;
6304 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6305 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6307 for (unsigned j = 0; j != BytesPerElement; ++j)
6309 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6312 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6316 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6319 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6322 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6326 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6327 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6328 /// information about the intrinsic.
6329 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6331 unsigned IntrinsicID =
6332 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6335 switch (IntrinsicID) {
6336 default: return false;
6337 // Comparison predicates.
6338 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6339 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6340 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6341 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6342 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6343 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6344 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6345 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6346 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6347 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6348 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6349 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6350 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6352 // Normal Comparisons.
6353 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6354 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6355 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6356 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6357 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6358 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6359 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6360 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6361 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6362 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6363 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6364 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6365 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6370 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6371 /// lower, do it, otherwise return null.
6372 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6373 SelectionDAG &DAG) const {
6374 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6375 // opcode number of the comparison.
6379 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6380 return SDValue(); // Don't custom lower most intrinsics.
6382 // If this is a non-dot comparison, make the VCMP node and we are done.
6384 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6385 Op.getOperand(1), Op.getOperand(2),
6386 DAG.getConstant(CompareOpc, MVT::i32));
6387 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6390 // Create the PPCISD altivec 'dot' comparison node.
6392 Op.getOperand(2), // LHS
6393 Op.getOperand(3), // RHS
6394 DAG.getConstant(CompareOpc, MVT::i32)
6396 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6397 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6399 // Now that we have the comparison, emit a copy from the CR to a GPR.
6400 // This is flagged to the above dot comparison.
6401 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6402 DAG.getRegister(PPC::CR6, MVT::i32),
6403 CompNode.getValue(1));
6405 // Unpack the result based on how the target uses it.
6406 unsigned BitNo; // Bit # of CR6.
6407 bool InvertBit; // Invert result?
6408 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6409 default: // Can't happen, don't crash on invalid number though.
6410 case 0: // Return the value of the EQ bit of CR6.
6411 BitNo = 0; InvertBit = false;
6413 case 1: // Return the inverted value of the EQ bit of CR6.
6414 BitNo = 0; InvertBit = true;
6416 case 2: // Return the value of the LT bit of CR6.
6417 BitNo = 2; InvertBit = false;
6419 case 3: // Return the inverted value of the LT bit of CR6.
6420 BitNo = 2; InvertBit = true;
6424 // Shift the bit into the low position.
6425 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6426 DAG.getConstant(8-(3-BitNo), MVT::i32));
6428 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6429 DAG.getConstant(1, MVT::i32));
6431 // If we are supposed to, toggle the bit.
6433 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6434 DAG.getConstant(1, MVT::i32));
6438 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6439 SelectionDAG &DAG) const {
6441 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6442 // instructions), but for smaller types, we need to first extend up to v2i32
6443 // before doing going farther.
6444 if (Op.getValueType() == MVT::v2i64) {
6445 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6446 if (ExtVT != MVT::v2i32) {
6447 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6448 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6449 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6450 ExtVT.getVectorElementType(), 4)));
6451 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6452 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6453 DAG.getValueType(MVT::v2i32));
6462 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6463 SelectionDAG &DAG) const {
6465 // Create a stack slot that is 16-byte aligned.
6466 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6467 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6468 EVT PtrVT = getPointerTy();
6469 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6471 // Store the input value into Value#0 of the stack slot.
6472 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6473 Op.getOperand(0), FIdx, MachinePointerInfo(),
6476 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6477 false, false, false, 0);
6480 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6482 if (Op.getValueType() == MVT::v4i32) {
6483 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6485 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6486 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6488 SDValue RHSSwap = // = vrlw RHS, 16
6489 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6491 // Shrinkify inputs to v8i16.
6492 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6493 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6494 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6496 // Low parts multiplied together, generating 32-bit results (we ignore the
6498 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6499 LHS, RHS, DAG, dl, MVT::v4i32);
6501 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6502 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6503 // Shift the high parts up 16 bits.
6504 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6506 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6507 } else if (Op.getValueType() == MVT::v8i16) {
6508 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6510 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6512 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6513 LHS, RHS, Zero, DAG, dl);
6514 } else if (Op.getValueType() == MVT::v16i8) {
6515 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6516 bool isLittleEndian = Subtarget.isLittleEndian();
6518 // Multiply the even 8-bit parts, producing 16-bit sums.
6519 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6520 LHS, RHS, DAG, dl, MVT::v8i16);
6521 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6523 // Multiply the odd 8-bit parts, producing 16-bit sums.
6524 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6525 LHS, RHS, DAG, dl, MVT::v8i16);
6526 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6528 // Merge the results together. Because vmuleub and vmuloub are
6529 // instructions with a big-endian bias, we must reverse the
6530 // element numbering and reverse the meaning of "odd" and "even"
6531 // when generating little endian code.
6533 for (unsigned i = 0; i != 8; ++i) {
6534 if (isLittleEndian) {
6536 Ops[i*2+1] = 2*i+16;
6539 Ops[i*2+1] = 2*i+1+16;
6543 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6545 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6547 llvm_unreachable("Unknown mul to lower!");
6551 /// LowerOperation - Provide custom lowering hooks for some operations.
6553 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6554 switch (Op.getOpcode()) {
6555 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6556 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6557 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6558 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6559 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6560 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6561 case ISD::SETCC: return LowerSETCC(Op, DAG);
6562 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6563 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6565 return LowerVASTART(Op, DAG, Subtarget);
6568 return LowerVAARG(Op, DAG, Subtarget);
6571 return LowerVACOPY(Op, DAG, Subtarget);
6573 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6574 case ISD::DYNAMIC_STACKALLOC:
6575 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6577 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6578 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6580 case ISD::LOAD: return LowerLOAD(Op, DAG);
6581 case ISD::STORE: return LowerSTORE(Op, DAG);
6582 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6583 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6584 case ISD::FP_TO_UINT:
6585 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6587 case ISD::UINT_TO_FP:
6588 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6589 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6591 // Lower 64-bit shifts.
6592 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6593 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6594 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6596 // Vector-related lowering.
6597 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6598 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6599 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6600 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6601 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6602 case ISD::MUL: return LowerMUL(Op, DAG);
6604 // For counter-based loop handling.
6605 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6607 // Frame & Return address.
6608 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6609 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6613 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6614 SmallVectorImpl<SDValue>&Results,
6615 SelectionDAG &DAG) const {
6616 const TargetMachine &TM = getTargetMachine();
6618 switch (N->getOpcode()) {
6620 llvm_unreachable("Do not know how to custom type legalize this operation!");
6621 case ISD::READCYCLECOUNTER: {
6622 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6623 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6625 Results.push_back(RTB);
6626 Results.push_back(RTB.getValue(1));
6627 Results.push_back(RTB.getValue(2));
6630 case ISD::INTRINSIC_W_CHAIN: {
6631 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6632 Intrinsic::ppc_is_decremented_ctr_nonzero)
6635 assert(N->getValueType(0) == MVT::i1 &&
6636 "Unexpected result type for CTR decrement intrinsic");
6637 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6638 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6639 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6642 Results.push_back(NewInt);
6643 Results.push_back(NewInt.getValue(1));
6647 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6648 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6651 EVT VT = N->getValueType(0);
6653 if (VT == MVT::i64) {
6654 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6656 Results.push_back(NewNode);
6657 Results.push_back(NewNode.getValue(1));
6661 case ISD::FP_ROUND_INREG: {
6662 assert(N->getValueType(0) == MVT::ppcf128);
6663 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6664 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6665 MVT::f64, N->getOperand(0),
6666 DAG.getIntPtrConstant(0));
6667 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6668 MVT::f64, N->getOperand(0),
6669 DAG.getIntPtrConstant(1));
6671 // Add the two halves of the long double in round-to-zero mode.
6672 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6674 // We know the low half is about to be thrown away, so just use something
6676 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6680 case ISD::FP_TO_SINT:
6681 // LowerFP_TO_INT() can only handle f32 and f64.
6682 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6684 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6690 //===----------------------------------------------------------------------===//
6691 // Other Lowering Code
6692 //===----------------------------------------------------------------------===//
6694 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6695 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6696 Function *Func = Intrinsic::getDeclaration(M, Id);
6697 return Builder.CreateCall(Func);
6700 // The mappings for emitLeading/TrailingFence is taken from
6701 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6702 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6703 AtomicOrdering Ord, bool IsStore,
6704 bool IsLoad) const {
6705 if (Ord == SequentiallyConsistent)
6706 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6707 else if (isAtLeastRelease(Ord))
6708 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6713 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6714 AtomicOrdering Ord, bool IsStore,
6715 bool IsLoad) const {
6716 if (IsLoad && isAtLeastAcquire(Ord))
6717 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6718 // FIXME: this is too conservative, a dependent branch + isync is enough.
6719 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6720 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6721 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6727 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6728 bool is64bit, unsigned BinOpcode) const {
6729 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6730 const TargetInstrInfo *TII =
6731 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6733 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6734 MachineFunction *F = BB->getParent();
6735 MachineFunction::iterator It = BB;
6738 unsigned dest = MI->getOperand(0).getReg();
6739 unsigned ptrA = MI->getOperand(1).getReg();
6740 unsigned ptrB = MI->getOperand(2).getReg();
6741 unsigned incr = MI->getOperand(3).getReg();
6742 DebugLoc dl = MI->getDebugLoc();
6744 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6745 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6746 F->insert(It, loopMBB);
6747 F->insert(It, exitMBB);
6748 exitMBB->splice(exitMBB->begin(), BB,
6749 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6750 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6752 MachineRegisterInfo &RegInfo = F->getRegInfo();
6753 unsigned TmpReg = (!BinOpcode) ? incr :
6754 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6755 : &PPC::GPRCRegClass);
6759 // fallthrough --> loopMBB
6760 BB->addSuccessor(loopMBB);
6763 // l[wd]arx dest, ptr
6764 // add r0, dest, incr
6765 // st[wd]cx. r0, ptr
6767 // fallthrough --> exitMBB
6769 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6770 .addReg(ptrA).addReg(ptrB);
6772 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6773 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6774 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6775 BuildMI(BB, dl, TII->get(PPC::BCC))
6776 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6777 BB->addSuccessor(loopMBB);
6778 BB->addSuccessor(exitMBB);
6787 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6788 MachineBasicBlock *BB,
6789 bool is8bit, // operation
6790 unsigned BinOpcode) const {
6791 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6792 const TargetInstrInfo *TII =
6793 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6794 // In 64 bit mode we have to use 64 bits for addresses, even though the
6795 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6796 // registers without caring whether they're 32 or 64, but here we're
6797 // doing actual arithmetic on the addresses.
6798 bool is64bit = Subtarget.isPPC64();
6799 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6801 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6802 MachineFunction *F = BB->getParent();
6803 MachineFunction::iterator It = BB;
6806 unsigned dest = MI->getOperand(0).getReg();
6807 unsigned ptrA = MI->getOperand(1).getReg();
6808 unsigned ptrB = MI->getOperand(2).getReg();
6809 unsigned incr = MI->getOperand(3).getReg();
6810 DebugLoc dl = MI->getDebugLoc();
6812 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6813 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6814 F->insert(It, loopMBB);
6815 F->insert(It, exitMBB);
6816 exitMBB->splice(exitMBB->begin(), BB,
6817 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6818 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6820 MachineRegisterInfo &RegInfo = F->getRegInfo();
6821 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6822 : &PPC::GPRCRegClass;
6823 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6824 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6825 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6826 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6827 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6828 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6829 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6830 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6831 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6832 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6833 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6835 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6839 // fallthrough --> loopMBB
6840 BB->addSuccessor(loopMBB);
6842 // The 4-byte load must be aligned, while a char or short may be
6843 // anywhere in the word. Hence all this nasty bookkeeping code.
6844 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6845 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6846 // xori shift, shift1, 24 [16]
6847 // rlwinm ptr, ptr1, 0, 0, 29
6848 // slw incr2, incr, shift
6849 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6850 // slw mask, mask2, shift
6852 // lwarx tmpDest, ptr
6853 // add tmp, tmpDest, incr2
6854 // andc tmp2, tmpDest, mask
6855 // and tmp3, tmp, mask
6856 // or tmp4, tmp3, tmp2
6859 // fallthrough --> exitMBB
6860 // srw dest, tmpDest, shift
6861 if (ptrA != ZeroReg) {
6862 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6863 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6864 .addReg(ptrA).addReg(ptrB);
6868 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6869 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6870 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6871 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6873 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6874 .addReg(Ptr1Reg).addImm(0).addImm(61);
6876 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6877 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6878 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6879 .addReg(incr).addReg(ShiftReg);
6881 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6883 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6884 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6886 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6887 .addReg(Mask2Reg).addReg(ShiftReg);
6890 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6891 .addReg(ZeroReg).addReg(PtrReg);
6893 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6894 .addReg(Incr2Reg).addReg(TmpDestReg);
6895 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6896 .addReg(TmpDestReg).addReg(MaskReg);
6897 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6898 .addReg(TmpReg).addReg(MaskReg);
6899 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6900 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6901 BuildMI(BB, dl, TII->get(PPC::STWCX))
6902 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6903 BuildMI(BB, dl, TII->get(PPC::BCC))
6904 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6905 BB->addSuccessor(loopMBB);
6906 BB->addSuccessor(exitMBB);
6911 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6916 llvm::MachineBasicBlock*
6917 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6918 MachineBasicBlock *MBB) const {
6919 DebugLoc DL = MI->getDebugLoc();
6920 const TargetInstrInfo *TII =
6921 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6923 MachineFunction *MF = MBB->getParent();
6924 MachineRegisterInfo &MRI = MF->getRegInfo();
6926 const BasicBlock *BB = MBB->getBasicBlock();
6927 MachineFunction::iterator I = MBB;
6931 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6932 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6934 unsigned DstReg = MI->getOperand(0).getReg();
6935 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6936 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6937 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6938 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6940 MVT PVT = getPointerTy();
6941 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6942 "Invalid Pointer Size!");
6943 // For v = setjmp(buf), we generate
6946 // SjLjSetup mainMBB
6952 // buf[LabelOffset] = LR
6956 // v = phi(main, restore)
6959 MachineBasicBlock *thisMBB = MBB;
6960 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6961 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6962 MF->insert(I, mainMBB);
6963 MF->insert(I, sinkMBB);
6965 MachineInstrBuilder MIB;
6967 // Transfer the remainder of BB and its successor edges to sinkMBB.
6968 sinkMBB->splice(sinkMBB->begin(), MBB,
6969 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6970 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6972 // Note that the structure of the jmp_buf used here is not compatible
6973 // with that used by libc, and is not designed to be. Specifically, it
6974 // stores only those 'reserved' registers that LLVM does not otherwise
6975 // understand how to spill. Also, by convention, by the time this
6976 // intrinsic is called, Clang has already stored the frame address in the
6977 // first slot of the buffer and stack address in the third. Following the
6978 // X86 target code, we'll store the jump address in the second slot. We also
6979 // need to save the TOC pointer (R2) to handle jumps between shared
6980 // libraries, and that will be stored in the fourth slot. The thread
6981 // identifier (R13) is not affected.
6984 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6985 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6986 const int64_t BPOffset = 4 * PVT.getStoreSize();
6988 // Prepare IP either in reg.
6989 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6990 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6991 unsigned BufReg = MI->getOperand(1).getReg();
6993 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6994 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6998 MIB.setMemRefs(MMOBegin, MMOEnd);
7001 // Naked functions never have a base pointer, and so we use r1. For all
7002 // other functions, this decision must be delayed until during PEI.
7004 if (MF->getFunction()->getAttributes().hasAttribute(
7005 AttributeSet::FunctionIndex, Attribute::Naked))
7006 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7008 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7010 MIB = BuildMI(*thisMBB, MI, DL,
7011 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7015 MIB.setMemRefs(MMOBegin, MMOEnd);
7018 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7019 const PPCRegisterInfo *TRI =
7020 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
7021 MIB.addRegMask(TRI->getNoPreservedMask());
7023 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7025 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7027 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7029 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7030 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7034 MIB = BuildMI(mainMBB, DL,
7035 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7038 if (Subtarget.isPPC64()) {
7039 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7041 .addImm(LabelOffset)
7044 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7046 .addImm(LabelOffset)
7050 MIB.setMemRefs(MMOBegin, MMOEnd);
7052 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7053 mainMBB->addSuccessor(sinkMBB);
7056 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7057 TII->get(PPC::PHI), DstReg)
7058 .addReg(mainDstReg).addMBB(mainMBB)
7059 .addReg(restoreDstReg).addMBB(thisMBB);
7061 MI->eraseFromParent();
7066 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7067 MachineBasicBlock *MBB) const {
7068 DebugLoc DL = MI->getDebugLoc();
7069 const TargetInstrInfo *TII =
7070 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7072 MachineFunction *MF = MBB->getParent();
7073 MachineRegisterInfo &MRI = MF->getRegInfo();
7076 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7077 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7079 MVT PVT = getPointerTy();
7080 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7081 "Invalid Pointer Size!");
7083 const TargetRegisterClass *RC =
7084 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7085 unsigned Tmp = MRI.createVirtualRegister(RC);
7086 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7087 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7088 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7089 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
7090 (Subtarget.isSVR4ABI() &&
7091 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
7092 PPC::R29 : PPC::R30);
7094 MachineInstrBuilder MIB;
7096 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7097 const int64_t SPOffset = 2 * PVT.getStoreSize();
7098 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7099 const int64_t BPOffset = 4 * PVT.getStoreSize();
7101 unsigned BufReg = MI->getOperand(0).getReg();
7103 // Reload FP (the jumped-to function may not have had a
7104 // frame pointer, and if so, then its r31 will be restored
7106 if (PVT == MVT::i64) {
7107 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7111 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7115 MIB.setMemRefs(MMOBegin, MMOEnd);
7118 if (PVT == MVT::i64) {
7119 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7120 .addImm(LabelOffset)
7123 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7124 .addImm(LabelOffset)
7127 MIB.setMemRefs(MMOBegin, MMOEnd);
7130 if (PVT == MVT::i64) {
7131 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7135 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7139 MIB.setMemRefs(MMOBegin, MMOEnd);
7142 if (PVT == MVT::i64) {
7143 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7147 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7151 MIB.setMemRefs(MMOBegin, MMOEnd);
7154 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7155 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7159 MIB.setMemRefs(MMOBegin, MMOEnd);
7163 BuildMI(*MBB, MI, DL,
7164 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7165 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7167 MI->eraseFromParent();
7172 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7173 MachineBasicBlock *BB) const {
7174 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7175 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7176 return emitEHSjLjSetJmp(MI, BB);
7177 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7178 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7179 return emitEHSjLjLongJmp(MI, BB);
7182 const TargetInstrInfo *TII =
7183 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7185 // To "insert" these instructions we actually have to insert their
7186 // control-flow patterns.
7187 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7188 MachineFunction::iterator It = BB;
7191 MachineFunction *F = BB->getParent();
7193 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7194 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7195 MI->getOpcode() == PPC::SELECT_I4 ||
7196 MI->getOpcode() == PPC::SELECT_I8)) {
7197 SmallVector<MachineOperand, 2> Cond;
7198 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7199 MI->getOpcode() == PPC::SELECT_CC_I8)
7200 Cond.push_back(MI->getOperand(4));
7202 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7203 Cond.push_back(MI->getOperand(1));
7205 DebugLoc dl = MI->getDebugLoc();
7206 const TargetInstrInfo *TII =
7207 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7208 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7209 Cond, MI->getOperand(2).getReg(),
7210 MI->getOperand(3).getReg());
7211 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7212 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7213 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7214 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7215 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7216 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7217 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7218 MI->getOpcode() == PPC::SELECT_I4 ||
7219 MI->getOpcode() == PPC::SELECT_I8 ||
7220 MI->getOpcode() == PPC::SELECT_F4 ||
7221 MI->getOpcode() == PPC::SELECT_F8 ||
7222 MI->getOpcode() == PPC::SELECT_VRRC ||
7223 MI->getOpcode() == PPC::SELECT_VSFRC ||
7224 MI->getOpcode() == PPC::SELECT_VSRC) {
7225 // The incoming instruction knows the destination vreg to set, the
7226 // condition code register to branch on, the true/false values to
7227 // select between, and a branch opcode to use.
7232 // cmpTY ccX, r1, r2
7234 // fallthrough --> copy0MBB
7235 MachineBasicBlock *thisMBB = BB;
7236 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7237 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7238 DebugLoc dl = MI->getDebugLoc();
7239 F->insert(It, copy0MBB);
7240 F->insert(It, sinkMBB);
7242 // Transfer the remainder of BB and its successor edges to sinkMBB.
7243 sinkMBB->splice(sinkMBB->begin(), BB,
7244 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7245 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7247 // Next, add the true and fallthrough blocks as its successors.
7248 BB->addSuccessor(copy0MBB);
7249 BB->addSuccessor(sinkMBB);
7251 if (MI->getOpcode() == PPC::SELECT_I4 ||
7252 MI->getOpcode() == PPC::SELECT_I8 ||
7253 MI->getOpcode() == PPC::SELECT_F4 ||
7254 MI->getOpcode() == PPC::SELECT_F8 ||
7255 MI->getOpcode() == PPC::SELECT_VRRC ||
7256 MI->getOpcode() == PPC::SELECT_VSFRC ||
7257 MI->getOpcode() == PPC::SELECT_VSRC) {
7258 BuildMI(BB, dl, TII->get(PPC::BC))
7259 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7261 unsigned SelectPred = MI->getOperand(4).getImm();
7262 BuildMI(BB, dl, TII->get(PPC::BCC))
7263 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7267 // %FalseValue = ...
7268 // # fallthrough to sinkMBB
7271 // Update machine-CFG edges
7272 BB->addSuccessor(sinkMBB);
7275 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7278 BuildMI(*BB, BB->begin(), dl,
7279 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7280 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7281 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7282 } else if (MI->getOpcode() == PPC::ReadTB) {
7283 // To read the 64-bit time-base register on a 32-bit target, we read the
7284 // two halves. Should the counter have wrapped while it was being read, we
7285 // need to try again.
7288 // mfspr Rx,TBU # load from TBU
7289 // mfspr Ry,TB # load from TB
7290 // mfspr Rz,TBU # load from TBU
7291 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7292 // bne readLoop # branch if they're not equal
7295 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7296 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7297 DebugLoc dl = MI->getDebugLoc();
7298 F->insert(It, readMBB);
7299 F->insert(It, sinkMBB);
7301 // Transfer the remainder of BB and its successor edges to sinkMBB.
7302 sinkMBB->splice(sinkMBB->begin(), BB,
7303 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7304 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7306 BB->addSuccessor(readMBB);
7309 MachineRegisterInfo &RegInfo = F->getRegInfo();
7310 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7311 unsigned LoReg = MI->getOperand(0).getReg();
7312 unsigned HiReg = MI->getOperand(1).getReg();
7314 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7315 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7316 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7318 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7320 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7321 .addReg(HiReg).addReg(ReadAgainReg);
7322 BuildMI(BB, dl, TII->get(PPC::BCC))
7323 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7325 BB->addSuccessor(readMBB);
7326 BB->addSuccessor(sinkMBB);
7328 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7329 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7330 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7331 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7332 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7333 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7334 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7335 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7337 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7338 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7339 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7340 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7341 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7342 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7343 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7344 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7346 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7347 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7348 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7349 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7350 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7351 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7352 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7353 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7355 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7356 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7357 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7358 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7359 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7360 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7361 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7362 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7364 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7365 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7366 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7367 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7368 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7369 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7370 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7371 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7373 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7374 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7375 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7376 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7377 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7378 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7379 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7380 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7382 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7383 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7384 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7385 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7386 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7387 BB = EmitAtomicBinary(MI, BB, false, 0);
7388 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7389 BB = EmitAtomicBinary(MI, BB, true, 0);
7391 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7392 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7393 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7395 unsigned dest = MI->getOperand(0).getReg();
7396 unsigned ptrA = MI->getOperand(1).getReg();
7397 unsigned ptrB = MI->getOperand(2).getReg();
7398 unsigned oldval = MI->getOperand(3).getReg();
7399 unsigned newval = MI->getOperand(4).getReg();
7400 DebugLoc dl = MI->getDebugLoc();
7402 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7403 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7404 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7405 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7406 F->insert(It, loop1MBB);
7407 F->insert(It, loop2MBB);
7408 F->insert(It, midMBB);
7409 F->insert(It, exitMBB);
7410 exitMBB->splice(exitMBB->begin(), BB,
7411 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7412 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7416 // fallthrough --> loopMBB
7417 BB->addSuccessor(loop1MBB);
7420 // l[wd]arx dest, ptr
7421 // cmp[wd] dest, oldval
7424 // st[wd]cx. newval, ptr
7428 // st[wd]cx. dest, ptr
7431 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7432 .addReg(ptrA).addReg(ptrB);
7433 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7434 .addReg(oldval).addReg(dest);
7435 BuildMI(BB, dl, TII->get(PPC::BCC))
7436 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7437 BB->addSuccessor(loop2MBB);
7438 BB->addSuccessor(midMBB);
7441 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7442 .addReg(newval).addReg(ptrA).addReg(ptrB);
7443 BuildMI(BB, dl, TII->get(PPC::BCC))
7444 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7445 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7446 BB->addSuccessor(loop1MBB);
7447 BB->addSuccessor(exitMBB);
7450 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7451 .addReg(dest).addReg(ptrA).addReg(ptrB);
7452 BB->addSuccessor(exitMBB);
7457 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7458 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7459 // We must use 64-bit registers for addresses when targeting 64-bit,
7460 // since we're actually doing arithmetic on them. Other registers
7462 bool is64bit = Subtarget.isPPC64();
7463 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7465 unsigned dest = MI->getOperand(0).getReg();
7466 unsigned ptrA = MI->getOperand(1).getReg();
7467 unsigned ptrB = MI->getOperand(2).getReg();
7468 unsigned oldval = MI->getOperand(3).getReg();
7469 unsigned newval = MI->getOperand(4).getReg();
7470 DebugLoc dl = MI->getDebugLoc();
7472 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7473 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7474 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7475 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7476 F->insert(It, loop1MBB);
7477 F->insert(It, loop2MBB);
7478 F->insert(It, midMBB);
7479 F->insert(It, exitMBB);
7480 exitMBB->splice(exitMBB->begin(), BB,
7481 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7482 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7484 MachineRegisterInfo &RegInfo = F->getRegInfo();
7485 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7486 : &PPC::GPRCRegClass;
7487 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7488 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7489 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7490 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7491 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7492 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7493 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7494 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7495 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7496 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7497 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7498 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7499 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7501 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7502 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7505 // fallthrough --> loopMBB
7506 BB->addSuccessor(loop1MBB);
7508 // The 4-byte load must be aligned, while a char or short may be
7509 // anywhere in the word. Hence all this nasty bookkeeping code.
7510 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7511 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7512 // xori shift, shift1, 24 [16]
7513 // rlwinm ptr, ptr1, 0, 0, 29
7514 // slw newval2, newval, shift
7515 // slw oldval2, oldval,shift
7516 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7517 // slw mask, mask2, shift
7518 // and newval3, newval2, mask
7519 // and oldval3, oldval2, mask
7521 // lwarx tmpDest, ptr
7522 // and tmp, tmpDest, mask
7523 // cmpw tmp, oldval3
7526 // andc tmp2, tmpDest, mask
7527 // or tmp4, tmp2, newval3
7532 // stwcx. tmpDest, ptr
7534 // srw dest, tmpDest, shift
7535 if (ptrA != ZeroReg) {
7536 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7537 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7538 .addReg(ptrA).addReg(ptrB);
7542 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7543 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7544 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7545 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7547 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7548 .addReg(Ptr1Reg).addImm(0).addImm(61);
7550 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7551 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7552 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7553 .addReg(newval).addReg(ShiftReg);
7554 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7555 .addReg(oldval).addReg(ShiftReg);
7557 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7559 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7560 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7561 .addReg(Mask3Reg).addImm(65535);
7563 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7564 .addReg(Mask2Reg).addReg(ShiftReg);
7565 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7566 .addReg(NewVal2Reg).addReg(MaskReg);
7567 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7568 .addReg(OldVal2Reg).addReg(MaskReg);
7571 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7572 .addReg(ZeroReg).addReg(PtrReg);
7573 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7574 .addReg(TmpDestReg).addReg(MaskReg);
7575 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7576 .addReg(TmpReg).addReg(OldVal3Reg);
7577 BuildMI(BB, dl, TII->get(PPC::BCC))
7578 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7579 BB->addSuccessor(loop2MBB);
7580 BB->addSuccessor(midMBB);
7583 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7584 .addReg(TmpDestReg).addReg(MaskReg);
7585 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7586 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7587 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7588 .addReg(ZeroReg).addReg(PtrReg);
7589 BuildMI(BB, dl, TII->get(PPC::BCC))
7590 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7591 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7592 BB->addSuccessor(loop1MBB);
7593 BB->addSuccessor(exitMBB);
7596 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7597 .addReg(ZeroReg).addReg(PtrReg);
7598 BB->addSuccessor(exitMBB);
7603 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7605 } else if (MI->getOpcode() == PPC::FADDrtz) {
7606 // This pseudo performs an FADD with rounding mode temporarily forced
7607 // to round-to-zero. We emit this via custom inserter since the FPSCR
7608 // is not modeled at the SelectionDAG level.
7609 unsigned Dest = MI->getOperand(0).getReg();
7610 unsigned Src1 = MI->getOperand(1).getReg();
7611 unsigned Src2 = MI->getOperand(2).getReg();
7612 DebugLoc dl = MI->getDebugLoc();
7614 MachineRegisterInfo &RegInfo = F->getRegInfo();
7615 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7617 // Save FPSCR value.
7618 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7620 // Set rounding mode to round-to-zero.
7621 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7622 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7624 // Perform addition.
7625 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7627 // Restore FPSCR value.
7628 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7629 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7630 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7631 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7632 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7633 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7634 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7635 PPC::ANDIo8 : PPC::ANDIo;
7636 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7637 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7639 MachineRegisterInfo &RegInfo = F->getRegInfo();
7640 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7641 &PPC::GPRCRegClass :
7642 &PPC::G8RCRegClass);
7644 DebugLoc dl = MI->getDebugLoc();
7645 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7646 .addReg(MI->getOperand(1).getReg()).addImm(1);
7647 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7648 MI->getOperand(0).getReg())
7649 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7651 llvm_unreachable("Unexpected instr type to insert");
7654 MI->eraseFromParent(); // The pseudo instruction is gone now.
7658 //===----------------------------------------------------------------------===//
7659 // Target Optimization Hooks
7660 //===----------------------------------------------------------------------===//
7662 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7663 DAGCombinerInfo &DCI,
7664 unsigned &RefinementSteps,
7665 bool &UseOneConstNR) const {
7666 EVT VT = Operand.getValueType();
7667 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7668 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7669 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7670 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7671 // Convergence is quadratic, so we essentially double the number of digits
7672 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7673 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7674 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7675 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7676 if (VT.getScalarType() == MVT::f64)
7678 UseOneConstNR = true;
7679 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7684 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7685 DAGCombinerInfo &DCI,
7686 unsigned &RefinementSteps) const {
7687 EVT VT = Operand.getValueType();
7688 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7689 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7690 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7691 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7692 // Convergence is quadratic, so we essentially double the number of digits
7693 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7694 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7695 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7696 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7697 if (VT.getScalarType() == MVT::f64)
7699 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7704 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7705 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7706 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7707 // enabled for division), this functionality is redundant with the default
7708 // combiner logic (once the division -> reciprocal/multiply transformation
7709 // has taken place). As a result, this matters more for older cores than for
7712 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7713 // reciprocal if there are two or more FDIVs (for embedded cores with only
7714 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7715 switch (Subtarget.getDarwinDirective()) {
7717 return NumUsers > 2;
7720 case PPC::DIR_E500mc:
7721 case PPC::DIR_E5500:
7722 return NumUsers > 1;
7726 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7727 unsigned Bytes, int Dist,
7728 SelectionDAG &DAG) {
7729 if (VT.getSizeInBits() / 8 != Bytes)
7732 SDValue BaseLoc = Base->getBasePtr();
7733 if (Loc.getOpcode() == ISD::FrameIndex) {
7734 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7736 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7737 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7738 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7739 int FS = MFI->getObjectSize(FI);
7740 int BFS = MFI->getObjectSize(BFI);
7741 if (FS != BFS || FS != (int)Bytes) return false;
7742 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7746 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7747 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7751 const GlobalValue *GV1 = nullptr;
7752 const GlobalValue *GV2 = nullptr;
7753 int64_t Offset1 = 0;
7754 int64_t Offset2 = 0;
7755 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7756 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7757 if (isGA1 && isGA2 && GV1 == GV2)
7758 return Offset1 == (Offset2 + Dist*Bytes);
7762 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7763 // not enforce equality of the chain operands.
7764 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7765 unsigned Bytes, int Dist,
7766 SelectionDAG &DAG) {
7767 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7768 EVT VT = LS->getMemoryVT();
7769 SDValue Loc = LS->getBasePtr();
7770 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7773 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7775 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7776 default: return false;
7777 case Intrinsic::ppc_altivec_lvx:
7778 case Intrinsic::ppc_altivec_lvxl:
7779 case Intrinsic::ppc_vsx_lxvw4x:
7782 case Intrinsic::ppc_vsx_lxvd2x:
7785 case Intrinsic::ppc_altivec_lvebx:
7788 case Intrinsic::ppc_altivec_lvehx:
7791 case Intrinsic::ppc_altivec_lvewx:
7796 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7799 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7801 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7802 default: return false;
7803 case Intrinsic::ppc_altivec_stvx:
7804 case Intrinsic::ppc_altivec_stvxl:
7805 case Intrinsic::ppc_vsx_stxvw4x:
7808 case Intrinsic::ppc_vsx_stxvd2x:
7811 case Intrinsic::ppc_altivec_stvebx:
7814 case Intrinsic::ppc_altivec_stvehx:
7817 case Intrinsic::ppc_altivec_stvewx:
7822 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7828 // Return true is there is a nearyby consecutive load to the one provided
7829 // (regardless of alignment). We search up and down the chain, looking though
7830 // token factors and other loads (but nothing else). As a result, a true result
7831 // indicates that it is safe to create a new consecutive load adjacent to the
7833 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7834 SDValue Chain = LD->getChain();
7835 EVT VT = LD->getMemoryVT();
7837 SmallSet<SDNode *, 16> LoadRoots;
7838 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7839 SmallSet<SDNode *, 16> Visited;
7841 // First, search up the chain, branching to follow all token-factor operands.
7842 // If we find a consecutive load, then we're done, otherwise, record all
7843 // nodes just above the top-level loads and token factors.
7844 while (!Queue.empty()) {
7845 SDNode *ChainNext = Queue.pop_back_val();
7846 if (!Visited.insert(ChainNext).second)
7849 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7850 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7853 if (!Visited.count(ChainLD->getChain().getNode()))
7854 Queue.push_back(ChainLD->getChain().getNode());
7855 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7856 for (const SDUse &O : ChainNext->ops())
7857 if (!Visited.count(O.getNode()))
7858 Queue.push_back(O.getNode());
7860 LoadRoots.insert(ChainNext);
7863 // Second, search down the chain, starting from the top-level nodes recorded
7864 // in the first phase. These top-level nodes are the nodes just above all
7865 // loads and token factors. Starting with their uses, recursively look though
7866 // all loads (just the chain uses) and token factors to find a consecutive
7871 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7872 IE = LoadRoots.end(); I != IE; ++I) {
7873 Queue.push_back(*I);
7875 while (!Queue.empty()) {
7876 SDNode *LoadRoot = Queue.pop_back_val();
7877 if (!Visited.insert(LoadRoot).second)
7880 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7881 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7884 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7885 UE = LoadRoot->use_end(); UI != UE; ++UI)
7886 if (((isa<MemSDNode>(*UI) &&
7887 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7888 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7889 Queue.push_back(*UI);
7896 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7897 DAGCombinerInfo &DCI) const {
7898 SelectionDAG &DAG = DCI.DAG;
7901 assert(Subtarget.useCRBits() &&
7902 "Expecting to be tracking CR bits");
7903 // If we're tracking CR bits, we need to be careful that we don't have:
7904 // trunc(binary-ops(zext(x), zext(y)))
7906 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7907 // such that we're unnecessarily moving things into GPRs when it would be
7908 // better to keep them in CR bits.
7910 // Note that trunc here can be an actual i1 trunc, or can be the effective
7911 // truncation that comes from a setcc or select_cc.
7912 if (N->getOpcode() == ISD::TRUNCATE &&
7913 N->getValueType(0) != MVT::i1)
7916 if (N->getOperand(0).getValueType() != MVT::i32 &&
7917 N->getOperand(0).getValueType() != MVT::i64)
7920 if (N->getOpcode() == ISD::SETCC ||
7921 N->getOpcode() == ISD::SELECT_CC) {
7922 // If we're looking at a comparison, then we need to make sure that the
7923 // high bits (all except for the first) don't matter the result.
7925 cast<CondCodeSDNode>(N->getOperand(
7926 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7927 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7929 if (ISD::isSignedIntSetCC(CC)) {
7930 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7931 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7933 } else if (ISD::isUnsignedIntSetCC(CC)) {
7934 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7935 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7936 !DAG.MaskedValueIsZero(N->getOperand(1),
7937 APInt::getHighBitsSet(OpBits, OpBits-1)))
7940 // This is neither a signed nor an unsigned comparison, just make sure
7941 // that the high bits are equal.
7942 APInt Op1Zero, Op1One;
7943 APInt Op2Zero, Op2One;
7944 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7945 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7947 // We don't really care about what is known about the first bit (if
7948 // anything), so clear it in all masks prior to comparing them.
7949 Op1Zero.clearBit(0); Op1One.clearBit(0);
7950 Op2Zero.clearBit(0); Op2One.clearBit(0);
7952 if (Op1Zero != Op2Zero || Op1One != Op2One)
7957 // We now know that the higher-order bits are irrelevant, we just need to
7958 // make sure that all of the intermediate operations are bit operations, and
7959 // all inputs are extensions.
7960 if (N->getOperand(0).getOpcode() != ISD::AND &&
7961 N->getOperand(0).getOpcode() != ISD::OR &&
7962 N->getOperand(0).getOpcode() != ISD::XOR &&
7963 N->getOperand(0).getOpcode() != ISD::SELECT &&
7964 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7965 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7966 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7967 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7968 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7971 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7972 N->getOperand(1).getOpcode() != ISD::AND &&
7973 N->getOperand(1).getOpcode() != ISD::OR &&
7974 N->getOperand(1).getOpcode() != ISD::XOR &&
7975 N->getOperand(1).getOpcode() != ISD::SELECT &&
7976 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7977 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7978 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7979 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7980 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7983 SmallVector<SDValue, 4> Inputs;
7984 SmallVector<SDValue, 8> BinOps, PromOps;
7985 SmallPtrSet<SDNode *, 16> Visited;
7987 for (unsigned i = 0; i < 2; ++i) {
7988 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7989 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7990 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7991 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7992 isa<ConstantSDNode>(N->getOperand(i)))
7993 Inputs.push_back(N->getOperand(i));
7995 BinOps.push_back(N->getOperand(i));
7997 if (N->getOpcode() == ISD::TRUNCATE)
8001 // Visit all inputs, collect all binary operations (and, or, xor and
8002 // select) that are all fed by extensions.
8003 while (!BinOps.empty()) {
8004 SDValue BinOp = BinOps.back();
8007 if (!Visited.insert(BinOp.getNode()).second)
8010 PromOps.push_back(BinOp);
8012 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8013 // The condition of the select is not promoted.
8014 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8016 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8019 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8020 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8021 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8022 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8023 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8024 Inputs.push_back(BinOp.getOperand(i));
8025 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8026 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8027 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8028 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8029 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8030 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8031 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8032 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8033 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8034 BinOps.push_back(BinOp.getOperand(i));
8036 // We have an input that is not an extension or another binary
8037 // operation; we'll abort this transformation.
8043 // Make sure that this is a self-contained cluster of operations (which
8044 // is not quite the same thing as saying that everything has only one
8046 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8047 if (isa<ConstantSDNode>(Inputs[i]))
8050 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8051 UE = Inputs[i].getNode()->use_end();
8054 if (User != N && !Visited.count(User))
8057 // Make sure that we're not going to promote the non-output-value
8058 // operand(s) or SELECT or SELECT_CC.
8059 // FIXME: Although we could sometimes handle this, and it does occur in
8060 // practice that one of the condition inputs to the select is also one of
8061 // the outputs, we currently can't deal with this.
8062 if (User->getOpcode() == ISD::SELECT) {
8063 if (User->getOperand(0) == Inputs[i])
8065 } else if (User->getOpcode() == ISD::SELECT_CC) {
8066 if (User->getOperand(0) == Inputs[i] ||
8067 User->getOperand(1) == Inputs[i])
8073 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8074 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8075 UE = PromOps[i].getNode()->use_end();
8078 if (User != N && !Visited.count(User))
8081 // Make sure that we're not going to promote the non-output-value
8082 // operand(s) or SELECT or SELECT_CC.
8083 // FIXME: Although we could sometimes handle this, and it does occur in
8084 // practice that one of the condition inputs to the select is also one of
8085 // the outputs, we currently can't deal with this.
8086 if (User->getOpcode() == ISD::SELECT) {
8087 if (User->getOperand(0) == PromOps[i])
8089 } else if (User->getOpcode() == ISD::SELECT_CC) {
8090 if (User->getOperand(0) == PromOps[i] ||
8091 User->getOperand(1) == PromOps[i])
8097 // Replace all inputs with the extension operand.
8098 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8099 // Constants may have users outside the cluster of to-be-promoted nodes,
8100 // and so we need to replace those as we do the promotions.
8101 if (isa<ConstantSDNode>(Inputs[i]))
8104 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8107 // Replace all operations (these are all the same, but have a different
8108 // (i1) return type). DAG.getNode will validate that the types of
8109 // a binary operator match, so go through the list in reverse so that
8110 // we've likely promoted both operands first. Any intermediate truncations or
8111 // extensions disappear.
8112 while (!PromOps.empty()) {
8113 SDValue PromOp = PromOps.back();
8116 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8117 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8118 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8119 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8120 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8121 PromOp.getOperand(0).getValueType() != MVT::i1) {
8122 // The operand is not yet ready (see comment below).
8123 PromOps.insert(PromOps.begin(), PromOp);
8127 SDValue RepValue = PromOp.getOperand(0);
8128 if (isa<ConstantSDNode>(RepValue))
8129 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8131 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8136 switch (PromOp.getOpcode()) {
8137 default: C = 0; break;
8138 case ISD::SELECT: C = 1; break;
8139 case ISD::SELECT_CC: C = 2; break;
8142 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8143 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8144 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8145 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8146 // The to-be-promoted operands of this node have not yet been
8147 // promoted (this should be rare because we're going through the
8148 // list backward, but if one of the operands has several users in
8149 // this cluster of to-be-promoted nodes, it is possible).
8150 PromOps.insert(PromOps.begin(), PromOp);
8154 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8155 PromOp.getNode()->op_end());
8157 // If there are any constant inputs, make sure they're replaced now.
8158 for (unsigned i = 0; i < 2; ++i)
8159 if (isa<ConstantSDNode>(Ops[C+i]))
8160 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8162 DAG.ReplaceAllUsesOfValueWith(PromOp,
8163 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8166 // Now we're left with the initial truncation itself.
8167 if (N->getOpcode() == ISD::TRUNCATE)
8168 return N->getOperand(0);
8170 // Otherwise, this is a comparison. The operands to be compared have just
8171 // changed type (to i1), but everything else is the same.
8172 return SDValue(N, 0);
8175 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8176 DAGCombinerInfo &DCI) const {
8177 SelectionDAG &DAG = DCI.DAG;
8180 // If we're tracking CR bits, we need to be careful that we don't have:
8181 // zext(binary-ops(trunc(x), trunc(y)))
8183 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8184 // such that we're unnecessarily moving things into CR bits that can more
8185 // efficiently stay in GPRs. Note that if we're not certain that the high
8186 // bits are set as required by the final extension, we still may need to do
8187 // some masking to get the proper behavior.
8189 // This same functionality is important on PPC64 when dealing with
8190 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8191 // the return values of functions. Because it is so similar, it is handled
8194 if (N->getValueType(0) != MVT::i32 &&
8195 N->getValueType(0) != MVT::i64)
8198 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8199 Subtarget.useCRBits()) ||
8200 (N->getOperand(0).getValueType() == MVT::i32 &&
8201 Subtarget.isPPC64())))
8204 if (N->getOperand(0).getOpcode() != ISD::AND &&
8205 N->getOperand(0).getOpcode() != ISD::OR &&
8206 N->getOperand(0).getOpcode() != ISD::XOR &&
8207 N->getOperand(0).getOpcode() != ISD::SELECT &&
8208 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8211 SmallVector<SDValue, 4> Inputs;
8212 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8213 SmallPtrSet<SDNode *, 16> Visited;
8215 // Visit all inputs, collect all binary operations (and, or, xor and
8216 // select) that are all fed by truncations.
8217 while (!BinOps.empty()) {
8218 SDValue BinOp = BinOps.back();
8221 if (!Visited.insert(BinOp.getNode()).second)
8224 PromOps.push_back(BinOp);
8226 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8227 // The condition of the select is not promoted.
8228 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8230 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8233 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8234 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8235 Inputs.push_back(BinOp.getOperand(i));
8236 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8237 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8238 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8239 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8240 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8241 BinOps.push_back(BinOp.getOperand(i));
8243 // We have an input that is not a truncation or another binary
8244 // operation; we'll abort this transformation.
8250 // The operands of a select that must be truncated when the select is
8251 // promoted because the operand is actually part of the to-be-promoted set.
8252 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8254 // Make sure that this is a self-contained cluster of operations (which
8255 // is not quite the same thing as saying that everything has only one
8257 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8258 if (isa<ConstantSDNode>(Inputs[i]))
8261 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8262 UE = Inputs[i].getNode()->use_end();
8265 if (User != N && !Visited.count(User))
8268 // If we're going to promote the non-output-value operand(s) or SELECT or
8269 // SELECT_CC, record them for truncation.
8270 if (User->getOpcode() == ISD::SELECT) {
8271 if (User->getOperand(0) == Inputs[i])
8272 SelectTruncOp[0].insert(std::make_pair(User,
8273 User->getOperand(0).getValueType()));
8274 } else if (User->getOpcode() == ISD::SELECT_CC) {
8275 if (User->getOperand(0) == Inputs[i])
8276 SelectTruncOp[0].insert(std::make_pair(User,
8277 User->getOperand(0).getValueType()));
8278 if (User->getOperand(1) == Inputs[i])
8279 SelectTruncOp[1].insert(std::make_pair(User,
8280 User->getOperand(1).getValueType()));
8285 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8286 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8287 UE = PromOps[i].getNode()->use_end();
8290 if (User != N && !Visited.count(User))
8293 // If we're going to promote the non-output-value operand(s) or SELECT or
8294 // SELECT_CC, record them for truncation.
8295 if (User->getOpcode() == ISD::SELECT) {
8296 if (User->getOperand(0) == PromOps[i])
8297 SelectTruncOp[0].insert(std::make_pair(User,
8298 User->getOperand(0).getValueType()));
8299 } else if (User->getOpcode() == ISD::SELECT_CC) {
8300 if (User->getOperand(0) == PromOps[i])
8301 SelectTruncOp[0].insert(std::make_pair(User,
8302 User->getOperand(0).getValueType()));
8303 if (User->getOperand(1) == PromOps[i])
8304 SelectTruncOp[1].insert(std::make_pair(User,
8305 User->getOperand(1).getValueType()));
8310 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8311 bool ReallyNeedsExt = false;
8312 if (N->getOpcode() != ISD::ANY_EXTEND) {
8313 // If all of the inputs are not already sign/zero extended, then
8314 // we'll still need to do that at the end.
8315 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8316 if (isa<ConstantSDNode>(Inputs[i]))
8320 Inputs[i].getOperand(0).getValueSizeInBits();
8321 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8323 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8324 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8325 APInt::getHighBitsSet(OpBits,
8326 OpBits-PromBits))) ||
8327 (N->getOpcode() == ISD::SIGN_EXTEND &&
8328 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8329 (OpBits-(PromBits-1)))) {
8330 ReallyNeedsExt = true;
8336 // Replace all inputs, either with the truncation operand, or a
8337 // truncation or extension to the final output type.
8338 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8339 // Constant inputs need to be replaced with the to-be-promoted nodes that
8340 // use them because they might have users outside of the cluster of
8342 if (isa<ConstantSDNode>(Inputs[i]))
8345 SDValue InSrc = Inputs[i].getOperand(0);
8346 if (Inputs[i].getValueType() == N->getValueType(0))
8347 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8348 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8349 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8350 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8351 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8352 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8353 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8355 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8356 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8359 // Replace all operations (these are all the same, but have a different
8360 // (promoted) return type). DAG.getNode will validate that the types of
8361 // a binary operator match, so go through the list in reverse so that
8362 // we've likely promoted both operands first.
8363 while (!PromOps.empty()) {
8364 SDValue PromOp = PromOps.back();
8368 switch (PromOp.getOpcode()) {
8369 default: C = 0; break;
8370 case ISD::SELECT: C = 1; break;
8371 case ISD::SELECT_CC: C = 2; break;
8374 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8375 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8376 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8377 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8378 // The to-be-promoted operands of this node have not yet been
8379 // promoted (this should be rare because we're going through the
8380 // list backward, but if one of the operands has several users in
8381 // this cluster of to-be-promoted nodes, it is possible).
8382 PromOps.insert(PromOps.begin(), PromOp);
8386 // For SELECT and SELECT_CC nodes, we do a similar check for any
8387 // to-be-promoted comparison inputs.
8388 if (PromOp.getOpcode() == ISD::SELECT ||
8389 PromOp.getOpcode() == ISD::SELECT_CC) {
8390 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8391 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8392 (SelectTruncOp[1].count(PromOp.getNode()) &&
8393 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8394 PromOps.insert(PromOps.begin(), PromOp);
8399 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8400 PromOp.getNode()->op_end());
8402 // If this node has constant inputs, then they'll need to be promoted here.
8403 for (unsigned i = 0; i < 2; ++i) {
8404 if (!isa<ConstantSDNode>(Ops[C+i]))
8406 if (Ops[C+i].getValueType() == N->getValueType(0))
8409 if (N->getOpcode() == ISD::SIGN_EXTEND)
8410 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8411 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8412 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8414 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8417 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8418 // truncate them again to the original value type.
8419 if (PromOp.getOpcode() == ISD::SELECT ||
8420 PromOp.getOpcode() == ISD::SELECT_CC) {
8421 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8422 if (SI0 != SelectTruncOp[0].end())
8423 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8424 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8425 if (SI1 != SelectTruncOp[1].end())
8426 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8429 DAG.ReplaceAllUsesOfValueWith(PromOp,
8430 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8433 // Now we're left with the initial extension itself.
8434 if (!ReallyNeedsExt)
8435 return N->getOperand(0);
8437 // To zero extend, just mask off everything except for the first bit (in the
8439 if (N->getOpcode() == ISD::ZERO_EXTEND)
8440 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8441 DAG.getConstant(APInt::getLowBitsSet(
8442 N->getValueSizeInBits(0), PromBits),
8443 N->getValueType(0)));
8445 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8446 "Invalid extension type");
8447 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8449 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8450 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8451 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8452 N->getOperand(0), ShiftCst), ShiftCst);
8455 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8456 DAGCombinerInfo &DCI) const {
8457 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8458 N->getOpcode() == ISD::UINT_TO_FP) &&
8459 "Need an int -> FP conversion node here");
8461 if (!Subtarget.has64BitSupport())
8464 SelectionDAG &DAG = DCI.DAG;
8468 // Don't handle ppc_fp128 here or i1 conversions.
8469 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8471 if (Op.getOperand(0).getValueType() == MVT::i1)
8474 // For i32 intermediate values, unfortunately, the conversion functions
8475 // leave the upper 32 bits of the value are undefined. Within the set of
8476 // scalar instructions, we have no method for zero- or sign-extending the
8477 // value. Thus, we cannot handle i32 intermediate values here.
8478 if (Op.getOperand(0).getValueType() == MVT::i32)
8481 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8482 "UINT_TO_FP is supported only with FPCVT");
8484 // If we have FCFIDS, then use it when converting to single-precision.
8485 // Otherwise, convert to double-precision and then round.
8486 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8487 (Op.getOpcode() == ISD::UINT_TO_FP ?
8488 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8489 (Op.getOpcode() == ISD::UINT_TO_FP ?
8490 PPCISD::FCFIDU : PPCISD::FCFID);
8491 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8492 MVT::f32 : MVT::f64;
8494 // If we're converting from a float, to an int, and back to a float again,
8495 // then we don't need the store/load pair at all.
8496 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8497 Subtarget.hasFPCVT()) ||
8498 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8499 SDValue Src = Op.getOperand(0).getOperand(0);
8500 if (Src.getValueType() == MVT::f32) {
8501 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8502 DCI.AddToWorklist(Src.getNode());
8506 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8509 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8510 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8512 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8513 FP = DAG.getNode(ISD::FP_ROUND, dl,
8514 MVT::f32, FP, DAG.getIntPtrConstant(0));
8515 DCI.AddToWorklist(FP.getNode());
8524 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8525 // builtins) into loads with swaps.
8526 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8527 DAGCombinerInfo &DCI) const {
8528 SelectionDAG &DAG = DCI.DAG;
8532 MachineMemOperand *MMO;
8534 switch (N->getOpcode()) {
8536 llvm_unreachable("Unexpected opcode for little endian VSX load");
8538 LoadSDNode *LD = cast<LoadSDNode>(N);
8539 Chain = LD->getChain();
8540 Base = LD->getBasePtr();
8541 MMO = LD->getMemOperand();
8542 // If the MMO suggests this isn't a load of a full vector, leave
8543 // things alone. For a built-in, we have to make the change for
8544 // correctness, so if there is a size problem that will be a bug.
8545 if (MMO->getSize() < 16)
8549 case ISD::INTRINSIC_W_CHAIN: {
8550 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8551 Chain = Intrin->getChain();
8552 Base = Intrin->getBasePtr();
8553 MMO = Intrin->getMemOperand();
8558 MVT VecTy = N->getValueType(0).getSimpleVT();
8559 SDValue LoadOps[] = { Chain, Base };
8560 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8561 DAG.getVTList(VecTy, MVT::Other),
8562 LoadOps, VecTy, MMO);
8563 DCI.AddToWorklist(Load.getNode());
8564 Chain = Load.getValue(1);
8565 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8566 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8567 DCI.AddToWorklist(Swap.getNode());
8571 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8572 // builtins) into stores with swaps.
8573 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8574 DAGCombinerInfo &DCI) const {
8575 SelectionDAG &DAG = DCI.DAG;
8580 MachineMemOperand *MMO;
8582 switch (N->getOpcode()) {
8584 llvm_unreachable("Unexpected opcode for little endian VSX store");
8586 StoreSDNode *ST = cast<StoreSDNode>(N);
8587 Chain = ST->getChain();
8588 Base = ST->getBasePtr();
8589 MMO = ST->getMemOperand();
8591 // If the MMO suggests this isn't a store of a full vector, leave
8592 // things alone. For a built-in, we have to make the change for
8593 // correctness, so if there is a size problem that will be a bug.
8594 if (MMO->getSize() < 16)
8598 case ISD::INTRINSIC_VOID: {
8599 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8600 Chain = Intrin->getChain();
8601 // Intrin->getBasePtr() oddly does not get what we want.
8602 Base = Intrin->getOperand(3);
8603 MMO = Intrin->getMemOperand();
8609 SDValue Src = N->getOperand(SrcOpnd);
8610 MVT VecTy = Src.getValueType().getSimpleVT();
8611 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8612 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8613 DCI.AddToWorklist(Swap.getNode());
8614 Chain = Swap.getValue(1);
8615 SDValue StoreOps[] = { Chain, Swap, Base };
8616 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8617 DAG.getVTList(MVT::Other),
8618 StoreOps, VecTy, MMO);
8619 DCI.AddToWorklist(Store.getNode());
8623 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8624 DAGCombinerInfo &DCI) const {
8625 const TargetMachine &TM = getTargetMachine();
8626 SelectionDAG &DAG = DCI.DAG;
8628 switch (N->getOpcode()) {
8631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8632 if (C->isNullValue()) // 0 << V -> 0.
8633 return N->getOperand(0);
8637 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8638 if (C->isNullValue()) // 0 >>u V -> 0.
8639 return N->getOperand(0);
8643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8644 if (C->isNullValue() || // 0 >>s V -> 0.
8645 C->isAllOnesValue()) // -1 >>s V -> -1.
8646 return N->getOperand(0);
8649 case ISD::SIGN_EXTEND:
8650 case ISD::ZERO_EXTEND:
8651 case ISD::ANY_EXTEND:
8652 return DAGCombineExtBoolTrunc(N, DCI);
8655 case ISD::SELECT_CC:
8656 return DAGCombineTruncBoolExt(N, DCI);
8657 case ISD::SINT_TO_FP:
8658 case ISD::UINT_TO_FP:
8659 return combineFPToIntToFP(N, DCI);
8661 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8662 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8663 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8664 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8665 N->getOperand(1).getValueType() == MVT::i32 &&
8666 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8667 SDValue Val = N->getOperand(1).getOperand(0);
8668 if (Val.getValueType() == MVT::f32) {
8669 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8670 DCI.AddToWorklist(Val.getNode());
8672 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8673 DCI.AddToWorklist(Val.getNode());
8676 N->getOperand(0), Val, N->getOperand(2),
8677 DAG.getValueType(N->getOperand(1).getValueType())
8680 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8681 DAG.getVTList(MVT::Other), Ops,
8682 cast<StoreSDNode>(N)->getMemoryVT(),
8683 cast<StoreSDNode>(N)->getMemOperand());
8684 DCI.AddToWorklist(Val.getNode());
8688 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8689 if (cast<StoreSDNode>(N)->isUnindexed() &&
8690 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8691 N->getOperand(1).getNode()->hasOneUse() &&
8692 (N->getOperand(1).getValueType() == MVT::i32 ||
8693 N->getOperand(1).getValueType() == MVT::i16 ||
8694 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8695 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8696 N->getOperand(1).getValueType() == MVT::i64))) {
8697 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8698 // Do an any-extend to 32-bits if this is a half-word input.
8699 if (BSwapOp.getValueType() == MVT::i16)
8700 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8703 N->getOperand(0), BSwapOp, N->getOperand(2),
8704 DAG.getValueType(N->getOperand(1).getValueType())
8707 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8708 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8709 cast<StoreSDNode>(N)->getMemOperand());
8712 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8713 EVT VT = N->getOperand(1).getValueType();
8714 if (VT.isSimple()) {
8715 MVT StoreVT = VT.getSimpleVT();
8716 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8717 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8718 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8719 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8720 return expandVSXStoreForLE(N, DCI);
8725 LoadSDNode *LD = cast<LoadSDNode>(N);
8726 EVT VT = LD->getValueType(0);
8728 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8729 if (VT.isSimple()) {
8730 MVT LoadVT = VT.getSimpleVT();
8731 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8732 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8733 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8734 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8735 return expandVSXLoadForLE(N, DCI);
8738 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8739 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8740 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8741 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8742 // P8 and later hardware should just use LOAD.
8743 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8744 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8745 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8746 LD->getAlignment() < ABIAlignment) {
8747 // This is a type-legal unaligned Altivec load.
8748 SDValue Chain = LD->getChain();
8749 SDValue Ptr = LD->getBasePtr();
8750 bool isLittleEndian = Subtarget.isLittleEndian();
8752 // This implements the loading of unaligned vectors as described in
8753 // the venerable Apple Velocity Engine overview. Specifically:
8754 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8755 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8757 // The general idea is to expand a sequence of one or more unaligned
8758 // loads into an alignment-based permutation-control instruction (lvsl
8759 // or lvsr), a series of regular vector loads (which always truncate
8760 // their input address to an aligned address), and a series of
8761 // permutations. The results of these permutations are the requested
8762 // loaded values. The trick is that the last "extra" load is not taken
8763 // from the address you might suspect (sizeof(vector) bytes after the
8764 // last requested load), but rather sizeof(vector) - 1 bytes after the
8765 // last requested vector. The point of this is to avoid a page fault if
8766 // the base address happened to be aligned. This works because if the
8767 // base address is aligned, then adding less than a full vector length
8768 // will cause the last vector in the sequence to be (re)loaded.
8769 // Otherwise, the next vector will be fetched as you might suspect was
8772 // We might be able to reuse the permutation generation from
8773 // a different base address offset from this one by an aligned amount.
8774 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8775 // optimization later.
8776 Intrinsic::ID Intr = (isLittleEndian ?
8777 Intrinsic::ppc_altivec_lvsr :
8778 Intrinsic::ppc_altivec_lvsl);
8779 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8781 // Create the new MMO for the new base load. It is like the original MMO,
8782 // but represents an area in memory almost twice the vector size centered
8783 // on the original address. If the address is unaligned, we might start
8784 // reading up to (sizeof(vector)-1) bytes below the address of the
8785 // original unaligned load.
8786 MachineFunction &MF = DAG.getMachineFunction();
8787 MachineMemOperand *BaseMMO =
8788 MF.getMachineMemOperand(LD->getMemOperand(),
8789 -LD->getMemoryVT().getStoreSize()+1,
8790 2*LD->getMemoryVT().getStoreSize()-1);
8792 // Create the new base load.
8793 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8795 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8797 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8798 DAG.getVTList(MVT::v4i32, MVT::Other),
8799 BaseLoadOps, MVT::v4i32, BaseMMO);
8801 // Note that the value of IncOffset (which is provided to the next
8802 // load's pointer info offset value, and thus used to calculate the
8803 // alignment), and the value of IncValue (which is actually used to
8804 // increment the pointer value) are different! This is because we
8805 // require the next load to appear to be aligned, even though it
8806 // is actually offset from the base pointer by a lesser amount.
8807 int IncOffset = VT.getSizeInBits() / 8;
8808 int IncValue = IncOffset;
8810 // Walk (both up and down) the chain looking for another load at the real
8811 // (aligned) offset (the alignment of the other load does not matter in
8812 // this case). If found, then do not use the offset reduction trick, as
8813 // that will prevent the loads from being later combined (as they would
8814 // otherwise be duplicates).
8815 if (!findConsecutiveLoad(LD, DAG))
8818 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8819 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8821 MachineMemOperand *ExtraMMO =
8822 MF.getMachineMemOperand(LD->getMemOperand(),
8823 1, 2*LD->getMemoryVT().getStoreSize()-1);
8824 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8826 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8827 DAG.getVTList(MVT::v4i32, MVT::Other),
8828 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8830 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8831 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8833 // Because vperm has a big-endian bias, we must reverse the order
8834 // of the input vectors and complement the permute control vector
8835 // when generating little endian code. We have already handled the
8836 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8837 // and ExtraLoad here.
8840 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8841 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8843 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8844 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8846 if (VT != MVT::v4i32)
8847 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8849 // The output of the permutation is our loaded result, the TokenFactor is
8851 DCI.CombineTo(N, Perm, TF);
8852 return SDValue(N, 0);
8856 case ISD::INTRINSIC_WO_CHAIN: {
8857 bool isLittleEndian = Subtarget.isLittleEndian();
8858 Intrinsic::ID Intr = (isLittleEndian ?
8859 Intrinsic::ppc_altivec_lvsr :
8860 Intrinsic::ppc_altivec_lvsl);
8861 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8862 N->getOperand(1)->getOpcode() == ISD::ADD) {
8863 SDValue Add = N->getOperand(1);
8865 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8866 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8867 Add.getValueType().getScalarType().getSizeInBits()))) {
8868 SDNode *BasePtr = Add->getOperand(0).getNode();
8869 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8870 UE = BasePtr->use_end(); UI != UE; ++UI) {
8871 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8872 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8874 // We've found another LVSL/LVSR, and this address is an aligned
8875 // multiple of that one. The results will be the same, so use the
8876 // one we've just found instead.
8878 return SDValue(*UI, 0);
8886 case ISD::INTRINSIC_W_CHAIN: {
8887 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8888 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8889 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8890 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8893 case Intrinsic::ppc_vsx_lxvw4x:
8894 case Intrinsic::ppc_vsx_lxvd2x:
8895 return expandVSXLoadForLE(N, DCI);
8900 case ISD::INTRINSIC_VOID: {
8901 // For little endian, VSX stores require generating xxswapd/stxvd2x.
8902 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8903 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8904 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8907 case Intrinsic::ppc_vsx_stxvw4x:
8908 case Intrinsic::ppc_vsx_stxvd2x:
8909 return expandVSXStoreForLE(N, DCI);
8915 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8916 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8917 N->getOperand(0).hasOneUse() &&
8918 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8919 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8920 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8921 N->getValueType(0) == MVT::i64))) {
8922 SDValue Load = N->getOperand(0);
8923 LoadSDNode *LD = cast<LoadSDNode>(Load);
8924 // Create the byte-swapping load.
8926 LD->getChain(), // Chain
8927 LD->getBasePtr(), // Ptr
8928 DAG.getValueType(N->getValueType(0)) // VT
8931 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8932 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8933 MVT::i64 : MVT::i32, MVT::Other),
8934 Ops, LD->getMemoryVT(), LD->getMemOperand());
8936 // If this is an i16 load, insert the truncate.
8937 SDValue ResVal = BSLoad;
8938 if (N->getValueType(0) == MVT::i16)
8939 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8941 // First, combine the bswap away. This makes the value produced by the
8943 DCI.CombineTo(N, ResVal);
8945 // Next, combine the load away, we give it a bogus result value but a real
8946 // chain result. The result value is dead because the bswap is dead.
8947 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8949 // Return N so it doesn't get rechecked!
8950 return SDValue(N, 0);
8954 case PPCISD::VCMP: {
8955 // If a VCMPo node already exists with exactly the same operands as this
8956 // node, use its result instead of this node (VCMPo computes both a CR6 and
8957 // a normal output).
8959 if (!N->getOperand(0).hasOneUse() &&
8960 !N->getOperand(1).hasOneUse() &&
8961 !N->getOperand(2).hasOneUse()) {
8963 // Scan all of the users of the LHS, looking for VCMPo's that match.
8964 SDNode *VCMPoNode = nullptr;
8966 SDNode *LHSN = N->getOperand(0).getNode();
8967 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8969 if (UI->getOpcode() == PPCISD::VCMPo &&
8970 UI->getOperand(1) == N->getOperand(1) &&
8971 UI->getOperand(2) == N->getOperand(2) &&
8972 UI->getOperand(0) == N->getOperand(0)) {
8977 // If there is no VCMPo node, or if the flag value has a single use, don't
8979 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8982 // Look at the (necessarily single) use of the flag value. If it has a
8983 // chain, this transformation is more complex. Note that multiple things
8984 // could use the value result, which we should ignore.
8985 SDNode *FlagUser = nullptr;
8986 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8987 FlagUser == nullptr; ++UI) {
8988 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8990 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8991 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8998 // If the user is a MFOCRF instruction, we know this is safe.
8999 // Otherwise we give up for right now.
9000 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9001 return SDValue(VCMPoNode, 0);
9006 SDValue Cond = N->getOperand(1);
9007 SDValue Target = N->getOperand(2);
9009 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9010 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9011 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9013 // We now need to make the intrinsic dead (it cannot be instruction
9015 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9016 assert(Cond.getNode()->hasOneUse() &&
9017 "Counter decrement has more than one use");
9019 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9020 N->getOperand(0), Target);
9025 // If this is a branch on an altivec predicate comparison, lower this so
9026 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9027 // lowering is done pre-legalize, because the legalizer lowers the predicate
9028 // compare down to code that is difficult to reassemble.
9029 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9030 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9032 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9033 // value. If so, pass-through the AND to get to the intrinsic.
9034 if (LHS.getOpcode() == ISD::AND &&
9035 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9036 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9037 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9038 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9039 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9041 LHS = LHS.getOperand(0);
9043 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9044 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9045 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9046 isa<ConstantSDNode>(RHS)) {
9047 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9048 "Counter decrement comparison is not EQ or NE");
9050 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9051 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9052 (CC == ISD::SETNE && !Val);
9054 // We now need to make the intrinsic dead (it cannot be instruction
9056 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9057 assert(LHS.getNode()->hasOneUse() &&
9058 "Counter decrement has more than one use");
9060 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9061 N->getOperand(0), N->getOperand(4));
9067 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9068 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9069 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9070 assert(isDot && "Can't compare against a vector result!");
9072 // If this is a comparison against something other than 0/1, then we know
9073 // that the condition is never/always true.
9074 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9075 if (Val != 0 && Val != 1) {
9076 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9077 return N->getOperand(0);
9078 // Always !=, turn it into an unconditional branch.
9079 return DAG.getNode(ISD::BR, dl, MVT::Other,
9080 N->getOperand(0), N->getOperand(4));
9083 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9085 // Create the PPCISD altivec 'dot' comparison node.
9087 LHS.getOperand(2), // LHS of compare
9088 LHS.getOperand(3), // RHS of compare
9089 DAG.getConstant(CompareOpc, MVT::i32)
9091 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9092 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9094 // Unpack the result based on how the target uses it.
9095 PPC::Predicate CompOpc;
9096 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9097 default: // Can't happen, don't crash on invalid number though.
9098 case 0: // Branch on the value of the EQ bit of CR6.
9099 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9101 case 1: // Branch on the inverted value of the EQ bit of CR6.
9102 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9104 case 2: // Branch on the value of the LT bit of CR6.
9105 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9107 case 3: // Branch on the inverted value of the LT bit of CR6.
9108 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9112 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9113 DAG.getConstant(CompOpc, MVT::i32),
9114 DAG.getRegister(PPC::CR6, MVT::i32),
9115 N->getOperand(4), CompNode.getValue(1));
9125 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9127 std::vector<SDNode *> *Created) const {
9128 // fold (sdiv X, pow2)
9129 EVT VT = N->getValueType(0);
9130 if (VT == MVT::i64 && !Subtarget.isPPC64())
9132 if ((VT != MVT::i32 && VT != MVT::i64) ||
9133 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9137 SDValue N0 = N->getOperand(0);
9139 bool IsNegPow2 = (-Divisor).isPowerOf2();
9140 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9141 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9143 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9145 Created->push_back(Op.getNode());
9148 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9150 Created->push_back(Op.getNode());
9156 //===----------------------------------------------------------------------===//
9157 // Inline Assembly Support
9158 //===----------------------------------------------------------------------===//
9160 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9163 const SelectionDAG &DAG,
9164 unsigned Depth) const {
9165 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9166 switch (Op.getOpcode()) {
9168 case PPCISD::LBRX: {
9169 // lhbrx is known to have the top bits cleared out.
9170 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9171 KnownZero = 0xFFFF0000;
9174 case ISD::INTRINSIC_WO_CHAIN: {
9175 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9177 case Intrinsic::ppc_altivec_vcmpbfp_p:
9178 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9179 case Intrinsic::ppc_altivec_vcmpequb_p:
9180 case Intrinsic::ppc_altivec_vcmpequh_p:
9181 case Intrinsic::ppc_altivec_vcmpequw_p:
9182 case Intrinsic::ppc_altivec_vcmpgefp_p:
9183 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9184 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9185 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9186 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9187 case Intrinsic::ppc_altivec_vcmpgtub_p:
9188 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9189 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9190 KnownZero = ~1U; // All bits but the low one are known to be zero.
9197 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9198 switch (Subtarget.getDarwinDirective()) {
9203 case PPC::DIR_PWR5X:
9205 case PPC::DIR_PWR6X:
9207 case PPC::DIR_PWR8: {
9211 const PPCInstrInfo *TII =
9212 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9215 // For small loops (between 5 and 8 instructions), align to a 32-byte
9216 // boundary so that the entire loop fits in one instruction-cache line.
9217 uint64_t LoopSize = 0;
9218 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9219 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9220 LoopSize += TII->GetInstSizeInBytes(J);
9222 if (LoopSize > 16 && LoopSize <= 32)
9229 return TargetLowering::getPrefLoopAlignment(ML);
9232 /// getConstraintType - Given a constraint, return the type of
9233 /// constraint it is for this target.
9234 PPCTargetLowering::ConstraintType
9235 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9236 if (Constraint.size() == 1) {
9237 switch (Constraint[0]) {
9244 return C_RegisterClass;
9246 // FIXME: While Z does indicate a memory constraint, it specifically
9247 // indicates an r+r address (used in conjunction with the 'y' modifier
9248 // in the replacement string). Currently, we're forcing the base
9249 // register to be r0 in the asm printer (which is interpreted as zero)
9250 // and forming the complete address in the second register. This is
9254 } else if (Constraint == "wc") { // individual CR bits.
9255 return C_RegisterClass;
9256 } else if (Constraint == "wa" || Constraint == "wd" ||
9257 Constraint == "wf" || Constraint == "ws") {
9258 return C_RegisterClass; // VSX registers.
9260 return TargetLowering::getConstraintType(Constraint);
9263 /// Examine constraint type and operand type and determine a weight value.
9264 /// This object must already have been set up with the operand type
9265 /// and the current alternative constraint selected.
9266 TargetLowering::ConstraintWeight
9267 PPCTargetLowering::getSingleConstraintMatchWeight(
9268 AsmOperandInfo &info, const char *constraint) const {
9269 ConstraintWeight weight = CW_Invalid;
9270 Value *CallOperandVal = info.CallOperandVal;
9271 // If we don't have a value, we can't do a match,
9272 // but allow it at the lowest weight.
9273 if (!CallOperandVal)
9275 Type *type = CallOperandVal->getType();
9277 // Look at the constraint type.
9278 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9279 return CW_Register; // an individual CR bit.
9280 else if ((StringRef(constraint) == "wa" ||
9281 StringRef(constraint) == "wd" ||
9282 StringRef(constraint) == "wf") &&
9285 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9288 switch (*constraint) {
9290 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9293 if (type->isIntegerTy())
9294 weight = CW_Register;
9297 if (type->isFloatTy())
9298 weight = CW_Register;
9301 if (type->isDoubleTy())
9302 weight = CW_Register;
9305 if (type->isVectorTy())
9306 weight = CW_Register;
9309 weight = CW_Register;
9318 std::pair<unsigned, const TargetRegisterClass*>
9319 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9321 if (Constraint.size() == 1) {
9322 // GCC RS6000 Constraint Letters
9323 switch (Constraint[0]) {
9325 if (VT == MVT::i64 && Subtarget.isPPC64())
9326 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9327 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9329 if (VT == MVT::i64 && Subtarget.isPPC64())
9330 return std::make_pair(0U, &PPC::G8RCRegClass);
9331 return std::make_pair(0U, &PPC::GPRCRegClass);
9333 if (VT == MVT::f32 || VT == MVT::i32)
9334 return std::make_pair(0U, &PPC::F4RCRegClass);
9335 if (VT == MVT::f64 || VT == MVT::i64)
9336 return std::make_pair(0U, &PPC::F8RCRegClass);
9339 return std::make_pair(0U, &PPC::VRRCRegClass);
9341 return std::make_pair(0U, &PPC::CRRCRegClass);
9343 } else if (Constraint == "wc") { // an individual CR bit.
9344 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9345 } else if (Constraint == "wa" || Constraint == "wd" ||
9346 Constraint == "wf") {
9347 return std::make_pair(0U, &PPC::VSRCRegClass);
9348 } else if (Constraint == "ws") {
9349 return std::make_pair(0U, &PPC::VSFRCRegClass);
9352 std::pair<unsigned, const TargetRegisterClass*> R =
9353 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9355 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9356 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9357 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9359 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9360 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9361 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9362 PPC::GPRCRegClass.contains(R.first)) {
9363 const TargetRegisterInfo *TRI =
9364 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9365 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9366 PPC::sub_32, &PPC::G8RCRegClass),
9367 &PPC::G8RCRegClass);
9370 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9371 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9373 R.second = &PPC::CRRCRegClass;
9380 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9381 /// vector. If it is invalid, don't add anything to Ops.
9382 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9383 std::string &Constraint,
9384 std::vector<SDValue>&Ops,
9385 SelectionDAG &DAG) const {
9388 // Only support length 1 constraints.
9389 if (Constraint.length() > 1) return;
9391 char Letter = Constraint[0];
9402 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9403 if (!CST) return; // Must be an immediate to match.
9404 int64_t Value = CST->getSExtValue();
9405 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9406 // numbers are printed as such.
9408 default: llvm_unreachable("Unknown constraint letter!");
9409 case 'I': // "I" is a signed 16-bit constant.
9410 if (isInt<16>(Value))
9411 Result = DAG.getTargetConstant(Value, TCVT);
9413 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9414 if (isShiftedUInt<16, 16>(Value))
9415 Result = DAG.getTargetConstant(Value, TCVT);
9417 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9418 if (isShiftedInt<16, 16>(Value))
9419 Result = DAG.getTargetConstant(Value, TCVT);
9421 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9422 if (isUInt<16>(Value))
9423 Result = DAG.getTargetConstant(Value, TCVT);
9425 case 'M': // "M" is a constant that is greater than 31.
9427 Result = DAG.getTargetConstant(Value, TCVT);
9429 case 'N': // "N" is a positive constant that is an exact power of two.
9430 if (Value > 0 && isPowerOf2_64(Value))
9431 Result = DAG.getTargetConstant(Value, TCVT);
9433 case 'O': // "O" is the constant zero.
9435 Result = DAG.getTargetConstant(Value, TCVT);
9437 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9438 if (isInt<16>(-Value))
9439 Result = DAG.getTargetConstant(Value, TCVT);
9446 if (Result.getNode()) {
9447 Ops.push_back(Result);
9451 // Handle standard constraint letters.
9452 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9455 // isLegalAddressingMode - Return true if the addressing mode represented
9456 // by AM is legal for this target, for a load/store of the specified type.
9457 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9459 // FIXME: PPC does not allow r+i addressing modes for vectors!
9461 // PPC allows a sign-extended 16-bit immediate field.
9462 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9465 // No global is ever allowed as a base.
9469 // PPC only support r+r,
9471 case 0: // "r+i" or just "i", depending on HasBaseReg.
9474 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9476 // Otherwise we have r+r or r+i.
9479 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9481 // Allow 2*r as r+r.
9484 // No other scales are supported.
9491 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9492 SelectionDAG &DAG) const {
9493 MachineFunction &MF = DAG.getMachineFunction();
9494 MachineFrameInfo *MFI = MF.getFrameInfo();
9495 MFI->setReturnAddressIsTaken(true);
9497 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9501 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9503 // Make sure the function does not optimize away the store of the RA to
9505 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9506 FuncInfo->setLRStoreRequired();
9507 bool isPPC64 = Subtarget.isPPC64();
9508 bool isDarwinABI = Subtarget.isDarwinABI();
9511 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9514 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9515 isPPC64? MVT::i64 : MVT::i32);
9516 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9517 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9519 MachinePointerInfo(), false, false, false, 0);
9522 // Just load the return address off the stack.
9523 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9524 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9525 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9528 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9529 SelectionDAG &DAG) const {
9531 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9533 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9534 bool isPPC64 = PtrVT == MVT::i64;
9536 MachineFunction &MF = DAG.getMachineFunction();
9537 MachineFrameInfo *MFI = MF.getFrameInfo();
9538 MFI->setFrameAddressIsTaken(true);
9540 // Naked functions never have a frame pointer, and so we use r1. For all
9541 // other functions, this decision must be delayed until during PEI.
9543 if (MF.getFunction()->getAttributes().hasAttribute(
9544 AttributeSet::FunctionIndex, Attribute::Naked))
9545 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9547 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9549 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9552 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9553 FrameAddr, MachinePointerInfo(), false, false,
9558 // FIXME? Maybe this could be a TableGen attribute on some registers and
9559 // this table could be generated automatically from RegInfo.
9560 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9562 bool isPPC64 = Subtarget.isPPC64();
9563 bool isDarwinABI = Subtarget.isDarwinABI();
9565 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9566 (!isPPC64 && VT != MVT::i32))
9567 report_fatal_error("Invalid register global variable type");
9569 bool is64Bit = isPPC64 && VT == MVT::i64;
9570 unsigned Reg = StringSwitch<unsigned>(RegName)
9571 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9572 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9573 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9574 (is64Bit ? PPC::X13 : PPC::R13))
9579 report_fatal_error("Invalid register name global variable");
9583 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9584 // The PowerPC target isn't yet aware of offsets.
9588 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9590 unsigned Intrinsic) const {
9592 switch (Intrinsic) {
9593 case Intrinsic::ppc_altivec_lvx:
9594 case Intrinsic::ppc_altivec_lvxl:
9595 case Intrinsic::ppc_altivec_lvebx:
9596 case Intrinsic::ppc_altivec_lvehx:
9597 case Intrinsic::ppc_altivec_lvewx:
9598 case Intrinsic::ppc_vsx_lxvd2x:
9599 case Intrinsic::ppc_vsx_lxvw4x: {
9601 switch (Intrinsic) {
9602 case Intrinsic::ppc_altivec_lvebx:
9605 case Intrinsic::ppc_altivec_lvehx:
9608 case Intrinsic::ppc_altivec_lvewx:
9611 case Intrinsic::ppc_vsx_lxvd2x:
9619 Info.opc = ISD::INTRINSIC_W_CHAIN;
9621 Info.ptrVal = I.getArgOperand(0);
9622 Info.offset = -VT.getStoreSize()+1;
9623 Info.size = 2*VT.getStoreSize()-1;
9626 Info.readMem = true;
9627 Info.writeMem = false;
9630 case Intrinsic::ppc_altivec_stvx:
9631 case Intrinsic::ppc_altivec_stvxl:
9632 case Intrinsic::ppc_altivec_stvebx:
9633 case Intrinsic::ppc_altivec_stvehx:
9634 case Intrinsic::ppc_altivec_stvewx:
9635 case Intrinsic::ppc_vsx_stxvd2x:
9636 case Intrinsic::ppc_vsx_stxvw4x: {
9638 switch (Intrinsic) {
9639 case Intrinsic::ppc_altivec_stvebx:
9642 case Intrinsic::ppc_altivec_stvehx:
9645 case Intrinsic::ppc_altivec_stvewx:
9648 case Intrinsic::ppc_vsx_stxvd2x:
9656 Info.opc = ISD::INTRINSIC_VOID;
9658 Info.ptrVal = I.getArgOperand(1);
9659 Info.offset = -VT.getStoreSize()+1;
9660 Info.size = 2*VT.getStoreSize()-1;
9663 Info.readMem = false;
9664 Info.writeMem = true;
9674 /// getOptimalMemOpType - Returns the target specific optimal type for load
9675 /// and store operations as a result of memset, memcpy, and memmove
9676 /// lowering. If DstAlign is zero that means it's safe to destination
9677 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9678 /// means there isn't a need to check it against alignment requirement,
9679 /// probably because the source does not need to be loaded. If 'IsMemset' is
9680 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9681 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9682 /// source is constant so it does not need to be loaded.
9683 /// It returns EVT::Other if the type should be determined using generic
9684 /// target-independent logic.
9685 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9686 unsigned DstAlign, unsigned SrcAlign,
9687 bool IsMemset, bool ZeroMemset,
9689 MachineFunction &MF) const {
9690 if (Subtarget.isPPC64()) {
9697 /// \brief Returns true if it is beneficial to convert a load of a constant
9698 /// to just the constant itself.
9699 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9701 assert(Ty->isIntegerTy());
9703 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9704 if (BitSize == 0 || BitSize > 64)
9709 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9710 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9712 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9713 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9714 return NumBits1 == 64 && NumBits2 == 32;
9717 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9718 if (!VT1.isInteger() || !VT2.isInteger())
9720 unsigned NumBits1 = VT1.getSizeInBits();
9721 unsigned NumBits2 = VT2.getSizeInBits();
9722 return NumBits1 == 64 && NumBits2 == 32;
9725 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9726 return isInt<16>(Imm) || isUInt<16>(Imm);
9729 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9730 return isInt<16>(Imm) || isUInt<16>(Imm);
9733 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9737 if (DisablePPCUnaligned)
9740 // PowerPC supports unaligned memory access for simple non-vector types.
9741 // Although accessing unaligned addresses is not as efficient as accessing
9742 // aligned addresses, it is generally more efficient than manual expansion,
9743 // and generally only traps for software emulation when crossing page
9749 if (VT.getSimpleVT().isVector()) {
9750 if (Subtarget.hasVSX()) {
9751 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9752 VT != MVT::v4f32 && VT != MVT::v4i32)
9759 if (VT == MVT::ppcf128)
9768 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9769 VT = VT.getScalarType();
9774 switch (VT.getSimpleVT().SimpleTy) {
9786 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9787 EVT VT , unsigned DefinedValues) const {
9788 if (VT == MVT::v2i64)
9791 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9794 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9795 if (DisableILPPref || Subtarget.enableMachineScheduler())
9796 return TargetLowering::getSchedulingPreference(N);
9801 // Create a fast isel object.
9803 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9804 const TargetLibraryInfo *LibInfo) const {
9805 return PPC::createFastISel(FuncInfo, LibInfo);