1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 if (Subtarget.useCRBits()) {
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
100 if (isPPC64 || Subtarget.hasFPCVT()) {
101 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
112 // PowerPC does not support direct load / store of condition registers
113 setOperationAction(ISD::LOAD, MVT::i1, Custom);
114 setOperationAction(ISD::STORE, MVT::i1, Custom);
116 // FIXME: Remove this once the ANDI glue bug is fixed:
118 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
120 for (MVT VT : MVT::integer_valuetypes()) {
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
123 setTruncStoreAction(VT, MVT::i1, Expand);
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
129 // This is used in the ppcf128->int sequence. Note it has different semantics
130 // from FP_ROUND: that rounds to nearest, this rounds to zero.
131 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
133 // We do not currently implement these libm ops for PowerPC.
134 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
141 // PowerPC has no SREM/UREM instructions
142 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::UREM, MVT::i32, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
148 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
157 // We don't support sin/cos/sqrt/fmod/pow
158 setOperationAction(ISD::FSIN , MVT::f64, Expand);
159 setOperationAction(ISD::FCOS , MVT::f64, Expand);
160 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
161 setOperationAction(ISD::FREM , MVT::f64, Expand);
162 setOperationAction(ISD::FPOW , MVT::f64, Expand);
163 setOperationAction(ISD::FMA , MVT::f64, Legal);
164 setOperationAction(ISD::FSIN , MVT::f32, Expand);
165 setOperationAction(ISD::FCOS , MVT::f32, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FREM , MVT::f32, Expand);
168 setOperationAction(ISD::FPOW , MVT::f32, Expand);
169 setOperationAction(ISD::FMA , MVT::f32, Legal);
171 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
173 // If we're enabling GP optimizations, use hardware square root
174 if (!Subtarget.hasFSQRT() &&
175 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
177 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
181 Subtarget.hasFRES()))
182 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
184 if (Subtarget.hasFCPSGN()) {
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
192 if (Subtarget.hasFPRND()) {
193 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
194 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
195 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
196 setOperationAction(ISD::FROUND, MVT::f64, Legal);
198 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
201 setOperationAction(ISD::FROUND, MVT::f32, Legal);
204 // PowerPC does not have BSWAP, CTPOP or CTTZ
205 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
207 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
209 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
214 if (Subtarget.hasPOPCNTD()) {
215 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
218 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
222 // PowerPC does not have ROTR
223 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
224 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
226 if (!Subtarget.useCRBits()) {
227 // PowerPC does not have Select
228 setOperationAction(ISD::SELECT, MVT::i32, Expand);
229 setOperationAction(ISD::SELECT, MVT::i64, Expand);
230 setOperationAction(ISD::SELECT, MVT::f32, Expand);
231 setOperationAction(ISD::SELECT, MVT::f64, Expand);
234 // PowerPC wants to turn select_cc of FP into fsel when possible.
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
238 // PowerPC wants to optimize integer setcc a bit
239 if (!Subtarget.useCRBits())
240 setOperationAction(ISD::SETCC, MVT::i32, Custom);
242 // PowerPC does not have BRCOND which requires SetCC
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
246 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
248 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
251 // PowerPC does not have [U|S]INT_TO_FP
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
257 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
260 // We cannot sextinreg(i1). Expand to shifts.
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
263 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
264 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
265 // support continuation, user-level threading, and etc.. As a result, no
266 // other SjLj exception interfaces are implemented and please don't build
267 // your own exception handling based on them.
268 // LLVM/Clang supports zero-cost DWARF exception handling.
269 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
270 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
272 // We want to legalize GlobalAddress and ConstantPool nodes into the
273 // appropriate instructions to materialize the address.
274 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
277 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
278 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
286 setOperationAction(ISD::TRAP, MVT::Other, Legal);
288 // TRAMPOLINE is custom lowered.
289 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
290 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
292 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
293 setOperationAction(ISD::VASTART , MVT::Other, Custom);
295 if (Subtarget.isSVR4ABI()) {
297 // VAARG always uses double-word chunks, so promote anything smaller.
298 setOperationAction(ISD::VAARG, MVT::i1, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i8, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i16, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i32, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::Other, Expand);
308 // VAARG is custom lowered with the 32-bit SVR4 ABI.
309 setOperationAction(ISD::VAARG, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::i64, Custom);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
315 if (Subtarget.isSVR4ABI() && !isPPC64)
316 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
319 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
321 // Use the default implementation.
322 setOperationAction(ISD::VAEND , MVT::Other, Expand);
323 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
324 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
326 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
328 // We want to custom lower some of our intrinsics.
329 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
331 // To handle counter-based loop conditions.
332 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
334 // Comparisons that require checking two conditions.
335 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
348 if (Subtarget.has64BitSupport()) {
349 // They also have instructions for converting between i64 and fp.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
354 // This is just the low 32 bits of a (signed) fp->i64 conversion.
355 // We cannot do this with Promote because i64 is not a legal type.
356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
361 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
362 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
365 // With the instructions enabled under FPCVT, we can do everything.
366 if (Subtarget.hasFPCVT()) {
367 if (Subtarget.has64BitSupport()) {
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
369 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
380 if (Subtarget.use64BitRegs()) {
381 // 64-bit PowerPC implementations can support i64 types directly
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
383 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
384 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
385 // 64-bit PowerPC wants to expand i128 shifts itself.
386 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
388 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
390 // 32-bit PowerPC wants to expand i64 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
396 if (Subtarget.hasAltivec()) {
397 // First set operation action for all vector types to expand. Then we
398 // will selectively turn on ones that can be effectively codegen'd.
399 for (MVT VT : MVT::vector_valuetypes()) {
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (MVT InnerVT : MVT::vector_valuetypes()) {
467 setTruncStoreAction(VT, InnerVT, Expand);
468 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
470 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
474 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
475 // with merges, splats, etc.
476 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
478 setOperationAction(ISD::AND , MVT::v4i32, Legal);
479 setOperationAction(ISD::OR , MVT::v4i32, Legal);
480 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
481 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
482 setOperationAction(ISD::SELECT, MVT::v4i32,
483 Subtarget.useCRBits() ? Legal : Expand);
484 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
487 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
489 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
490 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
491 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
499 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
502 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
503 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
504 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
507 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
508 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
509 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
512 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
519 // Altivec does not contain unordered floating-point compare instructions
520 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
525 if (Subtarget.hasVSX()) {
526 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
529 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
537 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
538 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
540 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
541 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
549 // Share the Altivec comparison restrictions.
550 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
555 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
556 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
558 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
562 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
563 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
565 // VSX v2i64 only supports non-arithmetic operations.
566 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
567 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
569 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
571 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
575 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
582 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
585 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
587 // Vector operation legalization checks the result type of
588 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
594 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
598 if (Subtarget.has64BitSupport())
599 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
604 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
608 setBooleanContents(ZeroOrOneBooleanContent);
609 // Altivec instructions set fields to all zeros or all ones.
610 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
613 // These libcalls are not available in 32-bit.
614 setLibcallName(RTLIB::SHL_I128, nullptr);
615 setLibcallName(RTLIB::SRL_I128, nullptr);
616 setLibcallName(RTLIB::SRA_I128, nullptr);
620 setStackPointerRegisterToSaveRestore(PPC::X1);
621 setExceptionPointerRegister(PPC::X3);
622 setExceptionSelectorRegister(PPC::X4);
624 setStackPointerRegisterToSaveRestore(PPC::R1);
625 setExceptionPointerRegister(PPC::R3);
626 setExceptionSelectorRegister(PPC::R4);
629 // We have target-specific dag combine patterns for the following nodes:
630 setTargetDAGCombine(ISD::SINT_TO_FP);
631 if (Subtarget.hasFPCVT())
632 setTargetDAGCombine(ISD::UINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 switch (Subtarget.getDarwinDirective()) {
686 case PPC::DIR_E500mc:
695 setPrefFunctionAlignment(4);
696 setPrefLoopAlignment(4);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores do better with aggressive inlining of memcpy and
710 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
722 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
723 /// the desired ByVal argument alignment.
724 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
725 unsigned MaxMaxAlign) {
726 if (MaxAlign == MaxMaxAlign)
728 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
729 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
731 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
733 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
739 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
742 if (EltAlign > MaxAlign)
744 if (MaxAlign == MaxMaxAlign)
750 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
751 /// function arguments in the caller parameter area.
752 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
753 // Darwin passes everything on 4 byte boundary.
754 if (Subtarget.isDarwin())
757 // 16byte and wider vectors are passed on 16byte boundary.
758 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
759 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
760 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
761 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
765 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
767 default: return nullptr;
768 case PPCISD::FSEL: return "PPCISD::FSEL";
769 case PPCISD::FCFID: return "PPCISD::FCFID";
770 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
771 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
772 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
776 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
777 case PPCISD::FRE: return "PPCISD::FRE";
778 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
779 case PPCISD::STFIWX: return "PPCISD::STFIWX";
780 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
781 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
782 case PPCISD::VPERM: return "PPCISD::VPERM";
783 case PPCISD::CMPB: return "PPCISD::CMPB";
784 case PPCISD::Hi: return "PPCISD::Hi";
785 case PPCISD::Lo: return "PPCISD::Lo";
786 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
795 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
796 case PPCISD::MTCTR: return "PPCISD::MTCTR";
797 case PPCISD::BCTRL: return "PPCISD::BCTRL";
798 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
799 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
800 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
801 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
802 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
803 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
804 case PPCISD::VCMP: return "PPCISD::VCMP";
805 case PPCISD::VCMPo: return "PPCISD::VCMPo";
806 case PPCISD::LBRX: return "PPCISD::LBRX";
807 case PPCISD::STBRX: return "PPCISD::STBRX";
808 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
809 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
810 case PPCISD::LARX: return "PPCISD::LARX";
811 case PPCISD::STCX: return "PPCISD::STCX";
812 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
813 case PPCISD::BDNZ: return "PPCISD::BDNZ";
814 case PPCISD::BDZ: return "PPCISD::BDZ";
815 case PPCISD::MFFS: return "PPCISD::MFFS";
816 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
817 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
818 case PPCISD::CR6SET: return "PPCISD::CR6SET";
819 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
820 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
821 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
822 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
823 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
824 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
825 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
826 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
827 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
828 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
829 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
830 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
831 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
832 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
833 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
834 case PPCISD::SC: return "PPCISD::SC";
838 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
841 return VT.changeVectorElementTypeToInteger();
844 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
845 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
849 //===----------------------------------------------------------------------===//
850 // Node matching predicates, for use by the tblgen matching code.
851 //===----------------------------------------------------------------------===//
853 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
854 static bool isFloatingPointZero(SDValue Op) {
855 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
856 return CFP->getValueAPF().isZero();
857 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
858 // Maybe this has already been legalized into the constant pool?
859 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
860 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
861 return CFP->getValueAPF().isZero();
866 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
867 /// true if Op is undef or if it matches the specified value.
868 static bool isConstantOrUndef(int Op, int Val) {
869 return Op < 0 || Op == Val;
872 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUHUM instruction.
874 /// The ShuffleKind distinguishes between big-endian operations with
875 /// two different inputs (0), either-endian operations with two identical
876 /// inputs (1), and little-endian operantion with two different inputs (2).
877 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
878 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
880 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
881 if (ShuffleKind == 0) {
884 for (unsigned i = 0; i != 16; ++i)
885 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
887 } else if (ShuffleKind == 2) {
890 for (unsigned i = 0; i != 16; ++i)
891 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
893 } else if (ShuffleKind == 1) {
894 unsigned j = IsLE ? 0 : 1;
895 for (unsigned i = 0; i != 8; ++i)
896 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
903 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
904 /// VPKUWUM instruction.
905 /// The ShuffleKind distinguishes between big-endian operations with
906 /// two different inputs (0), either-endian operations with two identical
907 /// inputs (1), and little-endian operantion with two different inputs (2).
908 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
909 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
911 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
912 if (ShuffleKind == 0) {
915 for (unsigned i = 0; i != 16; i += 2)
916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
919 } else if (ShuffleKind == 2) {
922 for (unsigned i = 0; i != 16; i += 2)
923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
926 } else if (ShuffleKind == 1) {
927 unsigned j = IsLE ? 0 : 2;
928 for (unsigned i = 0; i != 8; i += 2)
929 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
931 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
932 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
938 /// isVMerge - Common function, used to match vmrg* shuffles.
940 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned LHSStart, unsigned RHSStart) {
942 if (N->getValueType(0) != MVT::v16i8)
944 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
945 "Unsupported merge size!");
947 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
948 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
949 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
950 LHSStart+j+i*UnitSize) ||
951 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
952 RHSStart+j+i*UnitSize))
958 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
959 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
960 /// The ShuffleKind distinguishes between big-endian merges with two
961 /// different inputs (0), either-endian merges with two identical inputs (1),
962 /// and little-endian merges with two different inputs (2). For the latter,
963 /// the input operands are swapped (see PPCInstrAltivec.td).
964 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
965 unsigned ShuffleKind, SelectionDAG &DAG) {
966 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
967 if (ShuffleKind == 1) // unary
968 return isVMerge(N, UnitSize, 0, 0);
969 else if (ShuffleKind == 2) // swapped
970 return isVMerge(N, UnitSize, 0, 16);
974 if (ShuffleKind == 1) // unary
975 return isVMerge(N, UnitSize, 8, 8);
976 else if (ShuffleKind == 0) // normal
977 return isVMerge(N, UnitSize, 8, 24);
983 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
984 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
985 /// The ShuffleKind distinguishes between big-endian merges with two
986 /// different inputs (0), either-endian merges with two identical inputs (1),
987 /// and little-endian merges with two different inputs (2). For the latter,
988 /// the input operands are swapped (see PPCInstrAltivec.td).
989 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
990 unsigned ShuffleKind, SelectionDAG &DAG) {
991 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
992 if (ShuffleKind == 1) // unary
993 return isVMerge(N, UnitSize, 8, 8);
994 else if (ShuffleKind == 2) // swapped
995 return isVMerge(N, UnitSize, 8, 24);
999 if (ShuffleKind == 1) // unary
1000 return isVMerge(N, UnitSize, 0, 0);
1001 else if (ShuffleKind == 0) // normal
1002 return isVMerge(N, UnitSize, 0, 16);
1009 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1010 /// amount, otherwise return -1.
1011 /// The ShuffleKind distinguishes between big-endian operations with two
1012 /// different inputs (0), either-endian operations with two identical inputs
1013 /// (1), and little-endian operations with two different inputs (2). For the
1014 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1015 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1016 SelectionDAG &DAG) {
1017 if (N->getValueType(0) != MVT::v16i8)
1020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1022 // Find the first non-undef value in the shuffle mask.
1024 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1027 if (i == 16) return -1; // all undef.
1029 // Otherwise, check to see if the rest of the elements are consecutively
1030 // numbered from this value.
1031 unsigned ShiftAmt = SVOp->getMaskElt(i);
1032 if (ShiftAmt < i) return -1;
1035 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1037 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1038 // Check the rest of the elements to see if they are consecutive.
1039 for (++i; i != 16; ++i)
1040 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1042 } else if (ShuffleKind == 1) {
1043 // Check the rest of the elements to see if they are consecutive.
1044 for (++i; i != 16; ++i)
1045 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1050 if (ShuffleKind == 2 && isLE)
1051 ShiftAmt = 16 - ShiftAmt;
1056 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1057 /// specifies a splat of a single element that is suitable for input to
1058 /// VSPLTB/VSPLTH/VSPLTW.
1059 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1060 assert(N->getValueType(0) == MVT::v16i8 &&
1061 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1063 // This is a splat operation if each element of the permute is the same, and
1064 // if the value doesn't reference the second vector.
1065 unsigned ElementBase = N->getMaskElt(0);
1067 // FIXME: Handle UNDEF elements too!
1068 if (ElementBase >= 16)
1071 // Check that the indices are consecutive, in the case of a multi-byte element
1072 // splatted with a v16i8 mask.
1073 for (unsigned i = 1; i != EltSize; ++i)
1074 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1077 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1078 if (N->getMaskElt(i) < 0) continue;
1079 for (unsigned j = 0; j != EltSize; ++j)
1080 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1086 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1088 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1089 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1091 APInt APVal, APUndef;
1095 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1096 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1097 return CFP->getValueAPF().isNegZero();
1102 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1103 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1104 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1105 SelectionDAG &DAG) {
1106 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1107 assert(isSplatShuffleMask(SVOp, EltSize));
1108 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1109 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1111 return SVOp->getMaskElt(0) / EltSize;
1114 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1115 /// by using a vspltis[bhw] instruction of the specified element size, return
1116 /// the constant being splatted. The ByteSize field indicates the number of
1117 /// bytes of each element [124] -> [bhw].
1118 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1119 SDValue OpVal(nullptr, 0);
1121 // If ByteSize of the splat is bigger than the element size of the
1122 // build_vector, then we have a case where we are checking for a splat where
1123 // multiple elements of the buildvector are folded together into a single
1124 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1125 unsigned EltSize = 16/N->getNumOperands();
1126 if (EltSize < ByteSize) {
1127 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1128 SDValue UniquedVals[4];
1129 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1131 // See if all of the elements in the buildvector agree across.
1132 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1133 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1134 // If the element isn't a constant, bail fully out.
1135 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1138 if (!UniquedVals[i&(Multiple-1)].getNode())
1139 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1140 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1141 return SDValue(); // no match.
1144 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1145 // either constant or undef values that are identical for each chunk. See
1146 // if these chunks can form into a larger vspltis*.
1148 // Check to see if all of the leading entries are either 0 or -1. If
1149 // neither, then this won't fit into the immediate field.
1150 bool LeadingZero = true;
1151 bool LeadingOnes = true;
1152 for (unsigned i = 0; i != Multiple-1; ++i) {
1153 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1155 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1156 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1158 // Finally, check the least significant entry.
1160 if (!UniquedVals[Multiple-1].getNode())
1161 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1162 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1164 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1167 if (!UniquedVals[Multiple-1].getNode())
1168 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1169 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1170 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1171 return DAG.getTargetConstant(Val, MVT::i32);
1177 // Check to see if this buildvec has a single non-undef value in its elements.
1178 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1179 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1180 if (!OpVal.getNode())
1181 OpVal = N->getOperand(i);
1182 else if (OpVal != N->getOperand(i))
1186 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1188 unsigned ValSizeInBytes = EltSize;
1190 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1191 Value = CN->getZExtValue();
1192 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1193 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1194 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1197 // If the splat value is larger than the element value, then we can never do
1198 // this splat. The only case that we could fit the replicated bits into our
1199 // immediate field for would be zero, and we prefer to use vxor for it.
1200 if (ValSizeInBytes < ByteSize) return SDValue();
1202 // If the element value is larger than the splat value, cut it in half and
1203 // check to see if the two halves are equal. Continue doing this until we
1204 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1205 while (ValSizeInBytes > ByteSize) {
1206 ValSizeInBytes >>= 1;
1208 // If the top half equals the bottom half, we're still ok.
1209 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1210 (Value & ((1 << (8*ValSizeInBytes))-1)))
1214 // Properly sign extend the value.
1215 int MaskVal = SignExtend32(Value, ByteSize * 8);
1217 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1218 if (MaskVal == 0) return SDValue();
1220 // Finally, if this value fits in a 5 bit sext field, return it
1221 if (SignExtend32<5>(MaskVal) == MaskVal)
1222 return DAG.getTargetConstant(MaskVal, MVT::i32);
1226 //===----------------------------------------------------------------------===//
1227 // Addressing Mode Selection
1228 //===----------------------------------------------------------------------===//
1230 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1231 /// or 64-bit immediate, and if the value can be accurately represented as a
1232 /// sign extension from a 16-bit value. If so, this returns true and the
1234 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1235 if (!isa<ConstantSDNode>(N))
1238 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1239 if (N->getValueType(0) == MVT::i32)
1240 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1242 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1244 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1245 return isIntS16Immediate(Op.getNode(), Imm);
1249 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1250 /// can be represented as an indexed [r+r] operation. Returns false if it
1251 /// can be more efficiently represented with [r+imm].
1252 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1254 SelectionDAG &DAG) const {
1256 if (N.getOpcode() == ISD::ADD) {
1257 if (isIntS16Immediate(N.getOperand(1), imm))
1258 return false; // r+i
1259 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1260 return false; // r+i
1262 Base = N.getOperand(0);
1263 Index = N.getOperand(1);
1265 } else if (N.getOpcode() == ISD::OR) {
1266 if (isIntS16Immediate(N.getOperand(1), imm))
1267 return false; // r+i can fold it if we can.
1269 // If this is an or of disjoint bitfields, we can codegen this as an add
1270 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1272 APInt LHSKnownZero, LHSKnownOne;
1273 APInt RHSKnownZero, RHSKnownOne;
1274 DAG.computeKnownBits(N.getOperand(0),
1275 LHSKnownZero, LHSKnownOne);
1277 if (LHSKnownZero.getBoolValue()) {
1278 DAG.computeKnownBits(N.getOperand(1),
1279 RHSKnownZero, RHSKnownOne);
1280 // If all of the bits are known zero on the LHS or RHS, the add won't
1282 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1283 Base = N.getOperand(0);
1284 Index = N.getOperand(1);
1293 // If we happen to be doing an i64 load or store into a stack slot that has
1294 // less than a 4-byte alignment, then the frame-index elimination may need to
1295 // use an indexed load or store instruction (because the offset may not be a
1296 // multiple of 4). The extra register needed to hold the offset comes from the
1297 // register scavenger, and it is possible that the scavenger will need to use
1298 // an emergency spill slot. As a result, we need to make sure that a spill slot
1299 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1301 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1302 // FIXME: This does not handle the LWA case.
1306 // NOTE: We'll exclude negative FIs here, which come from argument
1307 // lowering, because there are no known test cases triggering this problem
1308 // using packed structures (or similar). We can remove this exclusion if
1309 // we find such a test case. The reason why this is so test-case driven is
1310 // because this entire 'fixup' is only to prevent crashes (from the
1311 // register scavenger) on not-really-valid inputs. For example, if we have:
1313 // %b = bitcast i1* %a to i64*
1314 // store i64* a, i64 b
1315 // then the store should really be marked as 'align 1', but is not. If it
1316 // were marked as 'align 1' then the indexed form would have been
1317 // instruction-selected initially, and the problem this 'fixup' is preventing
1318 // won't happen regardless.
1322 MachineFunction &MF = DAG.getMachineFunction();
1323 MachineFrameInfo *MFI = MF.getFrameInfo();
1325 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1329 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1330 FuncInfo->setHasNonRISpills();
1333 /// Returns true if the address N can be represented by a base register plus
1334 /// a signed 16-bit displacement [r+imm], and if it is not better
1335 /// represented as reg+reg. If Aligned is true, only accept displacements
1336 /// suitable for STD and friends, i.e. multiples of 4.
1337 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1340 bool Aligned) const {
1341 // FIXME dl should come from parent load or store, not from address
1343 // If this can be more profitably realized as r+r, fail.
1344 if (SelectAddressRegReg(N, Disp, Base, DAG))
1347 if (N.getOpcode() == ISD::ADD) {
1349 if (isIntS16Immediate(N.getOperand(1), imm) &&
1350 (!Aligned || (imm & 3) == 0)) {
1351 Disp = DAG.getTargetConstant(imm, N.getValueType());
1352 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1353 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1354 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1356 Base = N.getOperand(0);
1358 return true; // [r+i]
1359 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1360 // Match LOAD (ADD (X, Lo(G))).
1361 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1362 && "Cannot handle constant offsets yet!");
1363 Disp = N.getOperand(1).getOperand(0); // The global address.
1364 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1365 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1366 Disp.getOpcode() == ISD::TargetConstantPool ||
1367 Disp.getOpcode() == ISD::TargetJumpTable);
1368 Base = N.getOperand(0);
1369 return true; // [&g+r]
1371 } else if (N.getOpcode() == ISD::OR) {
1373 if (isIntS16Immediate(N.getOperand(1), imm) &&
1374 (!Aligned || (imm & 3) == 0)) {
1375 // If this is an or of disjoint bitfields, we can codegen this as an add
1376 // (for better address arithmetic) if the LHS and RHS of the OR are
1377 // provably disjoint.
1378 APInt LHSKnownZero, LHSKnownOne;
1379 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1381 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1382 // If all of the bits are known zero on the LHS or RHS, the add won't
1384 if (FrameIndexSDNode *FI =
1385 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1386 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1387 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1389 Base = N.getOperand(0);
1391 Disp = DAG.getTargetConstant(imm, N.getValueType());
1395 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1396 // Loading from a constant address.
1398 // If this address fits entirely in a 16-bit sext immediate field, codegen
1401 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1402 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1403 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 CN->getValueType(0));
1408 // Handle 32-bit sext immediates with LIS + addr mode.
1409 if ((CN->getValueType(0) == MVT::i32 ||
1410 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1411 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1412 int Addr = (int)CN->getZExtValue();
1414 // Otherwise, break this down into an LIS + disp.
1415 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1417 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1418 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1419 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1424 Disp = DAG.getTargetConstant(0, getPointerTy());
1425 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1426 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1427 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1430 return true; // [r+0]
1433 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1434 /// represented as an indexed [r+r] operation.
1435 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1437 SelectionDAG &DAG) const {
1438 // Check to see if we can easily represent this as an [r+r] address. This
1439 // will fail if it thinks that the address is more profitably represented as
1440 // reg+imm, e.g. where imm = 0.
1441 if (SelectAddressRegReg(N, Base, Index, DAG))
1444 // If the operand is an addition, always emit this as [r+r], since this is
1445 // better (for code size, and execution, as the memop does the add for free)
1446 // than emitting an explicit add.
1447 if (N.getOpcode() == ISD::ADD) {
1448 Base = N.getOperand(0);
1449 Index = N.getOperand(1);
1453 // Otherwise, do it the hard way, using R0 as the base register.
1454 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1460 /// getPreIndexedAddressParts - returns true by value, base pointer and
1461 /// offset pointer and addressing mode by reference if the node's address
1462 /// can be legally represented as pre-indexed load / store address.
1463 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1465 ISD::MemIndexedMode &AM,
1466 SelectionDAG &DAG) const {
1467 if (DisablePPCPreinc) return false;
1473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1474 Ptr = LD->getBasePtr();
1475 VT = LD->getMemoryVT();
1476 Alignment = LD->getAlignment();
1477 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1478 Ptr = ST->getBasePtr();
1479 VT = ST->getMemoryVT();
1480 Alignment = ST->getAlignment();
1485 // PowerPC doesn't have preinc load/store instructions for vectors.
1489 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1491 // Common code will reject creating a pre-inc form if the base pointer
1492 // is a frame index, or if N is a store and the base pointer is either
1493 // the same as or a predecessor of the value being stored. Check for
1494 // those situations here, and try with swapped Base/Offset instead.
1497 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1500 SDValue Val = cast<StoreSDNode>(N)->getValue();
1501 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1506 std::swap(Base, Offset);
1512 // LDU/STU can only handle immediates that are a multiple of 4.
1513 if (VT != MVT::i64) {
1514 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1517 // LDU/STU need an address with at least 4-byte alignment.
1521 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1525 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1526 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1527 // sext i32 to i64 when addr mode is r+i.
1528 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1529 LD->getExtensionType() == ISD::SEXTLOAD &&
1530 isa<ConstantSDNode>(Offset))
1538 //===----------------------------------------------------------------------===//
1539 // LowerOperation implementation
1540 //===----------------------------------------------------------------------===//
1542 /// GetLabelAccessInfo - Return true if we should reference labels using a
1543 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1544 static bool GetLabelAccessInfo(const TargetMachine &TM,
1545 const PPCSubtarget &Subtarget,
1546 unsigned &HiOpFlags, unsigned &LoOpFlags,
1547 const GlobalValue *GV = nullptr) {
1548 HiOpFlags = PPCII::MO_HA;
1549 LoOpFlags = PPCII::MO_LO;
1551 // Don't use the pic base if not in PIC relocation model.
1552 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1555 HiOpFlags |= PPCII::MO_PIC_FLAG;
1556 LoOpFlags |= PPCII::MO_PIC_FLAG;
1559 // If this is a reference to a global value that requires a non-lazy-ptr, make
1560 // sure that instruction lowering adds it.
1561 if (GV && Subtarget.hasLazyResolverStub(GV, TM)) {
1562 HiOpFlags |= PPCII::MO_NLP_FLAG;
1563 LoOpFlags |= PPCII::MO_NLP_FLAG;
1565 if (GV->hasHiddenVisibility()) {
1566 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1567 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1574 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1575 SelectionDAG &DAG) {
1576 EVT PtrVT = HiPart.getValueType();
1577 SDValue Zero = DAG.getConstant(0, PtrVT);
1580 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1581 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1583 // With PIC, the first instruction is actually "GR+hi(&G)".
1585 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1586 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1588 // Generate non-pic code that has direct accesses to the constant pool.
1589 // The address of the global is just (hi(&g)+lo(&g)).
1590 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1593 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1594 SelectionDAG &DAG) const {
1595 EVT PtrVT = Op.getValueType();
1596 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1597 const Constant *C = CP->getConstVal();
1599 // 64-bit SVR4 ABI code is always position-independent.
1600 // The actual address of the GlobalValue is stored in the TOC.
1601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1602 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1603 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1604 DAG.getRegister(PPC::X2, MVT::i64));
1607 unsigned MOHiFlag, MOLoFlag;
1609 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1611 if (isPIC && Subtarget.isSVR4ABI()) {
1612 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1613 PPCII::MO_PIC_FLAG);
1615 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1616 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1620 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1622 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1623 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1626 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1627 EVT PtrVT = Op.getValueType();
1628 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1630 // 64-bit SVR4 ABI code is always position-independent.
1631 // The actual address of the GlobalValue is stored in the TOC.
1632 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1633 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1634 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1635 DAG.getRegister(PPC::X2, MVT::i64));
1638 unsigned MOHiFlag, MOLoFlag;
1640 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1642 if (isPIC && Subtarget.isSVR4ABI()) {
1643 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1644 PPCII::MO_PIC_FLAG);
1646 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1647 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1650 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1651 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1652 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1655 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1656 SelectionDAG &DAG) const {
1657 EVT PtrVT = Op.getValueType();
1658 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1659 const BlockAddress *BA = BASDN->getBlockAddress();
1661 // 64-bit SVR4 ABI code is always position-independent.
1662 // The actual BlockAddress is stored in the TOC.
1663 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1664 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1665 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1666 DAG.getRegister(PPC::X2, MVT::i64));
1669 unsigned MOHiFlag, MOLoFlag;
1671 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1672 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1673 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1674 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1677 // Generate a call to __tls_get_addr for the given GOT entry Op.
1678 std::pair<SDValue,SDValue>
1679 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1680 SelectionDAG &DAG) const {
1682 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1683 TargetLowering::ArgListTy Args;
1684 TargetLowering::ArgListEntry Entry;
1686 Entry.Ty = IntPtrTy;
1687 Args.push_back(Entry);
1689 TargetLowering::CallLoweringInfo CLI(DAG);
1690 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1691 .setCallee(CallingConv::C, IntPtrTy,
1692 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1693 std::move(Args), 0);
1695 return LowerCallTo(CLI);
1698 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1699 SelectionDAG &DAG) const {
1701 // FIXME: TLS addresses currently use medium model code sequences,
1702 // which is the most useful form. Eventually support for small and
1703 // large models could be added if users need it, at the cost of
1704 // additional complexity.
1705 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1707 const GlobalValue *GV = GA->getGlobal();
1708 EVT PtrVT = getPointerTy();
1709 bool is64bit = Subtarget.isPPC64();
1710 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1711 PICLevel::Level picLevel = M->getPICLevel();
1713 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1715 if (Model == TLSModel::LocalExec) {
1716 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1717 PPCII::MO_TPREL_HA);
1718 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1719 PPCII::MO_TPREL_LO);
1720 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1721 is64bit ? MVT::i64 : MVT::i32);
1722 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1723 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1726 if (Model == TLSModel::InitialExec) {
1727 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1728 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1732 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1733 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1734 PtrVT, GOTReg, TGA);
1736 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1737 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1738 PtrVT, TGA, GOTPtr);
1739 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1742 if (Model == TLSModel::GeneralDynamic) {
1743 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1747 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1748 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1751 if (picLevel == PICLevel::Small)
1752 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1754 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1756 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1758 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1759 return CallResult.first;
1762 if (Model == TLSModel::LocalDynamic) {
1763 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1767 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1768 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1771 if (picLevel == PICLevel::Small)
1772 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1774 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1776 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1778 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1779 SDValue TLSAddr = CallResult.first;
1780 SDValue Chain = CallResult.second;
1781 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1782 Chain, TLSAddr, TGA);
1783 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1786 llvm_unreachable("Unknown TLS model!");
1789 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1790 SelectionDAG &DAG) const {
1791 EVT PtrVT = Op.getValueType();
1792 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1794 const GlobalValue *GV = GSDN->getGlobal();
1796 // 64-bit SVR4 ABI code is always position-independent.
1797 // The actual address of the GlobalValue is stored in the TOC.
1798 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1799 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1800 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1801 DAG.getRegister(PPC::X2, MVT::i64));
1804 unsigned MOHiFlag, MOLoFlag;
1806 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
1808 if (isPIC && Subtarget.isSVR4ABI()) {
1809 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1811 PPCII::MO_PIC_FLAG);
1812 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1813 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1817 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1819 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1821 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1823 // If the global reference is actually to a non-lazy-pointer, we have to do an
1824 // extra load to get the address of the global.
1825 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1826 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1827 false, false, false, 0);
1831 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1832 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1835 if (Op.getValueType() == MVT::v2i64) {
1836 // When the operands themselves are v2i64 values, we need to do something
1837 // special because VSX has no underlying comparison operations for these.
1838 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1839 // Equality can be handled by casting to the legal type for Altivec
1840 // comparisons, everything else needs to be expanded.
1841 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1842 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1843 DAG.getSetCC(dl, MVT::v4i32,
1844 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1845 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1852 // We handle most of these in the usual way.
1856 // If we're comparing for equality to zero, expose the fact that this is
1857 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1858 // fold the new nodes.
1859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1860 if (C->isNullValue() && CC == ISD::SETEQ) {
1861 EVT VT = Op.getOperand(0).getValueType();
1862 SDValue Zext = Op.getOperand(0);
1863 if (VT.bitsLT(MVT::i32)) {
1865 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1867 unsigned Log2b = Log2_32(VT.getSizeInBits());
1868 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1869 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1870 DAG.getConstant(Log2b, MVT::i32));
1871 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1873 // Leave comparisons against 0 and -1 alone for now, since they're usually
1874 // optimized. FIXME: revisit this when we can custom lower all setcc
1876 if (C->isAllOnesValue() || C->isNullValue())
1880 // If we have an integer seteq/setne, turn it into a compare against zero
1881 // by xor'ing the rhs with the lhs, which is faster than setting a
1882 // condition register, reading it back out, and masking the correct bit. The
1883 // normal approach here uses sub to do this instead of xor. Using xor exposes
1884 // the result to other bit-twiddling opportunities.
1885 EVT LHSVT = Op.getOperand(0).getValueType();
1886 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1887 EVT VT = Op.getValueType();
1888 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1890 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1895 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1896 const PPCSubtarget &Subtarget) const {
1897 SDNode *Node = Op.getNode();
1898 EVT VT = Node->getValueType(0);
1899 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1900 SDValue InChain = Node->getOperand(0);
1901 SDValue VAListPtr = Node->getOperand(1);
1902 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1905 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1908 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1909 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1910 false, false, false, 0);
1911 InChain = GprIndex.getValue(1);
1913 if (VT == MVT::i64) {
1914 // Check if GprIndex is even
1915 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1916 DAG.getConstant(1, MVT::i32));
1917 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1918 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1919 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1920 DAG.getConstant(1, MVT::i32));
1921 // Align GprIndex to be even if it isn't
1922 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1926 // fpr index is 1 byte after gpr
1927 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1928 DAG.getConstant(1, MVT::i32));
1931 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1932 FprPtr, MachinePointerInfo(SV), MVT::i8,
1933 false, false, false, 0);
1934 InChain = FprIndex.getValue(1);
1936 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1937 DAG.getConstant(8, MVT::i32));
1939 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1940 DAG.getConstant(4, MVT::i32));
1943 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1944 MachinePointerInfo(), false, false,
1946 InChain = OverflowArea.getValue(1);
1948 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1949 MachinePointerInfo(), false, false,
1951 InChain = RegSaveArea.getValue(1);
1953 // select overflow_area if index > 8
1954 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1955 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1957 // adjustment constant gpr_index * 4/8
1958 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1959 VT.isInteger() ? GprIndex : FprIndex,
1960 DAG.getConstant(VT.isInteger() ? 4 : 8,
1963 // OurReg = RegSaveArea + RegConstant
1964 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1967 // Floating types are 32 bytes into RegSaveArea
1968 if (VT.isFloatingPoint())
1969 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1970 DAG.getConstant(32, MVT::i32));
1972 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1973 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1974 VT.isInteger() ? GprIndex : FprIndex,
1975 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1978 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1979 VT.isInteger() ? VAListPtr : FprPtr,
1980 MachinePointerInfo(SV),
1981 MVT::i8, false, false, 0);
1983 // determine if we should load from reg_save_area or overflow_area
1984 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1986 // increase overflow_area by 4/8 if gpr/fpr > 8
1987 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1988 DAG.getConstant(VT.isInteger() ? 4 : 8,
1991 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1994 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1996 MachinePointerInfo(),
1997 MVT::i32, false, false, 0);
1999 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2000 false, false, false, 0);
2003 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2004 const PPCSubtarget &Subtarget) const {
2005 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2007 // We have to copy the entire va_list struct:
2008 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2009 return DAG.getMemcpy(Op.getOperand(0), Op,
2010 Op.getOperand(1), Op.getOperand(2),
2011 DAG.getConstant(12, MVT::i32), 8, false, true,
2012 MachinePointerInfo(), MachinePointerInfo());
2015 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2016 SelectionDAG &DAG) const {
2017 return Op.getOperand(0);
2020 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2021 SelectionDAG &DAG) const {
2022 SDValue Chain = Op.getOperand(0);
2023 SDValue Trmp = Op.getOperand(1); // trampoline
2024 SDValue FPtr = Op.getOperand(2); // nested function
2025 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2028 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2029 bool isPPC64 = (PtrVT == MVT::i64);
2031 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2034 TargetLowering::ArgListTy Args;
2035 TargetLowering::ArgListEntry Entry;
2037 Entry.Ty = IntPtrTy;
2038 Entry.Node = Trmp; Args.push_back(Entry);
2040 // TrampSize == (isPPC64 ? 48 : 40);
2041 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2042 isPPC64 ? MVT::i64 : MVT::i32);
2043 Args.push_back(Entry);
2045 Entry.Node = FPtr; Args.push_back(Entry);
2046 Entry.Node = Nest; Args.push_back(Entry);
2048 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2049 TargetLowering::CallLoweringInfo CLI(DAG);
2050 CLI.setDebugLoc(dl).setChain(Chain)
2051 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2052 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2053 std::move(Args), 0);
2055 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2056 return CallResult.second;
2059 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2060 const PPCSubtarget &Subtarget) const {
2061 MachineFunction &MF = DAG.getMachineFunction();
2062 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2066 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2067 // vastart just stores the address of the VarArgsFrameIndex slot into the
2068 // memory location argument.
2069 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2070 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2071 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2072 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2073 MachinePointerInfo(SV),
2077 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2078 // We suppose the given va_list is already allocated.
2081 // char gpr; /* index into the array of 8 GPRs
2082 // * stored in the register save area
2083 // * gpr=0 corresponds to r3,
2084 // * gpr=1 to r4, etc.
2086 // char fpr; /* index into the array of 8 FPRs
2087 // * stored in the register save area
2088 // * fpr=0 corresponds to f1,
2089 // * fpr=1 to f2, etc.
2091 // char *overflow_arg_area;
2092 // /* location on stack that holds
2093 // * the next overflow argument
2095 // char *reg_save_area;
2096 // /* where r3:r10 and f1:f8 (if saved)
2102 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2103 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2106 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2108 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2110 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2113 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2114 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2116 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2117 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2119 uint64_t FPROffset = 1;
2120 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2122 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2124 // Store first byte : number of int regs
2125 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2127 MachinePointerInfo(SV),
2128 MVT::i8, false, false, 0);
2129 uint64_t nextOffset = FPROffset;
2130 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2133 // Store second byte : number of float regs
2134 SDValue secondStore =
2135 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2136 MachinePointerInfo(SV, nextOffset), MVT::i8,
2138 nextOffset += StackOffset;
2139 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2141 // Store second word : arguments given on stack
2142 SDValue thirdStore =
2143 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2144 MachinePointerInfo(SV, nextOffset),
2146 nextOffset += FrameOffset;
2147 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2149 // Store third word : arguments given in registers
2150 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2151 MachinePointerInfo(SV, nextOffset),
2156 #include "PPCGenCallingConv.inc"
2158 // Function whose sole purpose is to kill compiler warnings
2159 // stemming from unused functions included from PPCGenCallingConv.inc.
2160 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2161 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2164 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2165 CCValAssign::LocInfo &LocInfo,
2166 ISD::ArgFlagsTy &ArgFlags,
2171 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2173 CCValAssign::LocInfo &LocInfo,
2174 ISD::ArgFlagsTy &ArgFlags,
2176 static const MCPhysReg ArgRegs[] = {
2177 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2178 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2180 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2182 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2184 // Skip one register if the first unallocated register has an even register
2185 // number and there are still argument registers available which have not been
2186 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2187 // need to skip a register if RegNum is odd.
2188 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2189 State.AllocateReg(ArgRegs[RegNum]);
2192 // Always return false here, as this function only makes sure that the first
2193 // unallocated register has an odd register number and does not actually
2194 // allocate a register for the current argument.
2198 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2200 CCValAssign::LocInfo &LocInfo,
2201 ISD::ArgFlagsTy &ArgFlags,
2203 static const MCPhysReg ArgRegs[] = {
2204 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2208 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2210 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2212 // If there is only one Floating-point register left we need to put both f64
2213 // values of a split ppc_fp128 value on the stack.
2214 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2215 State.AllocateReg(ArgRegs[RegNum]);
2218 // Always return false here, as this function only makes sure that the two f64
2219 // values a ppc_fp128 value is split into are both passed in registers or both
2220 // passed on the stack and does not actually allocate a register for the
2221 // current argument.
2225 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2227 static const MCPhysReg *GetFPR() {
2228 static const MCPhysReg FPR[] = {
2229 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2230 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2236 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2238 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2239 unsigned PtrByteSize) {
2240 unsigned ArgSize = ArgVT.getStoreSize();
2241 if (Flags.isByVal())
2242 ArgSize = Flags.getByValSize();
2244 // Round up to multiples of the pointer size, except for array members,
2245 // which are always packed.
2246 if (!Flags.isInConsecutiveRegs())
2247 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2252 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2254 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2255 ISD::ArgFlagsTy Flags,
2256 unsigned PtrByteSize) {
2257 unsigned Align = PtrByteSize;
2259 // Altivec parameters are padded to a 16 byte boundary.
2260 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2261 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2262 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2265 // ByVal parameters are aligned as requested.
2266 if (Flags.isByVal()) {
2267 unsigned BVAlign = Flags.getByValAlign();
2268 if (BVAlign > PtrByteSize) {
2269 if (BVAlign % PtrByteSize != 0)
2271 "ByVal alignment is not a multiple of the pointer size");
2277 // Array members are always packed to their original alignment.
2278 if (Flags.isInConsecutiveRegs()) {
2279 // If the array member was split into multiple registers, the first
2280 // needs to be aligned to the size of the full type. (Except for
2281 // ppcf128, which is only aligned as its f64 components.)
2282 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2283 Align = OrigVT.getStoreSize();
2285 Align = ArgVT.getStoreSize();
2291 /// CalculateStackSlotUsed - Return whether this argument will use its
2292 /// stack slot (instead of being passed in registers). ArgOffset,
2293 /// AvailableFPRs, and AvailableVRs must hold the current argument
2294 /// position, and will be updated to account for this argument.
2295 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2296 ISD::ArgFlagsTy Flags,
2297 unsigned PtrByteSize,
2298 unsigned LinkageSize,
2299 unsigned ParamAreaSize,
2300 unsigned &ArgOffset,
2301 unsigned &AvailableFPRs,
2302 unsigned &AvailableVRs) {
2303 bool UseMemory = false;
2305 // Respect alignment of argument on the stack.
2307 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2308 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2309 // If there's no space left in the argument save area, we must
2310 // use memory (this check also catches zero-sized arguments).
2311 if (ArgOffset >= LinkageSize + ParamAreaSize)
2314 // Allocate argument on the stack.
2315 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2316 if (Flags.isInConsecutiveRegsLast())
2317 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2318 // If we overran the argument save area, we must use memory
2319 // (this check catches arguments passed partially in memory)
2320 if (ArgOffset > LinkageSize + ParamAreaSize)
2323 // However, if the argument is actually passed in an FPR or a VR,
2324 // we don't use memory after all.
2325 if (!Flags.isByVal()) {
2326 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2327 if (AvailableFPRs > 0) {
2331 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2332 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2333 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2334 if (AvailableVRs > 0) {
2343 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2344 /// ensure minimum alignment required for target.
2345 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2346 unsigned NumBytes) {
2347 unsigned TargetAlign = Lowering->getStackAlignment();
2348 unsigned AlignMask = TargetAlign - 1;
2349 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2354 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2355 CallingConv::ID CallConv, bool isVarArg,
2356 const SmallVectorImpl<ISD::InputArg>
2358 SDLoc dl, SelectionDAG &DAG,
2359 SmallVectorImpl<SDValue> &InVals)
2361 if (Subtarget.isSVR4ABI()) {
2362 if (Subtarget.isPPC64())
2363 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2366 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2369 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2375 PPCTargetLowering::LowerFormalArguments_32SVR4(
2377 CallingConv::ID CallConv, bool isVarArg,
2378 const SmallVectorImpl<ISD::InputArg>
2380 SDLoc dl, SelectionDAG &DAG,
2381 SmallVectorImpl<SDValue> &InVals) const {
2383 // 32-bit SVR4 ABI Stack Frame Layout:
2384 // +-----------------------------------+
2385 // +--> | Back chain |
2386 // | +-----------------------------------+
2387 // | | Floating-point register save area |
2388 // | +-----------------------------------+
2389 // | | General register save area |
2390 // | +-----------------------------------+
2391 // | | CR save word |
2392 // | +-----------------------------------+
2393 // | | VRSAVE save word |
2394 // | +-----------------------------------+
2395 // | | Alignment padding |
2396 // | +-----------------------------------+
2397 // | | Vector register save area |
2398 // | +-----------------------------------+
2399 // | | Local variable space |
2400 // | +-----------------------------------+
2401 // | | Parameter list area |
2402 // | +-----------------------------------+
2403 // | | LR save word |
2404 // | +-----------------------------------+
2405 // SP--> +--- | Back chain |
2406 // +-----------------------------------+
2409 // System V Application Binary Interface PowerPC Processor Supplement
2410 // AltiVec Technology Programming Interface Manual
2412 MachineFunction &MF = DAG.getMachineFunction();
2413 MachineFrameInfo *MFI = MF.getFrameInfo();
2414 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2416 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2417 // Potential tail calls could cause overwriting of argument stack slots.
2418 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2419 (CallConv == CallingConv::Fast));
2420 unsigned PtrByteSize = 4;
2422 // Assign locations to all of the incoming arguments.
2423 SmallVector<CCValAssign, 16> ArgLocs;
2424 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2427 // Reserve space for the linkage area on the stack.
2428 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2429 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2431 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2434 CCValAssign &VA = ArgLocs[i];
2436 // Arguments stored in registers.
2437 if (VA.isRegLoc()) {
2438 const TargetRegisterClass *RC;
2439 EVT ValVT = VA.getValVT();
2441 switch (ValVT.getSimpleVT().SimpleTy) {
2443 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2446 RC = &PPC::GPRCRegClass;
2449 RC = &PPC::F4RCRegClass;
2452 if (Subtarget.hasVSX())
2453 RC = &PPC::VSFRCRegClass;
2455 RC = &PPC::F8RCRegClass;
2461 RC = &PPC::VRRCRegClass;
2465 RC = &PPC::VSHRCRegClass;
2469 // Transform the arguments stored in physical registers into virtual ones.
2470 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2471 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2472 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2474 if (ValVT == MVT::i1)
2475 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2477 InVals.push_back(ArgValue);
2479 // Argument stored in memory.
2480 assert(VA.isMemLoc());
2482 unsigned ArgSize = VA.getLocVT().getStoreSize();
2483 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2486 // Create load nodes to retrieve arguments from the stack.
2487 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2488 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2489 MachinePointerInfo(),
2490 false, false, false, 0));
2494 // Assign locations to all of the incoming aggregate by value arguments.
2495 // Aggregates passed by value are stored in the local variable space of the
2496 // caller's stack frame, right above the parameter list area.
2497 SmallVector<CCValAssign, 16> ByValArgLocs;
2498 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2499 ByValArgLocs, *DAG.getContext());
2501 // Reserve stack space for the allocations in CCInfo.
2502 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2504 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2506 // Area that is at least reserved in the caller of this function.
2507 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2508 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2510 // Set the size that is at least reserved in caller of this function. Tail
2511 // call optimized function's reserved stack space needs to be aligned so that
2512 // taking the difference between two stack areas will result in an aligned
2515 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2516 FuncInfo->setMinReservedArea(MinReservedArea);
2518 SmallVector<SDValue, 8> MemOps;
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start.
2523 static const MCPhysReg GPArgRegs[] = {
2524 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2525 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2527 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2529 static const MCPhysReg FPArgRegs[] = {
2530 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2533 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2534 if (DisablePPCFloatInVariadic)
2537 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2539 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2542 // Make room for NumGPArgRegs and NumFPArgRegs.
2543 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2544 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2546 FuncInfo->setVarArgsStackOffset(
2547 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2548 CCInfo.getNextStackOffset(), true));
2550 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2551 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2553 // The fixed integer arguments of a variadic function are stored to the
2554 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2555 // the result of va_next.
2556 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2557 // Get an existing live-in vreg, or add a new one.
2558 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2560 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2562 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2563 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2564 MachinePointerInfo(), false, false, 0);
2565 MemOps.push_back(Store);
2566 // Increment the address by four for the next argument to store
2567 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2568 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2571 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2573 // The double arguments are stored to the VarArgsFrameIndex
2575 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2576 // Get an existing live-in vreg, or add a new one.
2577 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2579 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2581 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2582 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2583 MachinePointerInfo(), false, false, 0);
2584 MemOps.push_back(Store);
2585 // Increment the address by eight for the next argument to store
2586 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2588 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2592 if (!MemOps.empty())
2593 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2598 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2599 // value to MVT::i64 and then truncate to the correct register size.
2601 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2602 SelectionDAG &DAG, SDValue ArgVal,
2605 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2606 DAG.getValueType(ObjectVT));
2607 else if (Flags.isZExt())
2608 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2609 DAG.getValueType(ObjectVT));
2611 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2615 PPCTargetLowering::LowerFormalArguments_64SVR4(
2617 CallingConv::ID CallConv, bool isVarArg,
2618 const SmallVectorImpl<ISD::InputArg>
2620 SDLoc dl, SelectionDAG &DAG,
2621 SmallVectorImpl<SDValue> &InVals) const {
2622 // TODO: add description of PPC stack frame format, or at least some docs.
2624 bool isELFv2ABI = Subtarget.isELFv2ABI();
2625 bool isLittleEndian = Subtarget.isLittleEndian();
2626 MachineFunction &MF = DAG.getMachineFunction();
2627 MachineFrameInfo *MFI = MF.getFrameInfo();
2628 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2630 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2631 "fastcc not supported on varargs functions");
2633 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2634 // Potential tail calls could cause overwriting of argument stack slots.
2635 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2636 (CallConv == CallingConv::Fast));
2637 unsigned PtrByteSize = 8;
2639 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2642 static const MCPhysReg GPR[] = {
2643 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2644 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2647 static const MCPhysReg *FPR = GetFPR();
2649 static const MCPhysReg VR[] = {
2650 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2651 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2653 static const MCPhysReg VSRH[] = {
2654 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2655 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2658 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2659 const unsigned Num_FPR_Regs = 13;
2660 const unsigned Num_VR_Regs = array_lengthof(VR);
2662 // Do a first pass over the arguments to determine whether the ABI
2663 // guarantees that our caller has allocated the parameter save area
2664 // on its stack frame. In the ELFv1 ABI, this is always the case;
2665 // in the ELFv2 ABI, it is true if this is a vararg function or if
2666 // any parameter is located in a stack slot.
2668 bool HasParameterArea = !isELFv2ABI || isVarArg;
2669 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2670 unsigned NumBytes = LinkageSize;
2671 unsigned AvailableFPRs = Num_FPR_Regs;
2672 unsigned AvailableVRs = Num_VR_Regs;
2673 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2674 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2675 PtrByteSize, LinkageSize, ParamAreaSize,
2676 NumBytes, AvailableFPRs, AvailableVRs))
2677 HasParameterArea = true;
2679 // Add DAG nodes to load the arguments or copy them out of registers. On
2680 // entry to a function on PPC, the arguments start after the linkage area,
2681 // although the first ones are often in registers.
2683 unsigned ArgOffset = LinkageSize;
2684 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2685 SmallVector<SDValue, 8> MemOps;
2686 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2687 unsigned CurArgIdx = 0;
2688 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2690 bool needsLoad = false;
2691 EVT ObjectVT = Ins[ArgNo].VT;
2692 EVT OrigVT = Ins[ArgNo].ArgVT;
2693 unsigned ObjSize = ObjectVT.getStoreSize();
2694 unsigned ArgSize = ObjSize;
2695 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2696 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2697 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2699 // We re-align the argument offset for each argument, except when using the
2700 // fast calling convention, when we need to make sure we do that only when
2701 // we'll actually use a stack slot.
2702 unsigned CurArgOffset, Align;
2703 auto ComputeArgOffset = [&]() {
2704 /* Respect alignment of argument on the stack. */
2705 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2706 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2707 CurArgOffset = ArgOffset;
2710 if (CallConv != CallingConv::Fast) {
2713 /* Compute GPR index associated with argument offset. */
2714 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2715 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2718 // FIXME the codegen can be much improved in some cases.
2719 // We do not have to keep everything in memory.
2720 if (Flags.isByVal()) {
2721 if (CallConv == CallingConv::Fast)
2724 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2725 ObjSize = Flags.getByValSize();
2726 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2727 // Empty aggregate parameters do not take up registers. Examples:
2731 // etc. However, we have to provide a place-holder in InVals, so
2732 // pretend we have an 8-byte item at the current address for that
2735 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2736 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2737 InVals.push_back(FIN);
2741 // Create a stack object covering all stack doublewords occupied
2742 // by the argument. If the argument is (fully or partially) on
2743 // the stack, or if the argument is fully in registers but the
2744 // caller has allocated the parameter save anyway, we can refer
2745 // directly to the caller's stack frame. Otherwise, create a
2746 // local copy in our own frame.
2748 if (HasParameterArea ||
2749 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2750 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2752 FI = MFI->CreateStackObject(ArgSize, Align, false);
2753 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2755 // Handle aggregates smaller than 8 bytes.
2756 if (ObjSize < PtrByteSize) {
2757 // The value of the object is its address, which differs from the
2758 // address of the enclosing doubleword on big-endian systems.
2760 if (!isLittleEndian) {
2761 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2762 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2764 InVals.push_back(Arg);
2766 if (GPR_idx != Num_GPR_Regs) {
2767 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2768 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2771 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2772 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2773 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2774 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2775 MachinePointerInfo(FuncArg),
2776 ObjType, false, false, 0);
2778 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2779 // store the whole register as-is to the parameter save area
2781 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2782 MachinePointerInfo(FuncArg),
2786 MemOps.push_back(Store);
2788 // Whether we copied from a register or not, advance the offset
2789 // into the parameter save area by a full doubleword.
2790 ArgOffset += PtrByteSize;
2794 // The value of the object is its address, which is the address of
2795 // its first stack doubleword.
2796 InVals.push_back(FIN);
2798 // Store whatever pieces of the object are in registers to memory.
2799 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2800 if (GPR_idx == Num_GPR_Regs)
2803 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2804 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2807 SDValue Off = DAG.getConstant(j, PtrVT);
2808 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2810 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2811 MachinePointerInfo(FuncArg, j),
2813 MemOps.push_back(Store);
2816 ArgOffset += ArgSize;
2820 switch (ObjectVT.getSimpleVT().SimpleTy) {
2821 default: llvm_unreachable("Unhandled argument type!");
2825 // These can be scalar arguments or elements of an integer array type
2826 // passed directly. Clang may use those instead of "byval" aggregate
2827 // types to avoid forcing arguments to memory unnecessarily.
2828 if (GPR_idx != Num_GPR_Regs) {
2829 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2830 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2832 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2833 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2834 // value to MVT::i64 and then truncate to the correct register size.
2835 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2837 if (CallConv == CallingConv::Fast)
2841 ArgSize = PtrByteSize;
2843 if (CallConv != CallingConv::Fast || needsLoad)
2849 // These can be scalar arguments or elements of a float array type
2850 // passed directly. The latter are used to implement ELFv2 homogenous
2851 // float aggregates.
2852 if (FPR_idx != Num_FPR_Regs) {
2855 if (ObjectVT == MVT::f32)
2856 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2858 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
2859 ? &PPC::VSFRCRegClass
2860 : &PPC::F8RCRegClass);
2862 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2864 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2865 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
2866 // once we support fp <-> gpr moves.
2868 // This can only ever happen in the presence of f32 array types,
2869 // since otherwise we never run out of FPRs before running out
2871 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2872 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2874 if (ObjectVT == MVT::f32) {
2875 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2876 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2877 DAG.getConstant(32, MVT::i32));
2878 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2881 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2883 if (CallConv == CallingConv::Fast)
2889 // When passing an array of floats, the array occupies consecutive
2890 // space in the argument area; only round up to the next doubleword
2891 // at the end of the array. Otherwise, each float takes 8 bytes.
2892 if (CallConv != CallingConv::Fast || needsLoad) {
2893 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2894 ArgOffset += ArgSize;
2895 if (Flags.isInConsecutiveRegsLast())
2896 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2905 // These can be scalar arguments or elements of a vector array type
2906 // passed directly. The latter are used to implement ELFv2 homogenous
2907 // vector aggregates.
2908 if (VR_idx != Num_VR_Regs) {
2909 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2910 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2911 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2912 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2915 if (CallConv == CallingConv::Fast)
2920 if (CallConv != CallingConv::Fast || needsLoad)
2925 // We need to load the argument to a virtual register if we determined
2926 // above that we ran out of physical registers of the appropriate type.
2928 if (ObjSize < ArgSize && !isLittleEndian)
2929 CurArgOffset += ArgSize - ObjSize;
2930 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2931 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2932 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2933 false, false, false, 0);
2936 InVals.push_back(ArgVal);
2939 // Area that is at least reserved in the caller of this function.
2940 unsigned MinReservedArea;
2941 if (HasParameterArea)
2942 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2944 MinReservedArea = LinkageSize;
2946 // Set the size that is at least reserved in caller of this function. Tail
2947 // call optimized functions' reserved stack space needs to be aligned so that
2948 // taking the difference between two stack areas will result in an aligned
2951 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2952 FuncInfo->setMinReservedArea(MinReservedArea);
2954 // If the function takes variable number of arguments, make a frame index for
2955 // the start of the first vararg value... for expansion of llvm.va_start.
2957 int Depth = ArgOffset;
2959 FuncInfo->setVarArgsFrameIndex(
2960 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2961 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2963 // If this function is vararg, store any remaining integer argument regs
2964 // to their spots on the stack so that they may be loaded by deferencing the
2965 // result of va_next.
2966 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2967 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2968 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2970 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2971 MachinePointerInfo(), false, false, 0);
2972 MemOps.push_back(Store);
2973 // Increment the address by four for the next argument to store
2974 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2975 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2979 if (!MemOps.empty())
2980 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2986 PPCTargetLowering::LowerFormalArguments_Darwin(
2988 CallingConv::ID CallConv, bool isVarArg,
2989 const SmallVectorImpl<ISD::InputArg>
2991 SDLoc dl, SelectionDAG &DAG,
2992 SmallVectorImpl<SDValue> &InVals) const {
2993 // TODO: add description of PPC stack frame format, or at least some docs.
2995 MachineFunction &MF = DAG.getMachineFunction();
2996 MachineFrameInfo *MFI = MF.getFrameInfo();
2997 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2999 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3000 bool isPPC64 = PtrVT == MVT::i64;
3001 // Potential tail calls could cause overwriting of argument stack slots.
3002 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3003 (CallConv == CallingConv::Fast));
3004 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3006 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
3008 unsigned ArgOffset = LinkageSize;
3009 // Area that is at least reserved in caller of this function.
3010 unsigned MinReservedArea = ArgOffset;
3012 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3013 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3014 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3016 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3017 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3018 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3021 static const MCPhysReg *FPR = GetFPR();
3023 static const MCPhysReg VR[] = {
3024 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3025 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3028 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3029 const unsigned Num_FPR_Regs = 13;
3030 const unsigned Num_VR_Regs = array_lengthof( VR);
3032 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3034 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3036 // In 32-bit non-varargs functions, the stack space for vectors is after the
3037 // stack space for non-vectors. We do not use this space unless we have
3038 // too many vectors to fit in registers, something that only occurs in
3039 // constructed examples:), but we have to walk the arglist to figure
3040 // that out...for the pathological case, compute VecArgOffset as the
3041 // start of the vector parameter area. Computing VecArgOffset is the
3042 // entire point of the following loop.
3043 unsigned VecArgOffset = ArgOffset;
3044 if (!isVarArg && !isPPC64) {
3045 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3047 EVT ObjectVT = Ins[ArgNo].VT;
3048 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3050 if (Flags.isByVal()) {
3051 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3052 unsigned ObjSize = Flags.getByValSize();
3054 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3055 VecArgOffset += ArgSize;
3059 switch(ObjectVT.getSimpleVT().SimpleTy) {
3060 default: llvm_unreachable("Unhandled argument type!");
3066 case MVT::i64: // PPC64
3068 // FIXME: We are guaranteed to be !isPPC64 at this point.
3069 // Does MVT::i64 apply?
3076 // Nothing to do, we're only looking at Nonvector args here.
3081 // We've found where the vector parameter area in memory is. Skip the
3082 // first 12 parameters; these don't use that memory.
3083 VecArgOffset = ((VecArgOffset+15)/16)*16;
3084 VecArgOffset += 12*16;
3086 // Add DAG nodes to load the arguments or copy them out of registers. On
3087 // entry to a function on PPC, the arguments start after the linkage area,
3088 // although the first ones are often in registers.
3090 SmallVector<SDValue, 8> MemOps;
3091 unsigned nAltivecParamsAtEnd = 0;
3092 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3093 unsigned CurArgIdx = 0;
3094 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3096 bool needsLoad = false;
3097 EVT ObjectVT = Ins[ArgNo].VT;
3098 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3099 unsigned ArgSize = ObjSize;
3100 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3101 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3102 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3104 unsigned CurArgOffset = ArgOffset;
3106 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3107 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3108 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3109 if (isVarArg || isPPC64) {
3110 MinReservedArea = ((MinReservedArea+15)/16)*16;
3111 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3114 } else nAltivecParamsAtEnd++;
3116 // Calculate min reserved area.
3117 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3121 // FIXME the codegen can be much improved in some cases.
3122 // We do not have to keep everything in memory.
3123 if (Flags.isByVal()) {
3124 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3125 ObjSize = Flags.getByValSize();
3126 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3127 // Objects of size 1 and 2 are right justified, everything else is
3128 // left justified. This means the memory address is adjusted forwards.
3129 if (ObjSize==1 || ObjSize==2) {
3130 CurArgOffset = CurArgOffset + (4 - ObjSize);
3132 // The value of the object is its address.
3133 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3134 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3135 InVals.push_back(FIN);
3136 if (ObjSize==1 || ObjSize==2) {
3137 if (GPR_idx != Num_GPR_Regs) {
3140 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3142 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3143 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3144 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3145 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3146 MachinePointerInfo(FuncArg),
3147 ObjType, false, false, 0);
3148 MemOps.push_back(Store);
3152 ArgOffset += PtrByteSize;
3156 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3157 // Store whatever pieces of the object are in registers
3158 // to memory. ArgOffset will be the address of the beginning
3160 if (GPR_idx != Num_GPR_Regs) {
3163 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3165 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3166 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3167 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3168 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3169 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3170 MachinePointerInfo(FuncArg, j),
3172 MemOps.push_back(Store);
3174 ArgOffset += PtrByteSize;
3176 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3183 switch (ObjectVT.getSimpleVT().SimpleTy) {
3184 default: llvm_unreachable("Unhandled argument type!");
3188 if (GPR_idx != Num_GPR_Regs) {
3189 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3190 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3192 if (ObjectVT == MVT::i1)
3193 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3198 ArgSize = PtrByteSize;
3200 // All int arguments reserve stack space in the Darwin ABI.
3201 ArgOffset += PtrByteSize;
3205 case MVT::i64: // PPC64
3206 if (GPR_idx != Num_GPR_Regs) {
3207 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3208 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3210 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3211 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3212 // value to MVT::i64 and then truncate to the correct register size.
3213 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3218 ArgSize = PtrByteSize;
3220 // All int arguments reserve stack space in the Darwin ABI.
3226 // Every 4 bytes of argument space consumes one of the GPRs available for
3227 // argument passing.
3228 if (GPR_idx != Num_GPR_Regs) {
3230 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3233 if (FPR_idx != Num_FPR_Regs) {
3236 if (ObjectVT == MVT::f32)
3237 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3239 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3241 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3247 // All FP arguments reserve stack space in the Darwin ABI.
3248 ArgOffset += isPPC64 ? 8 : ObjSize;
3254 // Note that vector arguments in registers don't reserve stack space,
3255 // except in varargs functions.
3256 if (VR_idx != Num_VR_Regs) {
3257 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3258 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3260 while ((ArgOffset % 16) != 0) {
3261 ArgOffset += PtrByteSize;
3262 if (GPR_idx != Num_GPR_Regs)
3266 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3270 if (!isVarArg && !isPPC64) {
3271 // Vectors go after all the nonvectors.
3272 CurArgOffset = VecArgOffset;
3275 // Vectors are aligned.
3276 ArgOffset = ((ArgOffset+15)/16)*16;
3277 CurArgOffset = ArgOffset;
3285 // We need to load the argument to a virtual register if we determined above
3286 // that we ran out of physical registers of the appropriate type.
3288 int FI = MFI->CreateFixedObject(ObjSize,
3289 CurArgOffset + (ArgSize - ObjSize),
3291 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3292 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3293 false, false, false, 0);
3296 InVals.push_back(ArgVal);
3299 // Allow for Altivec parameters at the end, if needed.
3300 if (nAltivecParamsAtEnd) {
3301 MinReservedArea = ((MinReservedArea+15)/16)*16;
3302 MinReservedArea += 16*nAltivecParamsAtEnd;
3305 // Area that is at least reserved in the caller of this function.
3306 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3308 // Set the size that is at least reserved in caller of this function. Tail
3309 // call optimized functions' reserved stack space needs to be aligned so that
3310 // taking the difference between two stack areas will result in an aligned
3313 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3314 FuncInfo->setMinReservedArea(MinReservedArea);
3316 // If the function takes variable number of arguments, make a frame index for
3317 // the start of the first vararg value... for expansion of llvm.va_start.
3319 int Depth = ArgOffset;
3321 FuncInfo->setVarArgsFrameIndex(
3322 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3324 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3326 // If this function is vararg, store any remaining integer argument regs
3327 // to their spots on the stack so that they may be loaded by deferencing the
3328 // result of va_next.
3329 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3333 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3335 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3337 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3338 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3339 MachinePointerInfo(), false, false, 0);
3340 MemOps.push_back(Store);
3341 // Increment the address by four for the next argument to store
3342 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3343 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3347 if (!MemOps.empty())
3348 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3353 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3354 /// adjusted to accommodate the arguments for the tailcall.
3355 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3356 unsigned ParamSize) {
3358 if (!isTailCall) return 0;
3360 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3361 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3362 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3363 // Remember only if the new adjustement is bigger.
3364 if (SPDiff < FI->getTailCallSPDelta())
3365 FI->setTailCallSPDelta(SPDiff);
3370 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3371 /// for tail call optimization. Targets which want to do tail call
3372 /// optimization should implement this function.
3374 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3375 CallingConv::ID CalleeCC,
3377 const SmallVectorImpl<ISD::InputArg> &Ins,
3378 SelectionDAG& DAG) const {
3379 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3382 // Variable argument functions are not supported.
3386 MachineFunction &MF = DAG.getMachineFunction();
3387 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3388 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3389 // Functions containing by val parameters are not supported.
3390 for (unsigned i = 0; i != Ins.size(); i++) {
3391 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3392 if (Flags.isByVal()) return false;
3395 // Non-PIC/GOT tail calls are supported.
3396 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3399 // At the moment we can only do local tail calls (in same module, hidden
3400 // or protected) if we are generating PIC.
3401 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3402 return G->getGlobal()->hasHiddenVisibility()
3403 || G->getGlobal()->hasProtectedVisibility();
3409 /// isCallCompatibleAddress - Return the immediate to use if the specified
3410 /// 32-bit value is representable in the immediate field of a BxA instruction.
3411 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3412 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3413 if (!C) return nullptr;
3415 int Addr = C->getZExtValue();
3416 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3417 SignExtend32<26>(Addr) != Addr)
3418 return nullptr; // Top 6 bits have to be sext of immediate.
3420 return DAG.getConstant((int)C->getZExtValue() >> 2,
3421 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3426 struct TailCallArgumentInfo {
3431 TailCallArgumentInfo() : FrameIdx(0) {}
3436 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3438 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3440 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3441 SmallVectorImpl<SDValue> &MemOpChains,
3443 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3444 SDValue Arg = TailCallArgs[i].Arg;
3445 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3446 int FI = TailCallArgs[i].FrameIdx;
3447 // Store relative to framepointer.
3448 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3449 MachinePointerInfo::getFixedStack(FI),
3454 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3455 /// the appropriate stack slot for the tail call optimized function call.
3456 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3457 MachineFunction &MF,
3466 // Calculate the new stack slot for the return address.
3467 int SlotSize = isPPC64 ? 8 : 4;
3468 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3470 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3471 NewRetAddrLoc, true);
3472 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3473 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3474 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3475 MachinePointerInfo::getFixedStack(NewRetAddr),
3478 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3479 // slot as the FP is never overwritten.
3482 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3483 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3485 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3486 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3487 MachinePointerInfo::getFixedStack(NewFPIdx),
3494 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3495 /// the position of the argument.
3497 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3498 SDValue Arg, int SPDiff, unsigned ArgOffset,
3499 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3500 int Offset = ArgOffset + SPDiff;
3501 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3502 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3503 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3504 SDValue FIN = DAG.getFrameIndex(FI, VT);
3505 TailCallArgumentInfo Info;
3507 Info.FrameIdxOp = FIN;
3509 TailCallArguments.push_back(Info);
3512 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3513 /// stack slot. Returns the chain as result and the loaded frame pointers in
3514 /// LROpOut/FPOpout. Used when tail calling.
3515 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3523 // Load the LR and FP stack slot for later adjusting.
3524 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3525 LROpOut = getReturnAddrFrameIndex(DAG);
3526 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3527 false, false, false, 0);
3528 Chain = SDValue(LROpOut.getNode(), 1);
3530 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3531 // slot as the FP is never overwritten.
3533 FPOpOut = getFramePointerFrameIndex(DAG);
3534 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3535 false, false, false, 0);
3536 Chain = SDValue(FPOpOut.getNode(), 1);
3542 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3543 /// by "Src" to address "Dst" of size "Size". Alignment information is
3544 /// specified by the specific parameter attribute. The copy will be passed as
3545 /// a byval function parameter.
3546 /// Sometimes what we are copying is the end of a larger object, the part that
3547 /// does not fit in registers.
3549 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3550 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3552 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3553 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3554 false, false, MachinePointerInfo(),
3555 MachinePointerInfo());
3558 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3561 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3562 SDValue Arg, SDValue PtrOff, int SPDiff,
3563 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3564 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3565 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3567 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3572 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3574 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3575 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3576 DAG.getConstant(ArgOffset, PtrVT));
3578 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3579 MachinePointerInfo(), false, false, 0));
3580 // Calculate and remember argument location.
3581 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3586 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3587 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3588 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3589 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3590 MachineFunction &MF = DAG.getMachineFunction();
3592 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3593 // might overwrite each other in case of tail call optimization.
3594 SmallVector<SDValue, 8> MemOpChains2;
3595 // Do not flag preceding copytoreg stuff together with the following stuff.
3597 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3599 if (!MemOpChains2.empty())
3600 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3602 // Store the return address to the appropriate stack slot.
3603 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3604 isPPC64, isDarwinABI, dl);
3606 // Emit callseq_end just before tailcall node.
3607 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3608 DAG.getIntPtrConstant(0, true), InFlag, dl);
3609 InFlag = Chain.getValue(1);
3612 // Is this global address that of a function that can be called by name? (as
3613 // opposed to something that must hold a descriptor for an indirect call).
3614 static bool isFunctionGlobalAddress(SDValue Callee) {
3615 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3616 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3617 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3620 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3627 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3628 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3629 bool isTailCall, bool IsPatchPoint,
3630 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3631 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3632 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3634 bool isPPC64 = Subtarget.isPPC64();
3635 bool isSVR4ABI = Subtarget.isSVR4ABI();
3636 bool isELFv2ABI = Subtarget.isELFv2ABI();
3638 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3639 NodeTys.push_back(MVT::Other); // Returns a chain
3640 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3642 unsigned CallOpc = PPCISD::CALL;
3644 bool needIndirectCall = true;
3645 if (!isSVR4ABI || !isPPC64)
3646 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3647 // If this is an absolute destination address, use the munged value.
3648 Callee = SDValue(Dest, 0);
3649 needIndirectCall = false;
3652 if (isFunctionGlobalAddress(Callee)) {
3653 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3654 // A call to a TLS address is actually an indirect call to a
3655 // thread-specific pointer.
3656 unsigned OpFlags = 0;
3657 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3658 (Subtarget.getTargetTriple().isMacOSX() &&
3659 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3660 (G->getGlobal()->isDeclaration() ||
3661 G->getGlobal()->isWeakForLinker())) ||
3662 (Subtarget.isTargetELF() && !isPPC64 &&
3663 !G->getGlobal()->hasLocalLinkage() &&
3664 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3665 // PC-relative references to external symbols should go through $stub,
3666 // unless we're building with the leopard linker or later, which
3667 // automatically synthesizes these stubs.
3668 OpFlags = PPCII::MO_PLT_OR_STUB;
3671 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3672 // every direct call is) turn it into a TargetGlobalAddress /
3673 // TargetExternalSymbol node so that legalize doesn't hack it.
3674 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3675 Callee.getValueType(), 0, OpFlags);
3676 needIndirectCall = false;
3679 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3680 unsigned char OpFlags = 0;
3682 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3683 (Subtarget.getTargetTriple().isMacOSX() &&
3684 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3685 (Subtarget.isTargetELF() && !isPPC64 &&
3686 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3687 // PC-relative references to external symbols should go through $stub,
3688 // unless we're building with the leopard linker or later, which
3689 // automatically synthesizes these stubs.
3690 OpFlags = PPCII::MO_PLT_OR_STUB;
3693 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3695 needIndirectCall = false;
3699 // We'll form an invalid direct call when lowering a patchpoint; the full
3700 // sequence for an indirect call is complicated, and many of the
3701 // instructions introduced might have side effects (and, thus, can't be
3702 // removed later). The call itself will be removed as soon as the
3703 // argument/return lowering is complete, so the fact that it has the wrong
3704 // kind of operands should not really matter.
3705 needIndirectCall = false;
3708 if (needIndirectCall) {
3709 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3710 // to do the call, we can't use PPCISD::CALL.
3711 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3713 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3714 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3715 // entry point, but to the function descriptor (the function entry point
3716 // address is part of the function descriptor though).
3717 // The function descriptor is a three doubleword structure with the
3718 // following fields: function entry point, TOC base address and
3719 // environment pointer.
3720 // Thus for a call through a function pointer, the following actions need
3722 // 1. Save the TOC of the caller in the TOC save area of its stack
3723 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3724 // 2. Load the address of the function entry point from the function
3726 // 3. Load the TOC of the callee from the function descriptor into r2.
3727 // 4. Load the environment pointer from the function descriptor into
3729 // 5. Branch to the function entry point address.
3730 // 6. On return of the callee, the TOC of the caller needs to be
3731 // restored (this is done in FinishCall()).
3733 // The loads are scheduled at the beginning of the call sequence, and the
3734 // register copies are flagged together to ensure that no other
3735 // operations can be scheduled in between. E.g. without flagging the
3736 // copies together, a TOC access in the caller could be scheduled between
3737 // the assignment of the callee TOC and the branch to the callee, which
3738 // results in the TOC access going through the TOC of the callee instead
3739 // of going through the TOC of the caller, which leads to incorrect code.
3741 // Load the address of the function entry point from the function
3743 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3744 if (LDChain.getValueType() == MVT::Glue)
3745 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3747 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3749 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3750 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3751 false, false, LoadsInv, 8);
3753 // Load environment pointer into r11.
3754 SDValue PtrOff = DAG.getIntPtrConstant(16);
3755 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3756 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3757 MPI.getWithOffset(16), false, false,
3760 SDValue TOCOff = DAG.getIntPtrConstant(8);
3761 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3762 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3763 MPI.getWithOffset(8), false, false,
3766 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3768 Chain = TOCVal.getValue(0);
3769 InFlag = TOCVal.getValue(1);
3771 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3774 Chain = EnvVal.getValue(0);
3775 InFlag = EnvVal.getValue(1);
3777 MTCTROps[0] = Chain;
3778 MTCTROps[1] = LoadFuncPtr;
3779 MTCTROps[2] = InFlag;
3782 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3783 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3784 InFlag = Chain.getValue(1);
3787 NodeTys.push_back(MVT::Other);
3788 NodeTys.push_back(MVT::Glue);
3789 Ops.push_back(Chain);
3790 CallOpc = PPCISD::BCTRL;
3791 Callee.setNode(nullptr);
3792 // Add use of X11 (holding environment pointer)
3793 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3794 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3795 // Add CTR register as callee so a bctr can be emitted later.
3797 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3800 // If this is a direct call, pass the chain and the callee.
3801 if (Callee.getNode()) {
3802 Ops.push_back(Chain);
3803 Ops.push_back(Callee);
3805 // If this is a call to __tls_get_addr, find the symbol whose address
3806 // is to be taken and add it to the list. This will be used to
3807 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3808 // We find the symbol by walking the chain to the CopyFromReg, walking
3809 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3810 // pulling the symbol from that node.
3811 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3812 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3813 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3814 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3815 SDValue TGTAddr = AddI->getOperand(1);
3816 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3817 "Didn't find target global TLS address where we expected one");
3818 Ops.push_back(TGTAddr);
3819 CallOpc = PPCISD::CALL_TLS;
3822 // If this is a tail call add stack pointer delta.
3824 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3826 // Add argument registers to the end of the list so that they are known live
3828 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3829 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3830 RegsToPass[i].second.getValueType()));
3832 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
3834 if (isSVR4ABI && isPPC64 && !IsPatchPoint)
3835 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3841 bool isLocalCall(const SDValue &Callee)
3843 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3844 return !G->getGlobal()->isDeclaration() &&
3845 !G->getGlobal()->isWeakForLinker();
3850 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3851 CallingConv::ID CallConv, bool isVarArg,
3852 const SmallVectorImpl<ISD::InputArg> &Ins,
3853 SDLoc dl, SelectionDAG &DAG,
3854 SmallVectorImpl<SDValue> &InVals) const {
3856 SmallVector<CCValAssign, 16> RVLocs;
3857 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3859 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3861 // Copy all of the result registers out of their specified physreg.
3862 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3863 CCValAssign &VA = RVLocs[i];
3864 assert(VA.isRegLoc() && "Can only return in registers!");
3866 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3867 VA.getLocReg(), VA.getLocVT(), InFlag);
3868 Chain = Val.getValue(1);
3869 InFlag = Val.getValue(2);
3871 switch (VA.getLocInfo()) {
3872 default: llvm_unreachable("Unknown loc info!");
3873 case CCValAssign::Full: break;
3874 case CCValAssign::AExt:
3875 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3877 case CCValAssign::ZExt:
3878 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3879 DAG.getValueType(VA.getValVT()));
3880 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3882 case CCValAssign::SExt:
3883 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3884 DAG.getValueType(VA.getValVT()));
3885 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3889 InVals.push_back(Val);
3896 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3897 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3899 SmallVector<std::pair<unsigned, SDValue>, 8>
3901 SDValue InFlag, SDValue Chain,
3902 SDValue CallSeqStart, SDValue &Callee,
3903 int SPDiff, unsigned NumBytes,
3904 const SmallVectorImpl<ISD::InputArg> &Ins,
3905 SmallVectorImpl<SDValue> &InVals,
3906 ImmutableCallSite *CS) const {
3908 bool isELFv2ABI = Subtarget.isELFv2ABI();
3909 std::vector<EVT> NodeTys;
3910 SmallVector<SDValue, 8> Ops;
3911 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3912 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3913 Ops, NodeTys, CS, Subtarget);
3915 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3916 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3917 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3919 // When performing tail call optimization the callee pops its arguments off
3920 // the stack. Account for this here so these bytes can be pushed back on in
3921 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3922 int BytesCalleePops =
3923 (CallConv == CallingConv::Fast &&
3924 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3926 // Add a register mask operand representing the call-preserved registers.
3927 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3928 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3929 assert(Mask && "Missing call preserved mask for calling convention");
3930 Ops.push_back(DAG.getRegisterMask(Mask));
3932 if (InFlag.getNode())
3933 Ops.push_back(InFlag);
3937 assert(((Callee.getOpcode() == ISD::Register &&
3938 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3939 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3940 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3941 isa<ConstantSDNode>(Callee)) &&
3942 "Expecting an global address, external symbol, absolute value or register");
3944 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3947 // Add a NOP immediately after the branch instruction when using the 64-bit
3948 // SVR4 ABI. At link time, if caller and callee are in a different module and
3949 // thus have a different TOC, the call will be replaced with a call to a stub
3950 // function which saves the current TOC, loads the TOC of the callee and
3951 // branches to the callee. The NOP will be replaced with a load instruction
3952 // which restores the TOC of the caller from the TOC save slot of the current
3953 // stack frame. If caller and callee belong to the same module (and have the
3954 // same TOC), the NOP will remain unchanged.
3956 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3958 if (CallOpc == PPCISD::BCTRL) {
3959 // This is a call through a function pointer.
3960 // Restore the caller TOC from the save area into R2.
3961 // See PrepareCall() for more information about calls through function
3962 // pointers in the 64-bit SVR4 ABI.
3963 // We are using a target-specific load with r2 hard coded, because the
3964 // result of a target-independent load would never go directly into r2,
3965 // since r2 is a reserved register (which prevents the register allocator
3966 // from allocating it), resulting in an additional register being
3967 // allocated and an unnecessary move instruction being generated.
3968 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3970 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3971 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3972 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3973 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3974 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3976 // The address needs to go after the chain input but before the flag (or
3977 // any other variadic arguments).
3978 Ops.insert(std::next(Ops.begin()), AddTOC);
3979 } else if ((CallOpc == PPCISD::CALL) &&
3980 (!isLocalCall(Callee) ||
3981 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3982 // Otherwise insert NOP for non-local calls.
3983 CallOpc = PPCISD::CALL_NOP;
3984 } else if (CallOpc == PPCISD::CALL_TLS)
3985 // For 64-bit SVR4, TLS calls are always non-local.
3986 CallOpc = PPCISD::CALL_NOP_TLS;
3989 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3990 InFlag = Chain.getValue(1);
3992 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3993 DAG.getIntPtrConstant(BytesCalleePops, true),
3996 InFlag = Chain.getValue(1);
3998 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3999 Ins, dl, DAG, InVals);
4003 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4004 SmallVectorImpl<SDValue> &InVals) const {
4005 SelectionDAG &DAG = CLI.DAG;
4007 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4008 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4009 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4010 SDValue Chain = CLI.Chain;
4011 SDValue Callee = CLI.Callee;
4012 bool &isTailCall = CLI.IsTailCall;
4013 CallingConv::ID CallConv = CLI.CallConv;
4014 bool isVarArg = CLI.IsVarArg;
4015 bool IsPatchPoint = CLI.IsPatchPoint;
4016 ImmutableCallSite *CS = CLI.CS;
4019 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4022 if (!isTailCall && CS && CS->isMustTailCall())
4023 report_fatal_error("failed to perform tail call elimination on a call "
4024 "site marked musttail");
4026 if (Subtarget.isSVR4ABI()) {
4027 if (Subtarget.isPPC64())
4028 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4029 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4030 dl, DAG, InVals, CS);
4032 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4033 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4034 dl, DAG, InVals, CS);
4037 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4038 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4039 dl, DAG, InVals, CS);
4043 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4044 CallingConv::ID CallConv, bool isVarArg,
4045 bool isTailCall, bool IsPatchPoint,
4046 const SmallVectorImpl<ISD::OutputArg> &Outs,
4047 const SmallVectorImpl<SDValue> &OutVals,
4048 const SmallVectorImpl<ISD::InputArg> &Ins,
4049 SDLoc dl, SelectionDAG &DAG,
4050 SmallVectorImpl<SDValue> &InVals,
4051 ImmutableCallSite *CS) const {
4052 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4053 // of the 32-bit SVR4 ABI stack frame layout.
4055 assert((CallConv == CallingConv::C ||
4056 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4058 unsigned PtrByteSize = 4;
4060 MachineFunction &MF = DAG.getMachineFunction();
4062 // Mark this function as potentially containing a function that contains a
4063 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4064 // and restoring the callers stack pointer in this functions epilog. This is
4065 // done because by tail calling the called function might overwrite the value
4066 // in this function's (MF) stack pointer stack slot 0(SP).
4067 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4068 CallConv == CallingConv::Fast)
4069 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4071 // Count how many bytes are to be pushed on the stack, including the linkage
4072 // area, parameter list area and the part of the local variable space which
4073 // contains copies of aggregates which are passed by value.
4075 // Assign locations to all of the outgoing arguments.
4076 SmallVector<CCValAssign, 16> ArgLocs;
4077 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4080 // Reserve space for the linkage area on the stack.
4081 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4085 // Handle fixed and variable vector arguments differently.
4086 // Fixed vector arguments go into registers as long as registers are
4087 // available. Variable vector arguments always go into memory.
4088 unsigned NumArgs = Outs.size();
4090 for (unsigned i = 0; i != NumArgs; ++i) {
4091 MVT ArgVT = Outs[i].VT;
4092 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4095 if (Outs[i].IsFixed) {
4096 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4099 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4105 errs() << "Call operand #" << i << " has unhandled type "
4106 << EVT(ArgVT).getEVTString() << "\n";
4108 llvm_unreachable(nullptr);
4112 // All arguments are treated the same.
4113 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4116 // Assign locations to all of the outgoing aggregate by value arguments.
4117 SmallVector<CCValAssign, 16> ByValArgLocs;
4118 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4119 ByValArgLocs, *DAG.getContext());
4121 // Reserve stack space for the allocations in CCInfo.
4122 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4124 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4126 // Size of the linkage area, parameter list area and the part of the local
4127 // space variable where copies of aggregates which are passed by value are
4129 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4131 // Calculate by how many bytes the stack has to be adjusted in case of tail
4132 // call optimization.
4133 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4135 // Adjust the stack pointer for the new arguments...
4136 // These operations are automatically eliminated by the prolog/epilog pass
4137 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4139 SDValue CallSeqStart = Chain;
4141 // Load the return address and frame pointer so it can be moved somewhere else
4144 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4147 // Set up a copy of the stack pointer for use loading and storing any
4148 // arguments that may not fit in the registers available for argument
4150 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4152 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4153 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4154 SmallVector<SDValue, 8> MemOpChains;
4156 bool seenFloatArg = false;
4157 // Walk the register/memloc assignments, inserting copies/loads.
4158 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4161 CCValAssign &VA = ArgLocs[i];
4162 SDValue Arg = OutVals[i];
4163 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4165 if (Flags.isByVal()) {
4166 // Argument is an aggregate which is passed by value, thus we need to
4167 // create a copy of it in the local variable space of the current stack
4168 // frame (which is the stack frame of the caller) and pass the address of
4169 // this copy to the callee.
4170 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4171 CCValAssign &ByValVA = ByValArgLocs[j++];
4172 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4174 // Memory reserved in the local variable space of the callers stack frame.
4175 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4177 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4178 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4180 // Create a copy of the argument in the local area of the current
4182 SDValue MemcpyCall =
4183 CreateCopyOfByValArgument(Arg, PtrOff,
4184 CallSeqStart.getNode()->getOperand(0),
4187 // This must go outside the CALLSEQ_START..END.
4188 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4189 CallSeqStart.getNode()->getOperand(1),
4191 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4192 NewCallSeqStart.getNode());
4193 Chain = CallSeqStart = NewCallSeqStart;
4195 // Pass the address of the aggregate copy on the stack either in a
4196 // physical register or in the parameter list area of the current stack
4197 // frame to the callee.
4201 if (VA.isRegLoc()) {
4202 if (Arg.getValueType() == MVT::i1)
4203 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4205 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4206 // Put argument in a physical register.
4207 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4209 // Put argument in the parameter list area of the current stack frame.
4210 assert(VA.isMemLoc());
4211 unsigned LocMemOffset = VA.getLocMemOffset();
4214 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4215 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4217 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4218 MachinePointerInfo(),
4221 // Calculate and remember argument location.
4222 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4228 if (!MemOpChains.empty())
4229 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4231 // Build a sequence of copy-to-reg nodes chained together with token chain
4232 // and flag operands which copy the outgoing args into the appropriate regs.
4234 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4235 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4236 RegsToPass[i].second, InFlag);
4237 InFlag = Chain.getValue(1);
4240 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4243 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4244 SDValue Ops[] = { Chain, InFlag };
4246 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4247 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4249 InFlag = Chain.getValue(1);
4253 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4254 false, TailCallArguments);
4256 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4257 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4258 NumBytes, Ins, InVals, CS);
4261 // Copy an argument into memory, being careful to do this outside the
4262 // call sequence for the call to which the argument belongs.
4264 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4265 SDValue CallSeqStart,
4266 ISD::ArgFlagsTy Flags,
4269 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4270 CallSeqStart.getNode()->getOperand(0),
4272 // The MEMCPY must go outside the CALLSEQ_START..END.
4273 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4274 CallSeqStart.getNode()->getOperand(1),
4276 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4277 NewCallSeqStart.getNode());
4278 return NewCallSeqStart;
4282 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4283 CallingConv::ID CallConv, bool isVarArg,
4284 bool isTailCall, bool IsPatchPoint,
4285 const SmallVectorImpl<ISD::OutputArg> &Outs,
4286 const SmallVectorImpl<SDValue> &OutVals,
4287 const SmallVectorImpl<ISD::InputArg> &Ins,
4288 SDLoc dl, SelectionDAG &DAG,
4289 SmallVectorImpl<SDValue> &InVals,
4290 ImmutableCallSite *CS) const {
4292 bool isELFv2ABI = Subtarget.isELFv2ABI();
4293 bool isLittleEndian = Subtarget.isLittleEndian();
4294 unsigned NumOps = Outs.size();
4296 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4297 unsigned PtrByteSize = 8;
4299 MachineFunction &MF = DAG.getMachineFunction();
4301 // Mark this function as potentially containing a function that contains a
4302 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4303 // and restoring the callers stack pointer in this functions epilog. This is
4304 // done because by tail calling the called function might overwrite the value
4305 // in this function's (MF) stack pointer stack slot 0(SP).
4306 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4307 CallConv == CallingConv::Fast)
4308 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4310 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4311 "fastcc not supported on varargs functions");
4313 // Count how many bytes are to be pushed on the stack, including the linkage
4314 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4315 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4316 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4317 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4319 unsigned NumBytes = LinkageSize;
4320 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4322 static const MCPhysReg GPR[] = {
4323 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4324 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4326 static const MCPhysReg *FPR = GetFPR();
4328 static const MCPhysReg VR[] = {
4329 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4330 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4332 static const MCPhysReg VSRH[] = {
4333 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4334 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4337 const unsigned NumGPRs = array_lengthof(GPR);
4338 const unsigned NumFPRs = 13;
4339 const unsigned NumVRs = array_lengthof(VR);
4341 // When using the fast calling convention, we don't provide backing for
4342 // arguments that will be in registers.
4343 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4345 // Add up all the space actually used.
4346 for (unsigned i = 0; i != NumOps; ++i) {
4347 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4348 EVT ArgVT = Outs[i].VT;
4349 EVT OrigVT = Outs[i].ArgVT;
4351 if (CallConv == CallingConv::Fast) {
4352 if (Flags.isByVal())
4353 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4355 switch (ArgVT.getSimpleVT().SimpleTy) {
4356 default: llvm_unreachable("Unexpected ValueType for argument!");
4360 if (++NumGPRsUsed <= NumGPRs)
4365 if (++NumFPRsUsed <= NumFPRs)
4374 if (++NumVRsUsed <= NumVRs)
4380 /* Respect alignment of argument on the stack. */
4382 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4383 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4385 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4386 if (Flags.isInConsecutiveRegsLast())
4387 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4390 unsigned NumBytesActuallyUsed = NumBytes;
4392 // The prolog code of the callee may store up to 8 GPR argument registers to
4393 // the stack, allowing va_start to index over them in memory if its varargs.
4394 // Because we cannot tell if this is needed on the caller side, we have to
4395 // conservatively assume that it is needed. As such, make sure we have at
4396 // least enough stack space for the caller to store the 8 GPRs.
4397 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4398 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4400 // Tail call needs the stack to be aligned.
4401 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4402 CallConv == CallingConv::Fast)
4403 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4405 // Calculate by how many bytes the stack has to be adjusted in case of tail
4406 // call optimization.
4407 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4409 // To protect arguments on the stack from being clobbered in a tail call,
4410 // force all the loads to happen before doing any other lowering.
4412 Chain = DAG.getStackArgumentTokenFactor(Chain);
4414 // Adjust the stack pointer for the new arguments...
4415 // These operations are automatically eliminated by the prolog/epilog pass
4416 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4418 SDValue CallSeqStart = Chain;
4420 // Load the return address and frame pointer so it can be move somewhere else
4423 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4426 // Set up a copy of the stack pointer for use loading and storing any
4427 // arguments that may not fit in the registers available for argument
4429 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4431 // Figure out which arguments are going to go in registers, and which in
4432 // memory. Also, if this is a vararg function, floating point operations
4433 // must be stored to our stack, and loaded into integer regs as well, if
4434 // any integer regs are available for argument passing.
4435 unsigned ArgOffset = LinkageSize;
4437 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4438 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4440 SmallVector<SDValue, 8> MemOpChains;
4441 for (unsigned i = 0; i != NumOps; ++i) {
4442 SDValue Arg = OutVals[i];
4443 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4444 EVT ArgVT = Outs[i].VT;
4445 EVT OrigVT = Outs[i].ArgVT;
4447 // PtrOff will be used to store the current argument to the stack if a
4448 // register cannot be found for it.
4451 // We re-align the argument offset for each argument, except when using the
4452 // fast calling convention, when we need to make sure we do that only when
4453 // we'll actually use a stack slot.
4454 auto ComputePtrOff = [&]() {
4455 /* Respect alignment of argument on the stack. */
4457 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4458 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4460 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4462 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4465 if (CallConv != CallingConv::Fast) {
4468 /* Compute GPR index associated with argument offset. */
4469 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4470 GPR_idx = std::min(GPR_idx, NumGPRs);
4473 // Promote integers to 64-bit values.
4474 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4475 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4476 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4477 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4480 // FIXME memcpy is used way more than necessary. Correctness first.
4481 // Note: "by value" is code for passing a structure by value, not
4483 if (Flags.isByVal()) {
4484 // Note: Size includes alignment padding, so
4485 // struct x { short a; char b; }
4486 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4487 // These are the proper values we need for right-justifying the
4488 // aggregate in a parameter register.
4489 unsigned Size = Flags.getByValSize();
4491 // An empty aggregate parameter takes up no storage and no
4496 if (CallConv == CallingConv::Fast)
4499 // All aggregates smaller than 8 bytes must be passed right-justified.
4500 if (Size==1 || Size==2 || Size==4) {
4501 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4502 if (GPR_idx != NumGPRs) {
4503 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4504 MachinePointerInfo(), VT,
4505 false, false, false, 0);
4506 MemOpChains.push_back(Load.getValue(1));
4507 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4509 ArgOffset += PtrByteSize;
4514 if (GPR_idx == NumGPRs && Size < 8) {
4515 SDValue AddPtr = PtrOff;
4516 if (!isLittleEndian) {
4517 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4518 PtrOff.getValueType());
4519 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4521 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4524 ArgOffset += PtrByteSize;
4527 // Copy entire object into memory. There are cases where gcc-generated
4528 // code assumes it is there, even if it could be put entirely into
4529 // registers. (This is not what the doc says.)
4531 // FIXME: The above statement is likely due to a misunderstanding of the
4532 // documents. All arguments must be copied into the parameter area BY
4533 // THE CALLEE in the event that the callee takes the address of any
4534 // formal argument. That has not yet been implemented. However, it is
4535 // reasonable to use the stack area as a staging area for the register
4538 // Skip this for small aggregates, as we will use the same slot for a
4539 // right-justified copy, below.
4541 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4545 // When a register is available, pass a small aggregate right-justified.
4546 if (Size < 8 && GPR_idx != NumGPRs) {
4547 // The easiest way to get this right-justified in a register
4548 // is to copy the structure into the rightmost portion of a
4549 // local variable slot, then load the whole slot into the
4551 // FIXME: The memcpy seems to produce pretty awful code for
4552 // small aggregates, particularly for packed ones.
4553 // FIXME: It would be preferable to use the slot in the
4554 // parameter save area instead of a new local variable.
4555 SDValue AddPtr = PtrOff;
4556 if (!isLittleEndian) {
4557 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4558 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4560 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4564 // Load the slot into the register.
4565 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4566 MachinePointerInfo(),
4567 false, false, false, 0);
4568 MemOpChains.push_back(Load.getValue(1));
4569 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4571 // Done with this argument.
4572 ArgOffset += PtrByteSize;
4576 // For aggregates larger than PtrByteSize, copy the pieces of the
4577 // object that fit into registers from the parameter save area.
4578 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4579 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4580 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4581 if (GPR_idx != NumGPRs) {
4582 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4583 MachinePointerInfo(),
4584 false, false, false, 0);
4585 MemOpChains.push_back(Load.getValue(1));
4586 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4587 ArgOffset += PtrByteSize;
4589 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4596 switch (Arg.getSimpleValueType().SimpleTy) {
4597 default: llvm_unreachable("Unexpected ValueType for argument!");
4601 // These can be scalar arguments or elements of an integer array type
4602 // passed directly. Clang may use those instead of "byval" aggregate
4603 // types to avoid forcing arguments to memory unnecessarily.
4604 if (GPR_idx != NumGPRs) {
4605 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4607 if (CallConv == CallingConv::Fast)
4610 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4611 true, isTailCall, false, MemOpChains,
4612 TailCallArguments, dl);
4613 if (CallConv == CallingConv::Fast)
4614 ArgOffset += PtrByteSize;
4616 if (CallConv != CallingConv::Fast)
4617 ArgOffset += PtrByteSize;
4621 // These can be scalar arguments or elements of a float array type
4622 // passed directly. The latter are used to implement ELFv2 homogenous
4623 // float aggregates.
4625 // Named arguments go into FPRs first, and once they overflow, the
4626 // remaining arguments go into GPRs and then the parameter save area.
4627 // Unnamed arguments for vararg functions always go to GPRs and
4628 // then the parameter save area. For now, put all arguments to vararg
4629 // routines always in both locations (FPR *and* GPR or stack slot).
4630 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4631 bool NeededLoad = false;
4633 // First load the argument into the next available FPR.
4634 if (FPR_idx != NumFPRs)
4635 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4637 // Next, load the argument into GPR or stack slot if needed.
4638 if (!NeedGPROrStack)
4640 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4641 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4642 // once we support fp <-> gpr moves.
4644 // In the non-vararg case, this can only ever happen in the
4645 // presence of f32 array types, since otherwise we never run
4646 // out of FPRs before running out of GPRs.
4649 // Double values are always passed in a single GPR.
4650 if (Arg.getValueType() != MVT::f32) {
4651 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4653 // Non-array float values are extended and passed in a GPR.
4654 } else if (!Flags.isInConsecutiveRegs()) {
4655 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4656 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4658 // If we have an array of floats, we collect every odd element
4659 // together with its predecessor into one GPR.
4660 } else if (ArgOffset % PtrByteSize != 0) {
4662 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4663 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4664 if (!isLittleEndian)
4666 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4668 // The final element, if even, goes into the first half of a GPR.
4669 } else if (Flags.isInConsecutiveRegsLast()) {
4670 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4671 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4672 if (!isLittleEndian)
4673 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4674 DAG.getConstant(32, MVT::i32));
4676 // Non-final even elements are skipped; they will be handled
4677 // together the with subsequent argument on the next go-around.
4681 if (ArgVal.getNode())
4682 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4684 if (CallConv == CallingConv::Fast)
4687 // Single-precision floating-point values are mapped to the
4688 // second (rightmost) word of the stack doubleword.
4689 if (Arg.getValueType() == MVT::f32 &&
4690 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4691 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4692 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4695 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4696 true, isTailCall, false, MemOpChains,
4697 TailCallArguments, dl);
4701 // When passing an array of floats, the array occupies consecutive
4702 // space in the argument area; only round up to the next doubleword
4703 // at the end of the array. Otherwise, each float takes 8 bytes.
4704 if (CallConv != CallingConv::Fast || NeededLoad) {
4705 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4706 Flags.isInConsecutiveRegs()) ? 4 : 8;
4707 if (Flags.isInConsecutiveRegsLast())
4708 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4718 // These can be scalar arguments or elements of a vector array type
4719 // passed directly. The latter are used to implement ELFv2 homogenous
4720 // vector aggregates.
4722 // For a varargs call, named arguments go into VRs or on the stack as
4723 // usual; unnamed arguments always go to the stack or the corresponding
4724 // GPRs when within range. For now, we always put the value in both
4725 // locations (or even all three).
4727 // We could elide this store in the case where the object fits
4728 // entirely in R registers. Maybe later.
4729 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4730 MachinePointerInfo(), false, false, 0);
4731 MemOpChains.push_back(Store);
4732 if (VR_idx != NumVRs) {
4733 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4734 MachinePointerInfo(),
4735 false, false, false, 0);
4736 MemOpChains.push_back(Load.getValue(1));
4738 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4739 Arg.getSimpleValueType() == MVT::v2i64) ?
4740 VSRH[VR_idx] : VR[VR_idx];
4743 RegsToPass.push_back(std::make_pair(VReg, Load));
4746 for (unsigned i=0; i<16; i+=PtrByteSize) {
4747 if (GPR_idx == NumGPRs)
4749 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4750 DAG.getConstant(i, PtrVT));
4751 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4752 false, false, false, 0);
4753 MemOpChains.push_back(Load.getValue(1));
4754 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4759 // Non-varargs Altivec params go into VRs or on the stack.
4760 if (VR_idx != NumVRs) {
4761 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4762 Arg.getSimpleValueType() == MVT::v2i64) ?
4763 VSRH[VR_idx] : VR[VR_idx];
4766 RegsToPass.push_back(std::make_pair(VReg, Arg));
4768 if (CallConv == CallingConv::Fast)
4771 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4772 true, isTailCall, true, MemOpChains,
4773 TailCallArguments, dl);
4774 if (CallConv == CallingConv::Fast)
4778 if (CallConv != CallingConv::Fast)
4784 assert(NumBytesActuallyUsed == ArgOffset);
4785 (void)NumBytesActuallyUsed;
4787 if (!MemOpChains.empty())
4788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4790 // Check if this is an indirect call (MTCTR/BCTRL).
4791 // See PrepareCall() for more information about calls through function
4792 // pointers in the 64-bit SVR4 ABI.
4793 if (!isTailCall && !IsPatchPoint &&
4794 !isFunctionGlobalAddress(Callee) &&
4795 !isa<ExternalSymbolSDNode>(Callee)) {
4796 // Load r2 into a virtual register and store it to the TOC save area.
4797 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4798 // TOC save area offset.
4799 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4800 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4801 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4802 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4803 MachinePointerInfo::getStack(TOCSaveOffset),
4805 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4806 // This does not mean the MTCTR instruction must use R12; it's easier
4807 // to model this as an extra parameter, so do that.
4808 if (isELFv2ABI && !IsPatchPoint)
4809 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4812 // Build a sequence of copy-to-reg nodes chained together with token chain
4813 // and flag operands which copy the outgoing args into the appropriate regs.
4815 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4816 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4817 RegsToPass[i].second, InFlag);
4818 InFlag = Chain.getValue(1);
4822 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4823 FPOp, true, TailCallArguments);
4825 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4826 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4827 NumBytes, Ins, InVals, CS);
4831 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4832 CallingConv::ID CallConv, bool isVarArg,
4833 bool isTailCall, bool IsPatchPoint,
4834 const SmallVectorImpl<ISD::OutputArg> &Outs,
4835 const SmallVectorImpl<SDValue> &OutVals,
4836 const SmallVectorImpl<ISD::InputArg> &Ins,
4837 SDLoc dl, SelectionDAG &DAG,
4838 SmallVectorImpl<SDValue> &InVals,
4839 ImmutableCallSite *CS) const {
4841 unsigned NumOps = Outs.size();
4843 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4844 bool isPPC64 = PtrVT == MVT::i64;
4845 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4847 MachineFunction &MF = DAG.getMachineFunction();
4849 // Mark this function as potentially containing a function that contains a
4850 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4851 // and restoring the callers stack pointer in this functions epilog. This is
4852 // done because by tail calling the called function might overwrite the value
4853 // in this function's (MF) stack pointer stack slot 0(SP).
4854 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4855 CallConv == CallingConv::Fast)
4856 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4858 // Count how many bytes are to be pushed on the stack, including the linkage
4859 // area, and parameter passing area. We start with 24/48 bytes, which is
4860 // prereserved space for [SP][CR][LR][3 x unused].
4861 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4863 unsigned NumBytes = LinkageSize;
4865 // Add up all the space actually used.
4866 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4867 // they all go in registers, but we must reserve stack space for them for
4868 // possible use by the caller. In varargs or 64-bit calls, parameters are
4869 // assigned stack space in order, with padding so Altivec parameters are
4871 unsigned nAltivecParamsAtEnd = 0;
4872 for (unsigned i = 0; i != NumOps; ++i) {
4873 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4874 EVT ArgVT = Outs[i].VT;
4875 // Varargs Altivec parameters are padded to a 16 byte boundary.
4876 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4877 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4878 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4879 if (!isVarArg && !isPPC64) {
4880 // Non-varargs Altivec parameters go after all the non-Altivec
4881 // parameters; handle those later so we know how much padding we need.
4882 nAltivecParamsAtEnd++;
4885 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4886 NumBytes = ((NumBytes+15)/16)*16;
4888 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4891 // Allow for Altivec parameters at the end, if needed.
4892 if (nAltivecParamsAtEnd) {
4893 NumBytes = ((NumBytes+15)/16)*16;
4894 NumBytes += 16*nAltivecParamsAtEnd;
4897 // The prolog code of the callee may store up to 8 GPR argument registers to
4898 // the stack, allowing va_start to index over them in memory if its varargs.
4899 // Because we cannot tell if this is needed on the caller side, we have to
4900 // conservatively assume that it is needed. As such, make sure we have at
4901 // least enough stack space for the caller to store the 8 GPRs.
4902 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4904 // Tail call needs the stack to be aligned.
4905 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4906 CallConv == CallingConv::Fast)
4907 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4909 // Calculate by how many bytes the stack has to be adjusted in case of tail
4910 // call optimization.
4911 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4913 // To protect arguments on the stack from being clobbered in a tail call,
4914 // force all the loads to happen before doing any other lowering.
4916 Chain = DAG.getStackArgumentTokenFactor(Chain);
4918 // Adjust the stack pointer for the new arguments...
4919 // These operations are automatically eliminated by the prolog/epilog pass
4920 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4922 SDValue CallSeqStart = Chain;
4924 // Load the return address and frame pointer so it can be move somewhere else
4927 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4930 // Set up a copy of the stack pointer for use loading and storing any
4931 // arguments that may not fit in the registers available for argument
4935 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4937 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4939 // Figure out which arguments are going to go in registers, and which in
4940 // memory. Also, if this is a vararg function, floating point operations
4941 // must be stored to our stack, and loaded into integer regs as well, if
4942 // any integer regs are available for argument passing.
4943 unsigned ArgOffset = LinkageSize;
4944 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4946 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4947 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4948 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4950 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4951 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4952 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4954 static const MCPhysReg *FPR = GetFPR();
4956 static const MCPhysReg VR[] = {
4957 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4958 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4960 const unsigned NumGPRs = array_lengthof(GPR_32);
4961 const unsigned NumFPRs = 13;
4962 const unsigned NumVRs = array_lengthof(VR);
4964 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4966 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4967 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4969 SmallVector<SDValue, 8> MemOpChains;
4970 for (unsigned i = 0; i != NumOps; ++i) {
4971 SDValue Arg = OutVals[i];
4972 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4974 // PtrOff will be used to store the current argument to the stack if a
4975 // register cannot be found for it.
4978 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4980 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4982 // On PPC64, promote integers to 64-bit values.
4983 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4984 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4985 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4986 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4989 // FIXME memcpy is used way more than necessary. Correctness first.
4990 // Note: "by value" is code for passing a structure by value, not
4992 if (Flags.isByVal()) {
4993 unsigned Size = Flags.getByValSize();
4994 // Very small objects are passed right-justified. Everything else is
4995 // passed left-justified.
4996 if (Size==1 || Size==2) {
4997 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4998 if (GPR_idx != NumGPRs) {
4999 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5000 MachinePointerInfo(), VT,
5001 false, false, false, 0);
5002 MemOpChains.push_back(Load.getValue(1));
5003 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5005 ArgOffset += PtrByteSize;
5007 SDValue Const = DAG.getConstant(PtrByteSize - Size,
5008 PtrOff.getValueType());
5009 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5010 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5013 ArgOffset += PtrByteSize;
5017 // Copy entire object into memory. There are cases where gcc-generated
5018 // code assumes it is there, even if it could be put entirely into
5019 // registers. (This is not what the doc says.)
5020 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5024 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5025 // copy the pieces of the object that fit into registers from the
5026 // parameter save area.
5027 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5028 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5029 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5030 if (GPR_idx != NumGPRs) {
5031 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5032 MachinePointerInfo(),
5033 false, false, false, 0);
5034 MemOpChains.push_back(Load.getValue(1));
5035 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5036 ArgOffset += PtrByteSize;
5038 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5045 switch (Arg.getSimpleValueType().SimpleTy) {
5046 default: llvm_unreachable("Unexpected ValueType for argument!");
5050 if (GPR_idx != NumGPRs) {
5051 if (Arg.getValueType() == MVT::i1)
5052 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5054 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5056 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5057 isPPC64, isTailCall, false, MemOpChains,
5058 TailCallArguments, dl);
5060 ArgOffset += PtrByteSize;
5064 if (FPR_idx != NumFPRs) {
5065 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5068 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5069 MachinePointerInfo(), false, false, 0);
5070 MemOpChains.push_back(Store);
5072 // Float varargs are always shadowed in available integer registers
5073 if (GPR_idx != NumGPRs) {
5074 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5075 MachinePointerInfo(), false, false,
5077 MemOpChains.push_back(Load.getValue(1));
5078 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5080 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5081 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5082 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5083 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5084 MachinePointerInfo(),
5085 false, false, false, 0);
5086 MemOpChains.push_back(Load.getValue(1));
5087 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5090 // If we have any FPRs remaining, we may also have GPRs remaining.
5091 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5093 if (GPR_idx != NumGPRs)
5095 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5096 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5100 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5101 isPPC64, isTailCall, false, MemOpChains,
5102 TailCallArguments, dl);
5106 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5113 // These go aligned on the stack, or in the corresponding R registers
5114 // when within range. The Darwin PPC ABI doc claims they also go in
5115 // V registers; in fact gcc does this only for arguments that are
5116 // prototyped, not for those that match the ... We do it for all
5117 // arguments, seems to work.
5118 while (ArgOffset % 16 !=0) {
5119 ArgOffset += PtrByteSize;
5120 if (GPR_idx != NumGPRs)
5123 // We could elide this store in the case where the object fits
5124 // entirely in R registers. Maybe later.
5125 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5126 DAG.getConstant(ArgOffset, PtrVT));
5127 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5128 MachinePointerInfo(), false, false, 0);
5129 MemOpChains.push_back(Store);
5130 if (VR_idx != NumVRs) {
5131 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5132 MachinePointerInfo(),
5133 false, false, false, 0);
5134 MemOpChains.push_back(Load.getValue(1));
5135 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5138 for (unsigned i=0; i<16; i+=PtrByteSize) {
5139 if (GPR_idx == NumGPRs)
5141 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5142 DAG.getConstant(i, PtrVT));
5143 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5144 false, false, false, 0);
5145 MemOpChains.push_back(Load.getValue(1));
5146 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5151 // Non-varargs Altivec params generally go in registers, but have
5152 // stack space allocated at the end.
5153 if (VR_idx != NumVRs) {
5154 // Doesn't have GPR space allocated.
5155 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5156 } else if (nAltivecParamsAtEnd==0) {
5157 // We are emitting Altivec params in order.
5158 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5159 isPPC64, isTailCall, true, MemOpChains,
5160 TailCallArguments, dl);
5166 // If all Altivec parameters fit in registers, as they usually do,
5167 // they get stack space following the non-Altivec parameters. We
5168 // don't track this here because nobody below needs it.
5169 // If there are more Altivec parameters than fit in registers emit
5171 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5173 // Offset is aligned; skip 1st 12 params which go in V registers.
5174 ArgOffset = ((ArgOffset+15)/16)*16;
5176 for (unsigned i = 0; i != NumOps; ++i) {
5177 SDValue Arg = OutVals[i];
5178 EVT ArgType = Outs[i].VT;
5179 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5180 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5183 // We are emitting Altivec params in order.
5184 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5185 isPPC64, isTailCall, true, MemOpChains,
5186 TailCallArguments, dl);
5193 if (!MemOpChains.empty())
5194 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5196 // On Darwin, R12 must contain the address of an indirect callee. This does
5197 // not mean the MTCTR instruction must use R12; it's easier to model this as
5198 // an extra parameter, so do that.
5200 !isFunctionGlobalAddress(Callee) &&
5201 !isa<ExternalSymbolSDNode>(Callee) &&
5202 !isBLACompatibleAddress(Callee, DAG))
5203 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5204 PPC::R12), Callee));
5206 // Build a sequence of copy-to-reg nodes chained together with token chain
5207 // and flag operands which copy the outgoing args into the appropriate regs.
5209 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5210 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5211 RegsToPass[i].second, InFlag);
5212 InFlag = Chain.getValue(1);
5216 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5217 FPOp, true, TailCallArguments);
5219 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5220 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5221 NumBytes, Ins, InVals, CS);
5225 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5226 MachineFunction &MF, bool isVarArg,
5227 const SmallVectorImpl<ISD::OutputArg> &Outs,
5228 LLVMContext &Context) const {
5229 SmallVector<CCValAssign, 16> RVLocs;
5230 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5231 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5235 PPCTargetLowering::LowerReturn(SDValue Chain,
5236 CallingConv::ID CallConv, bool isVarArg,
5237 const SmallVectorImpl<ISD::OutputArg> &Outs,
5238 const SmallVectorImpl<SDValue> &OutVals,
5239 SDLoc dl, SelectionDAG &DAG) const {
5241 SmallVector<CCValAssign, 16> RVLocs;
5242 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5244 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5247 SmallVector<SDValue, 4> RetOps(1, Chain);
5249 // Copy the result values into the output registers.
5250 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5251 CCValAssign &VA = RVLocs[i];
5252 assert(VA.isRegLoc() && "Can only return in registers!");
5254 SDValue Arg = OutVals[i];
5256 switch (VA.getLocInfo()) {
5257 default: llvm_unreachable("Unknown loc info!");
5258 case CCValAssign::Full: break;
5259 case CCValAssign::AExt:
5260 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5262 case CCValAssign::ZExt:
5263 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5265 case CCValAssign::SExt:
5266 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5270 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5271 Flag = Chain.getValue(1);
5272 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5275 RetOps[0] = Chain; // Update chain.
5277 // Add the flag if we have it.
5279 RetOps.push_back(Flag);
5281 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5284 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5285 const PPCSubtarget &Subtarget) const {
5286 // When we pop the dynamic allocation we need to restore the SP link.
5289 // Get the corect type for pointers.
5290 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5292 // Construct the stack pointer operand.
5293 bool isPPC64 = Subtarget.isPPC64();
5294 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5295 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5297 // Get the operands for the STACKRESTORE.
5298 SDValue Chain = Op.getOperand(0);
5299 SDValue SaveSP = Op.getOperand(1);
5301 // Load the old link SP.
5302 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5303 MachinePointerInfo(),
5304 false, false, false, 0);
5306 // Restore the stack pointer.
5307 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5309 // Store the old link SP.
5310 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5317 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5318 MachineFunction &MF = DAG.getMachineFunction();
5319 bool isPPC64 = Subtarget.isPPC64();
5320 bool isDarwinABI = Subtarget.isDarwinABI();
5321 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5323 // Get current frame pointer save index. The users of this index will be
5324 // primarily DYNALLOC instructions.
5325 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5326 int RASI = FI->getReturnAddrSaveIndex();
5328 // If the frame pointer save index hasn't been defined yet.
5330 // Find out what the fix offset of the frame pointer save area.
5331 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5332 // Allocate the frame index for frame pointer save area.
5333 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5335 FI->setReturnAddrSaveIndex(RASI);
5337 return DAG.getFrameIndex(RASI, PtrVT);
5341 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5342 MachineFunction &MF = DAG.getMachineFunction();
5343 bool isPPC64 = Subtarget.isPPC64();
5344 bool isDarwinABI = Subtarget.isDarwinABI();
5345 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5347 // Get current frame pointer save index. The users of this index will be
5348 // primarily DYNALLOC instructions.
5349 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5350 int FPSI = FI->getFramePointerSaveIndex();
5352 // If the frame pointer save index hasn't been defined yet.
5354 // Find out what the fix offset of the frame pointer save area.
5355 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5358 // Allocate the frame index for frame pointer save area.
5359 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5361 FI->setFramePointerSaveIndex(FPSI);
5363 return DAG.getFrameIndex(FPSI, PtrVT);
5366 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5368 const PPCSubtarget &Subtarget) const {
5370 SDValue Chain = Op.getOperand(0);
5371 SDValue Size = Op.getOperand(1);
5374 // Get the corect type for pointers.
5375 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5377 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5378 DAG.getConstant(0, PtrVT), Size);
5379 // Construct a node for the frame pointer save index.
5380 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5381 // Build a DYNALLOC node.
5382 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5383 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5384 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5387 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5388 SelectionDAG &DAG) const {
5390 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5391 DAG.getVTList(MVT::i32, MVT::Other),
5392 Op.getOperand(0), Op.getOperand(1));
5395 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5396 SelectionDAG &DAG) const {
5398 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5399 Op.getOperand(0), Op.getOperand(1));
5402 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5403 assert(Op.getValueType() == MVT::i1 &&
5404 "Custom lowering only for i1 loads");
5406 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5409 LoadSDNode *LD = cast<LoadSDNode>(Op);
5411 SDValue Chain = LD->getChain();
5412 SDValue BasePtr = LD->getBasePtr();
5413 MachineMemOperand *MMO = LD->getMemOperand();
5415 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5416 BasePtr, MVT::i8, MMO);
5417 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5419 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5420 return DAG.getMergeValues(Ops, dl);
5423 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5424 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5425 "Custom lowering only for i1 stores");
5427 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5430 StoreSDNode *ST = cast<StoreSDNode>(Op);
5432 SDValue Chain = ST->getChain();
5433 SDValue BasePtr = ST->getBasePtr();
5434 SDValue Value = ST->getValue();
5435 MachineMemOperand *MMO = ST->getMemOperand();
5437 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5438 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5441 // FIXME: Remove this once the ANDI glue bug is fixed:
5442 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5443 assert(Op.getValueType() == MVT::i1 &&
5444 "Custom lowering only for i1 results");
5447 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5451 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5453 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5454 // Not FP? Not a fsel.
5455 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5456 !Op.getOperand(2).getValueType().isFloatingPoint())
5459 // We might be able to do better than this under some circumstances, but in
5460 // general, fsel-based lowering of select is a finite-math-only optimization.
5461 // For more information, see section F.3 of the 2.06 ISA specification.
5462 if (!DAG.getTarget().Options.NoInfsFPMath ||
5463 !DAG.getTarget().Options.NoNaNsFPMath)
5466 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5468 EVT ResVT = Op.getValueType();
5469 EVT CmpVT = Op.getOperand(0).getValueType();
5470 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5471 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5474 // If the RHS of the comparison is a 0.0, we don't need to do the
5475 // subtraction at all.
5477 if (isFloatingPointZero(RHS))
5479 default: break; // SETUO etc aren't handled by fsel.
5483 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5484 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5485 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5486 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5487 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5488 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5489 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5492 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5495 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5496 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5497 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5500 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5503 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5504 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5505 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5506 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5511 default: break; // SETUO etc aren't handled by fsel.
5515 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5516 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5517 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5518 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5519 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5520 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5521 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5522 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5525 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5526 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5527 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5528 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5531 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5532 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5533 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5534 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5537 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5538 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5539 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5540 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5543 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5544 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5545 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5546 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5551 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5554 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5555 SDValue Src = Op.getOperand(0);
5556 if (Src.getValueType() == MVT::f32)
5557 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5560 switch (Op.getSimpleValueType().SimpleTy) {
5561 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5564 Op.getOpcode() == ISD::FP_TO_SINT
5566 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5570 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5571 "i64 FP_TO_UINT is supported only with FPCVT");
5572 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5578 // Convert the FP value to an int value through memory.
5579 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5580 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5581 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5582 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5583 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5585 // Emit a store to the stack slot.
5588 MachineFunction &MF = DAG.getMachineFunction();
5589 MachineMemOperand *MMO =
5590 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5591 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5592 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5593 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5595 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5596 MPI, false, false, 0);
5598 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5600 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5601 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5602 DAG.getConstant(4, FIPtr.getValueType()));
5603 MPI = MPI.getWithOffset(4);
5611 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5614 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5616 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5617 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5621 // We're trying to insert a regular store, S, and then a load, L. If the
5622 // incoming value, O, is a load, we might just be able to have our load use the
5623 // address used by O. However, we don't know if anything else will store to
5624 // that address before we can load from it. To prevent this situation, we need
5625 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5626 // the same chain operand as O, we create a token factor from the chain results
5627 // of O and L, and we replace all uses of O's chain result with that token
5628 // factor (see spliceIntoChain below for this last part).
5629 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5632 ISD::LoadExtType ET) const {
5634 if (ET == ISD::NON_EXTLOAD &&
5635 (Op.getOpcode() == ISD::FP_TO_UINT ||
5636 Op.getOpcode() == ISD::FP_TO_SINT) &&
5637 isOperationLegalOrCustom(Op.getOpcode(),
5638 Op.getOperand(0).getValueType())) {
5640 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5644 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5645 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5646 LD->isNonTemporal())
5648 if (LD->getMemoryVT() != MemVT)
5651 RLI.Ptr = LD->getBasePtr();
5652 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5653 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5654 "Non-pre-inc AM on PPC?");
5655 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5659 RLI.Chain = LD->getChain();
5660 RLI.MPI = LD->getPointerInfo();
5661 RLI.IsInvariant = LD->isInvariant();
5662 RLI.Alignment = LD->getAlignment();
5663 RLI.AAInfo = LD->getAAInfo();
5664 RLI.Ranges = LD->getRanges();
5666 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5670 // Given the head of the old chain, ResChain, insert a token factor containing
5671 // it and NewResChain, and make users of ResChain now be users of that token
5673 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5674 SDValue NewResChain,
5675 SelectionDAG &DAG) const {
5679 SDLoc dl(NewResChain);
5681 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5682 NewResChain, DAG.getUNDEF(MVT::Other));
5683 assert(TF.getNode() != NewResChain.getNode() &&
5684 "A new TF really is required here");
5686 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5687 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5690 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5691 SelectionDAG &DAG) const {
5693 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5694 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5697 if (Op.getOperand(0).getValueType() == MVT::i1)
5698 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5699 DAG.getConstantFP(1.0, Op.getValueType()),
5700 DAG.getConstantFP(0.0, Op.getValueType()));
5702 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5703 "UINT_TO_FP is supported only with FPCVT");
5705 // If we have FCFIDS, then use it when converting to single-precision.
5706 // Otherwise, convert to double-precision and then round.
5707 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5708 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
5710 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
5712 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5716 if (Op.getOperand(0).getValueType() == MVT::i64) {
5717 SDValue SINT = Op.getOperand(0);
5718 // When converting to single-precision, we actually need to convert
5719 // to double-precision first and then round to single-precision.
5720 // To avoid double-rounding effects during that operation, we have
5721 // to prepare the input operand. Bits that might be truncated when
5722 // converting to double-precision are replaced by a bit that won't
5723 // be lost at this stage, but is below the single-precision rounding
5726 // However, if -enable-unsafe-fp-math is in effect, accept double
5727 // rounding to avoid the extra overhead.
5728 if (Op.getValueType() == MVT::f32 &&
5729 !Subtarget.hasFPCVT() &&
5730 !DAG.getTarget().Options.UnsafeFPMath) {
5732 // Twiddle input to make sure the low 11 bits are zero. (If this
5733 // is the case, we are guaranteed the value will fit into the 53 bit
5734 // mantissa of an IEEE double-precision value without rounding.)
5735 // If any of those low 11 bits were not zero originally, make sure
5736 // bit 12 (value 2048) is set instead, so that the final rounding
5737 // to single-precision gets the correct result.
5738 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5739 SINT, DAG.getConstant(2047, MVT::i64));
5740 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5741 Round, DAG.getConstant(2047, MVT::i64));
5742 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5743 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5744 Round, DAG.getConstant(-2048, MVT::i64));
5746 // However, we cannot use that value unconditionally: if the magnitude
5747 // of the input value is small, the bit-twiddling we did above might
5748 // end up visibly changing the output. Fortunately, in that case, we
5749 // don't need to twiddle bits since the original input will convert
5750 // exactly to double-precision floating-point already. Therefore,
5751 // construct a conditional to use the original value if the top 11
5752 // bits are all sign-bit copies, and use the rounded value computed
5754 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5755 SINT, DAG.getConstant(53, MVT::i32));
5756 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5757 Cond, DAG.getConstant(1, MVT::i64));
5758 Cond = DAG.getSetCC(dl, MVT::i32,
5759 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5761 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5767 MachineFunction &MF = DAG.getMachineFunction();
5768 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5769 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5770 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5772 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5773 } else if (Subtarget.hasLFIWAX() &&
5774 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5775 MachineMemOperand *MMO =
5776 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5777 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5778 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5779 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5780 DAG.getVTList(MVT::f64, MVT::Other),
5781 Ops, MVT::i32, MMO);
5782 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5783 } else if (Subtarget.hasFPCVT() &&
5784 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5785 MachineMemOperand *MMO =
5786 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5787 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5788 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5789 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5790 DAG.getVTList(MVT::f64, MVT::Other),
5791 Ops, MVT::i32, MMO);
5792 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5793 } else if (((Subtarget.hasLFIWAX() &&
5794 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5795 (Subtarget.hasFPCVT() &&
5796 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5797 SINT.getOperand(0).getValueType() == MVT::i32) {
5798 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5799 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5801 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5802 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5805 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5806 MachinePointerInfo::getFixedStack(FrameIdx),
5809 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5810 "Expected an i32 store");
5814 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5817 MachineMemOperand *MMO =
5818 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5819 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5820 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5821 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5822 PPCISD::LFIWZX : PPCISD::LFIWAX,
5823 dl, DAG.getVTList(MVT::f64, MVT::Other),
5824 Ops, MVT::i32, MMO);
5826 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5828 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5830 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5831 FP = DAG.getNode(ISD::FP_ROUND, dl,
5832 MVT::f32, FP, DAG.getIntPtrConstant(0));
5836 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5837 "Unhandled INT_TO_FP type in custom expander!");
5838 // Since we only generate this in 64-bit mode, we can take advantage of
5839 // 64-bit registers. In particular, sign extend the input value into the
5840 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5841 // then lfd it and fcfid it.
5842 MachineFunction &MF = DAG.getMachineFunction();
5843 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5844 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5847 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5850 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5852 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5853 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5855 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5856 MachinePointerInfo::getFixedStack(FrameIdx),
5859 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5860 "Expected an i32 store");
5864 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5868 MachineMemOperand *MMO =
5869 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5870 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5871 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5872 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5873 PPCISD::LFIWZX : PPCISD::LFIWAX,
5874 dl, DAG.getVTList(MVT::f64, MVT::Other),
5875 Ops, MVT::i32, MMO);
5877 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5879 assert(Subtarget.isPPC64() &&
5880 "i32->FP without LFIWAX supported only on PPC64");
5882 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5883 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5885 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5888 // STD the extended value into the stack slot.
5889 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5890 MachinePointerInfo::getFixedStack(FrameIdx),
5893 // Load the value as a double.
5894 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5895 MachinePointerInfo::getFixedStack(FrameIdx),
5896 false, false, false, 0);
5899 // FCFID it and return it.
5900 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5901 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5902 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5906 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5907 SelectionDAG &DAG) const {
5910 The rounding mode is in bits 30:31 of FPSR, and has the following
5917 FLT_ROUNDS, on the other hand, expects the following:
5924 To perform the conversion, we do:
5925 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5928 MachineFunction &MF = DAG.getMachineFunction();
5929 EVT VT = Op.getValueType();
5930 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5932 // Save FP Control Word to register
5934 MVT::f64, // return register
5935 MVT::Glue // unused in this context
5937 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5939 // Save FP register to stack slot
5940 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5941 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5942 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5943 StackSlot, MachinePointerInfo(), false, false,0);
5945 // Load FP Control Word from low 32 bits of stack slot.
5946 SDValue Four = DAG.getConstant(4, PtrVT);
5947 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5948 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5949 false, false, false, 0);
5951 // Transform as necessary
5953 DAG.getNode(ISD::AND, dl, MVT::i32,
5954 CWD, DAG.getConstant(3, MVT::i32));
5956 DAG.getNode(ISD::SRL, dl, MVT::i32,
5957 DAG.getNode(ISD::AND, dl, MVT::i32,
5958 DAG.getNode(ISD::XOR, dl, MVT::i32,
5959 CWD, DAG.getConstant(3, MVT::i32)),
5960 DAG.getConstant(3, MVT::i32)),
5961 DAG.getConstant(1, MVT::i32));
5964 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5966 return DAG.getNode((VT.getSizeInBits() < 16 ?
5967 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5970 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5971 EVT VT = Op.getValueType();
5972 unsigned BitWidth = VT.getSizeInBits();
5974 assert(Op.getNumOperands() == 3 &&
5975 VT == Op.getOperand(1).getValueType() &&
5978 // Expand into a bunch of logical ops. Note that these ops
5979 // depend on the PPC behavior for oversized shift amounts.
5980 SDValue Lo = Op.getOperand(0);
5981 SDValue Hi = Op.getOperand(1);
5982 SDValue Amt = Op.getOperand(2);
5983 EVT AmtVT = Amt.getValueType();
5985 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5986 DAG.getConstant(BitWidth, AmtVT), Amt);
5987 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5988 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5989 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5990 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5991 DAG.getConstant(-BitWidth, AmtVT));
5992 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5993 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5994 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5995 SDValue OutOps[] = { OutLo, OutHi };
5996 return DAG.getMergeValues(OutOps, dl);
5999 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6000 EVT VT = Op.getValueType();
6002 unsigned BitWidth = VT.getSizeInBits();
6003 assert(Op.getNumOperands() == 3 &&
6004 VT == Op.getOperand(1).getValueType() &&
6007 // Expand into a bunch of logical ops. Note that these ops
6008 // depend on the PPC behavior for oversized shift amounts.
6009 SDValue Lo = Op.getOperand(0);
6010 SDValue Hi = Op.getOperand(1);
6011 SDValue Amt = Op.getOperand(2);
6012 EVT AmtVT = Amt.getValueType();
6014 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6015 DAG.getConstant(BitWidth, AmtVT), Amt);
6016 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6017 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6018 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6019 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6020 DAG.getConstant(-BitWidth, AmtVT));
6021 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6022 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6023 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6024 SDValue OutOps[] = { OutLo, OutHi };
6025 return DAG.getMergeValues(OutOps, dl);
6028 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6030 EVT VT = Op.getValueType();
6031 unsigned BitWidth = VT.getSizeInBits();
6032 assert(Op.getNumOperands() == 3 &&
6033 VT == Op.getOperand(1).getValueType() &&
6036 // Expand into a bunch of logical ops, followed by a select_cc.
6037 SDValue Lo = Op.getOperand(0);
6038 SDValue Hi = Op.getOperand(1);
6039 SDValue Amt = Op.getOperand(2);
6040 EVT AmtVT = Amt.getValueType();
6042 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6043 DAG.getConstant(BitWidth, AmtVT), Amt);
6044 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6045 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6046 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6047 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6048 DAG.getConstant(-BitWidth, AmtVT));
6049 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6050 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6051 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6052 Tmp4, Tmp6, ISD::SETLE);
6053 SDValue OutOps[] = { OutLo, OutHi };
6054 return DAG.getMergeValues(OutOps, dl);
6057 //===----------------------------------------------------------------------===//
6058 // Vector related lowering.
6061 /// BuildSplatI - Build a canonical splati of Val with an element size of
6062 /// SplatSize. Cast the result to VT.
6063 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6064 SelectionDAG &DAG, SDLoc dl) {
6065 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6067 static const EVT VTys[] = { // canonical VT to use for each size.
6068 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6071 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6073 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6077 EVT CanonicalVT = VTys[SplatSize-1];
6079 // Build a canonical splat for this value.
6080 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6081 SmallVector<SDValue, 8> Ops;
6082 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6083 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6084 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6087 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6088 /// specified intrinsic ID.
6089 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6090 SelectionDAG &DAG, SDLoc dl,
6091 EVT DestVT = MVT::Other) {
6092 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6093 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6094 DAG.getConstant(IID, MVT::i32), Op);
6097 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6098 /// specified intrinsic ID.
6099 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6100 SelectionDAG &DAG, SDLoc dl,
6101 EVT DestVT = MVT::Other) {
6102 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6104 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6107 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6108 /// specified intrinsic ID.
6109 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6110 SDValue Op2, SelectionDAG &DAG,
6111 SDLoc dl, EVT DestVT = MVT::Other) {
6112 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6113 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6114 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6118 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6119 /// amount. The result has the specified value type.
6120 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6121 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6122 // Force LHS/RHS to be the right type.
6123 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6124 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6127 for (unsigned i = 0; i != 16; ++i)
6129 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6130 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6133 // If this is a case we can't handle, return null and let the default
6134 // expansion code take care of it. If we CAN select this case, and if it
6135 // selects to a single instruction, return Op. Otherwise, if we can codegen
6136 // this case more efficiently than a constant pool load, lower it to the
6137 // sequence of ops that should be used.
6138 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6139 SelectionDAG &DAG) const {
6141 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6142 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6144 // Check if this is a splat of a constant value.
6145 APInt APSplatBits, APSplatUndef;
6146 unsigned SplatBitSize;
6148 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6149 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6152 unsigned SplatBits = APSplatBits.getZExtValue();
6153 unsigned SplatUndef = APSplatUndef.getZExtValue();
6154 unsigned SplatSize = SplatBitSize / 8;
6156 // First, handle single instruction cases.
6159 if (SplatBits == 0) {
6160 // Canonicalize all zero vectors to be v4i32.
6161 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6162 SDValue Z = DAG.getConstant(0, MVT::i32);
6163 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6164 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6169 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6170 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6172 if (SextVal >= -16 && SextVal <= 15)
6173 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6176 // Two instruction sequences.
6178 // If this value is in the range [-32,30] and is even, use:
6179 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6180 // If this value is in the range [17,31] and is odd, use:
6181 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6182 // If this value is in the range [-31,-17] and is odd, use:
6183 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6184 // Note the last two are three-instruction sequences.
6185 if (SextVal >= -32 && SextVal <= 31) {
6186 // To avoid having these optimizations undone by constant folding,
6187 // we convert to a pseudo that will be expanded later into one of
6189 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6190 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6191 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6192 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6193 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6194 if (VT == Op.getValueType())
6197 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6200 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6201 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6203 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6204 // Make -1 and vspltisw -1:
6205 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6207 // Make the VSLW intrinsic, computing 0x8000_0000.
6208 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6211 // xor by OnesV to invert it.
6212 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6213 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6216 // The remaining cases assume either big endian element order or
6217 // a splat-size that equates to the element size of the vector
6218 // to be built. An example that doesn't work for little endian is
6219 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6220 // and a vector element size of 16 bits. The code below will
6221 // produce the vector in big endian element order, which for little
6222 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6224 // For now, just avoid these optimizations in that case.
6225 // FIXME: Develop correct optimizations for LE with mismatched
6226 // splat and element sizes.
6228 if (Subtarget.isLittleEndian() &&
6229 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6232 // Check to see if this is a wide variety of vsplti*, binop self cases.
6233 static const signed char SplatCsts[] = {
6234 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6235 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6238 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6239 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6240 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6241 int i = SplatCsts[idx];
6243 // Figure out what shift amount will be used by altivec if shifted by i in
6245 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6247 // vsplti + shl self.
6248 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6249 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6250 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6251 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6252 Intrinsic::ppc_altivec_vslw
6254 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6255 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6258 // vsplti + srl self.
6259 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6260 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6261 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6262 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6263 Intrinsic::ppc_altivec_vsrw
6265 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6266 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6269 // vsplti + sra self.
6270 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6271 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6272 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6273 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6274 Intrinsic::ppc_altivec_vsraw
6276 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6277 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6280 // vsplti + rol self.
6281 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6282 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6283 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6284 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6285 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6286 Intrinsic::ppc_altivec_vrlw
6288 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6289 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6292 // t = vsplti c, result = vsldoi t, t, 1
6293 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6294 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6295 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6297 // t = vsplti c, result = vsldoi t, t, 2
6298 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6299 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6300 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6302 // t = vsplti c, result = vsldoi t, t, 3
6303 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6304 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6305 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6312 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6313 /// the specified operations to build the shuffle.
6314 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6315 SDValue RHS, SelectionDAG &DAG,
6317 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6318 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6319 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6322 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6334 if (OpNum == OP_COPY) {
6335 if (LHSID == (1*9+2)*9+3) return LHS;
6336 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6340 SDValue OpLHS, OpRHS;
6341 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6342 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6346 default: llvm_unreachable("Unknown i32 permute!");
6348 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6349 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6350 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6351 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6354 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6355 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6356 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6357 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6360 for (unsigned i = 0; i != 16; ++i)
6361 ShufIdxs[i] = (i&3)+0;
6364 for (unsigned i = 0; i != 16; ++i)
6365 ShufIdxs[i] = (i&3)+4;
6368 for (unsigned i = 0; i != 16; ++i)
6369 ShufIdxs[i] = (i&3)+8;
6372 for (unsigned i = 0; i != 16; ++i)
6373 ShufIdxs[i] = (i&3)+12;
6376 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6378 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6380 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6382 EVT VT = OpLHS.getValueType();
6383 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6384 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6385 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6386 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6389 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6390 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6391 /// return the code it can be lowered into. Worst case, it can always be
6392 /// lowered into a vperm.
6393 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6394 SelectionDAG &DAG) const {
6396 SDValue V1 = Op.getOperand(0);
6397 SDValue V2 = Op.getOperand(1);
6398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6399 EVT VT = Op.getValueType();
6400 bool isLittleEndian = Subtarget.isLittleEndian();
6402 // Cases that are handled by instructions that take permute immediates
6403 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6404 // selected by the instruction selector.
6405 if (V2.getOpcode() == ISD::UNDEF) {
6406 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6407 PPC::isSplatShuffleMask(SVOp, 2) ||
6408 PPC::isSplatShuffleMask(SVOp, 4) ||
6409 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6410 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6411 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6412 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6413 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6414 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6415 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6416 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6417 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6422 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6423 // and produce a fixed permutation. If any of these match, do not lower to
6425 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6426 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6427 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6428 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6429 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6430 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6431 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6432 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6433 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6434 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6437 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6438 // perfect shuffle table to emit an optimal matching sequence.
6439 ArrayRef<int> PermMask = SVOp->getMask();
6441 unsigned PFIndexes[4];
6442 bool isFourElementShuffle = true;
6443 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6444 unsigned EltNo = 8; // Start out undef.
6445 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6446 if (PermMask[i*4+j] < 0)
6447 continue; // Undef, ignore it.
6449 unsigned ByteSource = PermMask[i*4+j];
6450 if ((ByteSource & 3) != j) {
6451 isFourElementShuffle = false;
6456 EltNo = ByteSource/4;
6457 } else if (EltNo != ByteSource/4) {
6458 isFourElementShuffle = false;
6462 PFIndexes[i] = EltNo;
6465 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6466 // perfect shuffle vector to determine if it is cost effective to do this as
6467 // discrete instructions, or whether we should use a vperm.
6468 // For now, we skip this for little endian until such time as we have a
6469 // little-endian perfect shuffle table.
6470 if (isFourElementShuffle && !isLittleEndian) {
6471 // Compute the index in the perfect shuffle table.
6472 unsigned PFTableIndex =
6473 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6475 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6476 unsigned Cost = (PFEntry >> 30);
6478 // Determining when to avoid vperm is tricky. Many things affect the cost
6479 // of vperm, particularly how many times the perm mask needs to be computed.
6480 // For example, if the perm mask can be hoisted out of a loop or is already
6481 // used (perhaps because there are multiple permutes with the same shuffle
6482 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6483 // the loop requires an extra register.
6485 // As a compromise, we only emit discrete instructions if the shuffle can be
6486 // generated in 3 or fewer operations. When we have loop information
6487 // available, if this block is within a loop, we should avoid using vperm
6488 // for 3-operation perms and use a constant pool load instead.
6490 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6493 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6494 // vector that will get spilled to the constant pool.
6495 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6497 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6498 // that it is in input element units, not in bytes. Convert now.
6500 // For little endian, the order of the input vectors is reversed, and
6501 // the permutation mask is complemented with respect to 31. This is
6502 // necessary to produce proper semantics with the big-endian-biased vperm
6504 EVT EltVT = V1.getValueType().getVectorElementType();
6505 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6507 SmallVector<SDValue, 16> ResultMask;
6508 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6509 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6511 for (unsigned j = 0; j != BytesPerElement; ++j)
6513 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6516 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6520 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6523 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6526 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6530 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6531 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6532 /// information about the intrinsic.
6533 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6535 unsigned IntrinsicID =
6536 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6539 switch (IntrinsicID) {
6540 default: return false;
6541 // Comparison predicates.
6542 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6543 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6544 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6545 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6546 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6547 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6548 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6549 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6550 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6551 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6552 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6553 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6554 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6556 // Normal Comparisons.
6557 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6558 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6559 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6560 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6561 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6562 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6563 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6564 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6565 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6566 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6567 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6568 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6569 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6574 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6575 /// lower, do it, otherwise return null.
6576 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6577 SelectionDAG &DAG) const {
6578 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6579 // opcode number of the comparison.
6583 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6584 return SDValue(); // Don't custom lower most intrinsics.
6586 // If this is a non-dot comparison, make the VCMP node and we are done.
6588 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6589 Op.getOperand(1), Op.getOperand(2),
6590 DAG.getConstant(CompareOpc, MVT::i32));
6591 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6594 // Create the PPCISD altivec 'dot' comparison node.
6596 Op.getOperand(2), // LHS
6597 Op.getOperand(3), // RHS
6598 DAG.getConstant(CompareOpc, MVT::i32)
6600 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6601 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6603 // Now that we have the comparison, emit a copy from the CR to a GPR.
6604 // This is flagged to the above dot comparison.
6605 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6606 DAG.getRegister(PPC::CR6, MVT::i32),
6607 CompNode.getValue(1));
6609 // Unpack the result based on how the target uses it.
6610 unsigned BitNo; // Bit # of CR6.
6611 bool InvertBit; // Invert result?
6612 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6613 default: // Can't happen, don't crash on invalid number though.
6614 case 0: // Return the value of the EQ bit of CR6.
6615 BitNo = 0; InvertBit = false;
6617 case 1: // Return the inverted value of the EQ bit of CR6.
6618 BitNo = 0; InvertBit = true;
6620 case 2: // Return the value of the LT bit of CR6.
6621 BitNo = 2; InvertBit = false;
6623 case 3: // Return the inverted value of the LT bit of CR6.
6624 BitNo = 2; InvertBit = true;
6628 // Shift the bit into the low position.
6629 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6630 DAG.getConstant(8-(3-BitNo), MVT::i32));
6632 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6633 DAG.getConstant(1, MVT::i32));
6635 // If we are supposed to, toggle the bit.
6637 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6638 DAG.getConstant(1, MVT::i32));
6642 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6643 SelectionDAG &DAG) const {
6645 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6646 // instructions), but for smaller types, we need to first extend up to v2i32
6647 // before doing going farther.
6648 if (Op.getValueType() == MVT::v2i64) {
6649 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6650 if (ExtVT != MVT::v2i32) {
6651 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6652 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6653 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6654 ExtVT.getVectorElementType(), 4)));
6655 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6656 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6657 DAG.getValueType(MVT::v2i32));
6666 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6667 SelectionDAG &DAG) const {
6669 // Create a stack slot that is 16-byte aligned.
6670 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6671 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6672 EVT PtrVT = getPointerTy();
6673 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6675 // Store the input value into Value#0 of the stack slot.
6676 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6677 Op.getOperand(0), FIdx, MachinePointerInfo(),
6680 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6681 false, false, false, 0);
6684 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6686 if (Op.getValueType() == MVT::v4i32) {
6687 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6689 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6690 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6692 SDValue RHSSwap = // = vrlw RHS, 16
6693 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6695 // Shrinkify inputs to v8i16.
6696 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6697 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6698 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6700 // Low parts multiplied together, generating 32-bit results (we ignore the
6702 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6703 LHS, RHS, DAG, dl, MVT::v4i32);
6705 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6706 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6707 // Shift the high parts up 16 bits.
6708 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6710 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6711 } else if (Op.getValueType() == MVT::v8i16) {
6712 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6714 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6716 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6717 LHS, RHS, Zero, DAG, dl);
6718 } else if (Op.getValueType() == MVT::v16i8) {
6719 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6720 bool isLittleEndian = Subtarget.isLittleEndian();
6722 // Multiply the even 8-bit parts, producing 16-bit sums.
6723 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6724 LHS, RHS, DAG, dl, MVT::v8i16);
6725 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6727 // Multiply the odd 8-bit parts, producing 16-bit sums.
6728 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6729 LHS, RHS, DAG, dl, MVT::v8i16);
6730 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6732 // Merge the results together. Because vmuleub and vmuloub are
6733 // instructions with a big-endian bias, we must reverse the
6734 // element numbering and reverse the meaning of "odd" and "even"
6735 // when generating little endian code.
6737 for (unsigned i = 0; i != 8; ++i) {
6738 if (isLittleEndian) {
6740 Ops[i*2+1] = 2*i+16;
6743 Ops[i*2+1] = 2*i+1+16;
6747 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6749 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6751 llvm_unreachable("Unknown mul to lower!");
6755 /// LowerOperation - Provide custom lowering hooks for some operations.
6757 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6758 switch (Op.getOpcode()) {
6759 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6760 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6761 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6762 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6763 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6764 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6765 case ISD::SETCC: return LowerSETCC(Op, DAG);
6766 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6767 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6769 return LowerVASTART(Op, DAG, Subtarget);
6772 return LowerVAARG(Op, DAG, Subtarget);
6775 return LowerVACOPY(Op, DAG, Subtarget);
6777 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6778 case ISD::DYNAMIC_STACKALLOC:
6779 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6781 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6782 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6784 case ISD::LOAD: return LowerLOAD(Op, DAG);
6785 case ISD::STORE: return LowerSTORE(Op, DAG);
6786 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6787 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6788 case ISD::FP_TO_UINT:
6789 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6791 case ISD::UINT_TO_FP:
6792 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6793 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6795 // Lower 64-bit shifts.
6796 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6797 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6798 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6800 // Vector-related lowering.
6801 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6802 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6803 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6804 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6805 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6806 case ISD::MUL: return LowerMUL(Op, DAG);
6808 // For counter-based loop handling.
6809 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6811 // Frame & Return address.
6812 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6813 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6817 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6818 SmallVectorImpl<SDValue>&Results,
6819 SelectionDAG &DAG) const {
6821 switch (N->getOpcode()) {
6823 llvm_unreachable("Do not know how to custom type legalize this operation!");
6824 case ISD::READCYCLECOUNTER: {
6825 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6826 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6828 Results.push_back(RTB);
6829 Results.push_back(RTB.getValue(1));
6830 Results.push_back(RTB.getValue(2));
6833 case ISD::INTRINSIC_W_CHAIN: {
6834 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6835 Intrinsic::ppc_is_decremented_ctr_nonzero)
6838 assert(N->getValueType(0) == MVT::i1 &&
6839 "Unexpected result type for CTR decrement intrinsic");
6840 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6841 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6842 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6845 Results.push_back(NewInt);
6846 Results.push_back(NewInt.getValue(1));
6850 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
6853 EVT VT = N->getValueType(0);
6855 if (VT == MVT::i64) {
6856 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6858 Results.push_back(NewNode);
6859 Results.push_back(NewNode.getValue(1));
6863 case ISD::FP_ROUND_INREG: {
6864 assert(N->getValueType(0) == MVT::ppcf128);
6865 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6866 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6867 MVT::f64, N->getOperand(0),
6868 DAG.getIntPtrConstant(0));
6869 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6870 MVT::f64, N->getOperand(0),
6871 DAG.getIntPtrConstant(1));
6873 // Add the two halves of the long double in round-to-zero mode.
6874 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6876 // We know the low half is about to be thrown away, so just use something
6878 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6882 case ISD::FP_TO_SINT:
6883 // LowerFP_TO_INT() can only handle f32 and f64.
6884 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6886 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6892 //===----------------------------------------------------------------------===//
6893 // Other Lowering Code
6894 //===----------------------------------------------------------------------===//
6896 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6897 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6898 Function *Func = Intrinsic::getDeclaration(M, Id);
6899 return Builder.CreateCall(Func);
6902 // The mappings for emitLeading/TrailingFence is taken from
6903 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6904 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6905 AtomicOrdering Ord, bool IsStore,
6906 bool IsLoad) const {
6907 if (Ord == SequentiallyConsistent)
6908 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6909 else if (isAtLeastRelease(Ord))
6910 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6915 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6916 AtomicOrdering Ord, bool IsStore,
6917 bool IsLoad) const {
6918 if (IsLoad && isAtLeastAcquire(Ord))
6919 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6920 // FIXME: this is too conservative, a dependent branch + isync is enough.
6921 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6922 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6923 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6929 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6930 bool is64bit, unsigned BinOpcode) const {
6931 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6932 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6934 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6935 MachineFunction *F = BB->getParent();
6936 MachineFunction::iterator It = BB;
6939 unsigned dest = MI->getOperand(0).getReg();
6940 unsigned ptrA = MI->getOperand(1).getReg();
6941 unsigned ptrB = MI->getOperand(2).getReg();
6942 unsigned incr = MI->getOperand(3).getReg();
6943 DebugLoc dl = MI->getDebugLoc();
6945 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6946 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6947 F->insert(It, loopMBB);
6948 F->insert(It, exitMBB);
6949 exitMBB->splice(exitMBB->begin(), BB,
6950 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6951 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6953 MachineRegisterInfo &RegInfo = F->getRegInfo();
6954 unsigned TmpReg = (!BinOpcode) ? incr :
6955 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6956 : &PPC::GPRCRegClass);
6960 // fallthrough --> loopMBB
6961 BB->addSuccessor(loopMBB);
6964 // l[wd]arx dest, ptr
6965 // add r0, dest, incr
6966 // st[wd]cx. r0, ptr
6968 // fallthrough --> exitMBB
6970 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6971 .addReg(ptrA).addReg(ptrB);
6973 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6974 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6975 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6976 BuildMI(BB, dl, TII->get(PPC::BCC))
6977 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6978 BB->addSuccessor(loopMBB);
6979 BB->addSuccessor(exitMBB);
6988 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6989 MachineBasicBlock *BB,
6990 bool is8bit, // operation
6991 unsigned BinOpcode) const {
6992 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6993 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6994 // In 64 bit mode we have to use 64 bits for addresses, even though the
6995 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6996 // registers without caring whether they're 32 or 64, but here we're
6997 // doing actual arithmetic on the addresses.
6998 bool is64bit = Subtarget.isPPC64();
6999 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7001 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7002 MachineFunction *F = BB->getParent();
7003 MachineFunction::iterator It = BB;
7006 unsigned dest = MI->getOperand(0).getReg();
7007 unsigned ptrA = MI->getOperand(1).getReg();
7008 unsigned ptrB = MI->getOperand(2).getReg();
7009 unsigned incr = MI->getOperand(3).getReg();
7010 DebugLoc dl = MI->getDebugLoc();
7012 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7013 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7014 F->insert(It, loopMBB);
7015 F->insert(It, exitMBB);
7016 exitMBB->splice(exitMBB->begin(), BB,
7017 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7018 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7020 MachineRegisterInfo &RegInfo = F->getRegInfo();
7021 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7022 : &PPC::GPRCRegClass;
7023 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7024 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7025 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7026 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7027 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7028 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7029 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7030 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7031 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7032 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7033 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7035 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7039 // fallthrough --> loopMBB
7040 BB->addSuccessor(loopMBB);
7042 // The 4-byte load must be aligned, while a char or short may be
7043 // anywhere in the word. Hence all this nasty bookkeeping code.
7044 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7045 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7046 // xori shift, shift1, 24 [16]
7047 // rlwinm ptr, ptr1, 0, 0, 29
7048 // slw incr2, incr, shift
7049 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7050 // slw mask, mask2, shift
7052 // lwarx tmpDest, ptr
7053 // add tmp, tmpDest, incr2
7054 // andc tmp2, tmpDest, mask
7055 // and tmp3, tmp, mask
7056 // or tmp4, tmp3, tmp2
7059 // fallthrough --> exitMBB
7060 // srw dest, tmpDest, shift
7061 if (ptrA != ZeroReg) {
7062 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7063 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7064 .addReg(ptrA).addReg(ptrB);
7068 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7069 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7070 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7071 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7073 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7074 .addReg(Ptr1Reg).addImm(0).addImm(61);
7076 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7077 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7078 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7079 .addReg(incr).addReg(ShiftReg);
7081 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7083 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7084 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7086 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7087 .addReg(Mask2Reg).addReg(ShiftReg);
7090 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7091 .addReg(ZeroReg).addReg(PtrReg);
7093 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7094 .addReg(Incr2Reg).addReg(TmpDestReg);
7095 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7096 .addReg(TmpDestReg).addReg(MaskReg);
7097 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7098 .addReg(TmpReg).addReg(MaskReg);
7099 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7100 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7101 BuildMI(BB, dl, TII->get(PPC::STWCX))
7102 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7103 BuildMI(BB, dl, TII->get(PPC::BCC))
7104 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7105 BB->addSuccessor(loopMBB);
7106 BB->addSuccessor(exitMBB);
7111 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7116 llvm::MachineBasicBlock*
7117 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7118 MachineBasicBlock *MBB) const {
7119 DebugLoc DL = MI->getDebugLoc();
7120 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7122 MachineFunction *MF = MBB->getParent();
7123 MachineRegisterInfo &MRI = MF->getRegInfo();
7125 const BasicBlock *BB = MBB->getBasicBlock();
7126 MachineFunction::iterator I = MBB;
7130 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7131 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7133 unsigned DstReg = MI->getOperand(0).getReg();
7134 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7135 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7136 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7137 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7139 MVT PVT = getPointerTy();
7140 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7141 "Invalid Pointer Size!");
7142 // For v = setjmp(buf), we generate
7145 // SjLjSetup mainMBB
7151 // buf[LabelOffset] = LR
7155 // v = phi(main, restore)
7158 MachineBasicBlock *thisMBB = MBB;
7159 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7160 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7161 MF->insert(I, mainMBB);
7162 MF->insert(I, sinkMBB);
7164 MachineInstrBuilder MIB;
7166 // Transfer the remainder of BB and its successor edges to sinkMBB.
7167 sinkMBB->splice(sinkMBB->begin(), MBB,
7168 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7169 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7171 // Note that the structure of the jmp_buf used here is not compatible
7172 // with that used by libc, and is not designed to be. Specifically, it
7173 // stores only those 'reserved' registers that LLVM does not otherwise
7174 // understand how to spill. Also, by convention, by the time this
7175 // intrinsic is called, Clang has already stored the frame address in the
7176 // first slot of the buffer and stack address in the third. Following the
7177 // X86 target code, we'll store the jump address in the second slot. We also
7178 // need to save the TOC pointer (R2) to handle jumps between shared
7179 // libraries, and that will be stored in the fourth slot. The thread
7180 // identifier (R13) is not affected.
7183 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7184 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7185 const int64_t BPOffset = 4 * PVT.getStoreSize();
7187 // Prepare IP either in reg.
7188 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7189 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7190 unsigned BufReg = MI->getOperand(1).getReg();
7192 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7193 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7197 MIB.setMemRefs(MMOBegin, MMOEnd);
7200 // Naked functions never have a base pointer, and so we use r1. For all
7201 // other functions, this decision must be delayed until during PEI.
7203 if (MF->getFunction()->getAttributes().hasAttribute(
7204 AttributeSet::FunctionIndex, Attribute::Naked))
7205 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7207 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7209 MIB = BuildMI(*thisMBB, MI, DL,
7210 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7214 MIB.setMemRefs(MMOBegin, MMOEnd);
7217 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7218 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
7219 MIB.addRegMask(TRI->getNoPreservedMask());
7221 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7223 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7225 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7227 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7228 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7233 BuildMI(mainMBB, DL,
7234 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7237 if (Subtarget.isPPC64()) {
7238 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7240 .addImm(LabelOffset)
7243 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7245 .addImm(LabelOffset)
7249 MIB.setMemRefs(MMOBegin, MMOEnd);
7251 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7252 mainMBB->addSuccessor(sinkMBB);
7255 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7256 TII->get(PPC::PHI), DstReg)
7257 .addReg(mainDstReg).addMBB(mainMBB)
7258 .addReg(restoreDstReg).addMBB(thisMBB);
7260 MI->eraseFromParent();
7265 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7266 MachineBasicBlock *MBB) const {
7267 DebugLoc DL = MI->getDebugLoc();
7268 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7270 MachineFunction *MF = MBB->getParent();
7271 MachineRegisterInfo &MRI = MF->getRegInfo();
7274 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7275 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7277 MVT PVT = getPointerTy();
7278 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7279 "Invalid Pointer Size!");
7281 const TargetRegisterClass *RC =
7282 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7283 unsigned Tmp = MRI.createVirtualRegister(RC);
7284 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7285 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7286 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7290 : (Subtarget.isSVR4ABI() &&
7291 MF->getTarget().getRelocationModel() == Reloc::PIC_
7295 MachineInstrBuilder MIB;
7297 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7298 const int64_t SPOffset = 2 * PVT.getStoreSize();
7299 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7300 const int64_t BPOffset = 4 * PVT.getStoreSize();
7302 unsigned BufReg = MI->getOperand(0).getReg();
7304 // Reload FP (the jumped-to function may not have had a
7305 // frame pointer, and if so, then its r31 will be restored
7307 if (PVT == MVT::i64) {
7308 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7312 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7316 MIB.setMemRefs(MMOBegin, MMOEnd);
7319 if (PVT == MVT::i64) {
7320 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7321 .addImm(LabelOffset)
7324 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7325 .addImm(LabelOffset)
7328 MIB.setMemRefs(MMOBegin, MMOEnd);
7331 if (PVT == MVT::i64) {
7332 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7336 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7340 MIB.setMemRefs(MMOBegin, MMOEnd);
7343 if (PVT == MVT::i64) {
7344 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7348 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7352 MIB.setMemRefs(MMOBegin, MMOEnd);
7355 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7356 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7360 MIB.setMemRefs(MMOBegin, MMOEnd);
7364 BuildMI(*MBB, MI, DL,
7365 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7366 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7368 MI->eraseFromParent();
7373 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7374 MachineBasicBlock *BB) const {
7375 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7376 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7377 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
7378 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7379 // Call lowering should have added an r2 operand to indicate a dependence
7380 // on the TOC base pointer value. It can't however, because there is no
7381 // way to mark the dependence as implicit there, and so the stackmap code
7382 // will confuse it with a regular operand. Instead, add the dependence
7384 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
7387 return emitPatchPoint(MI, BB);
7390 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7391 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7392 return emitEHSjLjSetJmp(MI, BB);
7393 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7394 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7395 return emitEHSjLjLongJmp(MI, BB);
7398 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7400 // To "insert" these instructions we actually have to insert their
7401 // control-flow patterns.
7402 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7403 MachineFunction::iterator It = BB;
7406 MachineFunction *F = BB->getParent();
7408 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7409 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7410 MI->getOpcode() == PPC::SELECT_I4 ||
7411 MI->getOpcode() == PPC::SELECT_I8)) {
7412 SmallVector<MachineOperand, 2> Cond;
7413 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7414 MI->getOpcode() == PPC::SELECT_CC_I8)
7415 Cond.push_back(MI->getOperand(4));
7417 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7418 Cond.push_back(MI->getOperand(1));
7420 DebugLoc dl = MI->getDebugLoc();
7421 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7422 Cond, MI->getOperand(2).getReg(),
7423 MI->getOperand(3).getReg());
7424 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7425 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7426 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7427 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7428 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7429 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7430 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7431 MI->getOpcode() == PPC::SELECT_I4 ||
7432 MI->getOpcode() == PPC::SELECT_I8 ||
7433 MI->getOpcode() == PPC::SELECT_F4 ||
7434 MI->getOpcode() == PPC::SELECT_F8 ||
7435 MI->getOpcode() == PPC::SELECT_VRRC ||
7436 MI->getOpcode() == PPC::SELECT_VSFRC ||
7437 MI->getOpcode() == PPC::SELECT_VSRC) {
7438 // The incoming instruction knows the destination vreg to set, the
7439 // condition code register to branch on, the true/false values to
7440 // select between, and a branch opcode to use.
7445 // cmpTY ccX, r1, r2
7447 // fallthrough --> copy0MBB
7448 MachineBasicBlock *thisMBB = BB;
7449 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7450 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7451 DebugLoc dl = MI->getDebugLoc();
7452 F->insert(It, copy0MBB);
7453 F->insert(It, sinkMBB);
7455 // Transfer the remainder of BB and its successor edges to sinkMBB.
7456 sinkMBB->splice(sinkMBB->begin(), BB,
7457 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7458 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7460 // Next, add the true and fallthrough blocks as its successors.
7461 BB->addSuccessor(copy0MBB);
7462 BB->addSuccessor(sinkMBB);
7464 if (MI->getOpcode() == PPC::SELECT_I4 ||
7465 MI->getOpcode() == PPC::SELECT_I8 ||
7466 MI->getOpcode() == PPC::SELECT_F4 ||
7467 MI->getOpcode() == PPC::SELECT_F8 ||
7468 MI->getOpcode() == PPC::SELECT_VRRC ||
7469 MI->getOpcode() == PPC::SELECT_VSFRC ||
7470 MI->getOpcode() == PPC::SELECT_VSRC) {
7471 BuildMI(BB, dl, TII->get(PPC::BC))
7472 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7474 unsigned SelectPred = MI->getOperand(4).getImm();
7475 BuildMI(BB, dl, TII->get(PPC::BCC))
7476 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7480 // %FalseValue = ...
7481 // # fallthrough to sinkMBB
7484 // Update machine-CFG edges
7485 BB->addSuccessor(sinkMBB);
7488 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7491 BuildMI(*BB, BB->begin(), dl,
7492 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7493 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7494 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7495 } else if (MI->getOpcode() == PPC::ReadTB) {
7496 // To read the 64-bit time-base register on a 32-bit target, we read the
7497 // two halves. Should the counter have wrapped while it was being read, we
7498 // need to try again.
7501 // mfspr Rx,TBU # load from TBU
7502 // mfspr Ry,TB # load from TB
7503 // mfspr Rz,TBU # load from TBU
7504 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7505 // bne readLoop # branch if they're not equal
7508 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7509 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7510 DebugLoc dl = MI->getDebugLoc();
7511 F->insert(It, readMBB);
7512 F->insert(It, sinkMBB);
7514 // Transfer the remainder of BB and its successor edges to sinkMBB.
7515 sinkMBB->splice(sinkMBB->begin(), BB,
7516 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7517 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7519 BB->addSuccessor(readMBB);
7522 MachineRegisterInfo &RegInfo = F->getRegInfo();
7523 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7524 unsigned LoReg = MI->getOperand(0).getReg();
7525 unsigned HiReg = MI->getOperand(1).getReg();
7527 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7528 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7529 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7531 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7533 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7534 .addReg(HiReg).addReg(ReadAgainReg);
7535 BuildMI(BB, dl, TII->get(PPC::BCC))
7536 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7538 BB->addSuccessor(readMBB);
7539 BB->addSuccessor(sinkMBB);
7541 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7542 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7543 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7544 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7545 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7546 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7547 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7548 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7550 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7551 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7552 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7553 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7554 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7555 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7556 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7557 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7559 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7560 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7561 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7562 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7563 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7564 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7565 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7566 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7569 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7571 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7573 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7574 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7575 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7577 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7578 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7579 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7580 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7582 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7583 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7584 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7586 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7587 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7588 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7589 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7590 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7591 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7592 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7593 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7595 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7596 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7597 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7598 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7599 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7600 BB = EmitAtomicBinary(MI, BB, false, 0);
7601 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7602 BB = EmitAtomicBinary(MI, BB, true, 0);
7604 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7605 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7606 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7608 unsigned dest = MI->getOperand(0).getReg();
7609 unsigned ptrA = MI->getOperand(1).getReg();
7610 unsigned ptrB = MI->getOperand(2).getReg();
7611 unsigned oldval = MI->getOperand(3).getReg();
7612 unsigned newval = MI->getOperand(4).getReg();
7613 DebugLoc dl = MI->getDebugLoc();
7615 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7616 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7617 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7618 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7619 F->insert(It, loop1MBB);
7620 F->insert(It, loop2MBB);
7621 F->insert(It, midMBB);
7622 F->insert(It, exitMBB);
7623 exitMBB->splice(exitMBB->begin(), BB,
7624 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7625 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7629 // fallthrough --> loopMBB
7630 BB->addSuccessor(loop1MBB);
7633 // l[wd]arx dest, ptr
7634 // cmp[wd] dest, oldval
7637 // st[wd]cx. newval, ptr
7641 // st[wd]cx. dest, ptr
7644 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7645 .addReg(ptrA).addReg(ptrB);
7646 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7647 .addReg(oldval).addReg(dest);
7648 BuildMI(BB, dl, TII->get(PPC::BCC))
7649 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7650 BB->addSuccessor(loop2MBB);
7651 BB->addSuccessor(midMBB);
7654 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7655 .addReg(newval).addReg(ptrA).addReg(ptrB);
7656 BuildMI(BB, dl, TII->get(PPC::BCC))
7657 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7658 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7659 BB->addSuccessor(loop1MBB);
7660 BB->addSuccessor(exitMBB);
7663 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7664 .addReg(dest).addReg(ptrA).addReg(ptrB);
7665 BB->addSuccessor(exitMBB);
7670 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7671 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7672 // We must use 64-bit registers for addresses when targeting 64-bit,
7673 // since we're actually doing arithmetic on them. Other registers
7675 bool is64bit = Subtarget.isPPC64();
7676 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7678 unsigned dest = MI->getOperand(0).getReg();
7679 unsigned ptrA = MI->getOperand(1).getReg();
7680 unsigned ptrB = MI->getOperand(2).getReg();
7681 unsigned oldval = MI->getOperand(3).getReg();
7682 unsigned newval = MI->getOperand(4).getReg();
7683 DebugLoc dl = MI->getDebugLoc();
7685 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7686 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7687 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7688 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7689 F->insert(It, loop1MBB);
7690 F->insert(It, loop2MBB);
7691 F->insert(It, midMBB);
7692 F->insert(It, exitMBB);
7693 exitMBB->splice(exitMBB->begin(), BB,
7694 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7695 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7697 MachineRegisterInfo &RegInfo = F->getRegInfo();
7698 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7699 : &PPC::GPRCRegClass;
7700 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7701 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7702 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7703 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7704 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7705 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7706 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7707 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7708 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7709 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7710 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7711 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7712 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7714 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7715 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7718 // fallthrough --> loopMBB
7719 BB->addSuccessor(loop1MBB);
7721 // The 4-byte load must be aligned, while a char or short may be
7722 // anywhere in the word. Hence all this nasty bookkeeping code.
7723 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7724 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7725 // xori shift, shift1, 24 [16]
7726 // rlwinm ptr, ptr1, 0, 0, 29
7727 // slw newval2, newval, shift
7728 // slw oldval2, oldval,shift
7729 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7730 // slw mask, mask2, shift
7731 // and newval3, newval2, mask
7732 // and oldval3, oldval2, mask
7734 // lwarx tmpDest, ptr
7735 // and tmp, tmpDest, mask
7736 // cmpw tmp, oldval3
7739 // andc tmp2, tmpDest, mask
7740 // or tmp4, tmp2, newval3
7745 // stwcx. tmpDest, ptr
7747 // srw dest, tmpDest, shift
7748 if (ptrA != ZeroReg) {
7749 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7750 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7751 .addReg(ptrA).addReg(ptrB);
7755 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7756 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7757 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7758 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7760 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7761 .addReg(Ptr1Reg).addImm(0).addImm(61);
7763 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7764 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7765 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7766 .addReg(newval).addReg(ShiftReg);
7767 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7768 .addReg(oldval).addReg(ShiftReg);
7770 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7772 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7773 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7774 .addReg(Mask3Reg).addImm(65535);
7776 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7777 .addReg(Mask2Reg).addReg(ShiftReg);
7778 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7779 .addReg(NewVal2Reg).addReg(MaskReg);
7780 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7781 .addReg(OldVal2Reg).addReg(MaskReg);
7784 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7785 .addReg(ZeroReg).addReg(PtrReg);
7786 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7787 .addReg(TmpDestReg).addReg(MaskReg);
7788 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7789 .addReg(TmpReg).addReg(OldVal3Reg);
7790 BuildMI(BB, dl, TII->get(PPC::BCC))
7791 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7792 BB->addSuccessor(loop2MBB);
7793 BB->addSuccessor(midMBB);
7796 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7797 .addReg(TmpDestReg).addReg(MaskReg);
7798 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7799 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7800 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7801 .addReg(ZeroReg).addReg(PtrReg);
7802 BuildMI(BB, dl, TII->get(PPC::BCC))
7803 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7804 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7805 BB->addSuccessor(loop1MBB);
7806 BB->addSuccessor(exitMBB);
7809 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7810 .addReg(ZeroReg).addReg(PtrReg);
7811 BB->addSuccessor(exitMBB);
7816 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7818 } else if (MI->getOpcode() == PPC::FADDrtz) {
7819 // This pseudo performs an FADD with rounding mode temporarily forced
7820 // to round-to-zero. We emit this via custom inserter since the FPSCR
7821 // is not modeled at the SelectionDAG level.
7822 unsigned Dest = MI->getOperand(0).getReg();
7823 unsigned Src1 = MI->getOperand(1).getReg();
7824 unsigned Src2 = MI->getOperand(2).getReg();
7825 DebugLoc dl = MI->getDebugLoc();
7827 MachineRegisterInfo &RegInfo = F->getRegInfo();
7828 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7830 // Save FPSCR value.
7831 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7833 // Set rounding mode to round-to-zero.
7834 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7835 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7837 // Perform addition.
7838 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7840 // Restore FPSCR value.
7841 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7842 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7843 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7844 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7845 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7846 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7847 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7848 PPC::ANDIo8 : PPC::ANDIo;
7849 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7850 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7852 MachineRegisterInfo &RegInfo = F->getRegInfo();
7853 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7854 &PPC::GPRCRegClass :
7855 &PPC::G8RCRegClass);
7857 DebugLoc dl = MI->getDebugLoc();
7858 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7859 .addReg(MI->getOperand(1).getReg()).addImm(1);
7860 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7861 MI->getOperand(0).getReg())
7862 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7864 llvm_unreachable("Unexpected instr type to insert");
7867 MI->eraseFromParent(); // The pseudo instruction is gone now.
7871 //===----------------------------------------------------------------------===//
7872 // Target Optimization Hooks
7873 //===----------------------------------------------------------------------===//
7875 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7876 DAGCombinerInfo &DCI,
7877 unsigned &RefinementSteps,
7878 bool &UseOneConstNR) const {
7879 EVT VT = Operand.getValueType();
7880 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7881 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7882 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7883 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7884 // Convergence is quadratic, so we essentially double the number of digits
7885 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7886 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7887 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7888 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7889 if (VT.getScalarType() == MVT::f64)
7891 UseOneConstNR = true;
7892 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7897 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7898 DAGCombinerInfo &DCI,
7899 unsigned &RefinementSteps) const {
7900 EVT VT = Operand.getValueType();
7901 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7902 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7903 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7904 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7905 // Convergence is quadratic, so we essentially double the number of digits
7906 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7907 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7908 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7909 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7910 if (VT.getScalarType() == MVT::f64)
7912 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7917 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7918 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7919 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7920 // enabled for division), this functionality is redundant with the default
7921 // combiner logic (once the division -> reciprocal/multiply transformation
7922 // has taken place). As a result, this matters more for older cores than for
7925 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7926 // reciprocal if there are two or more FDIVs (for embedded cores with only
7927 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7928 switch (Subtarget.getDarwinDirective()) {
7930 return NumUsers > 2;
7933 case PPC::DIR_E500mc:
7934 case PPC::DIR_E5500:
7935 return NumUsers > 1;
7939 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7940 unsigned Bytes, int Dist,
7941 SelectionDAG &DAG) {
7942 if (VT.getSizeInBits() / 8 != Bytes)
7945 SDValue BaseLoc = Base->getBasePtr();
7946 if (Loc.getOpcode() == ISD::FrameIndex) {
7947 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7949 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7950 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7951 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7952 int FS = MFI->getObjectSize(FI);
7953 int BFS = MFI->getObjectSize(BFI);
7954 if (FS != BFS || FS != (int)Bytes) return false;
7955 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7959 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7960 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7964 const GlobalValue *GV1 = nullptr;
7965 const GlobalValue *GV2 = nullptr;
7966 int64_t Offset1 = 0;
7967 int64_t Offset2 = 0;
7968 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7969 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7970 if (isGA1 && isGA2 && GV1 == GV2)
7971 return Offset1 == (Offset2 + Dist*Bytes);
7975 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7976 // not enforce equality of the chain operands.
7977 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7978 unsigned Bytes, int Dist,
7979 SelectionDAG &DAG) {
7980 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7981 EVT VT = LS->getMemoryVT();
7982 SDValue Loc = LS->getBasePtr();
7983 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7986 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7988 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7989 default: return false;
7990 case Intrinsic::ppc_altivec_lvx:
7991 case Intrinsic::ppc_altivec_lvxl:
7992 case Intrinsic::ppc_vsx_lxvw4x:
7995 case Intrinsic::ppc_vsx_lxvd2x:
7998 case Intrinsic::ppc_altivec_lvebx:
8001 case Intrinsic::ppc_altivec_lvehx:
8004 case Intrinsic::ppc_altivec_lvewx:
8009 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
8012 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8014 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8015 default: return false;
8016 case Intrinsic::ppc_altivec_stvx:
8017 case Intrinsic::ppc_altivec_stvxl:
8018 case Intrinsic::ppc_vsx_stxvw4x:
8021 case Intrinsic::ppc_vsx_stxvd2x:
8024 case Intrinsic::ppc_altivec_stvebx:
8027 case Intrinsic::ppc_altivec_stvehx:
8030 case Intrinsic::ppc_altivec_stvewx:
8035 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8041 // Return true is there is a nearyby consecutive load to the one provided
8042 // (regardless of alignment). We search up and down the chain, looking though
8043 // token factors and other loads (but nothing else). As a result, a true result
8044 // indicates that it is safe to create a new consecutive load adjacent to the
8046 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8047 SDValue Chain = LD->getChain();
8048 EVT VT = LD->getMemoryVT();
8050 SmallSet<SDNode *, 16> LoadRoots;
8051 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8052 SmallSet<SDNode *, 16> Visited;
8054 // First, search up the chain, branching to follow all token-factor operands.
8055 // If we find a consecutive load, then we're done, otherwise, record all
8056 // nodes just above the top-level loads and token factors.
8057 while (!Queue.empty()) {
8058 SDNode *ChainNext = Queue.pop_back_val();
8059 if (!Visited.insert(ChainNext).second)
8062 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8063 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8066 if (!Visited.count(ChainLD->getChain().getNode()))
8067 Queue.push_back(ChainLD->getChain().getNode());
8068 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8069 for (const SDUse &O : ChainNext->ops())
8070 if (!Visited.count(O.getNode()))
8071 Queue.push_back(O.getNode());
8073 LoadRoots.insert(ChainNext);
8076 // Second, search down the chain, starting from the top-level nodes recorded
8077 // in the first phase. These top-level nodes are the nodes just above all
8078 // loads and token factors. Starting with their uses, recursively look though
8079 // all loads (just the chain uses) and token factors to find a consecutive
8084 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8085 IE = LoadRoots.end(); I != IE; ++I) {
8086 Queue.push_back(*I);
8088 while (!Queue.empty()) {
8089 SDNode *LoadRoot = Queue.pop_back_val();
8090 if (!Visited.insert(LoadRoot).second)
8093 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8094 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8097 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8098 UE = LoadRoot->use_end(); UI != UE; ++UI)
8099 if (((isa<MemSDNode>(*UI) &&
8100 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8101 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8102 Queue.push_back(*UI);
8109 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8110 DAGCombinerInfo &DCI) const {
8111 SelectionDAG &DAG = DCI.DAG;
8114 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
8115 // If we're tracking CR bits, we need to be careful that we don't have:
8116 // trunc(binary-ops(zext(x), zext(y)))
8118 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8119 // such that we're unnecessarily moving things into GPRs when it would be
8120 // better to keep them in CR bits.
8122 // Note that trunc here can be an actual i1 trunc, or can be the effective
8123 // truncation that comes from a setcc or select_cc.
8124 if (N->getOpcode() == ISD::TRUNCATE &&
8125 N->getValueType(0) != MVT::i1)
8128 if (N->getOperand(0).getValueType() != MVT::i32 &&
8129 N->getOperand(0).getValueType() != MVT::i64)
8132 if (N->getOpcode() == ISD::SETCC ||
8133 N->getOpcode() == ISD::SELECT_CC) {
8134 // If we're looking at a comparison, then we need to make sure that the
8135 // high bits (all except for the first) don't matter the result.
8137 cast<CondCodeSDNode>(N->getOperand(
8138 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8139 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8141 if (ISD::isSignedIntSetCC(CC)) {
8142 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8143 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8145 } else if (ISD::isUnsignedIntSetCC(CC)) {
8146 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8147 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8148 !DAG.MaskedValueIsZero(N->getOperand(1),
8149 APInt::getHighBitsSet(OpBits, OpBits-1)))
8152 // This is neither a signed nor an unsigned comparison, just make sure
8153 // that the high bits are equal.
8154 APInt Op1Zero, Op1One;
8155 APInt Op2Zero, Op2One;
8156 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8157 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8159 // We don't really care about what is known about the first bit (if
8160 // anything), so clear it in all masks prior to comparing them.
8161 Op1Zero.clearBit(0); Op1One.clearBit(0);
8162 Op2Zero.clearBit(0); Op2One.clearBit(0);
8164 if (Op1Zero != Op2Zero || Op1One != Op2One)
8169 // We now know that the higher-order bits are irrelevant, we just need to
8170 // make sure that all of the intermediate operations are bit operations, and
8171 // all inputs are extensions.
8172 if (N->getOperand(0).getOpcode() != ISD::AND &&
8173 N->getOperand(0).getOpcode() != ISD::OR &&
8174 N->getOperand(0).getOpcode() != ISD::XOR &&
8175 N->getOperand(0).getOpcode() != ISD::SELECT &&
8176 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8177 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8178 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8179 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8180 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8183 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8184 N->getOperand(1).getOpcode() != ISD::AND &&
8185 N->getOperand(1).getOpcode() != ISD::OR &&
8186 N->getOperand(1).getOpcode() != ISD::XOR &&
8187 N->getOperand(1).getOpcode() != ISD::SELECT &&
8188 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8189 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8190 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8191 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8192 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8195 SmallVector<SDValue, 4> Inputs;
8196 SmallVector<SDValue, 8> BinOps, PromOps;
8197 SmallPtrSet<SDNode *, 16> Visited;
8199 for (unsigned i = 0; i < 2; ++i) {
8200 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8201 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8202 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8203 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8204 isa<ConstantSDNode>(N->getOperand(i)))
8205 Inputs.push_back(N->getOperand(i));
8207 BinOps.push_back(N->getOperand(i));
8209 if (N->getOpcode() == ISD::TRUNCATE)
8213 // Visit all inputs, collect all binary operations (and, or, xor and
8214 // select) that are all fed by extensions.
8215 while (!BinOps.empty()) {
8216 SDValue BinOp = BinOps.back();
8219 if (!Visited.insert(BinOp.getNode()).second)
8222 PromOps.push_back(BinOp);
8224 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8225 // The condition of the select is not promoted.
8226 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8228 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8231 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8232 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8233 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8234 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8235 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8236 Inputs.push_back(BinOp.getOperand(i));
8237 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8238 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8239 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8240 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8241 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8242 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8243 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8244 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8245 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8246 BinOps.push_back(BinOp.getOperand(i));
8248 // We have an input that is not an extension or another binary
8249 // operation; we'll abort this transformation.
8255 // Make sure that this is a self-contained cluster of operations (which
8256 // is not quite the same thing as saying that everything has only one
8258 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8259 if (isa<ConstantSDNode>(Inputs[i]))
8262 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8263 UE = Inputs[i].getNode()->use_end();
8266 if (User != N && !Visited.count(User))
8269 // Make sure that we're not going to promote the non-output-value
8270 // operand(s) or SELECT or SELECT_CC.
8271 // FIXME: Although we could sometimes handle this, and it does occur in
8272 // practice that one of the condition inputs to the select is also one of
8273 // the outputs, we currently can't deal with this.
8274 if (User->getOpcode() == ISD::SELECT) {
8275 if (User->getOperand(0) == Inputs[i])
8277 } else if (User->getOpcode() == ISD::SELECT_CC) {
8278 if (User->getOperand(0) == Inputs[i] ||
8279 User->getOperand(1) == Inputs[i])
8285 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8286 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8287 UE = PromOps[i].getNode()->use_end();
8290 if (User != N && !Visited.count(User))
8293 // Make sure that we're not going to promote the non-output-value
8294 // operand(s) or SELECT or SELECT_CC.
8295 // FIXME: Although we could sometimes handle this, and it does occur in
8296 // practice that one of the condition inputs to the select is also one of
8297 // the outputs, we currently can't deal with this.
8298 if (User->getOpcode() == ISD::SELECT) {
8299 if (User->getOperand(0) == PromOps[i])
8301 } else if (User->getOpcode() == ISD::SELECT_CC) {
8302 if (User->getOperand(0) == PromOps[i] ||
8303 User->getOperand(1) == PromOps[i])
8309 // Replace all inputs with the extension operand.
8310 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8311 // Constants may have users outside the cluster of to-be-promoted nodes,
8312 // and so we need to replace those as we do the promotions.
8313 if (isa<ConstantSDNode>(Inputs[i]))
8316 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8319 // Replace all operations (these are all the same, but have a different
8320 // (i1) return type). DAG.getNode will validate that the types of
8321 // a binary operator match, so go through the list in reverse so that
8322 // we've likely promoted both operands first. Any intermediate truncations or
8323 // extensions disappear.
8324 while (!PromOps.empty()) {
8325 SDValue PromOp = PromOps.back();
8328 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8329 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8330 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8331 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8332 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8333 PromOp.getOperand(0).getValueType() != MVT::i1) {
8334 // The operand is not yet ready (see comment below).
8335 PromOps.insert(PromOps.begin(), PromOp);
8339 SDValue RepValue = PromOp.getOperand(0);
8340 if (isa<ConstantSDNode>(RepValue))
8341 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8343 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8348 switch (PromOp.getOpcode()) {
8349 default: C = 0; break;
8350 case ISD::SELECT: C = 1; break;
8351 case ISD::SELECT_CC: C = 2; break;
8354 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8355 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8356 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8357 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8358 // The to-be-promoted operands of this node have not yet been
8359 // promoted (this should be rare because we're going through the
8360 // list backward, but if one of the operands has several users in
8361 // this cluster of to-be-promoted nodes, it is possible).
8362 PromOps.insert(PromOps.begin(), PromOp);
8366 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8367 PromOp.getNode()->op_end());
8369 // If there are any constant inputs, make sure they're replaced now.
8370 for (unsigned i = 0; i < 2; ++i)
8371 if (isa<ConstantSDNode>(Ops[C+i]))
8372 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8374 DAG.ReplaceAllUsesOfValueWith(PromOp,
8375 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8378 // Now we're left with the initial truncation itself.
8379 if (N->getOpcode() == ISD::TRUNCATE)
8380 return N->getOperand(0);
8382 // Otherwise, this is a comparison. The operands to be compared have just
8383 // changed type (to i1), but everything else is the same.
8384 return SDValue(N, 0);
8387 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8388 DAGCombinerInfo &DCI) const {
8389 SelectionDAG &DAG = DCI.DAG;
8392 // If we're tracking CR bits, we need to be careful that we don't have:
8393 // zext(binary-ops(trunc(x), trunc(y)))
8395 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8396 // such that we're unnecessarily moving things into CR bits that can more
8397 // efficiently stay in GPRs. Note that if we're not certain that the high
8398 // bits are set as required by the final extension, we still may need to do
8399 // some masking to get the proper behavior.
8401 // This same functionality is important on PPC64 when dealing with
8402 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8403 // the return values of functions. Because it is so similar, it is handled
8406 if (N->getValueType(0) != MVT::i32 &&
8407 N->getValueType(0) != MVT::i64)
8410 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
8411 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
8414 if (N->getOperand(0).getOpcode() != ISD::AND &&
8415 N->getOperand(0).getOpcode() != ISD::OR &&
8416 N->getOperand(0).getOpcode() != ISD::XOR &&
8417 N->getOperand(0).getOpcode() != ISD::SELECT &&
8418 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8421 SmallVector<SDValue, 4> Inputs;
8422 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8423 SmallPtrSet<SDNode *, 16> Visited;
8425 // Visit all inputs, collect all binary operations (and, or, xor and
8426 // select) that are all fed by truncations.
8427 while (!BinOps.empty()) {
8428 SDValue BinOp = BinOps.back();
8431 if (!Visited.insert(BinOp.getNode()).second)
8434 PromOps.push_back(BinOp);
8436 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8437 // The condition of the select is not promoted.
8438 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8440 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8443 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8444 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8445 Inputs.push_back(BinOp.getOperand(i));
8446 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8447 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8448 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8449 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8450 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8451 BinOps.push_back(BinOp.getOperand(i));
8453 // We have an input that is not a truncation or another binary
8454 // operation; we'll abort this transformation.
8460 // The operands of a select that must be truncated when the select is
8461 // promoted because the operand is actually part of the to-be-promoted set.
8462 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8464 // Make sure that this is a self-contained cluster of operations (which
8465 // is not quite the same thing as saying that everything has only one
8467 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8468 if (isa<ConstantSDNode>(Inputs[i]))
8471 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8472 UE = Inputs[i].getNode()->use_end();
8475 if (User != N && !Visited.count(User))
8478 // If we're going to promote the non-output-value operand(s) or SELECT or
8479 // SELECT_CC, record them for truncation.
8480 if (User->getOpcode() == ISD::SELECT) {
8481 if (User->getOperand(0) == Inputs[i])
8482 SelectTruncOp[0].insert(std::make_pair(User,
8483 User->getOperand(0).getValueType()));
8484 } else if (User->getOpcode() == ISD::SELECT_CC) {
8485 if (User->getOperand(0) == Inputs[i])
8486 SelectTruncOp[0].insert(std::make_pair(User,
8487 User->getOperand(0).getValueType()));
8488 if (User->getOperand(1) == Inputs[i])
8489 SelectTruncOp[1].insert(std::make_pair(User,
8490 User->getOperand(1).getValueType()));
8495 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8496 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8497 UE = PromOps[i].getNode()->use_end();
8500 if (User != N && !Visited.count(User))
8503 // If we're going to promote the non-output-value operand(s) or SELECT or
8504 // SELECT_CC, record them for truncation.
8505 if (User->getOpcode() == ISD::SELECT) {
8506 if (User->getOperand(0) == PromOps[i])
8507 SelectTruncOp[0].insert(std::make_pair(User,
8508 User->getOperand(0).getValueType()));
8509 } else if (User->getOpcode() == ISD::SELECT_CC) {
8510 if (User->getOperand(0) == PromOps[i])
8511 SelectTruncOp[0].insert(std::make_pair(User,
8512 User->getOperand(0).getValueType()));
8513 if (User->getOperand(1) == PromOps[i])
8514 SelectTruncOp[1].insert(std::make_pair(User,
8515 User->getOperand(1).getValueType()));
8520 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8521 bool ReallyNeedsExt = false;
8522 if (N->getOpcode() != ISD::ANY_EXTEND) {
8523 // If all of the inputs are not already sign/zero extended, then
8524 // we'll still need to do that at the end.
8525 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8526 if (isa<ConstantSDNode>(Inputs[i]))
8530 Inputs[i].getOperand(0).getValueSizeInBits();
8531 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8533 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8534 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8535 APInt::getHighBitsSet(OpBits,
8536 OpBits-PromBits))) ||
8537 (N->getOpcode() == ISD::SIGN_EXTEND &&
8538 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8539 (OpBits-(PromBits-1)))) {
8540 ReallyNeedsExt = true;
8546 // Replace all inputs, either with the truncation operand, or a
8547 // truncation or extension to the final output type.
8548 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8549 // Constant inputs need to be replaced with the to-be-promoted nodes that
8550 // use them because they might have users outside of the cluster of
8552 if (isa<ConstantSDNode>(Inputs[i]))
8555 SDValue InSrc = Inputs[i].getOperand(0);
8556 if (Inputs[i].getValueType() == N->getValueType(0))
8557 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8558 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8559 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8560 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8561 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8562 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8563 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8565 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8566 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8569 // Replace all operations (these are all the same, but have a different
8570 // (promoted) return type). DAG.getNode will validate that the types of
8571 // a binary operator match, so go through the list in reverse so that
8572 // we've likely promoted both operands first.
8573 while (!PromOps.empty()) {
8574 SDValue PromOp = PromOps.back();
8578 switch (PromOp.getOpcode()) {
8579 default: C = 0; break;
8580 case ISD::SELECT: C = 1; break;
8581 case ISD::SELECT_CC: C = 2; break;
8584 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8585 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8586 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8587 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8588 // The to-be-promoted operands of this node have not yet been
8589 // promoted (this should be rare because we're going through the
8590 // list backward, but if one of the operands has several users in
8591 // this cluster of to-be-promoted nodes, it is possible).
8592 PromOps.insert(PromOps.begin(), PromOp);
8596 // For SELECT and SELECT_CC nodes, we do a similar check for any
8597 // to-be-promoted comparison inputs.
8598 if (PromOp.getOpcode() == ISD::SELECT ||
8599 PromOp.getOpcode() == ISD::SELECT_CC) {
8600 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8601 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8602 (SelectTruncOp[1].count(PromOp.getNode()) &&
8603 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8604 PromOps.insert(PromOps.begin(), PromOp);
8609 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8610 PromOp.getNode()->op_end());
8612 // If this node has constant inputs, then they'll need to be promoted here.
8613 for (unsigned i = 0; i < 2; ++i) {
8614 if (!isa<ConstantSDNode>(Ops[C+i]))
8616 if (Ops[C+i].getValueType() == N->getValueType(0))
8619 if (N->getOpcode() == ISD::SIGN_EXTEND)
8620 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8621 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8622 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8624 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8627 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8628 // truncate them again to the original value type.
8629 if (PromOp.getOpcode() == ISD::SELECT ||
8630 PromOp.getOpcode() == ISD::SELECT_CC) {
8631 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8632 if (SI0 != SelectTruncOp[0].end())
8633 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8634 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8635 if (SI1 != SelectTruncOp[1].end())
8636 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8639 DAG.ReplaceAllUsesOfValueWith(PromOp,
8640 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8643 // Now we're left with the initial extension itself.
8644 if (!ReallyNeedsExt)
8645 return N->getOperand(0);
8647 // To zero extend, just mask off everything except for the first bit (in the
8649 if (N->getOpcode() == ISD::ZERO_EXTEND)
8650 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8651 DAG.getConstant(APInt::getLowBitsSet(
8652 N->getValueSizeInBits(0), PromBits),
8653 N->getValueType(0)));
8655 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8656 "Invalid extension type");
8657 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8659 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8660 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8661 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8662 N->getOperand(0), ShiftCst), ShiftCst);
8665 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8666 DAGCombinerInfo &DCI) const {
8667 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8668 N->getOpcode() == ISD::UINT_TO_FP) &&
8669 "Need an int -> FP conversion node here");
8671 if (!Subtarget.has64BitSupport())
8674 SelectionDAG &DAG = DCI.DAG;
8678 // Don't handle ppc_fp128 here or i1 conversions.
8679 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8681 if (Op.getOperand(0).getValueType() == MVT::i1)
8684 // For i32 intermediate values, unfortunately, the conversion functions
8685 // leave the upper 32 bits of the value are undefined. Within the set of
8686 // scalar instructions, we have no method for zero- or sign-extending the
8687 // value. Thus, we cannot handle i32 intermediate values here.
8688 if (Op.getOperand(0).getValueType() == MVT::i32)
8691 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8692 "UINT_TO_FP is supported only with FPCVT");
8694 // If we have FCFIDS, then use it when converting to single-precision.
8695 // Otherwise, convert to double-precision and then round.
8696 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8697 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
8699 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
8701 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8705 // If we're converting from a float, to an int, and back to a float again,
8706 // then we don't need the store/load pair at all.
8707 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8708 Subtarget.hasFPCVT()) ||
8709 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8710 SDValue Src = Op.getOperand(0).getOperand(0);
8711 if (Src.getValueType() == MVT::f32) {
8712 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8713 DCI.AddToWorklist(Src.getNode());
8717 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8720 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8721 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8723 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8724 FP = DAG.getNode(ISD::FP_ROUND, dl,
8725 MVT::f32, FP, DAG.getIntPtrConstant(0));
8726 DCI.AddToWorklist(FP.getNode());
8735 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8736 // builtins) into loads with swaps.
8737 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8738 DAGCombinerInfo &DCI) const {
8739 SelectionDAG &DAG = DCI.DAG;
8743 MachineMemOperand *MMO;
8745 switch (N->getOpcode()) {
8747 llvm_unreachable("Unexpected opcode for little endian VSX load");
8749 LoadSDNode *LD = cast<LoadSDNode>(N);
8750 Chain = LD->getChain();
8751 Base = LD->getBasePtr();
8752 MMO = LD->getMemOperand();
8753 // If the MMO suggests this isn't a load of a full vector, leave
8754 // things alone. For a built-in, we have to make the change for
8755 // correctness, so if there is a size problem that will be a bug.
8756 if (MMO->getSize() < 16)
8760 case ISD::INTRINSIC_W_CHAIN: {
8761 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8762 Chain = Intrin->getChain();
8763 Base = Intrin->getBasePtr();
8764 MMO = Intrin->getMemOperand();
8769 MVT VecTy = N->getValueType(0).getSimpleVT();
8770 SDValue LoadOps[] = { Chain, Base };
8771 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8772 DAG.getVTList(VecTy, MVT::Other),
8773 LoadOps, VecTy, MMO);
8774 DCI.AddToWorklist(Load.getNode());
8775 Chain = Load.getValue(1);
8776 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8777 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8778 DCI.AddToWorklist(Swap.getNode());
8782 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8783 // builtins) into stores with swaps.
8784 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8785 DAGCombinerInfo &DCI) const {
8786 SelectionDAG &DAG = DCI.DAG;
8791 MachineMemOperand *MMO;
8793 switch (N->getOpcode()) {
8795 llvm_unreachable("Unexpected opcode for little endian VSX store");
8797 StoreSDNode *ST = cast<StoreSDNode>(N);
8798 Chain = ST->getChain();
8799 Base = ST->getBasePtr();
8800 MMO = ST->getMemOperand();
8802 // If the MMO suggests this isn't a store of a full vector, leave
8803 // things alone. For a built-in, we have to make the change for
8804 // correctness, so if there is a size problem that will be a bug.
8805 if (MMO->getSize() < 16)
8809 case ISD::INTRINSIC_VOID: {
8810 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8811 Chain = Intrin->getChain();
8812 // Intrin->getBasePtr() oddly does not get what we want.
8813 Base = Intrin->getOperand(3);
8814 MMO = Intrin->getMemOperand();
8820 SDValue Src = N->getOperand(SrcOpnd);
8821 MVT VecTy = Src.getValueType().getSimpleVT();
8822 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8823 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8824 DCI.AddToWorklist(Swap.getNode());
8825 Chain = Swap.getValue(1);
8826 SDValue StoreOps[] = { Chain, Swap, Base };
8827 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8828 DAG.getVTList(MVT::Other),
8829 StoreOps, VecTy, MMO);
8830 DCI.AddToWorklist(Store.getNode());
8834 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8835 DAGCombinerInfo &DCI) const {
8836 SelectionDAG &DAG = DCI.DAG;
8838 switch (N->getOpcode()) {
8841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8842 if (C->isNullValue()) // 0 << V -> 0.
8843 return N->getOperand(0);
8847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8848 if (C->isNullValue()) // 0 >>u V -> 0.
8849 return N->getOperand(0);
8853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8854 if (C->isNullValue() || // 0 >>s V -> 0.
8855 C->isAllOnesValue()) // -1 >>s V -> -1.
8856 return N->getOperand(0);
8859 case ISD::SIGN_EXTEND:
8860 case ISD::ZERO_EXTEND:
8861 case ISD::ANY_EXTEND:
8862 return DAGCombineExtBoolTrunc(N, DCI);
8865 case ISD::SELECT_CC:
8866 return DAGCombineTruncBoolExt(N, DCI);
8867 case ISD::SINT_TO_FP:
8868 case ISD::UINT_TO_FP:
8869 return combineFPToIntToFP(N, DCI);
8871 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8872 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
8873 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8874 N->getOperand(1).getValueType() == MVT::i32 &&
8875 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8876 SDValue Val = N->getOperand(1).getOperand(0);
8877 if (Val.getValueType() == MVT::f32) {
8878 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8879 DCI.AddToWorklist(Val.getNode());
8881 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8882 DCI.AddToWorklist(Val.getNode());
8885 N->getOperand(0), Val, N->getOperand(2),
8886 DAG.getValueType(N->getOperand(1).getValueType())
8889 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8890 DAG.getVTList(MVT::Other), Ops,
8891 cast<StoreSDNode>(N)->getMemoryVT(),
8892 cast<StoreSDNode>(N)->getMemOperand());
8893 DCI.AddToWorklist(Val.getNode());
8897 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8898 if (cast<StoreSDNode>(N)->isUnindexed() &&
8899 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8900 N->getOperand(1).getNode()->hasOneUse() &&
8901 (N->getOperand(1).getValueType() == MVT::i32 ||
8902 N->getOperand(1).getValueType() == MVT::i16 ||
8903 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
8904 N->getOperand(1).getValueType() == MVT::i64))) {
8905 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8906 // Do an any-extend to 32-bits if this is a half-word input.
8907 if (BSwapOp.getValueType() == MVT::i16)
8908 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8911 N->getOperand(0), BSwapOp, N->getOperand(2),
8912 DAG.getValueType(N->getOperand(1).getValueType())
8915 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8916 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8917 cast<StoreSDNode>(N)->getMemOperand());
8920 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8921 EVT VT = N->getOperand(1).getValueType();
8922 if (VT.isSimple()) {
8923 MVT StoreVT = VT.getSimpleVT();
8924 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8925 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8926 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8927 return expandVSXStoreForLE(N, DCI);
8932 LoadSDNode *LD = cast<LoadSDNode>(N);
8933 EVT VT = LD->getValueType(0);
8935 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8936 if (VT.isSimple()) {
8937 MVT LoadVT = VT.getSimpleVT();
8938 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8939 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8940 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8941 return expandVSXLoadForLE(N, DCI);
8944 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8945 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8946 if (ISD::isNON_EXTLoad(N) && VT.isVector() && Subtarget.hasAltivec() &&
8947 // P8 and later hardware should just use LOAD.
8948 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8949 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8950 LD->getAlignment() < ABIAlignment) {
8951 // This is a type-legal unaligned Altivec load.
8952 SDValue Chain = LD->getChain();
8953 SDValue Ptr = LD->getBasePtr();
8954 bool isLittleEndian = Subtarget.isLittleEndian();
8956 // This implements the loading of unaligned vectors as described in
8957 // the venerable Apple Velocity Engine overview. Specifically:
8958 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8959 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8961 // The general idea is to expand a sequence of one or more unaligned
8962 // loads into an alignment-based permutation-control instruction (lvsl
8963 // or lvsr), a series of regular vector loads (which always truncate
8964 // their input address to an aligned address), and a series of
8965 // permutations. The results of these permutations are the requested
8966 // loaded values. The trick is that the last "extra" load is not taken
8967 // from the address you might suspect (sizeof(vector) bytes after the
8968 // last requested load), but rather sizeof(vector) - 1 bytes after the
8969 // last requested vector. The point of this is to avoid a page fault if
8970 // the base address happened to be aligned. This works because if the
8971 // base address is aligned, then adding less than a full vector length
8972 // will cause the last vector in the sequence to be (re)loaded.
8973 // Otherwise, the next vector will be fetched as you might suspect was
8976 // We might be able to reuse the permutation generation from
8977 // a different base address offset from this one by an aligned amount.
8978 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8979 // optimization later.
8980 Intrinsic::ID Intr = (isLittleEndian ?
8981 Intrinsic::ppc_altivec_lvsr :
8982 Intrinsic::ppc_altivec_lvsl);
8983 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8985 // Create the new MMO for the new base load. It is like the original MMO,
8986 // but represents an area in memory almost twice the vector size centered
8987 // on the original address. If the address is unaligned, we might start
8988 // reading up to (sizeof(vector)-1) bytes below the address of the
8989 // original unaligned load.
8990 MachineFunction &MF = DAG.getMachineFunction();
8991 MachineMemOperand *BaseMMO =
8992 MF.getMachineMemOperand(LD->getMemOperand(),
8993 -LD->getMemoryVT().getStoreSize()+1,
8994 2*LD->getMemoryVT().getStoreSize()-1);
8996 // Create the new base load.
8997 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8999 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
9001 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9002 DAG.getVTList(MVT::v4i32, MVT::Other),
9003 BaseLoadOps, MVT::v4i32, BaseMMO);
9005 // Note that the value of IncOffset (which is provided to the next
9006 // load's pointer info offset value, and thus used to calculate the
9007 // alignment), and the value of IncValue (which is actually used to
9008 // increment the pointer value) are different! This is because we
9009 // require the next load to appear to be aligned, even though it
9010 // is actually offset from the base pointer by a lesser amount.
9011 int IncOffset = VT.getSizeInBits() / 8;
9012 int IncValue = IncOffset;
9014 // Walk (both up and down) the chain looking for another load at the real
9015 // (aligned) offset (the alignment of the other load does not matter in
9016 // this case). If found, then do not use the offset reduction trick, as
9017 // that will prevent the loads from being later combined (as they would
9018 // otherwise be duplicates).
9019 if (!findConsecutiveLoad(LD, DAG))
9022 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9025 MachineMemOperand *ExtraMMO =
9026 MF.getMachineMemOperand(LD->getMemOperand(),
9027 1, 2*LD->getMemoryVT().getStoreSize()-1);
9028 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9030 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9031 DAG.getVTList(MVT::v4i32, MVT::Other),
9032 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9034 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9035 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9037 // Because vperm has a big-endian bias, we must reverse the order
9038 // of the input vectors and complement the permute control vector
9039 // when generating little endian code. We have already handled the
9040 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9041 // and ExtraLoad here.
9044 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9045 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9047 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9048 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9050 if (VT != MVT::v4i32)
9051 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9053 // The output of the permutation is our loaded result, the TokenFactor is
9055 DCI.CombineTo(N, Perm, TF);
9056 return SDValue(N, 0);
9060 case ISD::INTRINSIC_WO_CHAIN: {
9061 bool isLittleEndian = Subtarget.isLittleEndian();
9062 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
9063 : Intrinsic::ppc_altivec_lvsl);
9064 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9065 N->getOperand(1)->getOpcode() == ISD::ADD) {
9066 SDValue Add = N->getOperand(1);
9068 if (DAG.MaskedValueIsZero(
9070 APInt::getAllOnesValue(4 /* 16 byte alignment */)
9072 Add.getValueType().getScalarType().getSizeInBits()))) {
9073 SDNode *BasePtr = Add->getOperand(0).getNode();
9074 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9075 UE = BasePtr->use_end();
9077 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9078 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9080 // We've found another LVSL/LVSR, and this address is an aligned
9081 // multiple of that one. The results will be the same, so use the
9082 // one we've just found instead.
9084 return SDValue(*UI, 0);
9092 case ISD::INTRINSIC_W_CHAIN: {
9093 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9094 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9095 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9098 case Intrinsic::ppc_vsx_lxvw4x:
9099 case Intrinsic::ppc_vsx_lxvd2x:
9100 return expandVSXLoadForLE(N, DCI);
9105 case ISD::INTRINSIC_VOID: {
9106 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9107 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9108 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9111 case Intrinsic::ppc_vsx_stxvw4x:
9112 case Intrinsic::ppc_vsx_stxvd2x:
9113 return expandVSXStoreForLE(N, DCI);
9119 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9120 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9121 N->getOperand(0).hasOneUse() &&
9122 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9123 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9124 N->getValueType(0) == MVT::i64))) {
9125 SDValue Load = N->getOperand(0);
9126 LoadSDNode *LD = cast<LoadSDNode>(Load);
9127 // Create the byte-swapping load.
9129 LD->getChain(), // Chain
9130 LD->getBasePtr(), // Ptr
9131 DAG.getValueType(N->getValueType(0)) // VT
9134 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9135 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9136 MVT::i64 : MVT::i32, MVT::Other),
9137 Ops, LD->getMemoryVT(), LD->getMemOperand());
9139 // If this is an i16 load, insert the truncate.
9140 SDValue ResVal = BSLoad;
9141 if (N->getValueType(0) == MVT::i16)
9142 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9144 // First, combine the bswap away. This makes the value produced by the
9146 DCI.CombineTo(N, ResVal);
9148 // Next, combine the load away, we give it a bogus result value but a real
9149 // chain result. The result value is dead because the bswap is dead.
9150 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9152 // Return N so it doesn't get rechecked!
9153 return SDValue(N, 0);
9157 case PPCISD::VCMP: {
9158 // If a VCMPo node already exists with exactly the same operands as this
9159 // node, use its result instead of this node (VCMPo computes both a CR6 and
9160 // a normal output).
9162 if (!N->getOperand(0).hasOneUse() &&
9163 !N->getOperand(1).hasOneUse() &&
9164 !N->getOperand(2).hasOneUse()) {
9166 // Scan all of the users of the LHS, looking for VCMPo's that match.
9167 SDNode *VCMPoNode = nullptr;
9169 SDNode *LHSN = N->getOperand(0).getNode();
9170 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9172 if (UI->getOpcode() == PPCISD::VCMPo &&
9173 UI->getOperand(1) == N->getOperand(1) &&
9174 UI->getOperand(2) == N->getOperand(2) &&
9175 UI->getOperand(0) == N->getOperand(0)) {
9180 // If there is no VCMPo node, or if the flag value has a single use, don't
9182 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9185 // Look at the (necessarily single) use of the flag value. If it has a
9186 // chain, this transformation is more complex. Note that multiple things
9187 // could use the value result, which we should ignore.
9188 SDNode *FlagUser = nullptr;
9189 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9190 FlagUser == nullptr; ++UI) {
9191 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9193 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9194 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9201 // If the user is a MFOCRF instruction, we know this is safe.
9202 // Otherwise we give up for right now.
9203 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9204 return SDValue(VCMPoNode, 0);
9209 SDValue Cond = N->getOperand(1);
9210 SDValue Target = N->getOperand(2);
9212 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9213 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9214 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9216 // We now need to make the intrinsic dead (it cannot be instruction
9218 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9219 assert(Cond.getNode()->hasOneUse() &&
9220 "Counter decrement has more than one use");
9222 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9223 N->getOperand(0), Target);
9228 // If this is a branch on an altivec predicate comparison, lower this so
9229 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9230 // lowering is done pre-legalize, because the legalizer lowers the predicate
9231 // compare down to code that is difficult to reassemble.
9232 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9233 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9235 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9236 // value. If so, pass-through the AND to get to the intrinsic.
9237 if (LHS.getOpcode() == ISD::AND &&
9238 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9239 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9240 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9241 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9242 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9244 LHS = LHS.getOperand(0);
9246 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9247 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9248 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9249 isa<ConstantSDNode>(RHS)) {
9250 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9251 "Counter decrement comparison is not EQ or NE");
9253 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9254 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9255 (CC == ISD::SETNE && !Val);
9257 // We now need to make the intrinsic dead (it cannot be instruction
9259 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9260 assert(LHS.getNode()->hasOneUse() &&
9261 "Counter decrement has more than one use");
9263 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9264 N->getOperand(0), N->getOperand(4));
9270 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9271 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9272 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9273 assert(isDot && "Can't compare against a vector result!");
9275 // If this is a comparison against something other than 0/1, then we know
9276 // that the condition is never/always true.
9277 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9278 if (Val != 0 && Val != 1) {
9279 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9280 return N->getOperand(0);
9281 // Always !=, turn it into an unconditional branch.
9282 return DAG.getNode(ISD::BR, dl, MVT::Other,
9283 N->getOperand(0), N->getOperand(4));
9286 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9288 // Create the PPCISD altivec 'dot' comparison node.
9290 LHS.getOperand(2), // LHS of compare
9291 LHS.getOperand(3), // RHS of compare
9292 DAG.getConstant(CompareOpc, MVT::i32)
9294 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9295 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9297 // Unpack the result based on how the target uses it.
9298 PPC::Predicate CompOpc;
9299 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9300 default: // Can't happen, don't crash on invalid number though.
9301 case 0: // Branch on the value of the EQ bit of CR6.
9302 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9304 case 1: // Branch on the inverted value of the EQ bit of CR6.
9305 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9307 case 2: // Branch on the value of the LT bit of CR6.
9308 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9310 case 3: // Branch on the inverted value of the LT bit of CR6.
9311 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9315 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9316 DAG.getConstant(CompOpc, MVT::i32),
9317 DAG.getRegister(PPC::CR6, MVT::i32),
9318 N->getOperand(4), CompNode.getValue(1));
9328 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9330 std::vector<SDNode *> *Created) const {
9331 // fold (sdiv X, pow2)
9332 EVT VT = N->getValueType(0);
9333 if (VT == MVT::i64 && !Subtarget.isPPC64())
9335 if ((VT != MVT::i32 && VT != MVT::i64) ||
9336 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9340 SDValue N0 = N->getOperand(0);
9342 bool IsNegPow2 = (-Divisor).isPowerOf2();
9343 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9344 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9346 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9348 Created->push_back(Op.getNode());
9351 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9353 Created->push_back(Op.getNode());
9359 //===----------------------------------------------------------------------===//
9360 // Inline Assembly Support
9361 //===----------------------------------------------------------------------===//
9363 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9366 const SelectionDAG &DAG,
9367 unsigned Depth) const {
9368 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9369 switch (Op.getOpcode()) {
9371 case PPCISD::LBRX: {
9372 // lhbrx is known to have the top bits cleared out.
9373 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9374 KnownZero = 0xFFFF0000;
9377 case ISD::INTRINSIC_WO_CHAIN: {
9378 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9380 case Intrinsic::ppc_altivec_vcmpbfp_p:
9381 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9382 case Intrinsic::ppc_altivec_vcmpequb_p:
9383 case Intrinsic::ppc_altivec_vcmpequh_p:
9384 case Intrinsic::ppc_altivec_vcmpequw_p:
9385 case Intrinsic::ppc_altivec_vcmpgefp_p:
9386 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9387 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9388 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9389 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9390 case Intrinsic::ppc_altivec_vcmpgtub_p:
9391 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9392 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9393 KnownZero = ~1U; // All bits but the low one are known to be zero.
9400 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9401 switch (Subtarget.getDarwinDirective()) {
9406 case PPC::DIR_PWR5X:
9408 case PPC::DIR_PWR6X:
9410 case PPC::DIR_PWR8: {
9414 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
9416 // For small loops (between 5 and 8 instructions), align to a 32-byte
9417 // boundary so that the entire loop fits in one instruction-cache line.
9418 uint64_t LoopSize = 0;
9419 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9420 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9421 LoopSize += TII->GetInstSizeInBytes(J);
9423 if (LoopSize > 16 && LoopSize <= 32)
9430 return TargetLowering::getPrefLoopAlignment(ML);
9433 /// getConstraintType - Given a constraint, return the type of
9434 /// constraint it is for this target.
9435 PPCTargetLowering::ConstraintType
9436 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9437 if (Constraint.size() == 1) {
9438 switch (Constraint[0]) {
9445 return C_RegisterClass;
9447 // FIXME: While Z does indicate a memory constraint, it specifically
9448 // indicates an r+r address (used in conjunction with the 'y' modifier
9449 // in the replacement string). Currently, we're forcing the base
9450 // register to be r0 in the asm printer (which is interpreted as zero)
9451 // and forming the complete address in the second register. This is
9455 } else if (Constraint == "wc") { // individual CR bits.
9456 return C_RegisterClass;
9457 } else if (Constraint == "wa" || Constraint == "wd" ||
9458 Constraint == "wf" || Constraint == "ws") {
9459 return C_RegisterClass; // VSX registers.
9461 return TargetLowering::getConstraintType(Constraint);
9464 /// Examine constraint type and operand type and determine a weight value.
9465 /// This object must already have been set up with the operand type
9466 /// and the current alternative constraint selected.
9467 TargetLowering::ConstraintWeight
9468 PPCTargetLowering::getSingleConstraintMatchWeight(
9469 AsmOperandInfo &info, const char *constraint) const {
9470 ConstraintWeight weight = CW_Invalid;
9471 Value *CallOperandVal = info.CallOperandVal;
9472 // If we don't have a value, we can't do a match,
9473 // but allow it at the lowest weight.
9474 if (!CallOperandVal)
9476 Type *type = CallOperandVal->getType();
9478 // Look at the constraint type.
9479 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9480 return CW_Register; // an individual CR bit.
9481 else if ((StringRef(constraint) == "wa" ||
9482 StringRef(constraint) == "wd" ||
9483 StringRef(constraint) == "wf") &&
9486 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9489 switch (*constraint) {
9491 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9494 if (type->isIntegerTy())
9495 weight = CW_Register;
9498 if (type->isFloatTy())
9499 weight = CW_Register;
9502 if (type->isDoubleTy())
9503 weight = CW_Register;
9506 if (type->isVectorTy())
9507 weight = CW_Register;
9510 weight = CW_Register;
9519 std::pair<unsigned, const TargetRegisterClass*>
9520 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9522 if (Constraint.size() == 1) {
9523 // GCC RS6000 Constraint Letters
9524 switch (Constraint[0]) {
9526 if (VT == MVT::i64 && Subtarget.isPPC64())
9527 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9528 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9530 if (VT == MVT::i64 && Subtarget.isPPC64())
9531 return std::make_pair(0U, &PPC::G8RCRegClass);
9532 return std::make_pair(0U, &PPC::GPRCRegClass);
9534 if (VT == MVT::f32 || VT == MVT::i32)
9535 return std::make_pair(0U, &PPC::F4RCRegClass);
9536 if (VT == MVT::f64 || VT == MVT::i64)
9537 return std::make_pair(0U, &PPC::F8RCRegClass);
9540 return std::make_pair(0U, &PPC::VRRCRegClass);
9542 return std::make_pair(0U, &PPC::CRRCRegClass);
9544 } else if (Constraint == "wc") { // an individual CR bit.
9545 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9546 } else if (Constraint == "wa" || Constraint == "wd" ||
9547 Constraint == "wf") {
9548 return std::make_pair(0U, &PPC::VSRCRegClass);
9549 } else if (Constraint == "ws") {
9550 return std::make_pair(0U, &PPC::VSFRCRegClass);
9553 std::pair<unsigned, const TargetRegisterClass*> R =
9554 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9556 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9557 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9558 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9560 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9561 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9562 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9563 PPC::GPRCRegClass.contains(R.first)) {
9564 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
9565 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9566 PPC::sub_32, &PPC::G8RCRegClass),
9567 &PPC::G8RCRegClass);
9570 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9571 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9573 R.second = &PPC::CRRCRegClass;
9580 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9581 /// vector. If it is invalid, don't add anything to Ops.
9582 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9583 std::string &Constraint,
9584 std::vector<SDValue>&Ops,
9585 SelectionDAG &DAG) const {
9588 // Only support length 1 constraints.
9589 if (Constraint.length() > 1) return;
9591 char Letter = Constraint[0];
9602 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9603 if (!CST) return; // Must be an immediate to match.
9604 int64_t Value = CST->getSExtValue();
9605 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9606 // numbers are printed as such.
9608 default: llvm_unreachable("Unknown constraint letter!");
9609 case 'I': // "I" is a signed 16-bit constant.
9610 if (isInt<16>(Value))
9611 Result = DAG.getTargetConstant(Value, TCVT);
9613 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9614 if (isShiftedUInt<16, 16>(Value))
9615 Result = DAG.getTargetConstant(Value, TCVT);
9617 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9618 if (isShiftedInt<16, 16>(Value))
9619 Result = DAG.getTargetConstant(Value, TCVT);
9621 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9622 if (isUInt<16>(Value))
9623 Result = DAG.getTargetConstant(Value, TCVT);
9625 case 'M': // "M" is a constant that is greater than 31.
9627 Result = DAG.getTargetConstant(Value, TCVT);
9629 case 'N': // "N" is a positive constant that is an exact power of two.
9630 if (Value > 0 && isPowerOf2_64(Value))
9631 Result = DAG.getTargetConstant(Value, TCVT);
9633 case 'O': // "O" is the constant zero.
9635 Result = DAG.getTargetConstant(Value, TCVT);
9637 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9638 if (isInt<16>(-Value))
9639 Result = DAG.getTargetConstant(Value, TCVT);
9646 if (Result.getNode()) {
9647 Ops.push_back(Result);
9651 // Handle standard constraint letters.
9652 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9655 // isLegalAddressingMode - Return true if the addressing mode represented
9656 // by AM is legal for this target, for a load/store of the specified type.
9657 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9659 // FIXME: PPC does not allow r+i addressing modes for vectors!
9661 // PPC allows a sign-extended 16-bit immediate field.
9662 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9665 // No global is ever allowed as a base.
9669 // PPC only support r+r,
9671 case 0: // "r+i" or just "i", depending on HasBaseReg.
9674 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9676 // Otherwise we have r+r or r+i.
9679 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9681 // Allow 2*r as r+r.
9684 // No other scales are supported.
9691 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9692 SelectionDAG &DAG) const {
9693 MachineFunction &MF = DAG.getMachineFunction();
9694 MachineFrameInfo *MFI = MF.getFrameInfo();
9695 MFI->setReturnAddressIsTaken(true);
9697 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9701 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9703 // Make sure the function does not optimize away the store of the RA to
9705 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9706 FuncInfo->setLRStoreRequired();
9707 bool isPPC64 = Subtarget.isPPC64();
9708 bool isDarwinABI = Subtarget.isDarwinABI();
9711 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9714 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9715 isPPC64? MVT::i64 : MVT::i32);
9716 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9717 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9719 MachinePointerInfo(), false, false, false, 0);
9722 // Just load the return address off the stack.
9723 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9724 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9725 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9728 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9729 SelectionDAG &DAG) const {
9731 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9733 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9734 bool isPPC64 = PtrVT == MVT::i64;
9736 MachineFunction &MF = DAG.getMachineFunction();
9737 MachineFrameInfo *MFI = MF.getFrameInfo();
9738 MFI->setFrameAddressIsTaken(true);
9740 // Naked functions never have a frame pointer, and so we use r1. For all
9741 // other functions, this decision must be delayed until during PEI.
9743 if (MF.getFunction()->getAttributes().hasAttribute(
9744 AttributeSet::FunctionIndex, Attribute::Naked))
9745 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9747 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9749 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9752 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9753 FrameAddr, MachinePointerInfo(), false, false,
9758 // FIXME? Maybe this could be a TableGen attribute on some registers and
9759 // this table could be generated automatically from RegInfo.
9760 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9762 bool isPPC64 = Subtarget.isPPC64();
9763 bool isDarwinABI = Subtarget.isDarwinABI();
9765 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9766 (!isPPC64 && VT != MVT::i32))
9767 report_fatal_error("Invalid register global variable type");
9769 bool is64Bit = isPPC64 && VT == MVT::i64;
9770 unsigned Reg = StringSwitch<unsigned>(RegName)
9771 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9772 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9773 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9774 (is64Bit ? PPC::X13 : PPC::R13))
9779 report_fatal_error("Invalid register name global variable");
9783 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9784 // The PowerPC target isn't yet aware of offsets.
9788 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9790 unsigned Intrinsic) const {
9792 switch (Intrinsic) {
9793 case Intrinsic::ppc_altivec_lvx:
9794 case Intrinsic::ppc_altivec_lvxl:
9795 case Intrinsic::ppc_altivec_lvebx:
9796 case Intrinsic::ppc_altivec_lvehx:
9797 case Intrinsic::ppc_altivec_lvewx:
9798 case Intrinsic::ppc_vsx_lxvd2x:
9799 case Intrinsic::ppc_vsx_lxvw4x: {
9801 switch (Intrinsic) {
9802 case Intrinsic::ppc_altivec_lvebx:
9805 case Intrinsic::ppc_altivec_lvehx:
9808 case Intrinsic::ppc_altivec_lvewx:
9811 case Intrinsic::ppc_vsx_lxvd2x:
9819 Info.opc = ISD::INTRINSIC_W_CHAIN;
9821 Info.ptrVal = I.getArgOperand(0);
9822 Info.offset = -VT.getStoreSize()+1;
9823 Info.size = 2*VT.getStoreSize()-1;
9826 Info.readMem = true;
9827 Info.writeMem = false;
9830 case Intrinsic::ppc_altivec_stvx:
9831 case Intrinsic::ppc_altivec_stvxl:
9832 case Intrinsic::ppc_altivec_stvebx:
9833 case Intrinsic::ppc_altivec_stvehx:
9834 case Intrinsic::ppc_altivec_stvewx:
9835 case Intrinsic::ppc_vsx_stxvd2x:
9836 case Intrinsic::ppc_vsx_stxvw4x: {
9838 switch (Intrinsic) {
9839 case Intrinsic::ppc_altivec_stvebx:
9842 case Intrinsic::ppc_altivec_stvehx:
9845 case Intrinsic::ppc_altivec_stvewx:
9848 case Intrinsic::ppc_vsx_stxvd2x:
9856 Info.opc = ISD::INTRINSIC_VOID;
9858 Info.ptrVal = I.getArgOperand(1);
9859 Info.offset = -VT.getStoreSize()+1;
9860 Info.size = 2*VT.getStoreSize()-1;
9863 Info.readMem = false;
9864 Info.writeMem = true;
9874 /// getOptimalMemOpType - Returns the target specific optimal type for load
9875 /// and store operations as a result of memset, memcpy, and memmove
9876 /// lowering. If DstAlign is zero that means it's safe to destination
9877 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9878 /// means there isn't a need to check it against alignment requirement,
9879 /// probably because the source does not need to be loaded. If 'IsMemset' is
9880 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9881 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9882 /// source is constant so it does not need to be loaded.
9883 /// It returns EVT::Other if the type should be determined using generic
9884 /// target-independent logic.
9885 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9886 unsigned DstAlign, unsigned SrcAlign,
9887 bool IsMemset, bool ZeroMemset,
9889 MachineFunction &MF) const {
9890 if (Subtarget.isPPC64()) {
9897 /// \brief Returns true if it is beneficial to convert a load of a constant
9898 /// to just the constant itself.
9899 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9901 assert(Ty->isIntegerTy());
9903 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9904 if (BitSize == 0 || BitSize > 64)
9909 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9910 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9912 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9913 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9914 return NumBits1 == 64 && NumBits2 == 32;
9917 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9918 if (!VT1.isInteger() || !VT2.isInteger())
9920 unsigned NumBits1 = VT1.getSizeInBits();
9921 unsigned NumBits2 = VT2.getSizeInBits();
9922 return NumBits1 == 64 && NumBits2 == 32;
9925 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9926 // Generally speaking, zexts are not free, but they are free when they can be
9927 // folded with other operations.
9928 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9929 EVT MemVT = LD->getMemoryVT();
9930 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9931 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9932 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9933 LD->getExtensionType() == ISD::ZEXTLOAD))
9937 // FIXME: Add other cases...
9938 // - 32-bit shifts with a zext to i64
9939 // - zext after ctlz, bswap, etc.
9940 // - zext after and by a constant mask
9942 return TargetLowering::isZExtFree(Val, VT2);
9945 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9946 assert(VT.isFloatingPoint());
9950 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9951 return isInt<16>(Imm) || isUInt<16>(Imm);
9954 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9955 return isInt<16>(Imm) || isUInt<16>(Imm);
9958 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9962 if (DisablePPCUnaligned)
9965 // PowerPC supports unaligned memory access for simple non-vector types.
9966 // Although accessing unaligned addresses is not as efficient as accessing
9967 // aligned addresses, it is generally more efficient than manual expansion,
9968 // and generally only traps for software emulation when crossing page
9974 if (VT.getSimpleVT().isVector()) {
9975 if (Subtarget.hasVSX()) {
9976 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9977 VT != MVT::v4f32 && VT != MVT::v4i32)
9984 if (VT == MVT::ppcf128)
9993 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9994 VT = VT.getScalarType();
9999 switch (VT.getSimpleVT().SimpleTy) {
10011 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
10012 // LR is a callee-save register, but we must treat it as clobbered by any call
10013 // site. Hence we include LR in the scratch registers, which are in turn added
10014 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
10015 // to CTR, which is used by any indirect call.
10016 static const MCPhysReg ScratchRegs[] = {
10017 PPC::X12, PPC::LR8, PPC::CTR8, 0
10020 return ScratchRegs;
10024 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10025 EVT VT , unsigned DefinedValues) const {
10026 if (VT == MVT::v2i64)
10029 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10032 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10033 if (DisableILPPref || Subtarget.enableMachineScheduler())
10034 return TargetLowering::getSchedulingPreference(N);
10039 // Create a fast isel object.
10041 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10042 const TargetLibraryInfo *LibInfo) const {
10043 return PPC::createFastISel(FuncInfo, LibInfo);