1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
101 if (Subtarget.useCRBits()) {
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 if (isPPC64 || Subtarget.hasFPCVT()) {
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
107 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
118 setOperationAction(ISD::STORE, MVT::i1, Custom);
120 // FIXME: Remove this once the ANDI glue bug is fixed:
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
124 for (MVT VT : MVT::integer_valuetypes()) {
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setTruncStoreAction(VT, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
185 Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (MVT VT : MVT::vector_valuetypes()) {
404 // add/sub are legal for all supported vector VT's.
405 setOperationAction(ISD::ADD , VT, Legal);
406 setOperationAction(ISD::SUB , VT, Legal);
408 // Vector instructions introduced in P8
409 if (Subtarget.hasP8Altivec()) {
410 setOperationAction(ISD::CTPOP, VT, Legal);
411 setOperationAction(ISD::CTLZ, VT, Legal);
414 setOperationAction(ISD::CTPOP, VT, Expand);
415 setOperationAction(ISD::CTLZ, VT, Expand);
418 // We promote all shuffles to v16i8.
419 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
420 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
422 // We promote all non-typed operations to v4i32.
423 setOperationAction(ISD::AND , VT, Promote);
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
425 setOperationAction(ISD::OR , VT, Promote);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
427 setOperationAction(ISD::XOR , VT, Promote);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
431 setOperationAction(ISD::SELECT, VT, Promote);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
433 setOperationAction(ISD::STORE, VT, Promote);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
436 // No other operations are legal.
437 setOperationAction(ISD::MUL , VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UDIV, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
442 setOperationAction(ISD::FDIV, VT, Expand);
443 setOperationAction(ISD::FREM, VT, Expand);
444 setOperationAction(ISD::FNEG, VT, Expand);
445 setOperationAction(ISD::FSQRT, VT, Expand);
446 setOperationAction(ISD::FLOG, VT, Expand);
447 setOperationAction(ISD::FLOG10, VT, Expand);
448 setOperationAction(ISD::FLOG2, VT, Expand);
449 setOperationAction(ISD::FEXP, VT, Expand);
450 setOperationAction(ISD::FEXP2, VT, Expand);
451 setOperationAction(ISD::FSIN, VT, Expand);
452 setOperationAction(ISD::FCOS, VT, Expand);
453 setOperationAction(ISD::FABS, VT, Expand);
454 setOperationAction(ISD::FPOWI, VT, Expand);
455 setOperationAction(ISD::FFLOOR, VT, Expand);
456 setOperationAction(ISD::FCEIL, VT, Expand);
457 setOperationAction(ISD::FTRUNC, VT, Expand);
458 setOperationAction(ISD::FRINT, VT, Expand);
459 setOperationAction(ISD::FNEARBYINT, VT, Expand);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
463 setOperationAction(ISD::MULHU, VT, Expand);
464 setOperationAction(ISD::MULHS, VT, Expand);
465 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
466 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::UDIVREM, VT, Expand);
468 setOperationAction(ISD::SDIVREM, VT, Expand);
469 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
470 setOperationAction(ISD::FPOW, VT, Expand);
471 setOperationAction(ISD::BSWAP, VT, Expand);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
473 setOperationAction(ISD::CTTZ, VT, Expand);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
475 setOperationAction(ISD::VSELECT, VT, Expand);
476 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
478 for (MVT InnerVT : MVT::vector_valuetypes()) {
479 setTruncStoreAction(VT, InnerVT, Expand);
480 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
481 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
486 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
487 // with merges, splats, etc.
488 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
494 setOperationAction(ISD::SELECT, MVT::v4i32,
495 Subtarget.useCRBits() ? Legal : Expand);
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
514 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
519 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
520 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
521 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
523 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
524 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
527 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
528 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
531 // Altivec does not contain unordered floating-point compare instructions
532 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
533 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
567 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
568 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
570 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
572 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
574 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
575 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
577 // VSX v2i64 only supports non-arithmetic operations.
578 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
579 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
581 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
583 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
585 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
587 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
588 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
590 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
592 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
594 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
595 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
596 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
597 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
599 // Vector operation legalization checks the result type of
600 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
602 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
606 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
609 if (Subtarget.hasP8Altivec())
610 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
613 if (Subtarget.has64BitSupport())
614 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
616 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
619 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
620 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
623 setBooleanContents(ZeroOrOneBooleanContent);
624 // Altivec instructions set fields to all zeros or all ones.
625 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
628 // These libcalls are not available in 32-bit.
629 setLibcallName(RTLIB::SHL_I128, nullptr);
630 setLibcallName(RTLIB::SRL_I128, nullptr);
631 setLibcallName(RTLIB::SRA_I128, nullptr);
635 setStackPointerRegisterToSaveRestore(PPC::X1);
636 setExceptionPointerRegister(PPC::X3);
637 setExceptionSelectorRegister(PPC::X4);
639 setStackPointerRegisterToSaveRestore(PPC::R1);
640 setExceptionPointerRegister(PPC::R3);
641 setExceptionSelectorRegister(PPC::R4);
644 // We have target-specific dag combine patterns for the following nodes:
645 setTargetDAGCombine(ISD::SINT_TO_FP);
646 if (Subtarget.hasFPCVT())
647 setTargetDAGCombine(ISD::UINT_TO_FP);
648 setTargetDAGCombine(ISD::LOAD);
649 setTargetDAGCombine(ISD::STORE);
650 setTargetDAGCombine(ISD::BR_CC);
651 if (Subtarget.useCRBits())
652 setTargetDAGCombine(ISD::BRCOND);
653 setTargetDAGCombine(ISD::BSWAP);
654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
655 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
656 setTargetDAGCombine(ISD::INTRINSIC_VOID);
658 setTargetDAGCombine(ISD::SIGN_EXTEND);
659 setTargetDAGCombine(ISD::ZERO_EXTEND);
660 setTargetDAGCombine(ISD::ANY_EXTEND);
662 if (Subtarget.useCRBits()) {
663 setTargetDAGCombine(ISD::TRUNCATE);
664 setTargetDAGCombine(ISD::SETCC);
665 setTargetDAGCombine(ISD::SELECT_CC);
668 // Use reciprocal estimates.
669 if (TM.Options.UnsafeFPMath) {
670 setTargetDAGCombine(ISD::FDIV);
671 setTargetDAGCombine(ISD::FSQRT);
674 // Darwin long double math library functions have $LDBL128 appended.
675 if (Subtarget.isDarwin()) {
676 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
677 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
678 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
679 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
680 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
681 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
682 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
683 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
684 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
685 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
688 // With 32 condition bits, we don't need to sink (and duplicate) compares
689 // aggressively in CodeGenPrep.
690 if (Subtarget.useCRBits()) {
691 setHasMultipleConditionRegisters();
692 setJumpIsExpensive();
695 setMinFunctionAlignment(2);
696 if (Subtarget.isDarwin())
697 setPrefFunctionAlignment(4);
699 switch (Subtarget.getDarwinDirective()) {
703 case PPC::DIR_E500mc:
712 setPrefFunctionAlignment(4);
713 setPrefLoopAlignment(4);
717 setInsertFencesForAtomic(true);
719 if (Subtarget.enableMachineScheduler())
720 setSchedulingPreference(Sched::Source);
722 setSchedulingPreference(Sched::Hybrid);
724 computeRegisterProperties();
726 // The Freescale cores do better with aggressive inlining of memcpy and
727 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
728 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
729 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
730 MaxStoresPerMemset = 32;
731 MaxStoresPerMemsetOptSize = 16;
732 MaxStoresPerMemcpy = 32;
733 MaxStoresPerMemcpyOptSize = 8;
734 MaxStoresPerMemmove = 32;
735 MaxStoresPerMemmoveOptSize = 8;
739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
740 /// the desired ByVal argument alignment.
741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
742 unsigned MaxMaxAlign) {
743 if (MaxAlign == MaxMaxAlign)
745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
746 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
748 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
750 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
751 unsigned EltAlign = 0;
752 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
753 if (EltAlign > MaxAlign)
755 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
756 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
757 unsigned EltAlign = 0;
758 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
759 if (EltAlign > MaxAlign)
761 if (MaxAlign == MaxMaxAlign)
767 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
768 /// function arguments in the caller parameter area.
769 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
770 // Darwin passes everything on 4 byte boundary.
771 if (Subtarget.isDarwin())
774 // 16byte and wider vectors are passed on 16byte boundary.
775 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
776 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
777 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
778 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
782 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
784 default: return nullptr;
785 case PPCISD::FSEL: return "PPCISD::FSEL";
786 case PPCISD::FCFID: return "PPCISD::FCFID";
787 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
788 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
789 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
790 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
791 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
792 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
793 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
794 case PPCISD::FRE: return "PPCISD::FRE";
795 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
796 case PPCISD::STFIWX: return "PPCISD::STFIWX";
797 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
798 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
799 case PPCISD::VPERM: return "PPCISD::VPERM";
800 case PPCISD::CMPB: return "PPCISD::CMPB";
801 case PPCISD::Hi: return "PPCISD::Hi";
802 case PPCISD::Lo: return "PPCISD::Lo";
803 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
804 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
805 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
806 case PPCISD::SRL: return "PPCISD::SRL";
807 case PPCISD::SRA: return "PPCISD::SRA";
808 case PPCISD::SHL: return "PPCISD::SHL";
809 case PPCISD::CALL: return "PPCISD::CALL";
810 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
811 case PPCISD::MTCTR: return "PPCISD::MTCTR";
812 case PPCISD::BCTRL: return "PPCISD::BCTRL";
813 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
814 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
815 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
816 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
817 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
818 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
819 case PPCISD::VCMP: return "PPCISD::VCMP";
820 case PPCISD::VCMPo: return "PPCISD::VCMPo";
821 case PPCISD::LBRX: return "PPCISD::LBRX";
822 case PPCISD::STBRX: return "PPCISD::STBRX";
823 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
824 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
825 case PPCISD::LARX: return "PPCISD::LARX";
826 case PPCISD::STCX: return "PPCISD::STCX";
827 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
828 case PPCISD::BDNZ: return "PPCISD::BDNZ";
829 case PPCISD::BDZ: return "PPCISD::BDZ";
830 case PPCISD::MFFS: return "PPCISD::MFFS";
831 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
832 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
833 case PPCISD::CR6SET: return "PPCISD::CR6SET";
834 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
835 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
836 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
837 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
838 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
839 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
840 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
841 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
842 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
843 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
844 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
845 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
846 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
847 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
848 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
849 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
850 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
851 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
852 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
853 case PPCISD::SC: return "PPCISD::SC";
857 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
859 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
860 return VT.changeVectorElementTypeToInteger();
863 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
864 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
868 //===----------------------------------------------------------------------===//
869 // Node matching predicates, for use by the tblgen matching code.
870 //===----------------------------------------------------------------------===//
872 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
873 static bool isFloatingPointZero(SDValue Op) {
874 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
875 return CFP->getValueAPF().isZero();
876 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
877 // Maybe this has already been legalized into the constant pool?
878 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
879 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
880 return CFP->getValueAPF().isZero();
885 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
886 /// true if Op is undef or if it matches the specified value.
887 static bool isConstantOrUndef(int Op, int Val) {
888 return Op < 0 || Op == Val;
891 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
892 /// VPKUHUM instruction.
893 /// The ShuffleKind distinguishes between big-endian operations with
894 /// two different inputs (0), either-endian operations with two identical
895 /// inputs (1), and little-endian operantion with two different inputs (2).
896 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
897 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
899 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
900 if (ShuffleKind == 0) {
903 for (unsigned i = 0; i != 16; ++i)
904 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
906 } else if (ShuffleKind == 2) {
909 for (unsigned i = 0; i != 16; ++i)
910 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
912 } else if (ShuffleKind == 1) {
913 unsigned j = IsLE ? 0 : 1;
914 for (unsigned i = 0; i != 8; ++i)
915 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
916 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
922 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
923 /// VPKUWUM instruction.
924 /// The ShuffleKind distinguishes between big-endian operations with
925 /// two different inputs (0), either-endian operations with two identical
926 /// inputs (1), and little-endian operantion with two different inputs (2).
927 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
928 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
930 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
931 if (ShuffleKind == 0) {
934 for (unsigned i = 0; i != 16; i += 2)
935 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
936 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
938 } else if (ShuffleKind == 2) {
941 for (unsigned i = 0; i != 16; i += 2)
942 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
943 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
945 } else if (ShuffleKind == 1) {
946 unsigned j = IsLE ? 0 : 2;
947 for (unsigned i = 0; i != 8; i += 2)
948 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
949 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
950 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
951 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
957 /// isVMerge - Common function, used to match vmrg* shuffles.
959 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
960 unsigned LHSStart, unsigned RHSStart) {
961 if (N->getValueType(0) != MVT::v16i8)
963 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
964 "Unsupported merge size!");
966 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
967 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
968 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
969 LHSStart+j+i*UnitSize) ||
970 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
971 RHSStart+j+i*UnitSize))
977 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
978 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
979 /// The ShuffleKind distinguishes between big-endian merges with two
980 /// different inputs (0), either-endian merges with two identical inputs (1),
981 /// and little-endian merges with two different inputs (2). For the latter,
982 /// the input operands are swapped (see PPCInstrAltivec.td).
983 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
984 unsigned ShuffleKind, SelectionDAG &DAG) {
985 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
986 if (ShuffleKind == 1) // unary
987 return isVMerge(N, UnitSize, 0, 0);
988 else if (ShuffleKind == 2) // swapped
989 return isVMerge(N, UnitSize, 0, 16);
993 if (ShuffleKind == 1) // unary
994 return isVMerge(N, UnitSize, 8, 8);
995 else if (ShuffleKind == 0) // normal
996 return isVMerge(N, UnitSize, 8, 24);
1002 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1003 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1004 /// The ShuffleKind distinguishes between big-endian merges with two
1005 /// different inputs (0), either-endian merges with two identical inputs (1),
1006 /// and little-endian merges with two different inputs (2). For the latter,
1007 /// the input operands are swapped (see PPCInstrAltivec.td).
1008 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1009 unsigned ShuffleKind, SelectionDAG &DAG) {
1010 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1011 if (ShuffleKind == 1) // unary
1012 return isVMerge(N, UnitSize, 8, 8);
1013 else if (ShuffleKind == 2) // swapped
1014 return isVMerge(N, UnitSize, 8, 24);
1018 if (ShuffleKind == 1) // unary
1019 return isVMerge(N, UnitSize, 0, 0);
1020 else if (ShuffleKind == 0) // normal
1021 return isVMerge(N, UnitSize, 0, 16);
1028 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1029 /// amount, otherwise return -1.
1030 /// The ShuffleKind distinguishes between big-endian operations with two
1031 /// different inputs (0), either-endian operations with two identical inputs
1032 /// (1), and little-endian operations with two different inputs (2). For the
1033 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1034 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1035 SelectionDAG &DAG) {
1036 if (N->getValueType(0) != MVT::v16i8)
1039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1041 // Find the first non-undef value in the shuffle mask.
1043 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1046 if (i == 16) return -1; // all undef.
1048 // Otherwise, check to see if the rest of the elements are consecutively
1049 // numbered from this value.
1050 unsigned ShiftAmt = SVOp->getMaskElt(i);
1051 if (ShiftAmt < i) return -1;
1054 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1056 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1057 // Check the rest of the elements to see if they are consecutive.
1058 for (++i; i != 16; ++i)
1059 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1061 } else if (ShuffleKind == 1) {
1062 // Check the rest of the elements to see if they are consecutive.
1063 for (++i; i != 16; ++i)
1064 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1069 if (ShuffleKind == 2 && isLE)
1070 ShiftAmt = 16 - ShiftAmt;
1075 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1076 /// specifies a splat of a single element that is suitable for input to
1077 /// VSPLTB/VSPLTH/VSPLTW.
1078 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1079 assert(N->getValueType(0) == MVT::v16i8 &&
1080 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1082 // This is a splat operation if each element of the permute is the same, and
1083 // if the value doesn't reference the second vector.
1084 unsigned ElementBase = N->getMaskElt(0);
1086 // FIXME: Handle UNDEF elements too!
1087 if (ElementBase >= 16)
1090 // Check that the indices are consecutive, in the case of a multi-byte element
1091 // splatted with a v16i8 mask.
1092 for (unsigned i = 1; i != EltSize; ++i)
1093 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1096 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1097 if (N->getMaskElt(i) < 0) continue;
1098 for (unsigned j = 0; j != EltSize; ++j)
1099 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1105 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1107 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1108 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1110 APInt APVal, APUndef;
1114 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1115 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1116 return CFP->getValueAPF().isNegZero();
1121 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1122 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1123 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1124 SelectionDAG &DAG) {
1125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1126 assert(isSplatShuffleMask(SVOp, EltSize));
1127 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1128 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1130 return SVOp->getMaskElt(0) / EltSize;
1133 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1134 /// by using a vspltis[bhw] instruction of the specified element size, return
1135 /// the constant being splatted. The ByteSize field indicates the number of
1136 /// bytes of each element [124] -> [bhw].
1137 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1138 SDValue OpVal(nullptr, 0);
1140 // If ByteSize of the splat is bigger than the element size of the
1141 // build_vector, then we have a case where we are checking for a splat where
1142 // multiple elements of the buildvector are folded together into a single
1143 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1144 unsigned EltSize = 16/N->getNumOperands();
1145 if (EltSize < ByteSize) {
1146 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1147 SDValue UniquedVals[4];
1148 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1150 // See if all of the elements in the buildvector agree across.
1151 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1152 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1153 // If the element isn't a constant, bail fully out.
1154 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1157 if (!UniquedVals[i&(Multiple-1)].getNode())
1158 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1159 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1160 return SDValue(); // no match.
1163 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1164 // either constant or undef values that are identical for each chunk. See
1165 // if these chunks can form into a larger vspltis*.
1167 // Check to see if all of the leading entries are either 0 or -1. If
1168 // neither, then this won't fit into the immediate field.
1169 bool LeadingZero = true;
1170 bool LeadingOnes = true;
1171 for (unsigned i = 0; i != Multiple-1; ++i) {
1172 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1174 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1175 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1177 // Finally, check the least significant entry.
1179 if (!UniquedVals[Multiple-1].getNode())
1180 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1181 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1183 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1186 if (!UniquedVals[Multiple-1].getNode())
1187 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1188 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1189 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1190 return DAG.getTargetConstant(Val, MVT::i32);
1196 // Check to see if this buildvec has a single non-undef value in its elements.
1197 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1198 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1199 if (!OpVal.getNode())
1200 OpVal = N->getOperand(i);
1201 else if (OpVal != N->getOperand(i))
1205 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1207 unsigned ValSizeInBytes = EltSize;
1209 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1210 Value = CN->getZExtValue();
1211 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1212 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1213 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1216 // If the splat value is larger than the element value, then we can never do
1217 // this splat. The only case that we could fit the replicated bits into our
1218 // immediate field for would be zero, and we prefer to use vxor for it.
1219 if (ValSizeInBytes < ByteSize) return SDValue();
1221 // If the element value is larger than the splat value, cut it in half and
1222 // check to see if the two halves are equal. Continue doing this until we
1223 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1224 while (ValSizeInBytes > ByteSize) {
1225 ValSizeInBytes >>= 1;
1227 // If the top half equals the bottom half, we're still ok.
1228 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1229 (Value & ((1 << (8*ValSizeInBytes))-1)))
1233 // Properly sign extend the value.
1234 int MaskVal = SignExtend32(Value, ByteSize * 8);
1236 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1237 if (MaskVal == 0) return SDValue();
1239 // Finally, if this value fits in a 5 bit sext field, return it
1240 if (SignExtend32<5>(MaskVal) == MaskVal)
1241 return DAG.getTargetConstant(MaskVal, MVT::i32);
1245 //===----------------------------------------------------------------------===//
1246 // Addressing Mode Selection
1247 //===----------------------------------------------------------------------===//
1249 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1250 /// or 64-bit immediate, and if the value can be accurately represented as a
1251 /// sign extension from a 16-bit value. If so, this returns true and the
1253 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1254 if (!isa<ConstantSDNode>(N))
1257 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1258 if (N->getValueType(0) == MVT::i32)
1259 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1261 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1263 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1264 return isIntS16Immediate(Op.getNode(), Imm);
1268 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1269 /// can be represented as an indexed [r+r] operation. Returns false if it
1270 /// can be more efficiently represented with [r+imm].
1271 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1273 SelectionDAG &DAG) const {
1275 if (N.getOpcode() == ISD::ADD) {
1276 if (isIntS16Immediate(N.getOperand(1), imm))
1277 return false; // r+i
1278 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1279 return false; // r+i
1281 Base = N.getOperand(0);
1282 Index = N.getOperand(1);
1284 } else if (N.getOpcode() == ISD::OR) {
1285 if (isIntS16Immediate(N.getOperand(1), imm))
1286 return false; // r+i can fold it if we can.
1288 // If this is an or of disjoint bitfields, we can codegen this as an add
1289 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1291 APInt LHSKnownZero, LHSKnownOne;
1292 APInt RHSKnownZero, RHSKnownOne;
1293 DAG.computeKnownBits(N.getOperand(0),
1294 LHSKnownZero, LHSKnownOne);
1296 if (LHSKnownZero.getBoolValue()) {
1297 DAG.computeKnownBits(N.getOperand(1),
1298 RHSKnownZero, RHSKnownOne);
1299 // If all of the bits are known zero on the LHS or RHS, the add won't
1301 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1302 Base = N.getOperand(0);
1303 Index = N.getOperand(1);
1312 // If we happen to be doing an i64 load or store into a stack slot that has
1313 // less than a 4-byte alignment, then the frame-index elimination may need to
1314 // use an indexed load or store instruction (because the offset may not be a
1315 // multiple of 4). The extra register needed to hold the offset comes from the
1316 // register scavenger, and it is possible that the scavenger will need to use
1317 // an emergency spill slot. As a result, we need to make sure that a spill slot
1318 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1320 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1321 // FIXME: This does not handle the LWA case.
1325 // NOTE: We'll exclude negative FIs here, which come from argument
1326 // lowering, because there are no known test cases triggering this problem
1327 // using packed structures (or similar). We can remove this exclusion if
1328 // we find such a test case. The reason why this is so test-case driven is
1329 // because this entire 'fixup' is only to prevent crashes (from the
1330 // register scavenger) on not-really-valid inputs. For example, if we have:
1332 // %b = bitcast i1* %a to i64*
1333 // store i64* a, i64 b
1334 // then the store should really be marked as 'align 1', but is not. If it
1335 // were marked as 'align 1' then the indexed form would have been
1336 // instruction-selected initially, and the problem this 'fixup' is preventing
1337 // won't happen regardless.
1341 MachineFunction &MF = DAG.getMachineFunction();
1342 MachineFrameInfo *MFI = MF.getFrameInfo();
1344 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1348 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1349 FuncInfo->setHasNonRISpills();
1352 /// Returns true if the address N can be represented by a base register plus
1353 /// a signed 16-bit displacement [r+imm], and if it is not better
1354 /// represented as reg+reg. If Aligned is true, only accept displacements
1355 /// suitable for STD and friends, i.e. multiples of 4.
1356 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1359 bool Aligned) const {
1360 // FIXME dl should come from parent load or store, not from address
1362 // If this can be more profitably realized as r+r, fail.
1363 if (SelectAddressRegReg(N, Disp, Base, DAG))
1366 if (N.getOpcode() == ISD::ADD) {
1368 if (isIntS16Immediate(N.getOperand(1), imm) &&
1369 (!Aligned || (imm & 3) == 0)) {
1370 Disp = DAG.getTargetConstant(imm, N.getValueType());
1371 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1372 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1373 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1375 Base = N.getOperand(0);
1377 return true; // [r+i]
1378 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1379 // Match LOAD (ADD (X, Lo(G))).
1380 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1381 && "Cannot handle constant offsets yet!");
1382 Disp = N.getOperand(1).getOperand(0); // The global address.
1383 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1384 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1385 Disp.getOpcode() == ISD::TargetConstantPool ||
1386 Disp.getOpcode() == ISD::TargetJumpTable);
1387 Base = N.getOperand(0);
1388 return true; // [&g+r]
1390 } else if (N.getOpcode() == ISD::OR) {
1392 if (isIntS16Immediate(N.getOperand(1), imm) &&
1393 (!Aligned || (imm & 3) == 0)) {
1394 // If this is an or of disjoint bitfields, we can codegen this as an add
1395 // (for better address arithmetic) if the LHS and RHS of the OR are
1396 // provably disjoint.
1397 APInt LHSKnownZero, LHSKnownOne;
1398 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1400 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1401 // If all of the bits are known zero on the LHS or RHS, the add won't
1403 if (FrameIndexSDNode *FI =
1404 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1405 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1406 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1408 Base = N.getOperand(0);
1410 Disp = DAG.getTargetConstant(imm, N.getValueType());
1414 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1415 // Loading from a constant address.
1417 // If this address fits entirely in a 16-bit sext immediate field, codegen
1420 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1421 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1422 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1423 CN->getValueType(0));
1427 // Handle 32-bit sext immediates with LIS + addr mode.
1428 if ((CN->getValueType(0) == MVT::i32 ||
1429 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1430 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1431 int Addr = (int)CN->getZExtValue();
1433 // Otherwise, break this down into an LIS + disp.
1434 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1436 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1437 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1438 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1443 Disp = DAG.getTargetConstant(0, getPointerTy());
1444 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1445 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1446 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1449 return true; // [r+0]
1452 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1453 /// represented as an indexed [r+r] operation.
1454 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1456 SelectionDAG &DAG) const {
1457 // Check to see if we can easily represent this as an [r+r] address. This
1458 // will fail if it thinks that the address is more profitably represented as
1459 // reg+imm, e.g. where imm = 0.
1460 if (SelectAddressRegReg(N, Base, Index, DAG))
1463 // If the operand is an addition, always emit this as [r+r], since this is
1464 // better (for code size, and execution, as the memop does the add for free)
1465 // than emitting an explicit add.
1466 if (N.getOpcode() == ISD::ADD) {
1467 Base = N.getOperand(0);
1468 Index = N.getOperand(1);
1472 // Otherwise, do it the hard way, using R0 as the base register.
1473 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1479 /// getPreIndexedAddressParts - returns true by value, base pointer and
1480 /// offset pointer and addressing mode by reference if the node's address
1481 /// can be legally represented as pre-indexed load / store address.
1482 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1484 ISD::MemIndexedMode &AM,
1485 SelectionDAG &DAG) const {
1486 if (DisablePPCPreinc) return false;
1492 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1493 Ptr = LD->getBasePtr();
1494 VT = LD->getMemoryVT();
1495 Alignment = LD->getAlignment();
1496 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1497 Ptr = ST->getBasePtr();
1498 VT = ST->getMemoryVT();
1499 Alignment = ST->getAlignment();
1504 // PowerPC doesn't have preinc load/store instructions for vectors.
1508 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1510 // Common code will reject creating a pre-inc form if the base pointer
1511 // is a frame index, or if N is a store and the base pointer is either
1512 // the same as or a predecessor of the value being stored. Check for
1513 // those situations here, and try with swapped Base/Offset instead.
1516 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1519 SDValue Val = cast<StoreSDNode>(N)->getValue();
1520 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1525 std::swap(Base, Offset);
1531 // LDU/STU can only handle immediates that are a multiple of 4.
1532 if (VT != MVT::i64) {
1533 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1536 // LDU/STU need an address with at least 4-byte alignment.
1540 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1544 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1545 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1546 // sext i32 to i64 when addr mode is r+i.
1547 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1548 LD->getExtensionType() == ISD::SEXTLOAD &&
1549 isa<ConstantSDNode>(Offset))
1557 //===----------------------------------------------------------------------===//
1558 // LowerOperation implementation
1559 //===----------------------------------------------------------------------===//
1561 /// GetLabelAccessInfo - Return true if we should reference labels using a
1562 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1563 static bool GetLabelAccessInfo(const TargetMachine &TM,
1564 const PPCSubtarget &Subtarget,
1565 unsigned &HiOpFlags, unsigned &LoOpFlags,
1566 const GlobalValue *GV = nullptr) {
1567 HiOpFlags = PPCII::MO_HA;
1568 LoOpFlags = PPCII::MO_LO;
1570 // Don't use the pic base if not in PIC relocation model.
1571 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1574 HiOpFlags |= PPCII::MO_PIC_FLAG;
1575 LoOpFlags |= PPCII::MO_PIC_FLAG;
1578 // If this is a reference to a global value that requires a non-lazy-ptr, make
1579 // sure that instruction lowering adds it.
1580 if (GV && Subtarget.hasLazyResolverStub(GV, TM)) {
1581 HiOpFlags |= PPCII::MO_NLP_FLAG;
1582 LoOpFlags |= PPCII::MO_NLP_FLAG;
1584 if (GV->hasHiddenVisibility()) {
1585 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1586 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1593 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1594 SelectionDAG &DAG) {
1595 EVT PtrVT = HiPart.getValueType();
1596 SDValue Zero = DAG.getConstant(0, PtrVT);
1599 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1600 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1602 // With PIC, the first instruction is actually "GR+hi(&G)".
1604 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1605 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1607 // Generate non-pic code that has direct accesses to the constant pool.
1608 // The address of the global is just (hi(&g)+lo(&g)).
1609 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1612 static void setUsesTOCBasePtr(MachineFunction &MF) {
1613 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1614 FuncInfo->setUsesTOCBasePtr();
1617 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1618 setUsesTOCBasePtr(DAG.getMachineFunction());
1621 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1622 SelectionDAG &DAG) const {
1623 EVT PtrVT = Op.getValueType();
1624 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1625 const Constant *C = CP->getConstVal();
1627 // 64-bit SVR4 ABI code is always position-independent.
1628 // The actual address of the GlobalValue is stored in the TOC.
1629 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1630 setUsesTOCBasePtr(DAG);
1631 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1632 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1633 DAG.getRegister(PPC::X2, MVT::i64));
1636 unsigned MOHiFlag, MOLoFlag;
1638 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1640 if (isPIC && Subtarget.isSVR4ABI()) {
1641 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1642 PPCII::MO_PIC_FLAG);
1644 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1645 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1649 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1651 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1652 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1655 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1656 EVT PtrVT = Op.getValueType();
1657 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1659 // 64-bit SVR4 ABI code is always position-independent.
1660 // The actual address of the GlobalValue is stored in the TOC.
1661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1662 setUsesTOCBasePtr(DAG);
1663 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1664 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1665 DAG.getRegister(PPC::X2, MVT::i64));
1668 unsigned MOHiFlag, MOLoFlag;
1670 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1672 if (isPIC && Subtarget.isSVR4ABI()) {
1673 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1674 PPCII::MO_PIC_FLAG);
1676 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1677 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1680 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1681 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1682 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1685 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1689 const BlockAddress *BA = BASDN->getBlockAddress();
1691 // 64-bit SVR4 ABI code is always position-independent.
1692 // The actual BlockAddress is stored in the TOC.
1693 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1694 setUsesTOCBasePtr(DAG);
1695 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1702 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1703 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1704 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1705 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1708 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1709 SelectionDAG &DAG) const {
1711 // FIXME: TLS addresses currently use medium model code sequences,
1712 // which is the most useful form. Eventually support for small and
1713 // large models could be added if users need it, at the cost of
1714 // additional complexity.
1715 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1717 const GlobalValue *GV = GA->getGlobal();
1718 EVT PtrVT = getPointerTy();
1719 bool is64bit = Subtarget.isPPC64();
1720 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1721 PICLevel::Level picLevel = M->getPICLevel();
1723 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1725 if (Model == TLSModel::LocalExec) {
1726 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1727 PPCII::MO_TPREL_HA);
1728 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 PPCII::MO_TPREL_LO);
1730 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1731 is64bit ? MVT::i64 : MVT::i32);
1732 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1733 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1736 if (Model == TLSModel::InitialExec) {
1737 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1738 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1742 setUsesTOCBasePtr(DAG);
1743 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1744 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1745 PtrVT, GOTReg, TGA);
1747 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1748 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1749 PtrVT, TGA, GOTPtr);
1750 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1753 if (Model == TLSModel::GeneralDynamic) {
1754 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1757 setUsesTOCBasePtr(DAG);
1758 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1759 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1762 if (picLevel == PICLevel::Small)
1763 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1765 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1767 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
1771 if (Model == TLSModel::LocalDynamic) {
1772 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1775 setUsesTOCBasePtr(DAG);
1776 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1777 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1780 if (picLevel == PICLevel::Small)
1781 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1783 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1785 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
1786 PtrVT, GOTPtr, TGA, TGA);
1787 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
1788 PtrVT, TLSAddr, TGA);
1789 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1792 llvm_unreachable("Unknown TLS model!");
1795 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1796 SelectionDAG &DAG) const {
1797 EVT PtrVT = Op.getValueType();
1798 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1800 const GlobalValue *GV = GSDN->getGlobal();
1802 // 64-bit SVR4 ABI code is always position-independent.
1803 // The actual address of the GlobalValue is stored in the TOC.
1804 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1805 setUsesTOCBasePtr(DAG);
1806 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1807 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1808 DAG.getRegister(PPC::X2, MVT::i64));
1811 unsigned MOHiFlag, MOLoFlag;
1813 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
1815 if (isPIC && Subtarget.isSVR4ABI()) {
1816 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1818 PPCII::MO_PIC_FLAG);
1819 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1820 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1824 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1826 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1828 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1830 // If the global reference is actually to a non-lazy-pointer, we have to do an
1831 // extra load to get the address of the global.
1832 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1833 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1834 false, false, false, 0);
1838 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1839 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1842 if (Op.getValueType() == MVT::v2i64) {
1843 // When the operands themselves are v2i64 values, we need to do something
1844 // special because VSX has no underlying comparison operations for these.
1845 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1846 // Equality can be handled by casting to the legal type for Altivec
1847 // comparisons, everything else needs to be expanded.
1848 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1849 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1850 DAG.getSetCC(dl, MVT::v4i32,
1851 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1852 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1859 // We handle most of these in the usual way.
1863 // If we're comparing for equality to zero, expose the fact that this is
1864 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1865 // fold the new nodes.
1866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1867 if (C->isNullValue() && CC == ISD::SETEQ) {
1868 EVT VT = Op.getOperand(0).getValueType();
1869 SDValue Zext = Op.getOperand(0);
1870 if (VT.bitsLT(MVT::i32)) {
1872 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1874 unsigned Log2b = Log2_32(VT.getSizeInBits());
1875 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1876 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1877 DAG.getConstant(Log2b, MVT::i32));
1878 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1880 // Leave comparisons against 0 and -1 alone for now, since they're usually
1881 // optimized. FIXME: revisit this when we can custom lower all setcc
1883 if (C->isAllOnesValue() || C->isNullValue())
1887 // If we have an integer seteq/setne, turn it into a compare against zero
1888 // by xor'ing the rhs with the lhs, which is faster than setting a
1889 // condition register, reading it back out, and masking the correct bit. The
1890 // normal approach here uses sub to do this instead of xor. Using xor exposes
1891 // the result to other bit-twiddling opportunities.
1892 EVT LHSVT = Op.getOperand(0).getValueType();
1893 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1894 EVT VT = Op.getValueType();
1895 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1897 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1902 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1903 const PPCSubtarget &Subtarget) const {
1904 SDNode *Node = Op.getNode();
1905 EVT VT = Node->getValueType(0);
1906 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1907 SDValue InChain = Node->getOperand(0);
1908 SDValue VAListPtr = Node->getOperand(1);
1909 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1912 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1915 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1916 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1917 false, false, false, 0);
1918 InChain = GprIndex.getValue(1);
1920 if (VT == MVT::i64) {
1921 // Check if GprIndex is even
1922 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1923 DAG.getConstant(1, MVT::i32));
1924 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1925 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1926 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1927 DAG.getConstant(1, MVT::i32));
1928 // Align GprIndex to be even if it isn't
1929 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1933 // fpr index is 1 byte after gpr
1934 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1935 DAG.getConstant(1, MVT::i32));
1938 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1939 FprPtr, MachinePointerInfo(SV), MVT::i8,
1940 false, false, false, 0);
1941 InChain = FprIndex.getValue(1);
1943 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1944 DAG.getConstant(8, MVT::i32));
1946 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1947 DAG.getConstant(4, MVT::i32));
1950 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1951 MachinePointerInfo(), false, false,
1953 InChain = OverflowArea.getValue(1);
1955 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1956 MachinePointerInfo(), false, false,
1958 InChain = RegSaveArea.getValue(1);
1960 // select overflow_area if index > 8
1961 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1962 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1964 // adjustment constant gpr_index * 4/8
1965 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1966 VT.isInteger() ? GprIndex : FprIndex,
1967 DAG.getConstant(VT.isInteger() ? 4 : 8,
1970 // OurReg = RegSaveArea + RegConstant
1971 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1974 // Floating types are 32 bytes into RegSaveArea
1975 if (VT.isFloatingPoint())
1976 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1977 DAG.getConstant(32, MVT::i32));
1979 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1980 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1981 VT.isInteger() ? GprIndex : FprIndex,
1982 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1985 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1986 VT.isInteger() ? VAListPtr : FprPtr,
1987 MachinePointerInfo(SV),
1988 MVT::i8, false, false, 0);
1990 // determine if we should load from reg_save_area or overflow_area
1991 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1993 // increase overflow_area by 4/8 if gpr/fpr > 8
1994 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1995 DAG.getConstant(VT.isInteger() ? 4 : 8,
1998 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2001 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2003 MachinePointerInfo(),
2004 MVT::i32, false, false, 0);
2006 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2007 false, false, false, 0);
2010 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2011 const PPCSubtarget &Subtarget) const {
2012 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2014 // We have to copy the entire va_list struct:
2015 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2016 return DAG.getMemcpy(Op.getOperand(0), Op,
2017 Op.getOperand(1), Op.getOperand(2),
2018 DAG.getConstant(12, MVT::i32), 8, false, true,
2019 MachinePointerInfo(), MachinePointerInfo());
2022 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2023 SelectionDAG &DAG) const {
2024 return Op.getOperand(0);
2027 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2028 SelectionDAG &DAG) const {
2029 SDValue Chain = Op.getOperand(0);
2030 SDValue Trmp = Op.getOperand(1); // trampoline
2031 SDValue FPtr = Op.getOperand(2); // nested function
2032 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2035 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2036 bool isPPC64 = (PtrVT == MVT::i64);
2038 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2041 TargetLowering::ArgListTy Args;
2042 TargetLowering::ArgListEntry Entry;
2044 Entry.Ty = IntPtrTy;
2045 Entry.Node = Trmp; Args.push_back(Entry);
2047 // TrampSize == (isPPC64 ? 48 : 40);
2048 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2049 isPPC64 ? MVT::i64 : MVT::i32);
2050 Args.push_back(Entry);
2052 Entry.Node = FPtr; Args.push_back(Entry);
2053 Entry.Node = Nest; Args.push_back(Entry);
2055 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2056 TargetLowering::CallLoweringInfo CLI(DAG);
2057 CLI.setDebugLoc(dl).setChain(Chain)
2058 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2059 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2060 std::move(Args), 0);
2062 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2063 return CallResult.second;
2066 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2067 const PPCSubtarget &Subtarget) const {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2073 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2074 // vastart just stores the address of the VarArgsFrameIndex slot into the
2075 // memory location argument.
2076 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2077 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2078 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2079 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2080 MachinePointerInfo(SV),
2084 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2085 // We suppose the given va_list is already allocated.
2088 // char gpr; /* index into the array of 8 GPRs
2089 // * stored in the register save area
2090 // * gpr=0 corresponds to r3,
2091 // * gpr=1 to r4, etc.
2093 // char fpr; /* index into the array of 8 FPRs
2094 // * stored in the register save area
2095 // * fpr=0 corresponds to f1,
2096 // * fpr=1 to f2, etc.
2098 // char *overflow_arg_area;
2099 // /* location on stack that holds
2100 // * the next overflow argument
2102 // char *reg_save_area;
2103 // /* where r3:r10 and f1:f8 (if saved)
2109 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2110 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2113 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2115 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2117 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2120 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2121 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2123 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2124 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2126 uint64_t FPROffset = 1;
2127 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2129 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2131 // Store first byte : number of int regs
2132 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2134 MachinePointerInfo(SV),
2135 MVT::i8, false, false, 0);
2136 uint64_t nextOffset = FPROffset;
2137 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2140 // Store second byte : number of float regs
2141 SDValue secondStore =
2142 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2143 MachinePointerInfo(SV, nextOffset), MVT::i8,
2145 nextOffset += StackOffset;
2146 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2148 // Store second word : arguments given on stack
2149 SDValue thirdStore =
2150 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2151 MachinePointerInfo(SV, nextOffset),
2153 nextOffset += FrameOffset;
2154 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2156 // Store third word : arguments given in registers
2157 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2158 MachinePointerInfo(SV, nextOffset),
2163 #include "PPCGenCallingConv.inc"
2165 // Function whose sole purpose is to kill compiler warnings
2166 // stemming from unused functions included from PPCGenCallingConv.inc.
2167 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2168 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2171 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2172 CCValAssign::LocInfo &LocInfo,
2173 ISD::ArgFlagsTy &ArgFlags,
2178 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2180 CCValAssign::LocInfo &LocInfo,
2181 ISD::ArgFlagsTy &ArgFlags,
2183 static const MCPhysReg ArgRegs[] = {
2184 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2185 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2187 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2189 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2191 // Skip one register if the first unallocated register has an even register
2192 // number and there are still argument registers available which have not been
2193 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2194 // need to skip a register if RegNum is odd.
2195 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2196 State.AllocateReg(ArgRegs[RegNum]);
2199 // Always return false here, as this function only makes sure that the first
2200 // unallocated register has an odd register number and does not actually
2201 // allocate a register for the current argument.
2205 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2207 CCValAssign::LocInfo &LocInfo,
2208 ISD::ArgFlagsTy &ArgFlags,
2210 static const MCPhysReg ArgRegs[] = {
2211 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2215 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2217 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2219 // If there is only one Floating-point register left we need to put both f64
2220 // values of a split ppc_fp128 value on the stack.
2221 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2222 State.AllocateReg(ArgRegs[RegNum]);
2225 // Always return false here, as this function only makes sure that the two f64
2226 // values a ppc_fp128 value is split into are both passed in registers or both
2227 // passed on the stack and does not actually allocate a register for the
2228 // current argument.
2232 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2234 static const MCPhysReg *GetFPR() {
2235 static const MCPhysReg FPR[] = {
2236 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2237 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2243 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2245 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2246 unsigned PtrByteSize) {
2247 unsigned ArgSize = ArgVT.getStoreSize();
2248 if (Flags.isByVal())
2249 ArgSize = Flags.getByValSize();
2251 // Round up to multiples of the pointer size, except for array members,
2252 // which are always packed.
2253 if (!Flags.isInConsecutiveRegs())
2254 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2259 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2261 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2262 ISD::ArgFlagsTy Flags,
2263 unsigned PtrByteSize) {
2264 unsigned Align = PtrByteSize;
2266 // Altivec parameters are padded to a 16 byte boundary.
2267 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2268 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2269 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2272 // ByVal parameters are aligned as requested.
2273 if (Flags.isByVal()) {
2274 unsigned BVAlign = Flags.getByValAlign();
2275 if (BVAlign > PtrByteSize) {
2276 if (BVAlign % PtrByteSize != 0)
2278 "ByVal alignment is not a multiple of the pointer size");
2284 // Array members are always packed to their original alignment.
2285 if (Flags.isInConsecutiveRegs()) {
2286 // If the array member was split into multiple registers, the first
2287 // needs to be aligned to the size of the full type. (Except for
2288 // ppcf128, which is only aligned as its f64 components.)
2289 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2290 Align = OrigVT.getStoreSize();
2292 Align = ArgVT.getStoreSize();
2298 /// CalculateStackSlotUsed - Return whether this argument will use its
2299 /// stack slot (instead of being passed in registers). ArgOffset,
2300 /// AvailableFPRs, and AvailableVRs must hold the current argument
2301 /// position, and will be updated to account for this argument.
2302 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2303 ISD::ArgFlagsTy Flags,
2304 unsigned PtrByteSize,
2305 unsigned LinkageSize,
2306 unsigned ParamAreaSize,
2307 unsigned &ArgOffset,
2308 unsigned &AvailableFPRs,
2309 unsigned &AvailableVRs) {
2310 bool UseMemory = false;
2312 // Respect alignment of argument on the stack.
2314 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2315 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2316 // If there's no space left in the argument save area, we must
2317 // use memory (this check also catches zero-sized arguments).
2318 if (ArgOffset >= LinkageSize + ParamAreaSize)
2321 // Allocate argument on the stack.
2322 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2323 if (Flags.isInConsecutiveRegsLast())
2324 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2325 // If we overran the argument save area, we must use memory
2326 // (this check catches arguments passed partially in memory)
2327 if (ArgOffset > LinkageSize + ParamAreaSize)
2330 // However, if the argument is actually passed in an FPR or a VR,
2331 // we don't use memory after all.
2332 if (!Flags.isByVal()) {
2333 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2334 if (AvailableFPRs > 0) {
2338 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2339 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2340 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2341 if (AvailableVRs > 0) {
2350 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2351 /// ensure minimum alignment required for target.
2352 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2353 unsigned NumBytes) {
2354 unsigned TargetAlign = Lowering->getStackAlignment();
2355 unsigned AlignMask = TargetAlign - 1;
2356 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2361 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2362 CallingConv::ID CallConv, bool isVarArg,
2363 const SmallVectorImpl<ISD::InputArg>
2365 SDLoc dl, SelectionDAG &DAG,
2366 SmallVectorImpl<SDValue> &InVals)
2368 if (Subtarget.isSVR4ABI()) {
2369 if (Subtarget.isPPC64())
2370 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2373 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2376 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2382 PPCTargetLowering::LowerFormalArguments_32SVR4(
2384 CallingConv::ID CallConv, bool isVarArg,
2385 const SmallVectorImpl<ISD::InputArg>
2387 SDLoc dl, SelectionDAG &DAG,
2388 SmallVectorImpl<SDValue> &InVals) const {
2390 // 32-bit SVR4 ABI Stack Frame Layout:
2391 // +-----------------------------------+
2392 // +--> | Back chain |
2393 // | +-----------------------------------+
2394 // | | Floating-point register save area |
2395 // | +-----------------------------------+
2396 // | | General register save area |
2397 // | +-----------------------------------+
2398 // | | CR save word |
2399 // | +-----------------------------------+
2400 // | | VRSAVE save word |
2401 // | +-----------------------------------+
2402 // | | Alignment padding |
2403 // | +-----------------------------------+
2404 // | | Vector register save area |
2405 // | +-----------------------------------+
2406 // | | Local variable space |
2407 // | +-----------------------------------+
2408 // | | Parameter list area |
2409 // | +-----------------------------------+
2410 // | | LR save word |
2411 // | +-----------------------------------+
2412 // SP--> +--- | Back chain |
2413 // +-----------------------------------+
2416 // System V Application Binary Interface PowerPC Processor Supplement
2417 // AltiVec Technology Programming Interface Manual
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2423 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2424 // Potential tail calls could cause overwriting of argument stack slots.
2425 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2426 (CallConv == CallingConv::Fast));
2427 unsigned PtrByteSize = 4;
2429 // Assign locations to all of the incoming arguments.
2430 SmallVector<CCValAssign, 16> ArgLocs;
2431 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2434 // Reserve space for the linkage area on the stack.
2435 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2436 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2438 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2440 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2441 CCValAssign &VA = ArgLocs[i];
2443 // Arguments stored in registers.
2444 if (VA.isRegLoc()) {
2445 const TargetRegisterClass *RC;
2446 EVT ValVT = VA.getValVT();
2448 switch (ValVT.getSimpleVT().SimpleTy) {
2450 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2453 RC = &PPC::GPRCRegClass;
2456 RC = &PPC::F4RCRegClass;
2459 if (Subtarget.hasVSX())
2460 RC = &PPC::VSFRCRegClass;
2462 RC = &PPC::F8RCRegClass;
2468 RC = &PPC::VRRCRegClass;
2472 RC = &PPC::VSHRCRegClass;
2476 // Transform the arguments stored in physical registers into virtual ones.
2477 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2478 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2479 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2481 if (ValVT == MVT::i1)
2482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2484 InVals.push_back(ArgValue);
2486 // Argument stored in memory.
2487 assert(VA.isMemLoc());
2489 unsigned ArgSize = VA.getLocVT().getStoreSize();
2490 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2493 // Create load nodes to retrieve arguments from the stack.
2494 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2495 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2496 MachinePointerInfo(),
2497 false, false, false, 0));
2501 // Assign locations to all of the incoming aggregate by value arguments.
2502 // Aggregates passed by value are stored in the local variable space of the
2503 // caller's stack frame, right above the parameter list area.
2504 SmallVector<CCValAssign, 16> ByValArgLocs;
2505 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2506 ByValArgLocs, *DAG.getContext());
2508 // Reserve stack space for the allocations in CCInfo.
2509 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2511 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2513 // Area that is at least reserved in the caller of this function.
2514 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2515 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2517 // Set the size that is at least reserved in caller of this function. Tail
2518 // call optimized function's reserved stack space needs to be aligned so that
2519 // taking the difference between two stack areas will result in an aligned
2522 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2523 FuncInfo->setMinReservedArea(MinReservedArea);
2525 SmallVector<SDValue, 8> MemOps;
2527 // If the function takes variable number of arguments, make a frame index for
2528 // the start of the first vararg value... for expansion of llvm.va_start.
2530 static const MCPhysReg GPArgRegs[] = {
2531 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2532 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2534 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2536 static const MCPhysReg FPArgRegs[] = {
2537 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2540 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2541 if (DisablePPCFloatInVariadic)
2544 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2546 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2549 // Make room for NumGPArgRegs and NumFPArgRegs.
2550 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2551 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2553 FuncInfo->setVarArgsStackOffset(
2554 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2555 CCInfo.getNextStackOffset(), true));
2557 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2558 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2560 // The fixed integer arguments of a variadic function are stored to the
2561 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2562 // the result of va_next.
2563 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2564 // Get an existing live-in vreg, or add a new one.
2565 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2567 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2569 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2570 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2571 MachinePointerInfo(), false, false, 0);
2572 MemOps.push_back(Store);
2573 // Increment the address by four for the next argument to store
2574 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2575 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2578 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2580 // The double arguments are stored to the VarArgsFrameIndex
2582 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2583 // Get an existing live-in vreg, or add a new one.
2584 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2586 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2589 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2590 MachinePointerInfo(), false, false, 0);
2591 MemOps.push_back(Store);
2592 // Increment the address by eight for the next argument to store
2593 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2595 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2599 if (!MemOps.empty())
2600 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2605 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2606 // value to MVT::i64 and then truncate to the correct register size.
2608 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2609 SelectionDAG &DAG, SDValue ArgVal,
2612 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2613 DAG.getValueType(ObjectVT));
2614 else if (Flags.isZExt())
2615 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2616 DAG.getValueType(ObjectVT));
2618 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2622 PPCTargetLowering::LowerFormalArguments_64SVR4(
2624 CallingConv::ID CallConv, bool isVarArg,
2625 const SmallVectorImpl<ISD::InputArg>
2627 SDLoc dl, SelectionDAG &DAG,
2628 SmallVectorImpl<SDValue> &InVals) const {
2629 // TODO: add description of PPC stack frame format, or at least some docs.
2631 bool isELFv2ABI = Subtarget.isELFv2ABI();
2632 bool isLittleEndian = Subtarget.isLittleEndian();
2633 MachineFunction &MF = DAG.getMachineFunction();
2634 MachineFrameInfo *MFI = MF.getFrameInfo();
2635 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2637 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2638 "fastcc not supported on varargs functions");
2640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2641 // Potential tail calls could cause overwriting of argument stack slots.
2642 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2643 (CallConv == CallingConv::Fast));
2644 unsigned PtrByteSize = 8;
2646 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2649 static const MCPhysReg GPR[] = {
2650 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2651 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2654 static const MCPhysReg *FPR = GetFPR();
2656 static const MCPhysReg VR[] = {
2657 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2658 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2660 static const MCPhysReg VSRH[] = {
2661 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2662 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2665 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2666 const unsigned Num_FPR_Regs = 13;
2667 const unsigned Num_VR_Regs = array_lengthof(VR);
2669 // Do a first pass over the arguments to determine whether the ABI
2670 // guarantees that our caller has allocated the parameter save area
2671 // on its stack frame. In the ELFv1 ABI, this is always the case;
2672 // in the ELFv2 ABI, it is true if this is a vararg function or if
2673 // any parameter is located in a stack slot.
2675 bool HasParameterArea = !isELFv2ABI || isVarArg;
2676 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2677 unsigned NumBytes = LinkageSize;
2678 unsigned AvailableFPRs = Num_FPR_Regs;
2679 unsigned AvailableVRs = Num_VR_Regs;
2680 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2681 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2682 PtrByteSize, LinkageSize, ParamAreaSize,
2683 NumBytes, AvailableFPRs, AvailableVRs))
2684 HasParameterArea = true;
2686 // Add DAG nodes to load the arguments or copy them out of registers. On
2687 // entry to a function on PPC, the arguments start after the linkage area,
2688 // although the first ones are often in registers.
2690 unsigned ArgOffset = LinkageSize;
2691 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2692 SmallVector<SDValue, 8> MemOps;
2693 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2694 unsigned CurArgIdx = 0;
2695 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2697 bool needsLoad = false;
2698 EVT ObjectVT = Ins[ArgNo].VT;
2699 EVT OrigVT = Ins[ArgNo].ArgVT;
2700 unsigned ObjSize = ObjectVT.getStoreSize();
2701 unsigned ArgSize = ObjSize;
2702 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2703 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2704 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2706 // We re-align the argument offset for each argument, except when using the
2707 // fast calling convention, when we need to make sure we do that only when
2708 // we'll actually use a stack slot.
2709 unsigned CurArgOffset, Align;
2710 auto ComputeArgOffset = [&]() {
2711 /* Respect alignment of argument on the stack. */
2712 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2713 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2714 CurArgOffset = ArgOffset;
2717 if (CallConv != CallingConv::Fast) {
2720 /* Compute GPR index associated with argument offset. */
2721 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2722 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2725 // FIXME the codegen can be much improved in some cases.
2726 // We do not have to keep everything in memory.
2727 if (Flags.isByVal()) {
2728 if (CallConv == CallingConv::Fast)
2731 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2732 ObjSize = Flags.getByValSize();
2733 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2734 // Empty aggregate parameters do not take up registers. Examples:
2738 // etc. However, we have to provide a place-holder in InVals, so
2739 // pretend we have an 8-byte item at the current address for that
2742 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2743 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2744 InVals.push_back(FIN);
2748 // Create a stack object covering all stack doublewords occupied
2749 // by the argument. If the argument is (fully or partially) on
2750 // the stack, or if the argument is fully in registers but the
2751 // caller has allocated the parameter save anyway, we can refer
2752 // directly to the caller's stack frame. Otherwise, create a
2753 // local copy in our own frame.
2755 if (HasParameterArea ||
2756 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2757 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2759 FI = MFI->CreateStackObject(ArgSize, Align, false);
2760 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2762 // Handle aggregates smaller than 8 bytes.
2763 if (ObjSize < PtrByteSize) {
2764 // The value of the object is its address, which differs from the
2765 // address of the enclosing doubleword on big-endian systems.
2767 if (!isLittleEndian) {
2768 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2769 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2771 InVals.push_back(Arg);
2773 if (GPR_idx != Num_GPR_Regs) {
2774 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2775 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2778 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2779 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2780 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2781 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2782 MachinePointerInfo(FuncArg),
2783 ObjType, false, false, 0);
2785 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2786 // store the whole register as-is to the parameter save area
2788 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2789 MachinePointerInfo(FuncArg),
2793 MemOps.push_back(Store);
2795 // Whether we copied from a register or not, advance the offset
2796 // into the parameter save area by a full doubleword.
2797 ArgOffset += PtrByteSize;
2801 // The value of the object is its address, which is the address of
2802 // its first stack doubleword.
2803 InVals.push_back(FIN);
2805 // Store whatever pieces of the object are in registers to memory.
2806 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2807 if (GPR_idx == Num_GPR_Regs)
2810 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2811 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2814 SDValue Off = DAG.getConstant(j, PtrVT);
2815 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2817 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2818 MachinePointerInfo(FuncArg, j),
2820 MemOps.push_back(Store);
2823 ArgOffset += ArgSize;
2827 switch (ObjectVT.getSimpleVT().SimpleTy) {
2828 default: llvm_unreachable("Unhandled argument type!");
2832 // These can be scalar arguments or elements of an integer array type
2833 // passed directly. Clang may use those instead of "byval" aggregate
2834 // types to avoid forcing arguments to memory unnecessarily.
2835 if (GPR_idx != Num_GPR_Regs) {
2836 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2837 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2839 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2840 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2841 // value to MVT::i64 and then truncate to the correct register size.
2842 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2844 if (CallConv == CallingConv::Fast)
2848 ArgSize = PtrByteSize;
2850 if (CallConv != CallingConv::Fast || needsLoad)
2856 // These can be scalar arguments or elements of a float array type
2857 // passed directly. The latter are used to implement ELFv2 homogenous
2858 // float aggregates.
2859 if (FPR_idx != Num_FPR_Regs) {
2862 if (ObjectVT == MVT::f32)
2863 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2865 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
2866 ? &PPC::VSFRCRegClass
2867 : &PPC::F8RCRegClass);
2869 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2871 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2872 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
2873 // once we support fp <-> gpr moves.
2875 // This can only ever happen in the presence of f32 array types,
2876 // since otherwise we never run out of FPRs before running out
2878 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2879 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2881 if (ObjectVT == MVT::f32) {
2882 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2883 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2884 DAG.getConstant(32, MVT::i32));
2885 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2888 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2890 if (CallConv == CallingConv::Fast)
2896 // When passing an array of floats, the array occupies consecutive
2897 // space in the argument area; only round up to the next doubleword
2898 // at the end of the array. Otherwise, each float takes 8 bytes.
2899 if (CallConv != CallingConv::Fast || needsLoad) {
2900 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2901 ArgOffset += ArgSize;
2902 if (Flags.isInConsecutiveRegsLast())
2903 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2912 // These can be scalar arguments or elements of a vector array type
2913 // passed directly. The latter are used to implement ELFv2 homogenous
2914 // vector aggregates.
2915 if (VR_idx != Num_VR_Regs) {
2916 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2917 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2918 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2919 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2922 if (CallConv == CallingConv::Fast)
2927 if (CallConv != CallingConv::Fast || needsLoad)
2932 // We need to load the argument to a virtual register if we determined
2933 // above that we ran out of physical registers of the appropriate type.
2935 if (ObjSize < ArgSize && !isLittleEndian)
2936 CurArgOffset += ArgSize - ObjSize;
2937 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2938 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2939 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2940 false, false, false, 0);
2943 InVals.push_back(ArgVal);
2946 // Area that is at least reserved in the caller of this function.
2947 unsigned MinReservedArea;
2948 if (HasParameterArea)
2949 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2951 MinReservedArea = LinkageSize;
2953 // Set the size that is at least reserved in caller of this function. Tail
2954 // call optimized functions' reserved stack space needs to be aligned so that
2955 // taking the difference between two stack areas will result in an aligned
2958 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2959 FuncInfo->setMinReservedArea(MinReservedArea);
2961 // If the function takes variable number of arguments, make a frame index for
2962 // the start of the first vararg value... for expansion of llvm.va_start.
2964 int Depth = ArgOffset;
2966 FuncInfo->setVarArgsFrameIndex(
2967 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2968 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2970 // If this function is vararg, store any remaining integer argument regs
2971 // to their spots on the stack so that they may be loaded by deferencing the
2972 // result of va_next.
2973 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2974 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2975 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2976 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2977 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2978 MachinePointerInfo(), false, false, 0);
2979 MemOps.push_back(Store);
2980 // Increment the address by four for the next argument to store
2981 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2982 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2986 if (!MemOps.empty())
2987 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2993 PPCTargetLowering::LowerFormalArguments_Darwin(
2995 CallingConv::ID CallConv, bool isVarArg,
2996 const SmallVectorImpl<ISD::InputArg>
2998 SDLoc dl, SelectionDAG &DAG,
2999 SmallVectorImpl<SDValue> &InVals) const {
3000 // TODO: add description of PPC stack frame format, or at least some docs.
3002 MachineFunction &MF = DAG.getMachineFunction();
3003 MachineFrameInfo *MFI = MF.getFrameInfo();
3004 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3006 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3007 bool isPPC64 = PtrVT == MVT::i64;
3008 // Potential tail calls could cause overwriting of argument stack slots.
3009 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3010 (CallConv == CallingConv::Fast));
3011 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3013 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
3015 unsigned ArgOffset = LinkageSize;
3016 // Area that is at least reserved in caller of this function.
3017 unsigned MinReservedArea = ArgOffset;
3019 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3020 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3021 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3023 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3024 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3025 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3028 static const MCPhysReg *FPR = GetFPR();
3030 static const MCPhysReg VR[] = {
3031 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3032 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3035 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3036 const unsigned Num_FPR_Regs = 13;
3037 const unsigned Num_VR_Regs = array_lengthof( VR);
3039 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3041 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3043 // In 32-bit non-varargs functions, the stack space for vectors is after the
3044 // stack space for non-vectors. We do not use this space unless we have
3045 // too many vectors to fit in registers, something that only occurs in
3046 // constructed examples:), but we have to walk the arglist to figure
3047 // that out...for the pathological case, compute VecArgOffset as the
3048 // start of the vector parameter area. Computing VecArgOffset is the
3049 // entire point of the following loop.
3050 unsigned VecArgOffset = ArgOffset;
3051 if (!isVarArg && !isPPC64) {
3052 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3054 EVT ObjectVT = Ins[ArgNo].VT;
3055 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3057 if (Flags.isByVal()) {
3058 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3059 unsigned ObjSize = Flags.getByValSize();
3061 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3062 VecArgOffset += ArgSize;
3066 switch(ObjectVT.getSimpleVT().SimpleTy) {
3067 default: llvm_unreachable("Unhandled argument type!");
3073 case MVT::i64: // PPC64
3075 // FIXME: We are guaranteed to be !isPPC64 at this point.
3076 // Does MVT::i64 apply?
3083 // Nothing to do, we're only looking at Nonvector args here.
3088 // We've found where the vector parameter area in memory is. Skip the
3089 // first 12 parameters; these don't use that memory.
3090 VecArgOffset = ((VecArgOffset+15)/16)*16;
3091 VecArgOffset += 12*16;
3093 // Add DAG nodes to load the arguments or copy them out of registers. On
3094 // entry to a function on PPC, the arguments start after the linkage area,
3095 // although the first ones are often in registers.
3097 SmallVector<SDValue, 8> MemOps;
3098 unsigned nAltivecParamsAtEnd = 0;
3099 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3100 unsigned CurArgIdx = 0;
3101 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3103 bool needsLoad = false;
3104 EVT ObjectVT = Ins[ArgNo].VT;
3105 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3106 unsigned ArgSize = ObjSize;
3107 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3108 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3109 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3111 unsigned CurArgOffset = ArgOffset;
3113 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3114 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3115 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3116 if (isVarArg || isPPC64) {
3117 MinReservedArea = ((MinReservedArea+15)/16)*16;
3118 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3121 } else nAltivecParamsAtEnd++;
3123 // Calculate min reserved area.
3124 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3128 // FIXME the codegen can be much improved in some cases.
3129 // We do not have to keep everything in memory.
3130 if (Flags.isByVal()) {
3131 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3132 ObjSize = Flags.getByValSize();
3133 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3134 // Objects of size 1 and 2 are right justified, everything else is
3135 // left justified. This means the memory address is adjusted forwards.
3136 if (ObjSize==1 || ObjSize==2) {
3137 CurArgOffset = CurArgOffset + (4 - ObjSize);
3139 // The value of the object is its address.
3140 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3141 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3142 InVals.push_back(FIN);
3143 if (ObjSize==1 || ObjSize==2) {
3144 if (GPR_idx != Num_GPR_Regs) {
3147 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3149 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3150 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3151 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3152 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3153 MachinePointerInfo(FuncArg),
3154 ObjType, false, false, 0);
3155 MemOps.push_back(Store);
3159 ArgOffset += PtrByteSize;
3163 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3164 // Store whatever pieces of the object are in registers
3165 // to memory. ArgOffset will be the address of the beginning
3167 if (GPR_idx != Num_GPR_Regs) {
3170 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3172 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3173 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3174 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3175 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3176 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3177 MachinePointerInfo(FuncArg, j),
3179 MemOps.push_back(Store);
3181 ArgOffset += PtrByteSize;
3183 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3190 switch (ObjectVT.getSimpleVT().SimpleTy) {
3191 default: llvm_unreachable("Unhandled argument type!");
3195 if (GPR_idx != Num_GPR_Regs) {
3196 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3197 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3199 if (ObjectVT == MVT::i1)
3200 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3205 ArgSize = PtrByteSize;
3207 // All int arguments reserve stack space in the Darwin ABI.
3208 ArgOffset += PtrByteSize;
3212 case MVT::i64: // PPC64
3213 if (GPR_idx != Num_GPR_Regs) {
3214 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3215 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3217 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3218 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3219 // value to MVT::i64 and then truncate to the correct register size.
3220 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3225 ArgSize = PtrByteSize;
3227 // All int arguments reserve stack space in the Darwin ABI.
3233 // Every 4 bytes of argument space consumes one of the GPRs available for
3234 // argument passing.
3235 if (GPR_idx != Num_GPR_Regs) {
3237 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3240 if (FPR_idx != Num_FPR_Regs) {
3243 if (ObjectVT == MVT::f32)
3244 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3246 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3248 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3254 // All FP arguments reserve stack space in the Darwin ABI.
3255 ArgOffset += isPPC64 ? 8 : ObjSize;
3261 // Note that vector arguments in registers don't reserve stack space,
3262 // except in varargs functions.
3263 if (VR_idx != Num_VR_Regs) {
3264 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3265 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3267 while ((ArgOffset % 16) != 0) {
3268 ArgOffset += PtrByteSize;
3269 if (GPR_idx != Num_GPR_Regs)
3273 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3277 if (!isVarArg && !isPPC64) {
3278 // Vectors go after all the nonvectors.
3279 CurArgOffset = VecArgOffset;
3282 // Vectors are aligned.
3283 ArgOffset = ((ArgOffset+15)/16)*16;
3284 CurArgOffset = ArgOffset;
3292 // We need to load the argument to a virtual register if we determined above
3293 // that we ran out of physical registers of the appropriate type.
3295 int FI = MFI->CreateFixedObject(ObjSize,
3296 CurArgOffset + (ArgSize - ObjSize),
3298 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3299 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3300 false, false, false, 0);
3303 InVals.push_back(ArgVal);
3306 // Allow for Altivec parameters at the end, if needed.
3307 if (nAltivecParamsAtEnd) {
3308 MinReservedArea = ((MinReservedArea+15)/16)*16;
3309 MinReservedArea += 16*nAltivecParamsAtEnd;
3312 // Area that is at least reserved in the caller of this function.
3313 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3315 // Set the size that is at least reserved in caller of this function. Tail
3316 // call optimized functions' reserved stack space needs to be aligned so that
3317 // taking the difference between two stack areas will result in an aligned
3320 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3321 FuncInfo->setMinReservedArea(MinReservedArea);
3323 // If the function takes variable number of arguments, make a frame index for
3324 // the start of the first vararg value... for expansion of llvm.va_start.
3326 int Depth = ArgOffset;
3328 FuncInfo->setVarArgsFrameIndex(
3329 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3331 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3333 // If this function is vararg, store any remaining integer argument regs
3334 // to their spots on the stack so that they may be loaded by deferencing the
3335 // result of va_next.
3336 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3340 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3342 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3344 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3345 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3346 MachinePointerInfo(), false, false, 0);
3347 MemOps.push_back(Store);
3348 // Increment the address by four for the next argument to store
3349 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3350 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3354 if (!MemOps.empty())
3355 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3360 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3361 /// adjusted to accommodate the arguments for the tailcall.
3362 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3363 unsigned ParamSize) {
3365 if (!isTailCall) return 0;
3367 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3368 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3369 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3370 // Remember only if the new adjustement is bigger.
3371 if (SPDiff < FI->getTailCallSPDelta())
3372 FI->setTailCallSPDelta(SPDiff);
3377 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3378 /// for tail call optimization. Targets which want to do tail call
3379 /// optimization should implement this function.
3381 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3382 CallingConv::ID CalleeCC,
3384 const SmallVectorImpl<ISD::InputArg> &Ins,
3385 SelectionDAG& DAG) const {
3386 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3389 // Variable argument functions are not supported.
3393 MachineFunction &MF = DAG.getMachineFunction();
3394 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3395 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3396 // Functions containing by val parameters are not supported.
3397 for (unsigned i = 0; i != Ins.size(); i++) {
3398 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3399 if (Flags.isByVal()) return false;
3402 // Non-PIC/GOT tail calls are supported.
3403 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3406 // At the moment we can only do local tail calls (in same module, hidden
3407 // or protected) if we are generating PIC.
3408 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3409 return G->getGlobal()->hasHiddenVisibility()
3410 || G->getGlobal()->hasProtectedVisibility();
3416 /// isCallCompatibleAddress - Return the immediate to use if the specified
3417 /// 32-bit value is representable in the immediate field of a BxA instruction.
3418 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3420 if (!C) return nullptr;
3422 int Addr = C->getZExtValue();
3423 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3424 SignExtend32<26>(Addr) != Addr)
3425 return nullptr; // Top 6 bits have to be sext of immediate.
3427 return DAG.getConstant((int)C->getZExtValue() >> 2,
3428 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3433 struct TailCallArgumentInfo {
3438 TailCallArgumentInfo() : FrameIdx(0) {}
3443 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3445 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3447 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3448 SmallVectorImpl<SDValue> &MemOpChains,
3450 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3451 SDValue Arg = TailCallArgs[i].Arg;
3452 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3453 int FI = TailCallArgs[i].FrameIdx;
3454 // Store relative to framepointer.
3455 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3456 MachinePointerInfo::getFixedStack(FI),
3461 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3462 /// the appropriate stack slot for the tail call optimized function call.
3463 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3464 MachineFunction &MF,
3473 // Calculate the new stack slot for the return address.
3474 int SlotSize = isPPC64 ? 8 : 4;
3475 const PPCFrameLowering *FL =
3476 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3477 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3478 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3479 NewRetAddrLoc, true);
3480 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3481 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3482 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3483 MachinePointerInfo::getFixedStack(NewRetAddr),
3486 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3487 // slot as the FP is never overwritten.
3489 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3490 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3492 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3493 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3494 MachinePointerInfo::getFixedStack(NewFPIdx),
3501 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3502 /// the position of the argument.
3504 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3505 SDValue Arg, int SPDiff, unsigned ArgOffset,
3506 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3507 int Offset = ArgOffset + SPDiff;
3508 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3509 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3510 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3511 SDValue FIN = DAG.getFrameIndex(FI, VT);
3512 TailCallArgumentInfo Info;
3514 Info.FrameIdxOp = FIN;
3516 TailCallArguments.push_back(Info);
3519 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3520 /// stack slot. Returns the chain as result and the loaded frame pointers in
3521 /// LROpOut/FPOpout. Used when tail calling.
3522 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3530 // Load the LR and FP stack slot for later adjusting.
3531 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3532 LROpOut = getReturnAddrFrameIndex(DAG);
3533 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3534 false, false, false, 0);
3535 Chain = SDValue(LROpOut.getNode(), 1);
3537 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3538 // slot as the FP is never overwritten.
3540 FPOpOut = getFramePointerFrameIndex(DAG);
3541 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3542 false, false, false, 0);
3543 Chain = SDValue(FPOpOut.getNode(), 1);
3549 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3550 /// by "Src" to address "Dst" of size "Size". Alignment information is
3551 /// specified by the specific parameter attribute. The copy will be passed as
3552 /// a byval function parameter.
3553 /// Sometimes what we are copying is the end of a larger object, the part that
3554 /// does not fit in registers.
3556 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3557 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3559 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3560 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3561 false, false, MachinePointerInfo(),
3562 MachinePointerInfo());
3565 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3568 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3569 SDValue Arg, SDValue PtrOff, int SPDiff,
3570 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3571 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3572 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3574 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3579 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3581 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3582 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3583 DAG.getConstant(ArgOffset, PtrVT));
3585 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3586 MachinePointerInfo(), false, false, 0));
3587 // Calculate and remember argument location.
3588 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3593 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3594 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3595 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3596 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3597 MachineFunction &MF = DAG.getMachineFunction();
3599 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3600 // might overwrite each other in case of tail call optimization.
3601 SmallVector<SDValue, 8> MemOpChains2;
3602 // Do not flag preceding copytoreg stuff together with the following stuff.
3604 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3606 if (!MemOpChains2.empty())
3607 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3609 // Store the return address to the appropriate stack slot.
3610 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3611 isPPC64, isDarwinABI, dl);
3613 // Emit callseq_end just before tailcall node.
3614 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3615 DAG.getIntPtrConstant(0, true), InFlag, dl);
3616 InFlag = Chain.getValue(1);
3619 // Is this global address that of a function that can be called by name? (as
3620 // opposed to something that must hold a descriptor for an indirect call).
3621 static bool isFunctionGlobalAddress(SDValue Callee) {
3622 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3623 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3624 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3627 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3634 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3635 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3636 bool isTailCall, bool IsPatchPoint,
3637 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3638 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3639 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3641 bool isPPC64 = Subtarget.isPPC64();
3642 bool isSVR4ABI = Subtarget.isSVR4ABI();
3643 bool isELFv2ABI = Subtarget.isELFv2ABI();
3645 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3646 NodeTys.push_back(MVT::Other); // Returns a chain
3647 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3649 unsigned CallOpc = PPCISD::CALL;
3651 bool needIndirectCall = true;
3652 if (!isSVR4ABI || !isPPC64)
3653 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3654 // If this is an absolute destination address, use the munged value.
3655 Callee = SDValue(Dest, 0);
3656 needIndirectCall = false;
3659 if (isFunctionGlobalAddress(Callee)) {
3660 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3661 // A call to a TLS address is actually an indirect call to a
3662 // thread-specific pointer.
3663 unsigned OpFlags = 0;
3664 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3665 (Subtarget.getTargetTriple().isMacOSX() &&
3666 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3667 (G->getGlobal()->isDeclaration() ||
3668 G->getGlobal()->isWeakForLinker())) ||
3669 (Subtarget.isTargetELF() && !isPPC64 &&
3670 !G->getGlobal()->hasLocalLinkage() &&
3671 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3672 // PC-relative references to external symbols should go through $stub,
3673 // unless we're building with the leopard linker or later, which
3674 // automatically synthesizes these stubs.
3675 OpFlags = PPCII::MO_PLT_OR_STUB;
3678 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3679 // every direct call is) turn it into a TargetGlobalAddress /
3680 // TargetExternalSymbol node so that legalize doesn't hack it.
3681 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3682 Callee.getValueType(), 0, OpFlags);
3683 needIndirectCall = false;
3686 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3687 unsigned char OpFlags = 0;
3689 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3690 (Subtarget.getTargetTriple().isMacOSX() &&
3691 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3692 (Subtarget.isTargetELF() && !isPPC64 &&
3693 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3694 // PC-relative references to external symbols should go through $stub,
3695 // unless we're building with the leopard linker or later, which
3696 // automatically synthesizes these stubs.
3697 OpFlags = PPCII::MO_PLT_OR_STUB;
3700 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3702 needIndirectCall = false;
3706 // We'll form an invalid direct call when lowering a patchpoint; the full
3707 // sequence for an indirect call is complicated, and many of the
3708 // instructions introduced might have side effects (and, thus, can't be
3709 // removed later). The call itself will be removed as soon as the
3710 // argument/return lowering is complete, so the fact that it has the wrong
3711 // kind of operands should not really matter.
3712 needIndirectCall = false;
3715 if (needIndirectCall) {
3716 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3717 // to do the call, we can't use PPCISD::CALL.
3718 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3720 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3721 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3722 // entry point, but to the function descriptor (the function entry point
3723 // address is part of the function descriptor though).
3724 // The function descriptor is a three doubleword structure with the
3725 // following fields: function entry point, TOC base address and
3726 // environment pointer.
3727 // Thus for a call through a function pointer, the following actions need
3729 // 1. Save the TOC of the caller in the TOC save area of its stack
3730 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3731 // 2. Load the address of the function entry point from the function
3733 // 3. Load the TOC of the callee from the function descriptor into r2.
3734 // 4. Load the environment pointer from the function descriptor into
3736 // 5. Branch to the function entry point address.
3737 // 6. On return of the callee, the TOC of the caller needs to be
3738 // restored (this is done in FinishCall()).
3740 // The loads are scheduled at the beginning of the call sequence, and the
3741 // register copies are flagged together to ensure that no other
3742 // operations can be scheduled in between. E.g. without flagging the
3743 // copies together, a TOC access in the caller could be scheduled between
3744 // the assignment of the callee TOC and the branch to the callee, which
3745 // results in the TOC access going through the TOC of the callee instead
3746 // of going through the TOC of the caller, which leads to incorrect code.
3748 // Load the address of the function entry point from the function
3750 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3751 if (LDChain.getValueType() == MVT::Glue)
3752 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3754 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3756 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3757 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3758 false, false, LoadsInv, 8);
3760 // Load environment pointer into r11.
3761 SDValue PtrOff = DAG.getIntPtrConstant(16);
3762 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3763 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3764 MPI.getWithOffset(16), false, false,
3767 SDValue TOCOff = DAG.getIntPtrConstant(8);
3768 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3769 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3770 MPI.getWithOffset(8), false, false,
3773 setUsesTOCBasePtr(DAG);
3774 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3776 Chain = TOCVal.getValue(0);
3777 InFlag = TOCVal.getValue(1);
3779 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3782 Chain = EnvVal.getValue(0);
3783 InFlag = EnvVal.getValue(1);
3785 MTCTROps[0] = Chain;
3786 MTCTROps[1] = LoadFuncPtr;
3787 MTCTROps[2] = InFlag;
3790 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3791 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3792 InFlag = Chain.getValue(1);
3795 NodeTys.push_back(MVT::Other);
3796 NodeTys.push_back(MVT::Glue);
3797 Ops.push_back(Chain);
3798 CallOpc = PPCISD::BCTRL;
3799 Callee.setNode(nullptr);
3800 // Add use of X11 (holding environment pointer)
3801 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3802 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3803 // Add CTR register as callee so a bctr can be emitted later.
3805 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3808 // If this is a direct call, pass the chain and the callee.
3809 if (Callee.getNode()) {
3810 Ops.push_back(Chain);
3811 Ops.push_back(Callee);
3813 // If this is a tail call add stack pointer delta.
3815 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3817 // Add argument registers to the end of the list so that they are known live
3819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3820 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3821 RegsToPass[i].second.getValueType()));
3823 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
3825 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
3826 setUsesTOCBasePtr(DAG);
3827 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3834 bool isLocalCall(const SDValue &Callee)
3836 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3837 return !G->getGlobal()->isDeclaration() &&
3838 !G->getGlobal()->isWeakForLinker();
3843 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3844 CallingConv::ID CallConv, bool isVarArg,
3845 const SmallVectorImpl<ISD::InputArg> &Ins,
3846 SDLoc dl, SelectionDAG &DAG,
3847 SmallVectorImpl<SDValue> &InVals) const {
3849 SmallVector<CCValAssign, 16> RVLocs;
3850 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3852 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3854 // Copy all of the result registers out of their specified physreg.
3855 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3856 CCValAssign &VA = RVLocs[i];
3857 assert(VA.isRegLoc() && "Can only return in registers!");
3859 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3860 VA.getLocReg(), VA.getLocVT(), InFlag);
3861 Chain = Val.getValue(1);
3862 InFlag = Val.getValue(2);
3864 switch (VA.getLocInfo()) {
3865 default: llvm_unreachable("Unknown loc info!");
3866 case CCValAssign::Full: break;
3867 case CCValAssign::AExt:
3868 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3870 case CCValAssign::ZExt:
3871 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3872 DAG.getValueType(VA.getValVT()));
3873 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3875 case CCValAssign::SExt:
3876 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3877 DAG.getValueType(VA.getValVT()));
3878 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3882 InVals.push_back(Val);
3889 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3890 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3892 SmallVector<std::pair<unsigned, SDValue>, 8>
3894 SDValue InFlag, SDValue Chain,
3895 SDValue CallSeqStart, SDValue &Callee,
3896 int SPDiff, unsigned NumBytes,
3897 const SmallVectorImpl<ISD::InputArg> &Ins,
3898 SmallVectorImpl<SDValue> &InVals,
3899 ImmutableCallSite *CS) const {
3901 std::vector<EVT> NodeTys;
3902 SmallVector<SDValue, 8> Ops;
3903 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3904 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3905 Ops, NodeTys, CS, Subtarget);
3907 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3908 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3909 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3911 // When performing tail call optimization the callee pops its arguments off
3912 // the stack. Account for this here so these bytes can be pushed back on in
3913 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3914 int BytesCalleePops =
3915 (CallConv == CallingConv::Fast &&
3916 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3918 // Add a register mask operand representing the call-preserved registers.
3919 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3920 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3921 assert(Mask && "Missing call preserved mask for calling convention");
3922 Ops.push_back(DAG.getRegisterMask(Mask));
3924 if (InFlag.getNode())
3925 Ops.push_back(InFlag);
3929 assert(((Callee.getOpcode() == ISD::Register &&
3930 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3931 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3932 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3933 isa<ConstantSDNode>(Callee)) &&
3934 "Expecting an global address, external symbol, absolute value or register");
3936 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3939 // Add a NOP immediately after the branch instruction when using the 64-bit
3940 // SVR4 ABI. At link time, if caller and callee are in a different module and
3941 // thus have a different TOC, the call will be replaced with a call to a stub
3942 // function which saves the current TOC, loads the TOC of the callee and
3943 // branches to the callee. The NOP will be replaced with a load instruction
3944 // which restores the TOC of the caller from the TOC save slot of the current
3945 // stack frame. If caller and callee belong to the same module (and have the
3946 // same TOC), the NOP will remain unchanged.
3948 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3950 if (CallOpc == PPCISD::BCTRL) {
3951 // This is a call through a function pointer.
3952 // Restore the caller TOC from the save area into R2.
3953 // See PrepareCall() for more information about calls through function
3954 // pointers in the 64-bit SVR4 ABI.
3955 // We are using a target-specific load with r2 hard coded, because the
3956 // result of a target-independent load would never go directly into r2,
3957 // since r2 is a reserved register (which prevents the register allocator
3958 // from allocating it), resulting in an additional register being
3959 // allocated and an unnecessary move instruction being generated.
3960 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3962 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3963 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3964 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3965 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3966 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3968 // The address needs to go after the chain input but before the flag (or
3969 // any other variadic arguments).
3970 Ops.insert(std::next(Ops.begin()), AddTOC);
3971 } else if ((CallOpc == PPCISD::CALL) &&
3972 (!isLocalCall(Callee) ||
3973 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
3974 // Otherwise insert NOP for non-local calls.
3975 CallOpc = PPCISD::CALL_NOP;
3978 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3979 InFlag = Chain.getValue(1);
3981 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3982 DAG.getIntPtrConstant(BytesCalleePops, true),
3985 InFlag = Chain.getValue(1);
3987 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3988 Ins, dl, DAG, InVals);
3992 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3993 SmallVectorImpl<SDValue> &InVals) const {
3994 SelectionDAG &DAG = CLI.DAG;
3996 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3997 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3998 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3999 SDValue Chain = CLI.Chain;
4000 SDValue Callee = CLI.Callee;
4001 bool &isTailCall = CLI.IsTailCall;
4002 CallingConv::ID CallConv = CLI.CallConv;
4003 bool isVarArg = CLI.IsVarArg;
4004 bool IsPatchPoint = CLI.IsPatchPoint;
4005 ImmutableCallSite *CS = CLI.CS;
4008 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4011 if (!isTailCall && CS && CS->isMustTailCall())
4012 report_fatal_error("failed to perform tail call elimination on a call "
4013 "site marked musttail");
4015 if (Subtarget.isSVR4ABI()) {
4016 if (Subtarget.isPPC64())
4017 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4018 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4019 dl, DAG, InVals, CS);
4021 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4022 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4023 dl, DAG, InVals, CS);
4026 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4027 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4028 dl, DAG, InVals, CS);
4032 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4033 CallingConv::ID CallConv, bool isVarArg,
4034 bool isTailCall, bool IsPatchPoint,
4035 const SmallVectorImpl<ISD::OutputArg> &Outs,
4036 const SmallVectorImpl<SDValue> &OutVals,
4037 const SmallVectorImpl<ISD::InputArg> &Ins,
4038 SDLoc dl, SelectionDAG &DAG,
4039 SmallVectorImpl<SDValue> &InVals,
4040 ImmutableCallSite *CS) const {
4041 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4042 // of the 32-bit SVR4 ABI stack frame layout.
4044 assert((CallConv == CallingConv::C ||
4045 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4047 unsigned PtrByteSize = 4;
4049 MachineFunction &MF = DAG.getMachineFunction();
4051 // Mark this function as potentially containing a function that contains a
4052 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4053 // and restoring the callers stack pointer in this functions epilog. This is
4054 // done because by tail calling the called function might overwrite the value
4055 // in this function's (MF) stack pointer stack slot 0(SP).
4056 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4057 CallConv == CallingConv::Fast)
4058 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4060 // Count how many bytes are to be pushed on the stack, including the linkage
4061 // area, parameter list area and the part of the local variable space which
4062 // contains copies of aggregates which are passed by value.
4064 // Assign locations to all of the outgoing arguments.
4065 SmallVector<CCValAssign, 16> ArgLocs;
4066 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4069 // Reserve space for the linkage area on the stack.
4070 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4074 // Handle fixed and variable vector arguments differently.
4075 // Fixed vector arguments go into registers as long as registers are
4076 // available. Variable vector arguments always go into memory.
4077 unsigned NumArgs = Outs.size();
4079 for (unsigned i = 0; i != NumArgs; ++i) {
4080 MVT ArgVT = Outs[i].VT;
4081 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4084 if (Outs[i].IsFixed) {
4085 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4088 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4094 errs() << "Call operand #" << i << " has unhandled type "
4095 << EVT(ArgVT).getEVTString() << "\n";
4097 llvm_unreachable(nullptr);
4101 // All arguments are treated the same.
4102 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4105 // Assign locations to all of the outgoing aggregate by value arguments.
4106 SmallVector<CCValAssign, 16> ByValArgLocs;
4107 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4108 ByValArgLocs, *DAG.getContext());
4110 // Reserve stack space for the allocations in CCInfo.
4111 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4113 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4115 // Size of the linkage area, parameter list area and the part of the local
4116 // space variable where copies of aggregates which are passed by value are
4118 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4120 // Calculate by how many bytes the stack has to be adjusted in case of tail
4121 // call optimization.
4122 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4124 // Adjust the stack pointer for the new arguments...
4125 // These operations are automatically eliminated by the prolog/epilog pass
4126 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4128 SDValue CallSeqStart = Chain;
4130 // Load the return address and frame pointer so it can be moved somewhere else
4133 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4136 // Set up a copy of the stack pointer for use loading and storing any
4137 // arguments that may not fit in the registers available for argument
4139 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4141 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4142 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4143 SmallVector<SDValue, 8> MemOpChains;
4145 bool seenFloatArg = false;
4146 // Walk the register/memloc assignments, inserting copies/loads.
4147 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4150 CCValAssign &VA = ArgLocs[i];
4151 SDValue Arg = OutVals[i];
4152 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4154 if (Flags.isByVal()) {
4155 // Argument is an aggregate which is passed by value, thus we need to
4156 // create a copy of it in the local variable space of the current stack
4157 // frame (which is the stack frame of the caller) and pass the address of
4158 // this copy to the callee.
4159 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4160 CCValAssign &ByValVA = ByValArgLocs[j++];
4161 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4163 // Memory reserved in the local variable space of the callers stack frame.
4164 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4166 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4167 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4169 // Create a copy of the argument in the local area of the current
4171 SDValue MemcpyCall =
4172 CreateCopyOfByValArgument(Arg, PtrOff,
4173 CallSeqStart.getNode()->getOperand(0),
4176 // This must go outside the CALLSEQ_START..END.
4177 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4178 CallSeqStart.getNode()->getOperand(1),
4180 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4181 NewCallSeqStart.getNode());
4182 Chain = CallSeqStart = NewCallSeqStart;
4184 // Pass the address of the aggregate copy on the stack either in a
4185 // physical register or in the parameter list area of the current stack
4186 // frame to the callee.
4190 if (VA.isRegLoc()) {
4191 if (Arg.getValueType() == MVT::i1)
4192 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4194 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4195 // Put argument in a physical register.
4196 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4198 // Put argument in the parameter list area of the current stack frame.
4199 assert(VA.isMemLoc());
4200 unsigned LocMemOffset = VA.getLocMemOffset();
4203 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4204 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4206 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4207 MachinePointerInfo(),
4210 // Calculate and remember argument location.
4211 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4217 if (!MemOpChains.empty())
4218 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4220 // Build a sequence of copy-to-reg nodes chained together with token chain
4221 // and flag operands which copy the outgoing args into the appropriate regs.
4223 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4224 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4225 RegsToPass[i].second, InFlag);
4226 InFlag = Chain.getValue(1);
4229 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4232 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4233 SDValue Ops[] = { Chain, InFlag };
4235 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4236 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4238 InFlag = Chain.getValue(1);
4242 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4243 false, TailCallArguments);
4245 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4246 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4247 NumBytes, Ins, InVals, CS);
4250 // Copy an argument into memory, being careful to do this outside the
4251 // call sequence for the call to which the argument belongs.
4253 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4254 SDValue CallSeqStart,
4255 ISD::ArgFlagsTy Flags,
4258 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4259 CallSeqStart.getNode()->getOperand(0),
4261 // The MEMCPY must go outside the CALLSEQ_START..END.
4262 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4263 CallSeqStart.getNode()->getOperand(1),
4265 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4266 NewCallSeqStart.getNode());
4267 return NewCallSeqStart;
4271 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4272 CallingConv::ID CallConv, bool isVarArg,
4273 bool isTailCall, bool IsPatchPoint,
4274 const SmallVectorImpl<ISD::OutputArg> &Outs,
4275 const SmallVectorImpl<SDValue> &OutVals,
4276 const SmallVectorImpl<ISD::InputArg> &Ins,
4277 SDLoc dl, SelectionDAG &DAG,
4278 SmallVectorImpl<SDValue> &InVals,
4279 ImmutableCallSite *CS) const {
4281 bool isELFv2ABI = Subtarget.isELFv2ABI();
4282 bool isLittleEndian = Subtarget.isLittleEndian();
4283 unsigned NumOps = Outs.size();
4285 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4286 unsigned PtrByteSize = 8;
4288 MachineFunction &MF = DAG.getMachineFunction();
4290 // Mark this function as potentially containing a function that contains a
4291 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4292 // and restoring the callers stack pointer in this functions epilog. This is
4293 // done because by tail calling the called function might overwrite the value
4294 // in this function's (MF) stack pointer stack slot 0(SP).
4295 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4296 CallConv == CallingConv::Fast)
4297 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4299 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4300 "fastcc not supported on varargs functions");
4302 // Count how many bytes are to be pushed on the stack, including the linkage
4303 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4304 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4305 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4306 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4308 unsigned NumBytes = LinkageSize;
4309 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4311 static const MCPhysReg GPR[] = {
4312 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4313 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4315 static const MCPhysReg *FPR = GetFPR();
4317 static const MCPhysReg VR[] = {
4318 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4319 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4321 static const MCPhysReg VSRH[] = {
4322 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4323 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4326 const unsigned NumGPRs = array_lengthof(GPR);
4327 const unsigned NumFPRs = 13;
4328 const unsigned NumVRs = array_lengthof(VR);
4330 // When using the fast calling convention, we don't provide backing for
4331 // arguments that will be in registers.
4332 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4334 // Add up all the space actually used.
4335 for (unsigned i = 0; i != NumOps; ++i) {
4336 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4337 EVT ArgVT = Outs[i].VT;
4338 EVT OrigVT = Outs[i].ArgVT;
4340 if (CallConv == CallingConv::Fast) {
4341 if (Flags.isByVal())
4342 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4344 switch (ArgVT.getSimpleVT().SimpleTy) {
4345 default: llvm_unreachable("Unexpected ValueType for argument!");
4349 if (++NumGPRsUsed <= NumGPRs)
4354 if (++NumFPRsUsed <= NumFPRs)
4363 if (++NumVRsUsed <= NumVRs)
4369 /* Respect alignment of argument on the stack. */
4371 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4372 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4374 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4375 if (Flags.isInConsecutiveRegsLast())
4376 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4379 unsigned NumBytesActuallyUsed = NumBytes;
4381 // The prolog code of the callee may store up to 8 GPR argument registers to
4382 // the stack, allowing va_start to index over them in memory if its varargs.
4383 // Because we cannot tell if this is needed on the caller side, we have to
4384 // conservatively assume that it is needed. As such, make sure we have at
4385 // least enough stack space for the caller to store the 8 GPRs.
4386 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4387 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4389 // Tail call needs the stack to be aligned.
4390 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4391 CallConv == CallingConv::Fast)
4392 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4394 // Calculate by how many bytes the stack has to be adjusted in case of tail
4395 // call optimization.
4396 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4398 // To protect arguments on the stack from being clobbered in a tail call,
4399 // force all the loads to happen before doing any other lowering.
4401 Chain = DAG.getStackArgumentTokenFactor(Chain);
4403 // Adjust the stack pointer for the new arguments...
4404 // These operations are automatically eliminated by the prolog/epilog pass
4405 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4407 SDValue CallSeqStart = Chain;
4409 // Load the return address and frame pointer so it can be move somewhere else
4412 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4415 // Set up a copy of the stack pointer for use loading and storing any
4416 // arguments that may not fit in the registers available for argument
4418 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4420 // Figure out which arguments are going to go in registers, and which in
4421 // memory. Also, if this is a vararg function, floating point operations
4422 // must be stored to our stack, and loaded into integer regs as well, if
4423 // any integer regs are available for argument passing.
4424 unsigned ArgOffset = LinkageSize;
4426 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4427 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4429 SmallVector<SDValue, 8> MemOpChains;
4430 for (unsigned i = 0; i != NumOps; ++i) {
4431 SDValue Arg = OutVals[i];
4432 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4433 EVT ArgVT = Outs[i].VT;
4434 EVT OrigVT = Outs[i].ArgVT;
4436 // PtrOff will be used to store the current argument to the stack if a
4437 // register cannot be found for it.
4440 // We re-align the argument offset for each argument, except when using the
4441 // fast calling convention, when we need to make sure we do that only when
4442 // we'll actually use a stack slot.
4443 auto ComputePtrOff = [&]() {
4444 /* Respect alignment of argument on the stack. */
4446 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4447 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4449 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4451 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4454 if (CallConv != CallingConv::Fast) {
4457 /* Compute GPR index associated with argument offset. */
4458 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4459 GPR_idx = std::min(GPR_idx, NumGPRs);
4462 // Promote integers to 64-bit values.
4463 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4464 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4465 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4466 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4469 // FIXME memcpy is used way more than necessary. Correctness first.
4470 // Note: "by value" is code for passing a structure by value, not
4472 if (Flags.isByVal()) {
4473 // Note: Size includes alignment padding, so
4474 // struct x { short a; char b; }
4475 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4476 // These are the proper values we need for right-justifying the
4477 // aggregate in a parameter register.
4478 unsigned Size = Flags.getByValSize();
4480 // An empty aggregate parameter takes up no storage and no
4485 if (CallConv == CallingConv::Fast)
4488 // All aggregates smaller than 8 bytes must be passed right-justified.
4489 if (Size==1 || Size==2 || Size==4) {
4490 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4491 if (GPR_idx != NumGPRs) {
4492 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4493 MachinePointerInfo(), VT,
4494 false, false, false, 0);
4495 MemOpChains.push_back(Load.getValue(1));
4496 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4498 ArgOffset += PtrByteSize;
4503 if (GPR_idx == NumGPRs && Size < 8) {
4504 SDValue AddPtr = PtrOff;
4505 if (!isLittleEndian) {
4506 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4507 PtrOff.getValueType());
4508 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4510 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4513 ArgOffset += PtrByteSize;
4516 // Copy entire object into memory. There are cases where gcc-generated
4517 // code assumes it is there, even if it could be put entirely into
4518 // registers. (This is not what the doc says.)
4520 // FIXME: The above statement is likely due to a misunderstanding of the
4521 // documents. All arguments must be copied into the parameter area BY
4522 // THE CALLEE in the event that the callee takes the address of any
4523 // formal argument. That has not yet been implemented. However, it is
4524 // reasonable to use the stack area as a staging area for the register
4527 // Skip this for small aggregates, as we will use the same slot for a
4528 // right-justified copy, below.
4530 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4534 // When a register is available, pass a small aggregate right-justified.
4535 if (Size < 8 && GPR_idx != NumGPRs) {
4536 // The easiest way to get this right-justified in a register
4537 // is to copy the structure into the rightmost portion of a
4538 // local variable slot, then load the whole slot into the
4540 // FIXME: The memcpy seems to produce pretty awful code for
4541 // small aggregates, particularly for packed ones.
4542 // FIXME: It would be preferable to use the slot in the
4543 // parameter save area instead of a new local variable.
4544 SDValue AddPtr = PtrOff;
4545 if (!isLittleEndian) {
4546 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4547 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4549 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4553 // Load the slot into the register.
4554 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4555 MachinePointerInfo(),
4556 false, false, false, 0);
4557 MemOpChains.push_back(Load.getValue(1));
4558 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4560 // Done with this argument.
4561 ArgOffset += PtrByteSize;
4565 // For aggregates larger than PtrByteSize, copy the pieces of the
4566 // object that fit into registers from the parameter save area.
4567 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4568 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4569 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4570 if (GPR_idx != NumGPRs) {
4571 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4572 MachinePointerInfo(),
4573 false, false, false, 0);
4574 MemOpChains.push_back(Load.getValue(1));
4575 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4576 ArgOffset += PtrByteSize;
4578 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4585 switch (Arg.getSimpleValueType().SimpleTy) {
4586 default: llvm_unreachable("Unexpected ValueType for argument!");
4590 // These can be scalar arguments or elements of an integer array type
4591 // passed directly. Clang may use those instead of "byval" aggregate
4592 // types to avoid forcing arguments to memory unnecessarily.
4593 if (GPR_idx != NumGPRs) {
4594 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4596 if (CallConv == CallingConv::Fast)
4599 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4600 true, isTailCall, false, MemOpChains,
4601 TailCallArguments, dl);
4602 if (CallConv == CallingConv::Fast)
4603 ArgOffset += PtrByteSize;
4605 if (CallConv != CallingConv::Fast)
4606 ArgOffset += PtrByteSize;
4610 // These can be scalar arguments or elements of a float array type
4611 // passed directly. The latter are used to implement ELFv2 homogenous
4612 // float aggregates.
4614 // Named arguments go into FPRs first, and once they overflow, the
4615 // remaining arguments go into GPRs and then the parameter save area.
4616 // Unnamed arguments for vararg functions always go to GPRs and
4617 // then the parameter save area. For now, put all arguments to vararg
4618 // routines always in both locations (FPR *and* GPR or stack slot).
4619 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4620 bool NeededLoad = false;
4622 // First load the argument into the next available FPR.
4623 if (FPR_idx != NumFPRs)
4624 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4626 // Next, load the argument into GPR or stack slot if needed.
4627 if (!NeedGPROrStack)
4629 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4630 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4631 // once we support fp <-> gpr moves.
4633 // In the non-vararg case, this can only ever happen in the
4634 // presence of f32 array types, since otherwise we never run
4635 // out of FPRs before running out of GPRs.
4638 // Double values are always passed in a single GPR.
4639 if (Arg.getValueType() != MVT::f32) {
4640 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4642 // Non-array float values are extended and passed in a GPR.
4643 } else if (!Flags.isInConsecutiveRegs()) {
4644 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4645 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4647 // If we have an array of floats, we collect every odd element
4648 // together with its predecessor into one GPR.
4649 } else if (ArgOffset % PtrByteSize != 0) {
4651 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4652 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4653 if (!isLittleEndian)
4655 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4657 // The final element, if even, goes into the first half of a GPR.
4658 } else if (Flags.isInConsecutiveRegsLast()) {
4659 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4660 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4661 if (!isLittleEndian)
4662 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4663 DAG.getConstant(32, MVT::i32));
4665 // Non-final even elements are skipped; they will be handled
4666 // together the with subsequent argument on the next go-around.
4670 if (ArgVal.getNode())
4671 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4673 if (CallConv == CallingConv::Fast)
4676 // Single-precision floating-point values are mapped to the
4677 // second (rightmost) word of the stack doubleword.
4678 if (Arg.getValueType() == MVT::f32 &&
4679 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4680 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4681 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4684 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4685 true, isTailCall, false, MemOpChains,
4686 TailCallArguments, dl);
4690 // When passing an array of floats, the array occupies consecutive
4691 // space in the argument area; only round up to the next doubleword
4692 // at the end of the array. Otherwise, each float takes 8 bytes.
4693 if (CallConv != CallingConv::Fast || NeededLoad) {
4694 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4695 Flags.isInConsecutiveRegs()) ? 4 : 8;
4696 if (Flags.isInConsecutiveRegsLast())
4697 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4707 // These can be scalar arguments or elements of a vector array type
4708 // passed directly. The latter are used to implement ELFv2 homogenous
4709 // vector aggregates.
4711 // For a varargs call, named arguments go into VRs or on the stack as
4712 // usual; unnamed arguments always go to the stack or the corresponding
4713 // GPRs when within range. For now, we always put the value in both
4714 // locations (or even all three).
4716 // We could elide this store in the case where the object fits
4717 // entirely in R registers. Maybe later.
4718 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4719 MachinePointerInfo(), false, false, 0);
4720 MemOpChains.push_back(Store);
4721 if (VR_idx != NumVRs) {
4722 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4723 MachinePointerInfo(),
4724 false, false, false, 0);
4725 MemOpChains.push_back(Load.getValue(1));
4727 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4728 Arg.getSimpleValueType() == MVT::v2i64) ?
4729 VSRH[VR_idx] : VR[VR_idx];
4732 RegsToPass.push_back(std::make_pair(VReg, Load));
4735 for (unsigned i=0; i<16; i+=PtrByteSize) {
4736 if (GPR_idx == NumGPRs)
4738 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4739 DAG.getConstant(i, PtrVT));
4740 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4741 false, false, false, 0);
4742 MemOpChains.push_back(Load.getValue(1));
4743 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4748 // Non-varargs Altivec params go into VRs or on the stack.
4749 if (VR_idx != NumVRs) {
4750 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4751 Arg.getSimpleValueType() == MVT::v2i64) ?
4752 VSRH[VR_idx] : VR[VR_idx];
4755 RegsToPass.push_back(std::make_pair(VReg, Arg));
4757 if (CallConv == CallingConv::Fast)
4760 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4761 true, isTailCall, true, MemOpChains,
4762 TailCallArguments, dl);
4763 if (CallConv == CallingConv::Fast)
4767 if (CallConv != CallingConv::Fast)
4773 assert(NumBytesActuallyUsed == ArgOffset);
4774 (void)NumBytesActuallyUsed;
4776 if (!MemOpChains.empty())
4777 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4779 // Check if this is an indirect call (MTCTR/BCTRL).
4780 // See PrepareCall() for more information about calls through function
4781 // pointers in the 64-bit SVR4 ABI.
4782 if (!isTailCall && !IsPatchPoint &&
4783 !isFunctionGlobalAddress(Callee) &&
4784 !isa<ExternalSymbolSDNode>(Callee)) {
4785 // Load r2 into a virtual register and store it to the TOC save area.
4786 setUsesTOCBasePtr(DAG);
4787 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4788 // TOC save area offset.
4789 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4790 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4791 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4792 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4793 MachinePointerInfo::getStack(TOCSaveOffset),
4795 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4796 // This does not mean the MTCTR instruction must use R12; it's easier
4797 // to model this as an extra parameter, so do that.
4798 if (isELFv2ABI && !IsPatchPoint)
4799 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4802 // Build a sequence of copy-to-reg nodes chained together with token chain
4803 // and flag operands which copy the outgoing args into the appropriate regs.
4805 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4806 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4807 RegsToPass[i].second, InFlag);
4808 InFlag = Chain.getValue(1);
4812 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4813 FPOp, true, TailCallArguments);
4815 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4816 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4817 NumBytes, Ins, InVals, CS);
4821 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4822 CallingConv::ID CallConv, bool isVarArg,
4823 bool isTailCall, bool IsPatchPoint,
4824 const SmallVectorImpl<ISD::OutputArg> &Outs,
4825 const SmallVectorImpl<SDValue> &OutVals,
4826 const SmallVectorImpl<ISD::InputArg> &Ins,
4827 SDLoc dl, SelectionDAG &DAG,
4828 SmallVectorImpl<SDValue> &InVals,
4829 ImmutableCallSite *CS) const {
4831 unsigned NumOps = Outs.size();
4833 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4834 bool isPPC64 = PtrVT == MVT::i64;
4835 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4837 MachineFunction &MF = DAG.getMachineFunction();
4839 // Mark this function as potentially containing a function that contains a
4840 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4841 // and restoring the callers stack pointer in this functions epilog. This is
4842 // done because by tail calling the called function might overwrite the value
4843 // in this function's (MF) stack pointer stack slot 0(SP).
4844 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4845 CallConv == CallingConv::Fast)
4846 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4848 // Count how many bytes are to be pushed on the stack, including the linkage
4849 // area, and parameter passing area. We start with 24/48 bytes, which is
4850 // prereserved space for [SP][CR][LR][3 x unused].
4851 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4853 unsigned NumBytes = LinkageSize;
4855 // Add up all the space actually used.
4856 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4857 // they all go in registers, but we must reserve stack space for them for
4858 // possible use by the caller. In varargs or 64-bit calls, parameters are
4859 // assigned stack space in order, with padding so Altivec parameters are
4861 unsigned nAltivecParamsAtEnd = 0;
4862 for (unsigned i = 0; i != NumOps; ++i) {
4863 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4864 EVT ArgVT = Outs[i].VT;
4865 // Varargs Altivec parameters are padded to a 16 byte boundary.
4866 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4867 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4868 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4869 if (!isVarArg && !isPPC64) {
4870 // Non-varargs Altivec parameters go after all the non-Altivec
4871 // parameters; handle those later so we know how much padding we need.
4872 nAltivecParamsAtEnd++;
4875 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4876 NumBytes = ((NumBytes+15)/16)*16;
4878 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4881 // Allow for Altivec parameters at the end, if needed.
4882 if (nAltivecParamsAtEnd) {
4883 NumBytes = ((NumBytes+15)/16)*16;
4884 NumBytes += 16*nAltivecParamsAtEnd;
4887 // The prolog code of the callee may store up to 8 GPR argument registers to
4888 // the stack, allowing va_start to index over them in memory if its varargs.
4889 // Because we cannot tell if this is needed on the caller side, we have to
4890 // conservatively assume that it is needed. As such, make sure we have at
4891 // least enough stack space for the caller to store the 8 GPRs.
4892 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4894 // Tail call needs the stack to be aligned.
4895 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4896 CallConv == CallingConv::Fast)
4897 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4899 // Calculate by how many bytes the stack has to be adjusted in case of tail
4900 // call optimization.
4901 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4903 // To protect arguments on the stack from being clobbered in a tail call,
4904 // force all the loads to happen before doing any other lowering.
4906 Chain = DAG.getStackArgumentTokenFactor(Chain);
4908 // Adjust the stack pointer for the new arguments...
4909 // These operations are automatically eliminated by the prolog/epilog pass
4910 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4912 SDValue CallSeqStart = Chain;
4914 // Load the return address and frame pointer so it can be move somewhere else
4917 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4920 // Set up a copy of the stack pointer for use loading and storing any
4921 // arguments that may not fit in the registers available for argument
4925 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4927 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4929 // Figure out which arguments are going to go in registers, and which in
4930 // memory. Also, if this is a vararg function, floating point operations
4931 // must be stored to our stack, and loaded into integer regs as well, if
4932 // any integer regs are available for argument passing.
4933 unsigned ArgOffset = LinkageSize;
4934 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4936 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4937 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4938 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4940 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4941 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4942 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4944 static const MCPhysReg *FPR = GetFPR();
4946 static const MCPhysReg VR[] = {
4947 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4948 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4950 const unsigned NumGPRs = array_lengthof(GPR_32);
4951 const unsigned NumFPRs = 13;
4952 const unsigned NumVRs = array_lengthof(VR);
4954 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4956 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4957 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4959 SmallVector<SDValue, 8> MemOpChains;
4960 for (unsigned i = 0; i != NumOps; ++i) {
4961 SDValue Arg = OutVals[i];
4962 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4964 // PtrOff will be used to store the current argument to the stack if a
4965 // register cannot be found for it.
4968 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4970 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4972 // On PPC64, promote integers to 64-bit values.
4973 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4974 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4975 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4976 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4979 // FIXME memcpy is used way more than necessary. Correctness first.
4980 // Note: "by value" is code for passing a structure by value, not
4982 if (Flags.isByVal()) {
4983 unsigned Size = Flags.getByValSize();
4984 // Very small objects are passed right-justified. Everything else is
4985 // passed left-justified.
4986 if (Size==1 || Size==2) {
4987 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4988 if (GPR_idx != NumGPRs) {
4989 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4990 MachinePointerInfo(), VT,
4991 false, false, false, 0);
4992 MemOpChains.push_back(Load.getValue(1));
4993 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4995 ArgOffset += PtrByteSize;
4997 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4998 PtrOff.getValueType());
4999 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5000 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5003 ArgOffset += PtrByteSize;
5007 // Copy entire object into memory. There are cases where gcc-generated
5008 // code assumes it is there, even if it could be put entirely into
5009 // registers. (This is not what the doc says.)
5010 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5014 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5015 // copy the pieces of the object that fit into registers from the
5016 // parameter save area.
5017 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5018 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5019 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5020 if (GPR_idx != NumGPRs) {
5021 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5022 MachinePointerInfo(),
5023 false, false, false, 0);
5024 MemOpChains.push_back(Load.getValue(1));
5025 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5026 ArgOffset += PtrByteSize;
5028 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5035 switch (Arg.getSimpleValueType().SimpleTy) {
5036 default: llvm_unreachable("Unexpected ValueType for argument!");
5040 if (GPR_idx != NumGPRs) {
5041 if (Arg.getValueType() == MVT::i1)
5042 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5044 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5046 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5047 isPPC64, isTailCall, false, MemOpChains,
5048 TailCallArguments, dl);
5050 ArgOffset += PtrByteSize;
5054 if (FPR_idx != NumFPRs) {
5055 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5058 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5059 MachinePointerInfo(), false, false, 0);
5060 MemOpChains.push_back(Store);
5062 // Float varargs are always shadowed in available integer registers
5063 if (GPR_idx != NumGPRs) {
5064 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5065 MachinePointerInfo(), false, false,
5067 MemOpChains.push_back(Load.getValue(1));
5068 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5070 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5071 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5072 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5073 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5074 MachinePointerInfo(),
5075 false, false, false, 0);
5076 MemOpChains.push_back(Load.getValue(1));
5077 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5080 // If we have any FPRs remaining, we may also have GPRs remaining.
5081 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5083 if (GPR_idx != NumGPRs)
5085 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5086 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5090 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5091 isPPC64, isTailCall, false, MemOpChains,
5092 TailCallArguments, dl);
5096 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5103 // These go aligned on the stack, or in the corresponding R registers
5104 // when within range. The Darwin PPC ABI doc claims they also go in
5105 // V registers; in fact gcc does this only for arguments that are
5106 // prototyped, not for those that match the ... We do it for all
5107 // arguments, seems to work.
5108 while (ArgOffset % 16 !=0) {
5109 ArgOffset += PtrByteSize;
5110 if (GPR_idx != NumGPRs)
5113 // We could elide this store in the case where the object fits
5114 // entirely in R registers. Maybe later.
5115 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5116 DAG.getConstant(ArgOffset, PtrVT));
5117 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5118 MachinePointerInfo(), false, false, 0);
5119 MemOpChains.push_back(Store);
5120 if (VR_idx != NumVRs) {
5121 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5122 MachinePointerInfo(),
5123 false, false, false, 0);
5124 MemOpChains.push_back(Load.getValue(1));
5125 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5128 for (unsigned i=0; i<16; i+=PtrByteSize) {
5129 if (GPR_idx == NumGPRs)
5131 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5132 DAG.getConstant(i, PtrVT));
5133 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5134 false, false, false, 0);
5135 MemOpChains.push_back(Load.getValue(1));
5136 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5141 // Non-varargs Altivec params generally go in registers, but have
5142 // stack space allocated at the end.
5143 if (VR_idx != NumVRs) {
5144 // Doesn't have GPR space allocated.
5145 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5146 } else if (nAltivecParamsAtEnd==0) {
5147 // We are emitting Altivec params in order.
5148 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5149 isPPC64, isTailCall, true, MemOpChains,
5150 TailCallArguments, dl);
5156 // If all Altivec parameters fit in registers, as they usually do,
5157 // they get stack space following the non-Altivec parameters. We
5158 // don't track this here because nobody below needs it.
5159 // If there are more Altivec parameters than fit in registers emit
5161 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5163 // Offset is aligned; skip 1st 12 params which go in V registers.
5164 ArgOffset = ((ArgOffset+15)/16)*16;
5166 for (unsigned i = 0; i != NumOps; ++i) {
5167 SDValue Arg = OutVals[i];
5168 EVT ArgType = Outs[i].VT;
5169 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5170 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5173 // We are emitting Altivec params in order.
5174 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5175 isPPC64, isTailCall, true, MemOpChains,
5176 TailCallArguments, dl);
5183 if (!MemOpChains.empty())
5184 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5186 // On Darwin, R12 must contain the address of an indirect callee. This does
5187 // not mean the MTCTR instruction must use R12; it's easier to model this as
5188 // an extra parameter, so do that.
5190 !isFunctionGlobalAddress(Callee) &&
5191 !isa<ExternalSymbolSDNode>(Callee) &&
5192 !isBLACompatibleAddress(Callee, DAG))
5193 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5194 PPC::R12), Callee));
5196 // Build a sequence of copy-to-reg nodes chained together with token chain
5197 // and flag operands which copy the outgoing args into the appropriate regs.
5199 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5200 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5201 RegsToPass[i].second, InFlag);
5202 InFlag = Chain.getValue(1);
5206 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5207 FPOp, true, TailCallArguments);
5209 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5210 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5211 NumBytes, Ins, InVals, CS);
5215 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5216 MachineFunction &MF, bool isVarArg,
5217 const SmallVectorImpl<ISD::OutputArg> &Outs,
5218 LLVMContext &Context) const {
5219 SmallVector<CCValAssign, 16> RVLocs;
5220 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5221 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5225 PPCTargetLowering::LowerReturn(SDValue Chain,
5226 CallingConv::ID CallConv, bool isVarArg,
5227 const SmallVectorImpl<ISD::OutputArg> &Outs,
5228 const SmallVectorImpl<SDValue> &OutVals,
5229 SDLoc dl, SelectionDAG &DAG) const {
5231 SmallVector<CCValAssign, 16> RVLocs;
5232 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5234 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5237 SmallVector<SDValue, 4> RetOps(1, Chain);
5239 // Copy the result values into the output registers.
5240 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5241 CCValAssign &VA = RVLocs[i];
5242 assert(VA.isRegLoc() && "Can only return in registers!");
5244 SDValue Arg = OutVals[i];
5246 switch (VA.getLocInfo()) {
5247 default: llvm_unreachable("Unknown loc info!");
5248 case CCValAssign::Full: break;
5249 case CCValAssign::AExt:
5250 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5252 case CCValAssign::ZExt:
5253 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5255 case CCValAssign::SExt:
5256 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5260 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5261 Flag = Chain.getValue(1);
5262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5265 RetOps[0] = Chain; // Update chain.
5267 // Add the flag if we have it.
5269 RetOps.push_back(Flag);
5271 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5274 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5275 const PPCSubtarget &Subtarget) const {
5276 // When we pop the dynamic allocation we need to restore the SP link.
5279 // Get the corect type for pointers.
5280 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5282 // Construct the stack pointer operand.
5283 bool isPPC64 = Subtarget.isPPC64();
5284 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5285 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5287 // Get the operands for the STACKRESTORE.
5288 SDValue Chain = Op.getOperand(0);
5289 SDValue SaveSP = Op.getOperand(1);
5291 // Load the old link SP.
5292 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5293 MachinePointerInfo(),
5294 false, false, false, 0);
5296 // Restore the stack pointer.
5297 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5299 // Store the old link SP.
5300 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5307 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5308 MachineFunction &MF = DAG.getMachineFunction();
5309 bool isPPC64 = Subtarget.isPPC64();
5310 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5312 // Get current frame pointer save index. The users of this index will be
5313 // primarily DYNALLOC instructions.
5314 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5315 int RASI = FI->getReturnAddrSaveIndex();
5317 // If the frame pointer save index hasn't been defined yet.
5319 // Find out what the fix offset of the frame pointer save area.
5320 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5321 // Allocate the frame index for frame pointer save area.
5322 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5324 FI->setReturnAddrSaveIndex(RASI);
5326 return DAG.getFrameIndex(RASI, PtrVT);
5330 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5331 MachineFunction &MF = DAG.getMachineFunction();
5332 bool isPPC64 = Subtarget.isPPC64();
5333 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5335 // Get current frame pointer save index. The users of this index will be
5336 // primarily DYNALLOC instructions.
5337 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5338 int FPSI = FI->getFramePointerSaveIndex();
5340 // If the frame pointer save index hasn't been defined yet.
5342 // Find out what the fix offset of the frame pointer save area.
5343 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5344 // Allocate the frame index for frame pointer save area.
5345 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5347 FI->setFramePointerSaveIndex(FPSI);
5349 return DAG.getFrameIndex(FPSI, PtrVT);
5352 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5354 const PPCSubtarget &Subtarget) const {
5356 SDValue Chain = Op.getOperand(0);
5357 SDValue Size = Op.getOperand(1);
5360 // Get the corect type for pointers.
5361 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5363 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5364 DAG.getConstant(0, PtrVT), Size);
5365 // Construct a node for the frame pointer save index.
5366 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5367 // Build a DYNALLOC node.
5368 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5369 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5370 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5373 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5374 SelectionDAG &DAG) const {
5376 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5377 DAG.getVTList(MVT::i32, MVT::Other),
5378 Op.getOperand(0), Op.getOperand(1));
5381 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5382 SelectionDAG &DAG) const {
5384 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5385 Op.getOperand(0), Op.getOperand(1));
5388 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5389 assert(Op.getValueType() == MVT::i1 &&
5390 "Custom lowering only for i1 loads");
5392 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5395 LoadSDNode *LD = cast<LoadSDNode>(Op);
5397 SDValue Chain = LD->getChain();
5398 SDValue BasePtr = LD->getBasePtr();
5399 MachineMemOperand *MMO = LD->getMemOperand();
5401 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5402 BasePtr, MVT::i8, MMO);
5403 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5405 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5406 return DAG.getMergeValues(Ops, dl);
5409 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5410 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5411 "Custom lowering only for i1 stores");
5413 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5416 StoreSDNode *ST = cast<StoreSDNode>(Op);
5418 SDValue Chain = ST->getChain();
5419 SDValue BasePtr = ST->getBasePtr();
5420 SDValue Value = ST->getValue();
5421 MachineMemOperand *MMO = ST->getMemOperand();
5423 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5424 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5427 // FIXME: Remove this once the ANDI glue bug is fixed:
5428 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5429 assert(Op.getValueType() == MVT::i1 &&
5430 "Custom lowering only for i1 results");
5433 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5437 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5439 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5440 // Not FP? Not a fsel.
5441 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5442 !Op.getOperand(2).getValueType().isFloatingPoint())
5445 // We might be able to do better than this under some circumstances, but in
5446 // general, fsel-based lowering of select is a finite-math-only optimization.
5447 // For more information, see section F.3 of the 2.06 ISA specification.
5448 if (!DAG.getTarget().Options.NoInfsFPMath ||
5449 !DAG.getTarget().Options.NoNaNsFPMath)
5452 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5454 EVT ResVT = Op.getValueType();
5455 EVT CmpVT = Op.getOperand(0).getValueType();
5456 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5457 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5460 // If the RHS of the comparison is a 0.0, we don't need to do the
5461 // subtraction at all.
5463 if (isFloatingPointZero(RHS))
5465 default: break; // SETUO etc aren't handled by fsel.
5469 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5470 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5471 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5472 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5473 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5474 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5475 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5478 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5481 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5482 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5483 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5486 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5489 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5490 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5491 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5492 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5497 default: break; // SETUO etc aren't handled by fsel.
5501 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5502 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5503 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5504 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5505 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5506 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5507 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5508 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5511 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5512 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5513 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5514 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5517 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5518 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5519 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5520 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5523 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5524 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5525 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5526 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5529 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5530 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5531 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5532 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5537 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5540 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5541 SDValue Src = Op.getOperand(0);
5542 if (Src.getValueType() == MVT::f32)
5543 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5546 switch (Op.getSimpleValueType().SimpleTy) {
5547 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5550 Op.getOpcode() == ISD::FP_TO_SINT
5552 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5556 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5557 "i64 FP_TO_UINT is supported only with FPCVT");
5558 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5564 // Convert the FP value to an int value through memory.
5565 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5566 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5567 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5568 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5569 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5571 // Emit a store to the stack slot.
5574 MachineFunction &MF = DAG.getMachineFunction();
5575 MachineMemOperand *MMO =
5576 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5577 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5578 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5579 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5581 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5582 MPI, false, false, 0);
5584 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5586 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5587 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5588 DAG.getConstant(4, FIPtr.getValueType()));
5589 MPI = MPI.getWithOffset(4);
5597 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5600 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5602 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5603 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5607 // We're trying to insert a regular store, S, and then a load, L. If the
5608 // incoming value, O, is a load, we might just be able to have our load use the
5609 // address used by O. However, we don't know if anything else will store to
5610 // that address before we can load from it. To prevent this situation, we need
5611 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5612 // the same chain operand as O, we create a token factor from the chain results
5613 // of O and L, and we replace all uses of O's chain result with that token
5614 // factor (see spliceIntoChain below for this last part).
5615 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5618 ISD::LoadExtType ET) const {
5620 if (ET == ISD::NON_EXTLOAD &&
5621 (Op.getOpcode() == ISD::FP_TO_UINT ||
5622 Op.getOpcode() == ISD::FP_TO_SINT) &&
5623 isOperationLegalOrCustom(Op.getOpcode(),
5624 Op.getOperand(0).getValueType())) {
5626 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5630 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5631 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5632 LD->isNonTemporal())
5634 if (LD->getMemoryVT() != MemVT)
5637 RLI.Ptr = LD->getBasePtr();
5638 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5639 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5640 "Non-pre-inc AM on PPC?");
5641 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5645 RLI.Chain = LD->getChain();
5646 RLI.MPI = LD->getPointerInfo();
5647 RLI.IsInvariant = LD->isInvariant();
5648 RLI.Alignment = LD->getAlignment();
5649 RLI.AAInfo = LD->getAAInfo();
5650 RLI.Ranges = LD->getRanges();
5652 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5656 // Given the head of the old chain, ResChain, insert a token factor containing
5657 // it and NewResChain, and make users of ResChain now be users of that token
5659 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5660 SDValue NewResChain,
5661 SelectionDAG &DAG) const {
5665 SDLoc dl(NewResChain);
5667 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5668 NewResChain, DAG.getUNDEF(MVT::Other));
5669 assert(TF.getNode() != NewResChain.getNode() &&
5670 "A new TF really is required here");
5672 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5673 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5676 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5677 SelectionDAG &DAG) const {
5679 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5680 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5683 if (Op.getOperand(0).getValueType() == MVT::i1)
5684 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5685 DAG.getConstantFP(1.0, Op.getValueType()),
5686 DAG.getConstantFP(0.0, Op.getValueType()));
5688 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5689 "UINT_TO_FP is supported only with FPCVT");
5691 // If we have FCFIDS, then use it when converting to single-precision.
5692 // Otherwise, convert to double-precision and then round.
5693 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5694 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
5696 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
5698 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5702 if (Op.getOperand(0).getValueType() == MVT::i64) {
5703 SDValue SINT = Op.getOperand(0);
5704 // When converting to single-precision, we actually need to convert
5705 // to double-precision first and then round to single-precision.
5706 // To avoid double-rounding effects during that operation, we have
5707 // to prepare the input operand. Bits that might be truncated when
5708 // converting to double-precision are replaced by a bit that won't
5709 // be lost at this stage, but is below the single-precision rounding
5712 // However, if -enable-unsafe-fp-math is in effect, accept double
5713 // rounding to avoid the extra overhead.
5714 if (Op.getValueType() == MVT::f32 &&
5715 !Subtarget.hasFPCVT() &&
5716 !DAG.getTarget().Options.UnsafeFPMath) {
5718 // Twiddle input to make sure the low 11 bits are zero. (If this
5719 // is the case, we are guaranteed the value will fit into the 53 bit
5720 // mantissa of an IEEE double-precision value without rounding.)
5721 // If any of those low 11 bits were not zero originally, make sure
5722 // bit 12 (value 2048) is set instead, so that the final rounding
5723 // to single-precision gets the correct result.
5724 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5725 SINT, DAG.getConstant(2047, MVT::i64));
5726 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5727 Round, DAG.getConstant(2047, MVT::i64));
5728 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5729 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5730 Round, DAG.getConstant(-2048, MVT::i64));
5732 // However, we cannot use that value unconditionally: if the magnitude
5733 // of the input value is small, the bit-twiddling we did above might
5734 // end up visibly changing the output. Fortunately, in that case, we
5735 // don't need to twiddle bits since the original input will convert
5736 // exactly to double-precision floating-point already. Therefore,
5737 // construct a conditional to use the original value if the top 11
5738 // bits are all sign-bit copies, and use the rounded value computed
5740 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5741 SINT, DAG.getConstant(53, MVT::i32));
5742 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5743 Cond, DAG.getConstant(1, MVT::i64));
5744 Cond = DAG.getSetCC(dl, MVT::i32,
5745 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5747 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5753 MachineFunction &MF = DAG.getMachineFunction();
5754 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5755 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5756 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5758 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5759 } else if (Subtarget.hasLFIWAX() &&
5760 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5761 MachineMemOperand *MMO =
5762 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5763 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5764 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5765 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5766 DAG.getVTList(MVT::f64, MVT::Other),
5767 Ops, MVT::i32, MMO);
5768 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5769 } else if (Subtarget.hasFPCVT() &&
5770 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5771 MachineMemOperand *MMO =
5772 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5773 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5774 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5775 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5776 DAG.getVTList(MVT::f64, MVT::Other),
5777 Ops, MVT::i32, MMO);
5778 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5779 } else if (((Subtarget.hasLFIWAX() &&
5780 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5781 (Subtarget.hasFPCVT() &&
5782 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5783 SINT.getOperand(0).getValueType() == MVT::i32) {
5784 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5785 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5787 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5788 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5791 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5792 MachinePointerInfo::getFixedStack(FrameIdx),
5795 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5796 "Expected an i32 store");
5800 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5803 MachineMemOperand *MMO =
5804 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5805 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5806 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5807 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5808 PPCISD::LFIWZX : PPCISD::LFIWAX,
5809 dl, DAG.getVTList(MVT::f64, MVT::Other),
5810 Ops, MVT::i32, MMO);
5812 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5814 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5816 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5817 FP = DAG.getNode(ISD::FP_ROUND, dl,
5818 MVT::f32, FP, DAG.getIntPtrConstant(0));
5822 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5823 "Unhandled INT_TO_FP type in custom expander!");
5824 // Since we only generate this in 64-bit mode, we can take advantage of
5825 // 64-bit registers. In particular, sign extend the input value into the
5826 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5827 // then lfd it and fcfid it.
5828 MachineFunction &MF = DAG.getMachineFunction();
5829 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5830 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5833 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5836 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5838 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5839 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5841 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5842 MachinePointerInfo::getFixedStack(FrameIdx),
5845 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5846 "Expected an i32 store");
5850 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5854 MachineMemOperand *MMO =
5855 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5856 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5857 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5858 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5859 PPCISD::LFIWZX : PPCISD::LFIWAX,
5860 dl, DAG.getVTList(MVT::f64, MVT::Other),
5861 Ops, MVT::i32, MMO);
5863 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5865 assert(Subtarget.isPPC64() &&
5866 "i32->FP without LFIWAX supported only on PPC64");
5868 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5869 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5871 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5874 // STD the extended value into the stack slot.
5875 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5876 MachinePointerInfo::getFixedStack(FrameIdx),
5879 // Load the value as a double.
5880 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5881 MachinePointerInfo::getFixedStack(FrameIdx),
5882 false, false, false, 0);
5885 // FCFID it and return it.
5886 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5887 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5888 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5892 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5893 SelectionDAG &DAG) const {
5896 The rounding mode is in bits 30:31 of FPSR, and has the following
5903 FLT_ROUNDS, on the other hand, expects the following:
5910 To perform the conversion, we do:
5911 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5914 MachineFunction &MF = DAG.getMachineFunction();
5915 EVT VT = Op.getValueType();
5916 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5918 // Save FP Control Word to register
5920 MVT::f64, // return register
5921 MVT::Glue // unused in this context
5923 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5925 // Save FP register to stack slot
5926 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5927 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5928 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5929 StackSlot, MachinePointerInfo(), false, false,0);
5931 // Load FP Control Word from low 32 bits of stack slot.
5932 SDValue Four = DAG.getConstant(4, PtrVT);
5933 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5934 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5935 false, false, false, 0);
5937 // Transform as necessary
5939 DAG.getNode(ISD::AND, dl, MVT::i32,
5940 CWD, DAG.getConstant(3, MVT::i32));
5942 DAG.getNode(ISD::SRL, dl, MVT::i32,
5943 DAG.getNode(ISD::AND, dl, MVT::i32,
5944 DAG.getNode(ISD::XOR, dl, MVT::i32,
5945 CWD, DAG.getConstant(3, MVT::i32)),
5946 DAG.getConstant(3, MVT::i32)),
5947 DAG.getConstant(1, MVT::i32));
5950 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5952 return DAG.getNode((VT.getSizeInBits() < 16 ?
5953 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5956 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5957 EVT VT = Op.getValueType();
5958 unsigned BitWidth = VT.getSizeInBits();
5960 assert(Op.getNumOperands() == 3 &&
5961 VT == Op.getOperand(1).getValueType() &&
5964 // Expand into a bunch of logical ops. Note that these ops
5965 // depend on the PPC behavior for oversized shift amounts.
5966 SDValue Lo = Op.getOperand(0);
5967 SDValue Hi = Op.getOperand(1);
5968 SDValue Amt = Op.getOperand(2);
5969 EVT AmtVT = Amt.getValueType();
5971 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5972 DAG.getConstant(BitWidth, AmtVT), Amt);
5973 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5974 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5975 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5976 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5977 DAG.getConstant(-BitWidth, AmtVT));
5978 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5979 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5980 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5981 SDValue OutOps[] = { OutLo, OutHi };
5982 return DAG.getMergeValues(OutOps, dl);
5985 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5986 EVT VT = Op.getValueType();
5988 unsigned BitWidth = VT.getSizeInBits();
5989 assert(Op.getNumOperands() == 3 &&
5990 VT == Op.getOperand(1).getValueType() &&
5993 // Expand into a bunch of logical ops. Note that these ops
5994 // depend on the PPC behavior for oversized shift amounts.
5995 SDValue Lo = Op.getOperand(0);
5996 SDValue Hi = Op.getOperand(1);
5997 SDValue Amt = Op.getOperand(2);
5998 EVT AmtVT = Amt.getValueType();
6000 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6001 DAG.getConstant(BitWidth, AmtVT), Amt);
6002 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6003 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6004 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6005 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6006 DAG.getConstant(-BitWidth, AmtVT));
6007 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6008 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6009 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6010 SDValue OutOps[] = { OutLo, OutHi };
6011 return DAG.getMergeValues(OutOps, dl);
6014 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6016 EVT VT = Op.getValueType();
6017 unsigned BitWidth = VT.getSizeInBits();
6018 assert(Op.getNumOperands() == 3 &&
6019 VT == Op.getOperand(1).getValueType() &&
6022 // Expand into a bunch of logical ops, followed by a select_cc.
6023 SDValue Lo = Op.getOperand(0);
6024 SDValue Hi = Op.getOperand(1);
6025 SDValue Amt = Op.getOperand(2);
6026 EVT AmtVT = Amt.getValueType();
6028 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6029 DAG.getConstant(BitWidth, AmtVT), Amt);
6030 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6031 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6032 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6033 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6034 DAG.getConstant(-BitWidth, AmtVT));
6035 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6036 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6037 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6038 Tmp4, Tmp6, ISD::SETLE);
6039 SDValue OutOps[] = { OutLo, OutHi };
6040 return DAG.getMergeValues(OutOps, dl);
6043 //===----------------------------------------------------------------------===//
6044 // Vector related lowering.
6047 /// BuildSplatI - Build a canonical splati of Val with an element size of
6048 /// SplatSize. Cast the result to VT.
6049 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6050 SelectionDAG &DAG, SDLoc dl) {
6051 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6053 static const EVT VTys[] = { // canonical VT to use for each size.
6054 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6057 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6059 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6063 EVT CanonicalVT = VTys[SplatSize-1];
6065 // Build a canonical splat for this value.
6066 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6067 SmallVector<SDValue, 8> Ops;
6068 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6069 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6070 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6073 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6074 /// specified intrinsic ID.
6075 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6076 SelectionDAG &DAG, SDLoc dl,
6077 EVT DestVT = MVT::Other) {
6078 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6079 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6080 DAG.getConstant(IID, MVT::i32), Op);
6083 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6084 /// specified intrinsic ID.
6085 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6086 SelectionDAG &DAG, SDLoc dl,
6087 EVT DestVT = MVT::Other) {
6088 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6089 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6090 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6093 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6094 /// specified intrinsic ID.
6095 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6096 SDValue Op2, SelectionDAG &DAG,
6097 SDLoc dl, EVT DestVT = MVT::Other) {
6098 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6099 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6100 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6104 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6105 /// amount. The result has the specified value type.
6106 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6107 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6108 // Force LHS/RHS to be the right type.
6109 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6110 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6113 for (unsigned i = 0; i != 16; ++i)
6115 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6116 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6119 // If this is a case we can't handle, return null and let the default
6120 // expansion code take care of it. If we CAN select this case, and if it
6121 // selects to a single instruction, return Op. Otherwise, if we can codegen
6122 // this case more efficiently than a constant pool load, lower it to the
6123 // sequence of ops that should be used.
6124 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6125 SelectionDAG &DAG) const {
6127 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6128 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6130 // Check if this is a splat of a constant value.
6131 APInt APSplatBits, APSplatUndef;
6132 unsigned SplatBitSize;
6134 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6135 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6138 unsigned SplatBits = APSplatBits.getZExtValue();
6139 unsigned SplatUndef = APSplatUndef.getZExtValue();
6140 unsigned SplatSize = SplatBitSize / 8;
6142 // First, handle single instruction cases.
6145 if (SplatBits == 0) {
6146 // Canonicalize all zero vectors to be v4i32.
6147 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6148 SDValue Z = DAG.getConstant(0, MVT::i32);
6149 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6150 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6155 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6156 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6158 if (SextVal >= -16 && SextVal <= 15)
6159 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6162 // Two instruction sequences.
6164 // If this value is in the range [-32,30] and is even, use:
6165 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6166 // If this value is in the range [17,31] and is odd, use:
6167 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6168 // If this value is in the range [-31,-17] and is odd, use:
6169 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6170 // Note the last two are three-instruction sequences.
6171 if (SextVal >= -32 && SextVal <= 31) {
6172 // To avoid having these optimizations undone by constant folding,
6173 // we convert to a pseudo that will be expanded later into one of
6175 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6176 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6177 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6178 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6179 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6180 if (VT == Op.getValueType())
6183 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6186 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6187 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6189 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6190 // Make -1 and vspltisw -1:
6191 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6193 // Make the VSLW intrinsic, computing 0x8000_0000.
6194 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6197 // xor by OnesV to invert it.
6198 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6199 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6202 // The remaining cases assume either big endian element order or
6203 // a splat-size that equates to the element size of the vector
6204 // to be built. An example that doesn't work for little endian is
6205 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6206 // and a vector element size of 16 bits. The code below will
6207 // produce the vector in big endian element order, which for little
6208 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6210 // For now, just avoid these optimizations in that case.
6211 // FIXME: Develop correct optimizations for LE with mismatched
6212 // splat and element sizes.
6214 if (Subtarget.isLittleEndian() &&
6215 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6218 // Check to see if this is a wide variety of vsplti*, binop self cases.
6219 static const signed char SplatCsts[] = {
6220 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6221 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6224 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6225 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6226 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6227 int i = SplatCsts[idx];
6229 // Figure out what shift amount will be used by altivec if shifted by i in
6231 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6233 // vsplti + shl self.
6234 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6235 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6236 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6237 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6238 Intrinsic::ppc_altivec_vslw
6240 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6241 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6244 // vsplti + srl self.
6245 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6246 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6247 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6248 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6249 Intrinsic::ppc_altivec_vsrw
6251 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6252 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6255 // vsplti + sra self.
6256 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6257 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6258 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6259 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6260 Intrinsic::ppc_altivec_vsraw
6262 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6263 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6266 // vsplti + rol self.
6267 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6268 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6269 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6270 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6271 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6272 Intrinsic::ppc_altivec_vrlw
6274 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6275 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6278 // t = vsplti c, result = vsldoi t, t, 1
6279 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6280 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6281 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6283 // t = vsplti c, result = vsldoi t, t, 2
6284 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6285 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6286 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6288 // t = vsplti c, result = vsldoi t, t, 3
6289 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6290 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6291 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6298 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6299 /// the specified operations to build the shuffle.
6300 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6301 SDValue RHS, SelectionDAG &DAG,
6303 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6304 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6305 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6308 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6320 if (OpNum == OP_COPY) {
6321 if (LHSID == (1*9+2)*9+3) return LHS;
6322 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6326 SDValue OpLHS, OpRHS;
6327 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6328 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6332 default: llvm_unreachable("Unknown i32 permute!");
6334 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6335 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6336 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6337 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6340 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6341 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6342 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6343 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6346 for (unsigned i = 0; i != 16; ++i)
6347 ShufIdxs[i] = (i&3)+0;
6350 for (unsigned i = 0; i != 16; ++i)
6351 ShufIdxs[i] = (i&3)+4;
6354 for (unsigned i = 0; i != 16; ++i)
6355 ShufIdxs[i] = (i&3)+8;
6358 for (unsigned i = 0; i != 16; ++i)
6359 ShufIdxs[i] = (i&3)+12;
6362 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6364 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6366 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6368 EVT VT = OpLHS.getValueType();
6369 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6370 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6371 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6372 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6375 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6376 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6377 /// return the code it can be lowered into. Worst case, it can always be
6378 /// lowered into a vperm.
6379 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6380 SelectionDAG &DAG) const {
6382 SDValue V1 = Op.getOperand(0);
6383 SDValue V2 = Op.getOperand(1);
6384 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6385 EVT VT = Op.getValueType();
6386 bool isLittleEndian = Subtarget.isLittleEndian();
6388 // Cases that are handled by instructions that take permute immediates
6389 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6390 // selected by the instruction selector.
6391 if (V2.getOpcode() == ISD::UNDEF) {
6392 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6393 PPC::isSplatShuffleMask(SVOp, 2) ||
6394 PPC::isSplatShuffleMask(SVOp, 4) ||
6395 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6396 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6397 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6398 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6399 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6400 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6401 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6402 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6403 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6408 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6409 // and produce a fixed permutation. If any of these match, do not lower to
6411 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6412 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6413 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6414 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6415 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6416 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6417 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6418 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6419 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6420 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6423 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6424 // perfect shuffle table to emit an optimal matching sequence.
6425 ArrayRef<int> PermMask = SVOp->getMask();
6427 unsigned PFIndexes[4];
6428 bool isFourElementShuffle = true;
6429 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6430 unsigned EltNo = 8; // Start out undef.
6431 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6432 if (PermMask[i*4+j] < 0)
6433 continue; // Undef, ignore it.
6435 unsigned ByteSource = PermMask[i*4+j];
6436 if ((ByteSource & 3) != j) {
6437 isFourElementShuffle = false;
6442 EltNo = ByteSource/4;
6443 } else if (EltNo != ByteSource/4) {
6444 isFourElementShuffle = false;
6448 PFIndexes[i] = EltNo;
6451 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6452 // perfect shuffle vector to determine if it is cost effective to do this as
6453 // discrete instructions, or whether we should use a vperm.
6454 // For now, we skip this for little endian until such time as we have a
6455 // little-endian perfect shuffle table.
6456 if (isFourElementShuffle && !isLittleEndian) {
6457 // Compute the index in the perfect shuffle table.
6458 unsigned PFTableIndex =
6459 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6461 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6462 unsigned Cost = (PFEntry >> 30);
6464 // Determining when to avoid vperm is tricky. Many things affect the cost
6465 // of vperm, particularly how many times the perm mask needs to be computed.
6466 // For example, if the perm mask can be hoisted out of a loop or is already
6467 // used (perhaps because there are multiple permutes with the same shuffle
6468 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6469 // the loop requires an extra register.
6471 // As a compromise, we only emit discrete instructions if the shuffle can be
6472 // generated in 3 or fewer operations. When we have loop information
6473 // available, if this block is within a loop, we should avoid using vperm
6474 // for 3-operation perms and use a constant pool load instead.
6476 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6479 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6480 // vector that will get spilled to the constant pool.
6481 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6483 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6484 // that it is in input element units, not in bytes. Convert now.
6486 // For little endian, the order of the input vectors is reversed, and
6487 // the permutation mask is complemented with respect to 31. This is
6488 // necessary to produce proper semantics with the big-endian-biased vperm
6490 EVT EltVT = V1.getValueType().getVectorElementType();
6491 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6493 SmallVector<SDValue, 16> ResultMask;
6494 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6495 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6497 for (unsigned j = 0; j != BytesPerElement; ++j)
6499 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6502 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6506 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6509 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6512 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6516 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6517 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6518 /// information about the intrinsic.
6519 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6521 unsigned IntrinsicID =
6522 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6525 switch (IntrinsicID) {
6526 default: return false;
6527 // Comparison predicates.
6528 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6529 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6530 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6531 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6532 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6533 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6534 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6535 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6536 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6537 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6538 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6539 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6540 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6542 // Normal Comparisons.
6543 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6544 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6545 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6546 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6547 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6548 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6549 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6550 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6551 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6552 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6553 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6554 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6555 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6560 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6561 /// lower, do it, otherwise return null.
6562 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6563 SelectionDAG &DAG) const {
6564 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6565 // opcode number of the comparison.
6569 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6570 return SDValue(); // Don't custom lower most intrinsics.
6572 // If this is a non-dot comparison, make the VCMP node and we are done.
6574 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6575 Op.getOperand(1), Op.getOperand(2),
6576 DAG.getConstant(CompareOpc, MVT::i32));
6577 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6580 // Create the PPCISD altivec 'dot' comparison node.
6582 Op.getOperand(2), // LHS
6583 Op.getOperand(3), // RHS
6584 DAG.getConstant(CompareOpc, MVT::i32)
6586 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6587 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6589 // Now that we have the comparison, emit a copy from the CR to a GPR.
6590 // This is flagged to the above dot comparison.
6591 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6592 DAG.getRegister(PPC::CR6, MVT::i32),
6593 CompNode.getValue(1));
6595 // Unpack the result based on how the target uses it.
6596 unsigned BitNo; // Bit # of CR6.
6597 bool InvertBit; // Invert result?
6598 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6599 default: // Can't happen, don't crash on invalid number though.
6600 case 0: // Return the value of the EQ bit of CR6.
6601 BitNo = 0; InvertBit = false;
6603 case 1: // Return the inverted value of the EQ bit of CR6.
6604 BitNo = 0; InvertBit = true;
6606 case 2: // Return the value of the LT bit of CR6.
6607 BitNo = 2; InvertBit = false;
6609 case 3: // Return the inverted value of the LT bit of CR6.
6610 BitNo = 2; InvertBit = true;
6614 // Shift the bit into the low position.
6615 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6616 DAG.getConstant(8-(3-BitNo), MVT::i32));
6618 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6619 DAG.getConstant(1, MVT::i32));
6621 // If we are supposed to, toggle the bit.
6623 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6624 DAG.getConstant(1, MVT::i32));
6628 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6629 SelectionDAG &DAG) const {
6631 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6632 // instructions), but for smaller types, we need to first extend up to v2i32
6633 // before doing going farther.
6634 if (Op.getValueType() == MVT::v2i64) {
6635 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6636 if (ExtVT != MVT::v2i32) {
6637 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6638 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6639 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6640 ExtVT.getVectorElementType(), 4)));
6641 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6642 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6643 DAG.getValueType(MVT::v2i32));
6652 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6653 SelectionDAG &DAG) const {
6655 // Create a stack slot that is 16-byte aligned.
6656 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6657 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6658 EVT PtrVT = getPointerTy();
6659 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6661 // Store the input value into Value#0 of the stack slot.
6662 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6663 Op.getOperand(0), FIdx, MachinePointerInfo(),
6666 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6667 false, false, false, 0);
6670 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6672 if (Op.getValueType() == MVT::v4i32) {
6673 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6675 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6676 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6678 SDValue RHSSwap = // = vrlw RHS, 16
6679 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6681 // Shrinkify inputs to v8i16.
6682 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6683 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6684 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6686 // Low parts multiplied together, generating 32-bit results (we ignore the
6688 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6689 LHS, RHS, DAG, dl, MVT::v4i32);
6691 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6692 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6693 // Shift the high parts up 16 bits.
6694 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6696 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6697 } else if (Op.getValueType() == MVT::v8i16) {
6698 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6700 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6702 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6703 LHS, RHS, Zero, DAG, dl);
6704 } else if (Op.getValueType() == MVT::v16i8) {
6705 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6706 bool isLittleEndian = Subtarget.isLittleEndian();
6708 // Multiply the even 8-bit parts, producing 16-bit sums.
6709 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6710 LHS, RHS, DAG, dl, MVT::v8i16);
6711 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6713 // Multiply the odd 8-bit parts, producing 16-bit sums.
6714 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6715 LHS, RHS, DAG, dl, MVT::v8i16);
6716 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6718 // Merge the results together. Because vmuleub and vmuloub are
6719 // instructions with a big-endian bias, we must reverse the
6720 // element numbering and reverse the meaning of "odd" and "even"
6721 // when generating little endian code.
6723 for (unsigned i = 0; i != 8; ++i) {
6724 if (isLittleEndian) {
6726 Ops[i*2+1] = 2*i+16;
6729 Ops[i*2+1] = 2*i+1+16;
6733 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6735 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6737 llvm_unreachable("Unknown mul to lower!");
6741 /// LowerOperation - Provide custom lowering hooks for some operations.
6743 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6744 switch (Op.getOpcode()) {
6745 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6746 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6747 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6748 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6749 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6750 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6751 case ISD::SETCC: return LowerSETCC(Op, DAG);
6752 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6753 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6755 return LowerVASTART(Op, DAG, Subtarget);
6758 return LowerVAARG(Op, DAG, Subtarget);
6761 return LowerVACOPY(Op, DAG, Subtarget);
6763 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6764 case ISD::DYNAMIC_STACKALLOC:
6765 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6767 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6768 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6770 case ISD::LOAD: return LowerLOAD(Op, DAG);
6771 case ISD::STORE: return LowerSTORE(Op, DAG);
6772 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6773 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6774 case ISD::FP_TO_UINT:
6775 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6777 case ISD::UINT_TO_FP:
6778 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6779 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6781 // Lower 64-bit shifts.
6782 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6783 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6784 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6786 // Vector-related lowering.
6787 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6788 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6789 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6790 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6791 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6792 case ISD::MUL: return LowerMUL(Op, DAG);
6794 // For counter-based loop handling.
6795 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6797 // Frame & Return address.
6798 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6799 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6803 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6804 SmallVectorImpl<SDValue>&Results,
6805 SelectionDAG &DAG) const {
6807 switch (N->getOpcode()) {
6809 llvm_unreachable("Do not know how to custom type legalize this operation!");
6810 case ISD::READCYCLECOUNTER: {
6811 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6812 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6814 Results.push_back(RTB);
6815 Results.push_back(RTB.getValue(1));
6816 Results.push_back(RTB.getValue(2));
6819 case ISD::INTRINSIC_W_CHAIN: {
6820 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6821 Intrinsic::ppc_is_decremented_ctr_nonzero)
6824 assert(N->getValueType(0) == MVT::i1 &&
6825 "Unexpected result type for CTR decrement intrinsic");
6826 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6827 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6828 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6831 Results.push_back(NewInt);
6832 Results.push_back(NewInt.getValue(1));
6836 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
6839 EVT VT = N->getValueType(0);
6841 if (VT == MVT::i64) {
6842 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6844 Results.push_back(NewNode);
6845 Results.push_back(NewNode.getValue(1));
6849 case ISD::FP_ROUND_INREG: {
6850 assert(N->getValueType(0) == MVT::ppcf128);
6851 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6852 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6853 MVT::f64, N->getOperand(0),
6854 DAG.getIntPtrConstant(0));
6855 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6856 MVT::f64, N->getOperand(0),
6857 DAG.getIntPtrConstant(1));
6859 // Add the two halves of the long double in round-to-zero mode.
6860 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6862 // We know the low half is about to be thrown away, so just use something
6864 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6868 case ISD::FP_TO_SINT:
6869 // LowerFP_TO_INT() can only handle f32 and f64.
6870 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6872 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6878 //===----------------------------------------------------------------------===//
6879 // Other Lowering Code
6880 //===----------------------------------------------------------------------===//
6882 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6883 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6884 Function *Func = Intrinsic::getDeclaration(M, Id);
6885 return Builder.CreateCall(Func);
6888 // The mappings for emitLeading/TrailingFence is taken from
6889 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6890 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6891 AtomicOrdering Ord, bool IsStore,
6892 bool IsLoad) const {
6893 if (Ord == SequentiallyConsistent)
6894 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6895 else if (isAtLeastRelease(Ord))
6896 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6901 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6902 AtomicOrdering Ord, bool IsStore,
6903 bool IsLoad) const {
6904 if (IsLoad && isAtLeastAcquire(Ord))
6905 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6906 // FIXME: this is too conservative, a dependent branch + isync is enough.
6907 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6908 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6909 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6915 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6916 bool is64bit, unsigned BinOpcode) const {
6917 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6918 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6920 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6921 MachineFunction *F = BB->getParent();
6922 MachineFunction::iterator It = BB;
6925 unsigned dest = MI->getOperand(0).getReg();
6926 unsigned ptrA = MI->getOperand(1).getReg();
6927 unsigned ptrB = MI->getOperand(2).getReg();
6928 unsigned incr = MI->getOperand(3).getReg();
6929 DebugLoc dl = MI->getDebugLoc();
6931 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6932 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6933 F->insert(It, loopMBB);
6934 F->insert(It, exitMBB);
6935 exitMBB->splice(exitMBB->begin(), BB,
6936 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6937 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6939 MachineRegisterInfo &RegInfo = F->getRegInfo();
6940 unsigned TmpReg = (!BinOpcode) ? incr :
6941 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6942 : &PPC::GPRCRegClass);
6946 // fallthrough --> loopMBB
6947 BB->addSuccessor(loopMBB);
6950 // l[wd]arx dest, ptr
6951 // add r0, dest, incr
6952 // st[wd]cx. r0, ptr
6954 // fallthrough --> exitMBB
6956 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6957 .addReg(ptrA).addReg(ptrB);
6959 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6960 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6961 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6962 BuildMI(BB, dl, TII->get(PPC::BCC))
6963 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6964 BB->addSuccessor(loopMBB);
6965 BB->addSuccessor(exitMBB);
6974 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6975 MachineBasicBlock *BB,
6976 bool is8bit, // operation
6977 unsigned BinOpcode) const {
6978 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6979 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6980 // In 64 bit mode we have to use 64 bits for addresses, even though the
6981 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6982 // registers without caring whether they're 32 or 64, but here we're
6983 // doing actual arithmetic on the addresses.
6984 bool is64bit = Subtarget.isPPC64();
6985 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6987 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6988 MachineFunction *F = BB->getParent();
6989 MachineFunction::iterator It = BB;
6992 unsigned dest = MI->getOperand(0).getReg();
6993 unsigned ptrA = MI->getOperand(1).getReg();
6994 unsigned ptrB = MI->getOperand(2).getReg();
6995 unsigned incr = MI->getOperand(3).getReg();
6996 DebugLoc dl = MI->getDebugLoc();
6998 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6999 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7000 F->insert(It, loopMBB);
7001 F->insert(It, exitMBB);
7002 exitMBB->splice(exitMBB->begin(), BB,
7003 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7004 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7006 MachineRegisterInfo &RegInfo = F->getRegInfo();
7007 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7008 : &PPC::GPRCRegClass;
7009 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7010 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7011 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7012 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7013 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7014 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7015 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7016 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7017 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7018 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7019 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7021 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7025 // fallthrough --> loopMBB
7026 BB->addSuccessor(loopMBB);
7028 // The 4-byte load must be aligned, while a char or short may be
7029 // anywhere in the word. Hence all this nasty bookkeeping code.
7030 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7031 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7032 // xori shift, shift1, 24 [16]
7033 // rlwinm ptr, ptr1, 0, 0, 29
7034 // slw incr2, incr, shift
7035 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7036 // slw mask, mask2, shift
7038 // lwarx tmpDest, ptr
7039 // add tmp, tmpDest, incr2
7040 // andc tmp2, tmpDest, mask
7041 // and tmp3, tmp, mask
7042 // or tmp4, tmp3, tmp2
7045 // fallthrough --> exitMBB
7046 // srw dest, tmpDest, shift
7047 if (ptrA != ZeroReg) {
7048 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7049 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7050 .addReg(ptrA).addReg(ptrB);
7054 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7055 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7056 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7057 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7059 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7060 .addReg(Ptr1Reg).addImm(0).addImm(61);
7062 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7063 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7064 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7065 .addReg(incr).addReg(ShiftReg);
7067 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7069 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7070 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7072 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7073 .addReg(Mask2Reg).addReg(ShiftReg);
7076 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7077 .addReg(ZeroReg).addReg(PtrReg);
7079 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7080 .addReg(Incr2Reg).addReg(TmpDestReg);
7081 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7082 .addReg(TmpDestReg).addReg(MaskReg);
7083 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7084 .addReg(TmpReg).addReg(MaskReg);
7085 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7086 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7087 BuildMI(BB, dl, TII->get(PPC::STWCX))
7088 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7089 BuildMI(BB, dl, TII->get(PPC::BCC))
7090 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7091 BB->addSuccessor(loopMBB);
7092 BB->addSuccessor(exitMBB);
7097 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7102 llvm::MachineBasicBlock*
7103 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7104 MachineBasicBlock *MBB) const {
7105 DebugLoc DL = MI->getDebugLoc();
7106 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7108 MachineFunction *MF = MBB->getParent();
7109 MachineRegisterInfo &MRI = MF->getRegInfo();
7111 const BasicBlock *BB = MBB->getBasicBlock();
7112 MachineFunction::iterator I = MBB;
7116 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7117 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7119 unsigned DstReg = MI->getOperand(0).getReg();
7120 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7121 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7122 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7123 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7125 MVT PVT = getPointerTy();
7126 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7127 "Invalid Pointer Size!");
7128 // For v = setjmp(buf), we generate
7131 // SjLjSetup mainMBB
7137 // buf[LabelOffset] = LR
7141 // v = phi(main, restore)
7144 MachineBasicBlock *thisMBB = MBB;
7145 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7146 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7147 MF->insert(I, mainMBB);
7148 MF->insert(I, sinkMBB);
7150 MachineInstrBuilder MIB;
7152 // Transfer the remainder of BB and its successor edges to sinkMBB.
7153 sinkMBB->splice(sinkMBB->begin(), MBB,
7154 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7155 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7157 // Note that the structure of the jmp_buf used here is not compatible
7158 // with that used by libc, and is not designed to be. Specifically, it
7159 // stores only those 'reserved' registers that LLVM does not otherwise
7160 // understand how to spill. Also, by convention, by the time this
7161 // intrinsic is called, Clang has already stored the frame address in the
7162 // first slot of the buffer and stack address in the third. Following the
7163 // X86 target code, we'll store the jump address in the second slot. We also
7164 // need to save the TOC pointer (R2) to handle jumps between shared
7165 // libraries, and that will be stored in the fourth slot. The thread
7166 // identifier (R13) is not affected.
7169 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7170 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7171 const int64_t BPOffset = 4 * PVT.getStoreSize();
7173 // Prepare IP either in reg.
7174 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7175 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7176 unsigned BufReg = MI->getOperand(1).getReg();
7178 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7179 setUsesTOCBasePtr(*MBB->getParent());
7180 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7184 MIB.setMemRefs(MMOBegin, MMOEnd);
7187 // Naked functions never have a base pointer, and so we use r1. For all
7188 // other functions, this decision must be delayed until during PEI.
7190 if (MF->getFunction()->getAttributes().hasAttribute(
7191 AttributeSet::FunctionIndex, Attribute::Naked))
7192 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7194 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7196 MIB = BuildMI(*thisMBB, MI, DL,
7197 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7201 MIB.setMemRefs(MMOBegin, MMOEnd);
7204 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7205 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
7206 MIB.addRegMask(TRI->getNoPreservedMask());
7208 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7210 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7212 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7214 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7215 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7220 BuildMI(mainMBB, DL,
7221 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7224 if (Subtarget.isPPC64()) {
7225 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7227 .addImm(LabelOffset)
7230 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7232 .addImm(LabelOffset)
7236 MIB.setMemRefs(MMOBegin, MMOEnd);
7238 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7239 mainMBB->addSuccessor(sinkMBB);
7242 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7243 TII->get(PPC::PHI), DstReg)
7244 .addReg(mainDstReg).addMBB(mainMBB)
7245 .addReg(restoreDstReg).addMBB(thisMBB);
7247 MI->eraseFromParent();
7252 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7253 MachineBasicBlock *MBB) const {
7254 DebugLoc DL = MI->getDebugLoc();
7255 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7257 MachineFunction *MF = MBB->getParent();
7258 MachineRegisterInfo &MRI = MF->getRegInfo();
7261 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7262 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7264 MVT PVT = getPointerTy();
7265 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7266 "Invalid Pointer Size!");
7268 const TargetRegisterClass *RC =
7269 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7270 unsigned Tmp = MRI.createVirtualRegister(RC);
7271 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7272 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7273 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7277 : (Subtarget.isSVR4ABI() &&
7278 MF->getTarget().getRelocationModel() == Reloc::PIC_
7282 MachineInstrBuilder MIB;
7284 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7285 const int64_t SPOffset = 2 * PVT.getStoreSize();
7286 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7287 const int64_t BPOffset = 4 * PVT.getStoreSize();
7289 unsigned BufReg = MI->getOperand(0).getReg();
7291 // Reload FP (the jumped-to function may not have had a
7292 // frame pointer, and if so, then its r31 will be restored
7294 if (PVT == MVT::i64) {
7295 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7299 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7303 MIB.setMemRefs(MMOBegin, MMOEnd);
7306 if (PVT == MVT::i64) {
7307 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7308 .addImm(LabelOffset)
7311 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7312 .addImm(LabelOffset)
7315 MIB.setMemRefs(MMOBegin, MMOEnd);
7318 if (PVT == MVT::i64) {
7319 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7323 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7327 MIB.setMemRefs(MMOBegin, MMOEnd);
7330 if (PVT == MVT::i64) {
7331 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7335 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7339 MIB.setMemRefs(MMOBegin, MMOEnd);
7342 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7343 setUsesTOCBasePtr(*MBB->getParent());
7344 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7348 MIB.setMemRefs(MMOBegin, MMOEnd);
7352 BuildMI(*MBB, MI, DL,
7353 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7354 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7356 MI->eraseFromParent();
7361 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7362 MachineBasicBlock *BB) const {
7363 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7364 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7365 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
7366 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7367 // Call lowering should have added an r2 operand to indicate a dependence
7368 // on the TOC base pointer value. It can't however, because there is no
7369 // way to mark the dependence as implicit there, and so the stackmap code
7370 // will confuse it with a regular operand. Instead, add the dependence
7372 setUsesTOCBasePtr(*BB->getParent());
7373 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
7376 return emitPatchPoint(MI, BB);
7379 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7380 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7381 return emitEHSjLjSetJmp(MI, BB);
7382 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7383 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7384 return emitEHSjLjLongJmp(MI, BB);
7387 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7389 // To "insert" these instructions we actually have to insert their
7390 // control-flow patterns.
7391 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7392 MachineFunction::iterator It = BB;
7395 MachineFunction *F = BB->getParent();
7397 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7398 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7399 MI->getOpcode() == PPC::SELECT_I4 ||
7400 MI->getOpcode() == PPC::SELECT_I8)) {
7401 SmallVector<MachineOperand, 2> Cond;
7402 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7403 MI->getOpcode() == PPC::SELECT_CC_I8)
7404 Cond.push_back(MI->getOperand(4));
7406 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7407 Cond.push_back(MI->getOperand(1));
7409 DebugLoc dl = MI->getDebugLoc();
7410 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7411 Cond, MI->getOperand(2).getReg(),
7412 MI->getOperand(3).getReg());
7413 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7414 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7415 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7416 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7417 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7418 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7419 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7420 MI->getOpcode() == PPC::SELECT_I4 ||
7421 MI->getOpcode() == PPC::SELECT_I8 ||
7422 MI->getOpcode() == PPC::SELECT_F4 ||
7423 MI->getOpcode() == PPC::SELECT_F8 ||
7424 MI->getOpcode() == PPC::SELECT_VRRC ||
7425 MI->getOpcode() == PPC::SELECT_VSFRC ||
7426 MI->getOpcode() == PPC::SELECT_VSRC) {
7427 // The incoming instruction knows the destination vreg to set, the
7428 // condition code register to branch on, the true/false values to
7429 // select between, and a branch opcode to use.
7434 // cmpTY ccX, r1, r2
7436 // fallthrough --> copy0MBB
7437 MachineBasicBlock *thisMBB = BB;
7438 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7439 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7440 DebugLoc dl = MI->getDebugLoc();
7441 F->insert(It, copy0MBB);
7442 F->insert(It, sinkMBB);
7444 // Transfer the remainder of BB and its successor edges to sinkMBB.
7445 sinkMBB->splice(sinkMBB->begin(), BB,
7446 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7447 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7449 // Next, add the true and fallthrough blocks as its successors.
7450 BB->addSuccessor(copy0MBB);
7451 BB->addSuccessor(sinkMBB);
7453 if (MI->getOpcode() == PPC::SELECT_I4 ||
7454 MI->getOpcode() == PPC::SELECT_I8 ||
7455 MI->getOpcode() == PPC::SELECT_F4 ||
7456 MI->getOpcode() == PPC::SELECT_F8 ||
7457 MI->getOpcode() == PPC::SELECT_VRRC ||
7458 MI->getOpcode() == PPC::SELECT_VSFRC ||
7459 MI->getOpcode() == PPC::SELECT_VSRC) {
7460 BuildMI(BB, dl, TII->get(PPC::BC))
7461 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7463 unsigned SelectPred = MI->getOperand(4).getImm();
7464 BuildMI(BB, dl, TII->get(PPC::BCC))
7465 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7469 // %FalseValue = ...
7470 // # fallthrough to sinkMBB
7473 // Update machine-CFG edges
7474 BB->addSuccessor(sinkMBB);
7477 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7480 BuildMI(*BB, BB->begin(), dl,
7481 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7482 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7483 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7484 } else if (MI->getOpcode() == PPC::ReadTB) {
7485 // To read the 64-bit time-base register on a 32-bit target, we read the
7486 // two halves. Should the counter have wrapped while it was being read, we
7487 // need to try again.
7490 // mfspr Rx,TBU # load from TBU
7491 // mfspr Ry,TB # load from TB
7492 // mfspr Rz,TBU # load from TBU
7493 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7494 // bne readLoop # branch if they're not equal
7497 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7498 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7499 DebugLoc dl = MI->getDebugLoc();
7500 F->insert(It, readMBB);
7501 F->insert(It, sinkMBB);
7503 // Transfer the remainder of BB and its successor edges to sinkMBB.
7504 sinkMBB->splice(sinkMBB->begin(), BB,
7505 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7506 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7508 BB->addSuccessor(readMBB);
7511 MachineRegisterInfo &RegInfo = F->getRegInfo();
7512 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7513 unsigned LoReg = MI->getOperand(0).getReg();
7514 unsigned HiReg = MI->getOperand(1).getReg();
7516 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7517 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7518 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7520 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7522 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7523 .addReg(HiReg).addReg(ReadAgainReg);
7524 BuildMI(BB, dl, TII->get(PPC::BCC))
7525 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7527 BB->addSuccessor(readMBB);
7528 BB->addSuccessor(sinkMBB);
7530 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7531 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7532 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7533 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7534 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7535 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7536 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7537 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7539 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7540 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7541 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7542 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7543 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7544 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7545 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7546 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7548 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7549 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7550 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7551 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7552 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7553 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7554 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7555 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7557 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7558 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7559 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7560 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7561 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7562 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7563 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7564 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7566 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7567 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7569 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7571 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7573 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7575 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7576 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7577 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7578 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7579 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7580 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7582 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7584 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7585 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7586 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7587 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7588 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7589 BB = EmitAtomicBinary(MI, BB, false, 0);
7590 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7591 BB = EmitAtomicBinary(MI, BB, true, 0);
7593 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7594 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7595 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7597 unsigned dest = MI->getOperand(0).getReg();
7598 unsigned ptrA = MI->getOperand(1).getReg();
7599 unsigned ptrB = MI->getOperand(2).getReg();
7600 unsigned oldval = MI->getOperand(3).getReg();
7601 unsigned newval = MI->getOperand(4).getReg();
7602 DebugLoc dl = MI->getDebugLoc();
7604 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7605 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7606 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7607 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7608 F->insert(It, loop1MBB);
7609 F->insert(It, loop2MBB);
7610 F->insert(It, midMBB);
7611 F->insert(It, exitMBB);
7612 exitMBB->splice(exitMBB->begin(), BB,
7613 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7614 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7618 // fallthrough --> loopMBB
7619 BB->addSuccessor(loop1MBB);
7622 // l[wd]arx dest, ptr
7623 // cmp[wd] dest, oldval
7626 // st[wd]cx. newval, ptr
7630 // st[wd]cx. dest, ptr
7633 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7634 .addReg(ptrA).addReg(ptrB);
7635 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7636 .addReg(oldval).addReg(dest);
7637 BuildMI(BB, dl, TII->get(PPC::BCC))
7638 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7639 BB->addSuccessor(loop2MBB);
7640 BB->addSuccessor(midMBB);
7643 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7644 .addReg(newval).addReg(ptrA).addReg(ptrB);
7645 BuildMI(BB, dl, TII->get(PPC::BCC))
7646 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7647 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7648 BB->addSuccessor(loop1MBB);
7649 BB->addSuccessor(exitMBB);
7652 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7653 .addReg(dest).addReg(ptrA).addReg(ptrB);
7654 BB->addSuccessor(exitMBB);
7659 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7660 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7661 // We must use 64-bit registers for addresses when targeting 64-bit,
7662 // since we're actually doing arithmetic on them. Other registers
7664 bool is64bit = Subtarget.isPPC64();
7665 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7667 unsigned dest = MI->getOperand(0).getReg();
7668 unsigned ptrA = MI->getOperand(1).getReg();
7669 unsigned ptrB = MI->getOperand(2).getReg();
7670 unsigned oldval = MI->getOperand(3).getReg();
7671 unsigned newval = MI->getOperand(4).getReg();
7672 DebugLoc dl = MI->getDebugLoc();
7674 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7675 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7676 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7677 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7678 F->insert(It, loop1MBB);
7679 F->insert(It, loop2MBB);
7680 F->insert(It, midMBB);
7681 F->insert(It, exitMBB);
7682 exitMBB->splice(exitMBB->begin(), BB,
7683 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7684 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7686 MachineRegisterInfo &RegInfo = F->getRegInfo();
7687 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7688 : &PPC::GPRCRegClass;
7689 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7690 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7691 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7692 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7693 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7694 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7695 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7696 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7697 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7698 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7699 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7700 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7701 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7703 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7704 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7707 // fallthrough --> loopMBB
7708 BB->addSuccessor(loop1MBB);
7710 // The 4-byte load must be aligned, while a char or short may be
7711 // anywhere in the word. Hence all this nasty bookkeeping code.
7712 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7713 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7714 // xori shift, shift1, 24 [16]
7715 // rlwinm ptr, ptr1, 0, 0, 29
7716 // slw newval2, newval, shift
7717 // slw oldval2, oldval,shift
7718 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7719 // slw mask, mask2, shift
7720 // and newval3, newval2, mask
7721 // and oldval3, oldval2, mask
7723 // lwarx tmpDest, ptr
7724 // and tmp, tmpDest, mask
7725 // cmpw tmp, oldval3
7728 // andc tmp2, tmpDest, mask
7729 // or tmp4, tmp2, newval3
7734 // stwcx. tmpDest, ptr
7736 // srw dest, tmpDest, shift
7737 if (ptrA != ZeroReg) {
7738 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7739 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7740 .addReg(ptrA).addReg(ptrB);
7744 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7745 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7746 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7747 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7749 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7750 .addReg(Ptr1Reg).addImm(0).addImm(61);
7752 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7753 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7754 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7755 .addReg(newval).addReg(ShiftReg);
7756 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7757 .addReg(oldval).addReg(ShiftReg);
7759 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7761 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7762 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7763 .addReg(Mask3Reg).addImm(65535);
7765 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7766 .addReg(Mask2Reg).addReg(ShiftReg);
7767 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7768 .addReg(NewVal2Reg).addReg(MaskReg);
7769 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7770 .addReg(OldVal2Reg).addReg(MaskReg);
7773 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7774 .addReg(ZeroReg).addReg(PtrReg);
7775 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7776 .addReg(TmpDestReg).addReg(MaskReg);
7777 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7778 .addReg(TmpReg).addReg(OldVal3Reg);
7779 BuildMI(BB, dl, TII->get(PPC::BCC))
7780 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7781 BB->addSuccessor(loop2MBB);
7782 BB->addSuccessor(midMBB);
7785 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7786 .addReg(TmpDestReg).addReg(MaskReg);
7787 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7788 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7789 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7790 .addReg(ZeroReg).addReg(PtrReg);
7791 BuildMI(BB, dl, TII->get(PPC::BCC))
7792 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7793 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7794 BB->addSuccessor(loop1MBB);
7795 BB->addSuccessor(exitMBB);
7798 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7799 .addReg(ZeroReg).addReg(PtrReg);
7800 BB->addSuccessor(exitMBB);
7805 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7807 } else if (MI->getOpcode() == PPC::FADDrtz) {
7808 // This pseudo performs an FADD with rounding mode temporarily forced
7809 // to round-to-zero. We emit this via custom inserter since the FPSCR
7810 // is not modeled at the SelectionDAG level.
7811 unsigned Dest = MI->getOperand(0).getReg();
7812 unsigned Src1 = MI->getOperand(1).getReg();
7813 unsigned Src2 = MI->getOperand(2).getReg();
7814 DebugLoc dl = MI->getDebugLoc();
7816 MachineRegisterInfo &RegInfo = F->getRegInfo();
7817 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7819 // Save FPSCR value.
7820 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7822 // Set rounding mode to round-to-zero.
7823 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7824 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7826 // Perform addition.
7827 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7829 // Restore FPSCR value.
7830 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7831 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7832 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7833 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7834 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7835 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7836 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7837 PPC::ANDIo8 : PPC::ANDIo;
7838 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7839 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7841 MachineRegisterInfo &RegInfo = F->getRegInfo();
7842 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7843 &PPC::GPRCRegClass :
7844 &PPC::G8RCRegClass);
7846 DebugLoc dl = MI->getDebugLoc();
7847 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7848 .addReg(MI->getOperand(1).getReg()).addImm(1);
7849 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7850 MI->getOperand(0).getReg())
7851 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7853 llvm_unreachable("Unexpected instr type to insert");
7856 MI->eraseFromParent(); // The pseudo instruction is gone now.
7860 //===----------------------------------------------------------------------===//
7861 // Target Optimization Hooks
7862 //===----------------------------------------------------------------------===//
7864 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7865 DAGCombinerInfo &DCI,
7866 unsigned &RefinementSteps,
7867 bool &UseOneConstNR) const {
7868 EVT VT = Operand.getValueType();
7869 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7870 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7871 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7872 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7873 // Convergence is quadratic, so we essentially double the number of digits
7874 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7875 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7876 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7877 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7878 if (VT.getScalarType() == MVT::f64)
7880 UseOneConstNR = true;
7881 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7886 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7887 DAGCombinerInfo &DCI,
7888 unsigned &RefinementSteps) const {
7889 EVT VT = Operand.getValueType();
7890 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7891 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7892 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7893 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7894 // Convergence is quadratic, so we essentially double the number of digits
7895 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7896 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7897 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7898 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7899 if (VT.getScalarType() == MVT::f64)
7901 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7906 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7907 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7908 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7909 // enabled for division), this functionality is redundant with the default
7910 // combiner logic (once the division -> reciprocal/multiply transformation
7911 // has taken place). As a result, this matters more for older cores than for
7914 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7915 // reciprocal if there are two or more FDIVs (for embedded cores with only
7916 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7917 switch (Subtarget.getDarwinDirective()) {
7919 return NumUsers > 2;
7922 case PPC::DIR_E500mc:
7923 case PPC::DIR_E5500:
7924 return NumUsers > 1;
7928 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7929 unsigned Bytes, int Dist,
7930 SelectionDAG &DAG) {
7931 if (VT.getSizeInBits() / 8 != Bytes)
7934 SDValue BaseLoc = Base->getBasePtr();
7935 if (Loc.getOpcode() == ISD::FrameIndex) {
7936 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7938 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7939 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7940 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7941 int FS = MFI->getObjectSize(FI);
7942 int BFS = MFI->getObjectSize(BFI);
7943 if (FS != BFS || FS != (int)Bytes) return false;
7944 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7948 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7949 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7953 const GlobalValue *GV1 = nullptr;
7954 const GlobalValue *GV2 = nullptr;
7955 int64_t Offset1 = 0;
7956 int64_t Offset2 = 0;
7957 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7958 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7959 if (isGA1 && isGA2 && GV1 == GV2)
7960 return Offset1 == (Offset2 + Dist*Bytes);
7964 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7965 // not enforce equality of the chain operands.
7966 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7967 unsigned Bytes, int Dist,
7968 SelectionDAG &DAG) {
7969 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7970 EVT VT = LS->getMemoryVT();
7971 SDValue Loc = LS->getBasePtr();
7972 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7975 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7977 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7978 default: return false;
7979 case Intrinsic::ppc_altivec_lvx:
7980 case Intrinsic::ppc_altivec_lvxl:
7981 case Intrinsic::ppc_vsx_lxvw4x:
7984 case Intrinsic::ppc_vsx_lxvd2x:
7987 case Intrinsic::ppc_altivec_lvebx:
7990 case Intrinsic::ppc_altivec_lvehx:
7993 case Intrinsic::ppc_altivec_lvewx:
7998 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
8001 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8003 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8004 default: return false;
8005 case Intrinsic::ppc_altivec_stvx:
8006 case Intrinsic::ppc_altivec_stvxl:
8007 case Intrinsic::ppc_vsx_stxvw4x:
8010 case Intrinsic::ppc_vsx_stxvd2x:
8013 case Intrinsic::ppc_altivec_stvebx:
8016 case Intrinsic::ppc_altivec_stvehx:
8019 case Intrinsic::ppc_altivec_stvewx:
8024 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8030 // Return true is there is a nearyby consecutive load to the one provided
8031 // (regardless of alignment). We search up and down the chain, looking though
8032 // token factors and other loads (but nothing else). As a result, a true result
8033 // indicates that it is safe to create a new consecutive load adjacent to the
8035 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8036 SDValue Chain = LD->getChain();
8037 EVT VT = LD->getMemoryVT();
8039 SmallSet<SDNode *, 16> LoadRoots;
8040 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8041 SmallSet<SDNode *, 16> Visited;
8043 // First, search up the chain, branching to follow all token-factor operands.
8044 // If we find a consecutive load, then we're done, otherwise, record all
8045 // nodes just above the top-level loads and token factors.
8046 while (!Queue.empty()) {
8047 SDNode *ChainNext = Queue.pop_back_val();
8048 if (!Visited.insert(ChainNext).second)
8051 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8052 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8055 if (!Visited.count(ChainLD->getChain().getNode()))
8056 Queue.push_back(ChainLD->getChain().getNode());
8057 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8058 for (const SDUse &O : ChainNext->ops())
8059 if (!Visited.count(O.getNode()))
8060 Queue.push_back(O.getNode());
8062 LoadRoots.insert(ChainNext);
8065 // Second, search down the chain, starting from the top-level nodes recorded
8066 // in the first phase. These top-level nodes are the nodes just above all
8067 // loads and token factors. Starting with their uses, recursively look though
8068 // all loads (just the chain uses) and token factors to find a consecutive
8073 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8074 IE = LoadRoots.end(); I != IE; ++I) {
8075 Queue.push_back(*I);
8077 while (!Queue.empty()) {
8078 SDNode *LoadRoot = Queue.pop_back_val();
8079 if (!Visited.insert(LoadRoot).second)
8082 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8083 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8086 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8087 UE = LoadRoot->use_end(); UI != UE; ++UI)
8088 if (((isa<MemSDNode>(*UI) &&
8089 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8090 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8091 Queue.push_back(*UI);
8098 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8099 DAGCombinerInfo &DCI) const {
8100 SelectionDAG &DAG = DCI.DAG;
8103 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
8104 // If we're tracking CR bits, we need to be careful that we don't have:
8105 // trunc(binary-ops(zext(x), zext(y)))
8107 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8108 // such that we're unnecessarily moving things into GPRs when it would be
8109 // better to keep them in CR bits.
8111 // Note that trunc here can be an actual i1 trunc, or can be the effective
8112 // truncation that comes from a setcc or select_cc.
8113 if (N->getOpcode() == ISD::TRUNCATE &&
8114 N->getValueType(0) != MVT::i1)
8117 if (N->getOperand(0).getValueType() != MVT::i32 &&
8118 N->getOperand(0).getValueType() != MVT::i64)
8121 if (N->getOpcode() == ISD::SETCC ||
8122 N->getOpcode() == ISD::SELECT_CC) {
8123 // If we're looking at a comparison, then we need to make sure that the
8124 // high bits (all except for the first) don't matter the result.
8126 cast<CondCodeSDNode>(N->getOperand(
8127 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8128 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8130 if (ISD::isSignedIntSetCC(CC)) {
8131 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8132 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8134 } else if (ISD::isUnsignedIntSetCC(CC)) {
8135 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8136 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8137 !DAG.MaskedValueIsZero(N->getOperand(1),
8138 APInt::getHighBitsSet(OpBits, OpBits-1)))
8141 // This is neither a signed nor an unsigned comparison, just make sure
8142 // that the high bits are equal.
8143 APInt Op1Zero, Op1One;
8144 APInt Op2Zero, Op2One;
8145 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8146 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8148 // We don't really care about what is known about the first bit (if
8149 // anything), so clear it in all masks prior to comparing them.
8150 Op1Zero.clearBit(0); Op1One.clearBit(0);
8151 Op2Zero.clearBit(0); Op2One.clearBit(0);
8153 if (Op1Zero != Op2Zero || Op1One != Op2One)
8158 // We now know that the higher-order bits are irrelevant, we just need to
8159 // make sure that all of the intermediate operations are bit operations, and
8160 // all inputs are extensions.
8161 if (N->getOperand(0).getOpcode() != ISD::AND &&
8162 N->getOperand(0).getOpcode() != ISD::OR &&
8163 N->getOperand(0).getOpcode() != ISD::XOR &&
8164 N->getOperand(0).getOpcode() != ISD::SELECT &&
8165 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8166 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8167 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8168 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8169 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8172 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8173 N->getOperand(1).getOpcode() != ISD::AND &&
8174 N->getOperand(1).getOpcode() != ISD::OR &&
8175 N->getOperand(1).getOpcode() != ISD::XOR &&
8176 N->getOperand(1).getOpcode() != ISD::SELECT &&
8177 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8178 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8179 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8180 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8181 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8184 SmallVector<SDValue, 4> Inputs;
8185 SmallVector<SDValue, 8> BinOps, PromOps;
8186 SmallPtrSet<SDNode *, 16> Visited;
8188 for (unsigned i = 0; i < 2; ++i) {
8189 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8190 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8191 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8192 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8193 isa<ConstantSDNode>(N->getOperand(i)))
8194 Inputs.push_back(N->getOperand(i));
8196 BinOps.push_back(N->getOperand(i));
8198 if (N->getOpcode() == ISD::TRUNCATE)
8202 // Visit all inputs, collect all binary operations (and, or, xor and
8203 // select) that are all fed by extensions.
8204 while (!BinOps.empty()) {
8205 SDValue BinOp = BinOps.back();
8208 if (!Visited.insert(BinOp.getNode()).second)
8211 PromOps.push_back(BinOp);
8213 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8214 // The condition of the select is not promoted.
8215 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8217 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8220 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8221 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8222 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8223 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8224 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8225 Inputs.push_back(BinOp.getOperand(i));
8226 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8227 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8228 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8229 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8230 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8231 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8232 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8233 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8234 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8235 BinOps.push_back(BinOp.getOperand(i));
8237 // We have an input that is not an extension or another binary
8238 // operation; we'll abort this transformation.
8244 // Make sure that this is a self-contained cluster of operations (which
8245 // is not quite the same thing as saying that everything has only one
8247 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8248 if (isa<ConstantSDNode>(Inputs[i]))
8251 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8252 UE = Inputs[i].getNode()->use_end();
8255 if (User != N && !Visited.count(User))
8258 // Make sure that we're not going to promote the non-output-value
8259 // operand(s) or SELECT or SELECT_CC.
8260 // FIXME: Although we could sometimes handle this, and it does occur in
8261 // practice that one of the condition inputs to the select is also one of
8262 // the outputs, we currently can't deal with this.
8263 if (User->getOpcode() == ISD::SELECT) {
8264 if (User->getOperand(0) == Inputs[i])
8266 } else if (User->getOpcode() == ISD::SELECT_CC) {
8267 if (User->getOperand(0) == Inputs[i] ||
8268 User->getOperand(1) == Inputs[i])
8274 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8275 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8276 UE = PromOps[i].getNode()->use_end();
8279 if (User != N && !Visited.count(User))
8282 // Make sure that we're not going to promote the non-output-value
8283 // operand(s) or SELECT or SELECT_CC.
8284 // FIXME: Although we could sometimes handle this, and it does occur in
8285 // practice that one of the condition inputs to the select is also one of
8286 // the outputs, we currently can't deal with this.
8287 if (User->getOpcode() == ISD::SELECT) {
8288 if (User->getOperand(0) == PromOps[i])
8290 } else if (User->getOpcode() == ISD::SELECT_CC) {
8291 if (User->getOperand(0) == PromOps[i] ||
8292 User->getOperand(1) == PromOps[i])
8298 // Replace all inputs with the extension operand.
8299 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8300 // Constants may have users outside the cluster of to-be-promoted nodes,
8301 // and so we need to replace those as we do the promotions.
8302 if (isa<ConstantSDNode>(Inputs[i]))
8305 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8308 // Replace all operations (these are all the same, but have a different
8309 // (i1) return type). DAG.getNode will validate that the types of
8310 // a binary operator match, so go through the list in reverse so that
8311 // we've likely promoted both operands first. Any intermediate truncations or
8312 // extensions disappear.
8313 while (!PromOps.empty()) {
8314 SDValue PromOp = PromOps.back();
8317 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8318 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8319 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8320 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8321 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8322 PromOp.getOperand(0).getValueType() != MVT::i1) {
8323 // The operand is not yet ready (see comment below).
8324 PromOps.insert(PromOps.begin(), PromOp);
8328 SDValue RepValue = PromOp.getOperand(0);
8329 if (isa<ConstantSDNode>(RepValue))
8330 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8332 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8337 switch (PromOp.getOpcode()) {
8338 default: C = 0; break;
8339 case ISD::SELECT: C = 1; break;
8340 case ISD::SELECT_CC: C = 2; break;
8343 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8344 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8345 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8346 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8347 // The to-be-promoted operands of this node have not yet been
8348 // promoted (this should be rare because we're going through the
8349 // list backward, but if one of the operands has several users in
8350 // this cluster of to-be-promoted nodes, it is possible).
8351 PromOps.insert(PromOps.begin(), PromOp);
8355 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8356 PromOp.getNode()->op_end());
8358 // If there are any constant inputs, make sure they're replaced now.
8359 for (unsigned i = 0; i < 2; ++i)
8360 if (isa<ConstantSDNode>(Ops[C+i]))
8361 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8363 DAG.ReplaceAllUsesOfValueWith(PromOp,
8364 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8367 // Now we're left with the initial truncation itself.
8368 if (N->getOpcode() == ISD::TRUNCATE)
8369 return N->getOperand(0);
8371 // Otherwise, this is a comparison. The operands to be compared have just
8372 // changed type (to i1), but everything else is the same.
8373 return SDValue(N, 0);
8376 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8377 DAGCombinerInfo &DCI) const {
8378 SelectionDAG &DAG = DCI.DAG;
8381 // If we're tracking CR bits, we need to be careful that we don't have:
8382 // zext(binary-ops(trunc(x), trunc(y)))
8384 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8385 // such that we're unnecessarily moving things into CR bits that can more
8386 // efficiently stay in GPRs. Note that if we're not certain that the high
8387 // bits are set as required by the final extension, we still may need to do
8388 // some masking to get the proper behavior.
8390 // This same functionality is important on PPC64 when dealing with
8391 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8392 // the return values of functions. Because it is so similar, it is handled
8395 if (N->getValueType(0) != MVT::i32 &&
8396 N->getValueType(0) != MVT::i64)
8399 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
8400 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
8403 if (N->getOperand(0).getOpcode() != ISD::AND &&
8404 N->getOperand(0).getOpcode() != ISD::OR &&
8405 N->getOperand(0).getOpcode() != ISD::XOR &&
8406 N->getOperand(0).getOpcode() != ISD::SELECT &&
8407 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8410 SmallVector<SDValue, 4> Inputs;
8411 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8412 SmallPtrSet<SDNode *, 16> Visited;
8414 // Visit all inputs, collect all binary operations (and, or, xor and
8415 // select) that are all fed by truncations.
8416 while (!BinOps.empty()) {
8417 SDValue BinOp = BinOps.back();
8420 if (!Visited.insert(BinOp.getNode()).second)
8423 PromOps.push_back(BinOp);
8425 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8426 // The condition of the select is not promoted.
8427 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8429 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8432 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8433 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8434 Inputs.push_back(BinOp.getOperand(i));
8435 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8436 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8437 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8438 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8439 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8440 BinOps.push_back(BinOp.getOperand(i));
8442 // We have an input that is not a truncation or another binary
8443 // operation; we'll abort this transformation.
8449 // The operands of a select that must be truncated when the select is
8450 // promoted because the operand is actually part of the to-be-promoted set.
8451 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8453 // Make sure that this is a self-contained cluster of operations (which
8454 // is not quite the same thing as saying that everything has only one
8456 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8457 if (isa<ConstantSDNode>(Inputs[i]))
8460 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8461 UE = Inputs[i].getNode()->use_end();
8464 if (User != N && !Visited.count(User))
8467 // If we're going to promote the non-output-value operand(s) or SELECT or
8468 // SELECT_CC, record them for truncation.
8469 if (User->getOpcode() == ISD::SELECT) {
8470 if (User->getOperand(0) == Inputs[i])
8471 SelectTruncOp[0].insert(std::make_pair(User,
8472 User->getOperand(0).getValueType()));
8473 } else if (User->getOpcode() == ISD::SELECT_CC) {
8474 if (User->getOperand(0) == Inputs[i])
8475 SelectTruncOp[0].insert(std::make_pair(User,
8476 User->getOperand(0).getValueType()));
8477 if (User->getOperand(1) == Inputs[i])
8478 SelectTruncOp[1].insert(std::make_pair(User,
8479 User->getOperand(1).getValueType()));
8484 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8485 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8486 UE = PromOps[i].getNode()->use_end();
8489 if (User != N && !Visited.count(User))
8492 // If we're going to promote the non-output-value operand(s) or SELECT or
8493 // SELECT_CC, record them for truncation.
8494 if (User->getOpcode() == ISD::SELECT) {
8495 if (User->getOperand(0) == PromOps[i])
8496 SelectTruncOp[0].insert(std::make_pair(User,
8497 User->getOperand(0).getValueType()));
8498 } else if (User->getOpcode() == ISD::SELECT_CC) {
8499 if (User->getOperand(0) == PromOps[i])
8500 SelectTruncOp[0].insert(std::make_pair(User,
8501 User->getOperand(0).getValueType()));
8502 if (User->getOperand(1) == PromOps[i])
8503 SelectTruncOp[1].insert(std::make_pair(User,
8504 User->getOperand(1).getValueType()));
8509 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8510 bool ReallyNeedsExt = false;
8511 if (N->getOpcode() != ISD::ANY_EXTEND) {
8512 // If all of the inputs are not already sign/zero extended, then
8513 // we'll still need to do that at the end.
8514 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8515 if (isa<ConstantSDNode>(Inputs[i]))
8519 Inputs[i].getOperand(0).getValueSizeInBits();
8520 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8522 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8523 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8524 APInt::getHighBitsSet(OpBits,
8525 OpBits-PromBits))) ||
8526 (N->getOpcode() == ISD::SIGN_EXTEND &&
8527 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8528 (OpBits-(PromBits-1)))) {
8529 ReallyNeedsExt = true;
8535 // Replace all inputs, either with the truncation operand, or a
8536 // truncation or extension to the final output type.
8537 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8538 // Constant inputs need to be replaced with the to-be-promoted nodes that
8539 // use them because they might have users outside of the cluster of
8541 if (isa<ConstantSDNode>(Inputs[i]))
8544 SDValue InSrc = Inputs[i].getOperand(0);
8545 if (Inputs[i].getValueType() == N->getValueType(0))
8546 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8547 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8548 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8549 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8550 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8551 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8552 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8554 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8555 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8558 // Replace all operations (these are all the same, but have a different
8559 // (promoted) return type). DAG.getNode will validate that the types of
8560 // a binary operator match, so go through the list in reverse so that
8561 // we've likely promoted both operands first.
8562 while (!PromOps.empty()) {
8563 SDValue PromOp = PromOps.back();
8567 switch (PromOp.getOpcode()) {
8568 default: C = 0; break;
8569 case ISD::SELECT: C = 1; break;
8570 case ISD::SELECT_CC: C = 2; break;
8573 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8574 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8575 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8576 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8577 // The to-be-promoted operands of this node have not yet been
8578 // promoted (this should be rare because we're going through the
8579 // list backward, but if one of the operands has several users in
8580 // this cluster of to-be-promoted nodes, it is possible).
8581 PromOps.insert(PromOps.begin(), PromOp);
8585 // For SELECT and SELECT_CC nodes, we do a similar check for any
8586 // to-be-promoted comparison inputs.
8587 if (PromOp.getOpcode() == ISD::SELECT ||
8588 PromOp.getOpcode() == ISD::SELECT_CC) {
8589 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8590 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8591 (SelectTruncOp[1].count(PromOp.getNode()) &&
8592 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8593 PromOps.insert(PromOps.begin(), PromOp);
8598 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8599 PromOp.getNode()->op_end());
8601 // If this node has constant inputs, then they'll need to be promoted here.
8602 for (unsigned i = 0; i < 2; ++i) {
8603 if (!isa<ConstantSDNode>(Ops[C+i]))
8605 if (Ops[C+i].getValueType() == N->getValueType(0))
8608 if (N->getOpcode() == ISD::SIGN_EXTEND)
8609 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8610 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8611 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8613 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8616 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8617 // truncate them again to the original value type.
8618 if (PromOp.getOpcode() == ISD::SELECT ||
8619 PromOp.getOpcode() == ISD::SELECT_CC) {
8620 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8621 if (SI0 != SelectTruncOp[0].end())
8622 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8623 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8624 if (SI1 != SelectTruncOp[1].end())
8625 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8628 DAG.ReplaceAllUsesOfValueWith(PromOp,
8629 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8632 // Now we're left with the initial extension itself.
8633 if (!ReallyNeedsExt)
8634 return N->getOperand(0);
8636 // To zero extend, just mask off everything except for the first bit (in the
8638 if (N->getOpcode() == ISD::ZERO_EXTEND)
8639 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8640 DAG.getConstant(APInt::getLowBitsSet(
8641 N->getValueSizeInBits(0), PromBits),
8642 N->getValueType(0)));
8644 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8645 "Invalid extension type");
8646 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8648 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8649 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8650 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8651 N->getOperand(0), ShiftCst), ShiftCst);
8654 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8655 DAGCombinerInfo &DCI) const {
8656 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8657 N->getOpcode() == ISD::UINT_TO_FP) &&
8658 "Need an int -> FP conversion node here");
8660 if (!Subtarget.has64BitSupport())
8663 SelectionDAG &DAG = DCI.DAG;
8667 // Don't handle ppc_fp128 here or i1 conversions.
8668 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8670 if (Op.getOperand(0).getValueType() == MVT::i1)
8673 // For i32 intermediate values, unfortunately, the conversion functions
8674 // leave the upper 32 bits of the value are undefined. Within the set of
8675 // scalar instructions, we have no method for zero- or sign-extending the
8676 // value. Thus, we cannot handle i32 intermediate values here.
8677 if (Op.getOperand(0).getValueType() == MVT::i32)
8680 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8681 "UINT_TO_FP is supported only with FPCVT");
8683 // If we have FCFIDS, then use it when converting to single-precision.
8684 // Otherwise, convert to double-precision and then round.
8685 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8686 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
8688 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
8690 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8694 // If we're converting from a float, to an int, and back to a float again,
8695 // then we don't need the store/load pair at all.
8696 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8697 Subtarget.hasFPCVT()) ||
8698 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8699 SDValue Src = Op.getOperand(0).getOperand(0);
8700 if (Src.getValueType() == MVT::f32) {
8701 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8702 DCI.AddToWorklist(Src.getNode());
8706 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8709 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8710 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8712 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8713 FP = DAG.getNode(ISD::FP_ROUND, dl,
8714 MVT::f32, FP, DAG.getIntPtrConstant(0));
8715 DCI.AddToWorklist(FP.getNode());
8724 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8725 // builtins) into loads with swaps.
8726 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8727 DAGCombinerInfo &DCI) const {
8728 SelectionDAG &DAG = DCI.DAG;
8732 MachineMemOperand *MMO;
8734 switch (N->getOpcode()) {
8736 llvm_unreachable("Unexpected opcode for little endian VSX load");
8738 LoadSDNode *LD = cast<LoadSDNode>(N);
8739 Chain = LD->getChain();
8740 Base = LD->getBasePtr();
8741 MMO = LD->getMemOperand();
8742 // If the MMO suggests this isn't a load of a full vector, leave
8743 // things alone. For a built-in, we have to make the change for
8744 // correctness, so if there is a size problem that will be a bug.
8745 if (MMO->getSize() < 16)
8749 case ISD::INTRINSIC_W_CHAIN: {
8750 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8751 Chain = Intrin->getChain();
8752 Base = Intrin->getBasePtr();
8753 MMO = Intrin->getMemOperand();
8758 MVT VecTy = N->getValueType(0).getSimpleVT();
8759 SDValue LoadOps[] = { Chain, Base };
8760 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8761 DAG.getVTList(VecTy, MVT::Other),
8762 LoadOps, VecTy, MMO);
8763 DCI.AddToWorklist(Load.getNode());
8764 Chain = Load.getValue(1);
8765 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8766 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8767 DCI.AddToWorklist(Swap.getNode());
8771 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8772 // builtins) into stores with swaps.
8773 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8774 DAGCombinerInfo &DCI) const {
8775 SelectionDAG &DAG = DCI.DAG;
8780 MachineMemOperand *MMO;
8782 switch (N->getOpcode()) {
8784 llvm_unreachable("Unexpected opcode for little endian VSX store");
8786 StoreSDNode *ST = cast<StoreSDNode>(N);
8787 Chain = ST->getChain();
8788 Base = ST->getBasePtr();
8789 MMO = ST->getMemOperand();
8791 // If the MMO suggests this isn't a store of a full vector, leave
8792 // things alone. For a built-in, we have to make the change for
8793 // correctness, so if there is a size problem that will be a bug.
8794 if (MMO->getSize() < 16)
8798 case ISD::INTRINSIC_VOID: {
8799 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8800 Chain = Intrin->getChain();
8801 // Intrin->getBasePtr() oddly does not get what we want.
8802 Base = Intrin->getOperand(3);
8803 MMO = Intrin->getMemOperand();
8809 SDValue Src = N->getOperand(SrcOpnd);
8810 MVT VecTy = Src.getValueType().getSimpleVT();
8811 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8812 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8813 DCI.AddToWorklist(Swap.getNode());
8814 Chain = Swap.getValue(1);
8815 SDValue StoreOps[] = { Chain, Swap, Base };
8816 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8817 DAG.getVTList(MVT::Other),
8818 StoreOps, VecTy, MMO);
8819 DCI.AddToWorklist(Store.getNode());
8823 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8824 DAGCombinerInfo &DCI) const {
8825 SelectionDAG &DAG = DCI.DAG;
8827 switch (N->getOpcode()) {
8830 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8831 if (C->isNullValue()) // 0 << V -> 0.
8832 return N->getOperand(0);
8836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8837 if (C->isNullValue()) // 0 >>u V -> 0.
8838 return N->getOperand(0);
8842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8843 if (C->isNullValue() || // 0 >>s V -> 0.
8844 C->isAllOnesValue()) // -1 >>s V -> -1.
8845 return N->getOperand(0);
8848 case ISD::SIGN_EXTEND:
8849 case ISD::ZERO_EXTEND:
8850 case ISD::ANY_EXTEND:
8851 return DAGCombineExtBoolTrunc(N, DCI);
8854 case ISD::SELECT_CC:
8855 return DAGCombineTruncBoolExt(N, DCI);
8856 case ISD::SINT_TO_FP:
8857 case ISD::UINT_TO_FP:
8858 return combineFPToIntToFP(N, DCI);
8860 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8861 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
8862 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8863 N->getOperand(1).getValueType() == MVT::i32 &&
8864 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8865 SDValue Val = N->getOperand(1).getOperand(0);
8866 if (Val.getValueType() == MVT::f32) {
8867 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8868 DCI.AddToWorklist(Val.getNode());
8870 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8871 DCI.AddToWorklist(Val.getNode());
8874 N->getOperand(0), Val, N->getOperand(2),
8875 DAG.getValueType(N->getOperand(1).getValueType())
8878 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8879 DAG.getVTList(MVT::Other), Ops,
8880 cast<StoreSDNode>(N)->getMemoryVT(),
8881 cast<StoreSDNode>(N)->getMemOperand());
8882 DCI.AddToWorklist(Val.getNode());
8886 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8887 if (cast<StoreSDNode>(N)->isUnindexed() &&
8888 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8889 N->getOperand(1).getNode()->hasOneUse() &&
8890 (N->getOperand(1).getValueType() == MVT::i32 ||
8891 N->getOperand(1).getValueType() == MVT::i16 ||
8892 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
8893 N->getOperand(1).getValueType() == MVT::i64))) {
8894 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8895 // Do an any-extend to 32-bits if this is a half-word input.
8896 if (BSwapOp.getValueType() == MVT::i16)
8897 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8900 N->getOperand(0), BSwapOp, N->getOperand(2),
8901 DAG.getValueType(N->getOperand(1).getValueType())
8904 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8905 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8906 cast<StoreSDNode>(N)->getMemOperand());
8909 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8910 EVT VT = N->getOperand(1).getValueType();
8911 if (VT.isSimple()) {
8912 MVT StoreVT = VT.getSimpleVT();
8913 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8914 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8915 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8916 return expandVSXStoreForLE(N, DCI);
8921 LoadSDNode *LD = cast<LoadSDNode>(N);
8922 EVT VT = LD->getValueType(0);
8924 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8925 if (VT.isSimple()) {
8926 MVT LoadVT = VT.getSimpleVT();
8927 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8928 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8929 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8930 return expandVSXLoadForLE(N, DCI);
8933 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8934 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8935 if (ISD::isNON_EXTLoad(N) && VT.isVector() && Subtarget.hasAltivec() &&
8936 // P8 and later hardware should just use LOAD.
8937 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8938 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8939 LD->getAlignment() < ABIAlignment) {
8940 // This is a type-legal unaligned Altivec load.
8941 SDValue Chain = LD->getChain();
8942 SDValue Ptr = LD->getBasePtr();
8943 bool isLittleEndian = Subtarget.isLittleEndian();
8945 // This implements the loading of unaligned vectors as described in
8946 // the venerable Apple Velocity Engine overview. Specifically:
8947 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8948 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8950 // The general idea is to expand a sequence of one or more unaligned
8951 // loads into an alignment-based permutation-control instruction (lvsl
8952 // or lvsr), a series of regular vector loads (which always truncate
8953 // their input address to an aligned address), and a series of
8954 // permutations. The results of these permutations are the requested
8955 // loaded values. The trick is that the last "extra" load is not taken
8956 // from the address you might suspect (sizeof(vector) bytes after the
8957 // last requested load), but rather sizeof(vector) - 1 bytes after the
8958 // last requested vector. The point of this is to avoid a page fault if
8959 // the base address happened to be aligned. This works because if the
8960 // base address is aligned, then adding less than a full vector length
8961 // will cause the last vector in the sequence to be (re)loaded.
8962 // Otherwise, the next vector will be fetched as you might suspect was
8965 // We might be able to reuse the permutation generation from
8966 // a different base address offset from this one by an aligned amount.
8967 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8968 // optimization later.
8969 Intrinsic::ID Intr = (isLittleEndian ?
8970 Intrinsic::ppc_altivec_lvsr :
8971 Intrinsic::ppc_altivec_lvsl);
8972 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8974 // Create the new MMO for the new base load. It is like the original MMO,
8975 // but represents an area in memory almost twice the vector size centered
8976 // on the original address. If the address is unaligned, we might start
8977 // reading up to (sizeof(vector)-1) bytes below the address of the
8978 // original unaligned load.
8979 MachineFunction &MF = DAG.getMachineFunction();
8980 MachineMemOperand *BaseMMO =
8981 MF.getMachineMemOperand(LD->getMemOperand(),
8982 -LD->getMemoryVT().getStoreSize()+1,
8983 2*LD->getMemoryVT().getStoreSize()-1);
8985 // Create the new base load.
8986 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8988 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8990 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8991 DAG.getVTList(MVT::v4i32, MVT::Other),
8992 BaseLoadOps, MVT::v4i32, BaseMMO);
8994 // Note that the value of IncOffset (which is provided to the next
8995 // load's pointer info offset value, and thus used to calculate the
8996 // alignment), and the value of IncValue (which is actually used to
8997 // increment the pointer value) are different! This is because we
8998 // require the next load to appear to be aligned, even though it
8999 // is actually offset from the base pointer by a lesser amount.
9000 int IncOffset = VT.getSizeInBits() / 8;
9001 int IncValue = IncOffset;
9003 // Walk (both up and down) the chain looking for another load at the real
9004 // (aligned) offset (the alignment of the other load does not matter in
9005 // this case). If found, then do not use the offset reduction trick, as
9006 // that will prevent the loads from being later combined (as they would
9007 // otherwise be duplicates).
9008 if (!findConsecutiveLoad(LD, DAG))
9011 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9012 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9014 MachineMemOperand *ExtraMMO =
9015 MF.getMachineMemOperand(LD->getMemOperand(),
9016 1, 2*LD->getMemoryVT().getStoreSize()-1);
9017 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9019 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9020 DAG.getVTList(MVT::v4i32, MVT::Other),
9021 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9023 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9024 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9026 // Because vperm has a big-endian bias, we must reverse the order
9027 // of the input vectors and complement the permute control vector
9028 // when generating little endian code. We have already handled the
9029 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9030 // and ExtraLoad here.
9033 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9034 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9036 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9037 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9039 if (VT != MVT::v4i32)
9040 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9042 // The output of the permutation is our loaded result, the TokenFactor is
9044 DCI.CombineTo(N, Perm, TF);
9045 return SDValue(N, 0);
9049 case ISD::INTRINSIC_WO_CHAIN: {
9050 bool isLittleEndian = Subtarget.isLittleEndian();
9051 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
9052 : Intrinsic::ppc_altivec_lvsl);
9053 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9054 N->getOperand(1)->getOpcode() == ISD::ADD) {
9055 SDValue Add = N->getOperand(1);
9057 if (DAG.MaskedValueIsZero(
9059 APInt::getAllOnesValue(4 /* 16 byte alignment */)
9061 Add.getValueType().getScalarType().getSizeInBits()))) {
9062 SDNode *BasePtr = Add->getOperand(0).getNode();
9063 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9064 UE = BasePtr->use_end();
9066 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9067 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9069 // We've found another LVSL/LVSR, and this address is an aligned
9070 // multiple of that one. The results will be the same, so use the
9071 // one we've just found instead.
9073 return SDValue(*UI, 0);
9081 case ISD::INTRINSIC_W_CHAIN: {
9082 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9083 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9084 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9087 case Intrinsic::ppc_vsx_lxvw4x:
9088 case Intrinsic::ppc_vsx_lxvd2x:
9089 return expandVSXLoadForLE(N, DCI);
9094 case ISD::INTRINSIC_VOID: {
9095 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9096 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9097 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9100 case Intrinsic::ppc_vsx_stxvw4x:
9101 case Intrinsic::ppc_vsx_stxvd2x:
9102 return expandVSXStoreForLE(N, DCI);
9108 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9109 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9110 N->getOperand(0).hasOneUse() &&
9111 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9112 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9113 N->getValueType(0) == MVT::i64))) {
9114 SDValue Load = N->getOperand(0);
9115 LoadSDNode *LD = cast<LoadSDNode>(Load);
9116 // Create the byte-swapping load.
9118 LD->getChain(), // Chain
9119 LD->getBasePtr(), // Ptr
9120 DAG.getValueType(N->getValueType(0)) // VT
9123 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9124 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9125 MVT::i64 : MVT::i32, MVT::Other),
9126 Ops, LD->getMemoryVT(), LD->getMemOperand());
9128 // If this is an i16 load, insert the truncate.
9129 SDValue ResVal = BSLoad;
9130 if (N->getValueType(0) == MVT::i16)
9131 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9133 // First, combine the bswap away. This makes the value produced by the
9135 DCI.CombineTo(N, ResVal);
9137 // Next, combine the load away, we give it a bogus result value but a real
9138 // chain result. The result value is dead because the bswap is dead.
9139 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9141 // Return N so it doesn't get rechecked!
9142 return SDValue(N, 0);
9146 case PPCISD::VCMP: {
9147 // If a VCMPo node already exists with exactly the same operands as this
9148 // node, use its result instead of this node (VCMPo computes both a CR6 and
9149 // a normal output).
9151 if (!N->getOperand(0).hasOneUse() &&
9152 !N->getOperand(1).hasOneUse() &&
9153 !N->getOperand(2).hasOneUse()) {
9155 // Scan all of the users of the LHS, looking for VCMPo's that match.
9156 SDNode *VCMPoNode = nullptr;
9158 SDNode *LHSN = N->getOperand(0).getNode();
9159 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9161 if (UI->getOpcode() == PPCISD::VCMPo &&
9162 UI->getOperand(1) == N->getOperand(1) &&
9163 UI->getOperand(2) == N->getOperand(2) &&
9164 UI->getOperand(0) == N->getOperand(0)) {
9169 // If there is no VCMPo node, or if the flag value has a single use, don't
9171 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9174 // Look at the (necessarily single) use of the flag value. If it has a
9175 // chain, this transformation is more complex. Note that multiple things
9176 // could use the value result, which we should ignore.
9177 SDNode *FlagUser = nullptr;
9178 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9179 FlagUser == nullptr; ++UI) {
9180 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9182 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9183 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9190 // If the user is a MFOCRF instruction, we know this is safe.
9191 // Otherwise we give up for right now.
9192 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9193 return SDValue(VCMPoNode, 0);
9198 SDValue Cond = N->getOperand(1);
9199 SDValue Target = N->getOperand(2);
9201 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9202 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9203 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9205 // We now need to make the intrinsic dead (it cannot be instruction
9207 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9208 assert(Cond.getNode()->hasOneUse() &&
9209 "Counter decrement has more than one use");
9211 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9212 N->getOperand(0), Target);
9217 // If this is a branch on an altivec predicate comparison, lower this so
9218 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9219 // lowering is done pre-legalize, because the legalizer lowers the predicate
9220 // compare down to code that is difficult to reassemble.
9221 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9222 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9224 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9225 // value. If so, pass-through the AND to get to the intrinsic.
9226 if (LHS.getOpcode() == ISD::AND &&
9227 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9228 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9229 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9230 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9231 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9233 LHS = LHS.getOperand(0);
9235 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9236 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9237 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9238 isa<ConstantSDNode>(RHS)) {
9239 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9240 "Counter decrement comparison is not EQ or NE");
9242 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9243 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9244 (CC == ISD::SETNE && !Val);
9246 // We now need to make the intrinsic dead (it cannot be instruction
9248 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9249 assert(LHS.getNode()->hasOneUse() &&
9250 "Counter decrement has more than one use");
9252 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9253 N->getOperand(0), N->getOperand(4));
9259 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9260 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9261 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9262 assert(isDot && "Can't compare against a vector result!");
9264 // If this is a comparison against something other than 0/1, then we know
9265 // that the condition is never/always true.
9266 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9267 if (Val != 0 && Val != 1) {
9268 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9269 return N->getOperand(0);
9270 // Always !=, turn it into an unconditional branch.
9271 return DAG.getNode(ISD::BR, dl, MVT::Other,
9272 N->getOperand(0), N->getOperand(4));
9275 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9277 // Create the PPCISD altivec 'dot' comparison node.
9279 LHS.getOperand(2), // LHS of compare
9280 LHS.getOperand(3), // RHS of compare
9281 DAG.getConstant(CompareOpc, MVT::i32)
9283 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9284 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9286 // Unpack the result based on how the target uses it.
9287 PPC::Predicate CompOpc;
9288 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9289 default: // Can't happen, don't crash on invalid number though.
9290 case 0: // Branch on the value of the EQ bit of CR6.
9291 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9293 case 1: // Branch on the inverted value of the EQ bit of CR6.
9294 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9296 case 2: // Branch on the value of the LT bit of CR6.
9297 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9299 case 3: // Branch on the inverted value of the LT bit of CR6.
9300 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9304 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9305 DAG.getConstant(CompOpc, MVT::i32),
9306 DAG.getRegister(PPC::CR6, MVT::i32),
9307 N->getOperand(4), CompNode.getValue(1));
9317 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9319 std::vector<SDNode *> *Created) const {
9320 // fold (sdiv X, pow2)
9321 EVT VT = N->getValueType(0);
9322 if (VT == MVT::i64 && !Subtarget.isPPC64())
9324 if ((VT != MVT::i32 && VT != MVT::i64) ||
9325 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9329 SDValue N0 = N->getOperand(0);
9331 bool IsNegPow2 = (-Divisor).isPowerOf2();
9332 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9333 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9335 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9337 Created->push_back(Op.getNode());
9340 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9342 Created->push_back(Op.getNode());
9348 //===----------------------------------------------------------------------===//
9349 // Inline Assembly Support
9350 //===----------------------------------------------------------------------===//
9352 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9355 const SelectionDAG &DAG,
9356 unsigned Depth) const {
9357 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9358 switch (Op.getOpcode()) {
9360 case PPCISD::LBRX: {
9361 // lhbrx is known to have the top bits cleared out.
9362 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9363 KnownZero = 0xFFFF0000;
9366 case ISD::INTRINSIC_WO_CHAIN: {
9367 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9369 case Intrinsic::ppc_altivec_vcmpbfp_p:
9370 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9371 case Intrinsic::ppc_altivec_vcmpequb_p:
9372 case Intrinsic::ppc_altivec_vcmpequh_p:
9373 case Intrinsic::ppc_altivec_vcmpequw_p:
9374 case Intrinsic::ppc_altivec_vcmpgefp_p:
9375 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9376 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9377 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9378 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9379 case Intrinsic::ppc_altivec_vcmpgtub_p:
9380 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9381 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9382 KnownZero = ~1U; // All bits but the low one are known to be zero.
9389 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9390 switch (Subtarget.getDarwinDirective()) {
9395 case PPC::DIR_PWR5X:
9397 case PPC::DIR_PWR6X:
9399 case PPC::DIR_PWR8: {
9403 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
9405 // For small loops (between 5 and 8 instructions), align to a 32-byte
9406 // boundary so that the entire loop fits in one instruction-cache line.
9407 uint64_t LoopSize = 0;
9408 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9409 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9410 LoopSize += TII->GetInstSizeInBytes(J);
9412 if (LoopSize > 16 && LoopSize <= 32)
9419 return TargetLowering::getPrefLoopAlignment(ML);
9422 /// getConstraintType - Given a constraint, return the type of
9423 /// constraint it is for this target.
9424 PPCTargetLowering::ConstraintType
9425 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9426 if (Constraint.size() == 1) {
9427 switch (Constraint[0]) {
9434 return C_RegisterClass;
9436 // FIXME: While Z does indicate a memory constraint, it specifically
9437 // indicates an r+r address (used in conjunction with the 'y' modifier
9438 // in the replacement string). Currently, we're forcing the base
9439 // register to be r0 in the asm printer (which is interpreted as zero)
9440 // and forming the complete address in the second register. This is
9444 } else if (Constraint == "wc") { // individual CR bits.
9445 return C_RegisterClass;
9446 } else if (Constraint == "wa" || Constraint == "wd" ||
9447 Constraint == "wf" || Constraint == "ws") {
9448 return C_RegisterClass; // VSX registers.
9450 return TargetLowering::getConstraintType(Constraint);
9453 /// Examine constraint type and operand type and determine a weight value.
9454 /// This object must already have been set up with the operand type
9455 /// and the current alternative constraint selected.
9456 TargetLowering::ConstraintWeight
9457 PPCTargetLowering::getSingleConstraintMatchWeight(
9458 AsmOperandInfo &info, const char *constraint) const {
9459 ConstraintWeight weight = CW_Invalid;
9460 Value *CallOperandVal = info.CallOperandVal;
9461 // If we don't have a value, we can't do a match,
9462 // but allow it at the lowest weight.
9463 if (!CallOperandVal)
9465 Type *type = CallOperandVal->getType();
9467 // Look at the constraint type.
9468 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9469 return CW_Register; // an individual CR bit.
9470 else if ((StringRef(constraint) == "wa" ||
9471 StringRef(constraint) == "wd" ||
9472 StringRef(constraint) == "wf") &&
9475 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9478 switch (*constraint) {
9480 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9483 if (type->isIntegerTy())
9484 weight = CW_Register;
9487 if (type->isFloatTy())
9488 weight = CW_Register;
9491 if (type->isDoubleTy())
9492 weight = CW_Register;
9495 if (type->isVectorTy())
9496 weight = CW_Register;
9499 weight = CW_Register;
9508 std::pair<unsigned, const TargetRegisterClass*>
9509 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9511 if (Constraint.size() == 1) {
9512 // GCC RS6000 Constraint Letters
9513 switch (Constraint[0]) {
9515 if (VT == MVT::i64 && Subtarget.isPPC64())
9516 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9517 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9519 if (VT == MVT::i64 && Subtarget.isPPC64())
9520 return std::make_pair(0U, &PPC::G8RCRegClass);
9521 return std::make_pair(0U, &PPC::GPRCRegClass);
9523 if (VT == MVT::f32 || VT == MVT::i32)
9524 return std::make_pair(0U, &PPC::F4RCRegClass);
9525 if (VT == MVT::f64 || VT == MVT::i64)
9526 return std::make_pair(0U, &PPC::F8RCRegClass);
9529 return std::make_pair(0U, &PPC::VRRCRegClass);
9531 return std::make_pair(0U, &PPC::CRRCRegClass);
9533 } else if (Constraint == "wc") { // an individual CR bit.
9534 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9535 } else if (Constraint == "wa" || Constraint == "wd" ||
9536 Constraint == "wf") {
9537 return std::make_pair(0U, &PPC::VSRCRegClass);
9538 } else if (Constraint == "ws") {
9539 return std::make_pair(0U, &PPC::VSFRCRegClass);
9542 std::pair<unsigned, const TargetRegisterClass*> R =
9543 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9545 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9546 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9547 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9549 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9550 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9551 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9552 PPC::GPRCRegClass.contains(R.first)) {
9553 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
9554 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9555 PPC::sub_32, &PPC::G8RCRegClass),
9556 &PPC::G8RCRegClass);
9559 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9560 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9562 R.second = &PPC::CRRCRegClass;
9569 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9570 /// vector. If it is invalid, don't add anything to Ops.
9571 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9572 std::string &Constraint,
9573 std::vector<SDValue>&Ops,
9574 SelectionDAG &DAG) const {
9577 // Only support length 1 constraints.
9578 if (Constraint.length() > 1) return;
9580 char Letter = Constraint[0];
9591 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9592 if (!CST) return; // Must be an immediate to match.
9593 int64_t Value = CST->getSExtValue();
9594 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9595 // numbers are printed as such.
9597 default: llvm_unreachable("Unknown constraint letter!");
9598 case 'I': // "I" is a signed 16-bit constant.
9599 if (isInt<16>(Value))
9600 Result = DAG.getTargetConstant(Value, TCVT);
9602 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9603 if (isShiftedUInt<16, 16>(Value))
9604 Result = DAG.getTargetConstant(Value, TCVT);
9606 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9607 if (isShiftedInt<16, 16>(Value))
9608 Result = DAG.getTargetConstant(Value, TCVT);
9610 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9611 if (isUInt<16>(Value))
9612 Result = DAG.getTargetConstant(Value, TCVT);
9614 case 'M': // "M" is a constant that is greater than 31.
9616 Result = DAG.getTargetConstant(Value, TCVT);
9618 case 'N': // "N" is a positive constant that is an exact power of two.
9619 if (Value > 0 && isPowerOf2_64(Value))
9620 Result = DAG.getTargetConstant(Value, TCVT);
9622 case 'O': // "O" is the constant zero.
9624 Result = DAG.getTargetConstant(Value, TCVT);
9626 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9627 if (isInt<16>(-Value))
9628 Result = DAG.getTargetConstant(Value, TCVT);
9635 if (Result.getNode()) {
9636 Ops.push_back(Result);
9640 // Handle standard constraint letters.
9641 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9644 // isLegalAddressingMode - Return true if the addressing mode represented
9645 // by AM is legal for this target, for a load/store of the specified type.
9646 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9648 // FIXME: PPC does not allow r+i addressing modes for vectors!
9650 // PPC allows a sign-extended 16-bit immediate field.
9651 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9654 // No global is ever allowed as a base.
9658 // PPC only support r+r,
9660 case 0: // "r+i" or just "i", depending on HasBaseReg.
9663 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9665 // Otherwise we have r+r or r+i.
9668 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9670 // Allow 2*r as r+r.
9673 // No other scales are supported.
9680 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9681 SelectionDAG &DAG) const {
9682 MachineFunction &MF = DAG.getMachineFunction();
9683 MachineFrameInfo *MFI = MF.getFrameInfo();
9684 MFI->setReturnAddressIsTaken(true);
9686 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9690 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9692 // Make sure the function does not optimize away the store of the RA to
9694 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9695 FuncInfo->setLRStoreRequired();
9696 bool isPPC64 = Subtarget.isPPC64();
9699 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9701 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(),
9702 isPPC64 ? MVT::i64 : MVT::i32);
9703 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9704 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9706 MachinePointerInfo(), false, false, false, 0);
9709 // Just load the return address off the stack.
9710 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9711 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9712 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9715 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9716 SelectionDAG &DAG) const {
9718 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9720 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9721 bool isPPC64 = PtrVT == MVT::i64;
9723 MachineFunction &MF = DAG.getMachineFunction();
9724 MachineFrameInfo *MFI = MF.getFrameInfo();
9725 MFI->setFrameAddressIsTaken(true);
9727 // Naked functions never have a frame pointer, and so we use r1. For all
9728 // other functions, this decision must be delayed until during PEI.
9730 if (MF.getFunction()->getAttributes().hasAttribute(
9731 AttributeSet::FunctionIndex, Attribute::Naked))
9732 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9734 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9736 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9739 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9740 FrameAddr, MachinePointerInfo(), false, false,
9745 // FIXME? Maybe this could be a TableGen attribute on some registers and
9746 // this table could be generated automatically from RegInfo.
9747 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9749 bool isPPC64 = Subtarget.isPPC64();
9750 bool isDarwinABI = Subtarget.isDarwinABI();
9752 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9753 (!isPPC64 && VT != MVT::i32))
9754 report_fatal_error("Invalid register global variable type");
9756 bool is64Bit = isPPC64 && VT == MVT::i64;
9757 unsigned Reg = StringSwitch<unsigned>(RegName)
9758 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9759 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
9760 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9761 (is64Bit ? PPC::X13 : PPC::R13))
9766 report_fatal_error("Invalid register name global variable");
9770 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9771 // The PowerPC target isn't yet aware of offsets.
9775 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9777 unsigned Intrinsic) const {
9779 switch (Intrinsic) {
9780 case Intrinsic::ppc_altivec_lvx:
9781 case Intrinsic::ppc_altivec_lvxl:
9782 case Intrinsic::ppc_altivec_lvebx:
9783 case Intrinsic::ppc_altivec_lvehx:
9784 case Intrinsic::ppc_altivec_lvewx:
9785 case Intrinsic::ppc_vsx_lxvd2x:
9786 case Intrinsic::ppc_vsx_lxvw4x: {
9788 switch (Intrinsic) {
9789 case Intrinsic::ppc_altivec_lvebx:
9792 case Intrinsic::ppc_altivec_lvehx:
9795 case Intrinsic::ppc_altivec_lvewx:
9798 case Intrinsic::ppc_vsx_lxvd2x:
9806 Info.opc = ISD::INTRINSIC_W_CHAIN;
9808 Info.ptrVal = I.getArgOperand(0);
9809 Info.offset = -VT.getStoreSize()+1;
9810 Info.size = 2*VT.getStoreSize()-1;
9813 Info.readMem = true;
9814 Info.writeMem = false;
9817 case Intrinsic::ppc_altivec_stvx:
9818 case Intrinsic::ppc_altivec_stvxl:
9819 case Intrinsic::ppc_altivec_stvebx:
9820 case Intrinsic::ppc_altivec_stvehx:
9821 case Intrinsic::ppc_altivec_stvewx:
9822 case Intrinsic::ppc_vsx_stxvd2x:
9823 case Intrinsic::ppc_vsx_stxvw4x: {
9825 switch (Intrinsic) {
9826 case Intrinsic::ppc_altivec_stvebx:
9829 case Intrinsic::ppc_altivec_stvehx:
9832 case Intrinsic::ppc_altivec_stvewx:
9835 case Intrinsic::ppc_vsx_stxvd2x:
9843 Info.opc = ISD::INTRINSIC_VOID;
9845 Info.ptrVal = I.getArgOperand(1);
9846 Info.offset = -VT.getStoreSize()+1;
9847 Info.size = 2*VT.getStoreSize()-1;
9850 Info.readMem = false;
9851 Info.writeMem = true;
9861 /// getOptimalMemOpType - Returns the target specific optimal type for load
9862 /// and store operations as a result of memset, memcpy, and memmove
9863 /// lowering. If DstAlign is zero that means it's safe to destination
9864 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9865 /// means there isn't a need to check it against alignment requirement,
9866 /// probably because the source does not need to be loaded. If 'IsMemset' is
9867 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9868 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9869 /// source is constant so it does not need to be loaded.
9870 /// It returns EVT::Other if the type should be determined using generic
9871 /// target-independent logic.
9872 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9873 unsigned DstAlign, unsigned SrcAlign,
9874 bool IsMemset, bool ZeroMemset,
9876 MachineFunction &MF) const {
9877 if (Subtarget.isPPC64()) {
9884 /// \brief Returns true if it is beneficial to convert a load of a constant
9885 /// to just the constant itself.
9886 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9888 assert(Ty->isIntegerTy());
9890 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9891 if (BitSize == 0 || BitSize > 64)
9896 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9897 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9899 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9900 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9901 return NumBits1 == 64 && NumBits2 == 32;
9904 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9905 if (!VT1.isInteger() || !VT2.isInteger())
9907 unsigned NumBits1 = VT1.getSizeInBits();
9908 unsigned NumBits2 = VT2.getSizeInBits();
9909 return NumBits1 == 64 && NumBits2 == 32;
9912 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9913 // Generally speaking, zexts are not free, but they are free when they can be
9914 // folded with other operations.
9915 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9916 EVT MemVT = LD->getMemoryVT();
9917 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9918 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9919 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9920 LD->getExtensionType() == ISD::ZEXTLOAD))
9924 // FIXME: Add other cases...
9925 // - 32-bit shifts with a zext to i64
9926 // - zext after ctlz, bswap, etc.
9927 // - zext after and by a constant mask
9929 return TargetLowering::isZExtFree(Val, VT2);
9932 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9933 assert(VT.isFloatingPoint());
9937 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9938 return isInt<16>(Imm) || isUInt<16>(Imm);
9941 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9942 return isInt<16>(Imm) || isUInt<16>(Imm);
9945 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9949 if (DisablePPCUnaligned)
9952 // PowerPC supports unaligned memory access for simple non-vector types.
9953 // Although accessing unaligned addresses is not as efficient as accessing
9954 // aligned addresses, it is generally more efficient than manual expansion,
9955 // and generally only traps for software emulation when crossing page
9961 if (VT.getSimpleVT().isVector()) {
9962 if (Subtarget.hasVSX()) {
9963 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9964 VT != MVT::v4f32 && VT != MVT::v4i32)
9971 if (VT == MVT::ppcf128)
9980 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9981 VT = VT.getScalarType();
9986 switch (VT.getSimpleVT().SimpleTy) {
9998 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
9999 // LR is a callee-save register, but we must treat it as clobbered by any call
10000 // site. Hence we include LR in the scratch registers, which are in turn added
10001 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
10002 // to CTR, which is used by any indirect call.
10003 static const MCPhysReg ScratchRegs[] = {
10004 PPC::X12, PPC::LR8, PPC::CTR8, 0
10007 return ScratchRegs;
10011 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10012 EVT VT , unsigned DefinedValues) const {
10013 if (VT == MVT::v2i64)
10016 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10019 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10020 if (DisableILPPref || Subtarget.enableMachineScheduler())
10021 return TargetLowering::getSchedulingPreference(N);
10026 // Create a fast isel object.
10028 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10029 const TargetLibraryInfo *LibInfo) const {
10030 return PPC::createFastISel(FuncInfo, LibInfo);