1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 if (Subtarget.useCRBits()) {
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
100 if (isPPC64 || Subtarget.hasFPCVT()) {
101 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
112 // PowerPC does not support direct load / store of condition registers
113 setOperationAction(ISD::LOAD, MVT::i1, Custom);
114 setOperationAction(ISD::STORE, MVT::i1, Custom);
116 // FIXME: Remove this once the ANDI glue bug is fixed:
118 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
120 for (MVT VT : MVT::integer_valuetypes()) {
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
123 setTruncStoreAction(VT, MVT::i1, Expand);
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
129 // This is used in the ppcf128->int sequence. Note it has different semantics
130 // from FP_ROUND: that rounds to nearest, this rounds to zero.
131 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
133 // We do not currently implement these libm ops for PowerPC.
134 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
141 // PowerPC has no SREM/UREM instructions
142 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::UREM, MVT::i32, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
148 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
157 // We don't support sin/cos/sqrt/fmod/pow
158 setOperationAction(ISD::FSIN , MVT::f64, Expand);
159 setOperationAction(ISD::FCOS , MVT::f64, Expand);
160 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
161 setOperationAction(ISD::FREM , MVT::f64, Expand);
162 setOperationAction(ISD::FPOW , MVT::f64, Expand);
163 setOperationAction(ISD::FMA , MVT::f64, Legal);
164 setOperationAction(ISD::FSIN , MVT::f32, Expand);
165 setOperationAction(ISD::FCOS , MVT::f32, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FREM , MVT::f32, Expand);
168 setOperationAction(ISD::FPOW , MVT::f32, Expand);
169 setOperationAction(ISD::FMA , MVT::f32, Legal);
171 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
173 // If we're enabling GP optimizations, use hardware square root
174 if (!Subtarget.hasFSQRT() &&
175 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
177 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
181 Subtarget.hasFRES()))
182 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
184 if (Subtarget.hasFCPSGN()) {
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
192 if (Subtarget.hasFPRND()) {
193 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
194 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
195 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
196 setOperationAction(ISD::FROUND, MVT::f64, Legal);
198 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
201 setOperationAction(ISD::FROUND, MVT::f32, Legal);
204 // PowerPC does not have BSWAP, CTPOP or CTTZ
205 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
207 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
209 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
214 if (Subtarget.hasPOPCNTD()) {
215 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
218 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
222 // PowerPC does not have ROTR
223 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
224 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
226 if (!Subtarget.useCRBits()) {
227 // PowerPC does not have Select
228 setOperationAction(ISD::SELECT, MVT::i32, Expand);
229 setOperationAction(ISD::SELECT, MVT::i64, Expand);
230 setOperationAction(ISD::SELECT, MVT::f32, Expand);
231 setOperationAction(ISD::SELECT, MVT::f64, Expand);
234 // PowerPC wants to turn select_cc of FP into fsel when possible.
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
238 // PowerPC wants to optimize integer setcc a bit
239 if (!Subtarget.useCRBits())
240 setOperationAction(ISD::SETCC, MVT::i32, Custom);
242 // PowerPC does not have BRCOND which requires SetCC
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
246 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
248 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
251 // PowerPC does not have [U|S]INT_TO_FP
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
257 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
260 // We cannot sextinreg(i1). Expand to shifts.
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
263 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
264 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
265 // support continuation, user-level threading, and etc.. As a result, no
266 // other SjLj exception interfaces are implemented and please don't build
267 // your own exception handling based on them.
268 // LLVM/Clang supports zero-cost DWARF exception handling.
269 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
270 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
272 // We want to legalize GlobalAddress and ConstantPool nodes into the
273 // appropriate instructions to materialize the address.
274 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
277 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
278 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
286 setOperationAction(ISD::TRAP, MVT::Other, Legal);
288 // TRAMPOLINE is custom lowered.
289 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
290 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
292 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
293 setOperationAction(ISD::VASTART , MVT::Other, Custom);
295 if (Subtarget.isSVR4ABI()) {
297 // VAARG always uses double-word chunks, so promote anything smaller.
298 setOperationAction(ISD::VAARG, MVT::i1, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i8, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i16, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i32, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::Other, Expand);
308 // VAARG is custom lowered with the 32-bit SVR4 ABI.
309 setOperationAction(ISD::VAARG, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::i64, Custom);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
315 if (Subtarget.isSVR4ABI() && !isPPC64)
316 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
319 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
321 // Use the default implementation.
322 setOperationAction(ISD::VAEND , MVT::Other, Expand);
323 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
324 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
326 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
328 // We want to custom lower some of our intrinsics.
329 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
331 // To handle counter-based loop conditions.
332 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
334 // Comparisons that require checking two conditions.
335 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
348 if (Subtarget.has64BitSupport()) {
349 // They also have instructions for converting between i64 and fp.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
354 // This is just the low 32 bits of a (signed) fp->i64 conversion.
355 // We cannot do this with Promote because i64 is not a legal type.
356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
361 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
362 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
365 // With the instructions enabled under FPCVT, we can do everything.
366 if (Subtarget.hasFPCVT()) {
367 if (Subtarget.has64BitSupport()) {
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
369 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
380 if (Subtarget.use64BitRegs()) {
381 // 64-bit PowerPC implementations can support i64 types directly
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
383 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
384 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
385 // 64-bit PowerPC wants to expand i128 shifts itself.
386 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
388 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
390 // 32-bit PowerPC wants to expand i64 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
396 if (Subtarget.hasAltivec()) {
397 // First set operation action for all vector types to expand. Then we
398 // will selectively turn on ones that can be effectively codegen'd.
399 for (MVT VT : MVT::vector_valuetypes()) {
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (MVT InnerVT : MVT::vector_valuetypes()) {
467 setTruncStoreAction(VT, InnerVT, Expand);
468 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
470 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
474 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
475 // with merges, splats, etc.
476 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
478 setOperationAction(ISD::AND , MVT::v4i32, Legal);
479 setOperationAction(ISD::OR , MVT::v4i32, Legal);
480 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
481 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
482 setOperationAction(ISD::SELECT, MVT::v4i32,
483 Subtarget.useCRBits() ? Legal : Expand);
484 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
487 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
489 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
490 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
491 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
499 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
502 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
503 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
504 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
507 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
508 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
509 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
512 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
519 // Altivec does not contain unordered floating-point compare instructions
520 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
525 if (Subtarget.hasVSX()) {
526 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
529 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
537 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
538 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
540 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
541 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
549 // Share the Altivec comparison restrictions.
550 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
555 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
556 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
558 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
562 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
563 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
565 // VSX v2i64 only supports non-arithmetic operations.
566 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
567 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
569 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
571 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
575 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
582 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
585 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
587 // Vector operation legalization checks the result type of
588 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
594 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
598 if (Subtarget.has64BitSupport())
599 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
604 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
608 setBooleanContents(ZeroOrOneBooleanContent);
609 // Altivec instructions set fields to all zeros or all ones.
610 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
613 // These libcalls are not available in 32-bit.
614 setLibcallName(RTLIB::SHL_I128, nullptr);
615 setLibcallName(RTLIB::SRL_I128, nullptr);
616 setLibcallName(RTLIB::SRA_I128, nullptr);
620 setStackPointerRegisterToSaveRestore(PPC::X1);
621 setExceptionPointerRegister(PPC::X3);
622 setExceptionSelectorRegister(PPC::X4);
624 setStackPointerRegisterToSaveRestore(PPC::R1);
625 setExceptionPointerRegister(PPC::R3);
626 setExceptionSelectorRegister(PPC::R4);
629 // We have target-specific dag combine patterns for the following nodes:
630 setTargetDAGCombine(ISD::SINT_TO_FP);
631 if (Subtarget.hasFPCVT())
632 setTargetDAGCombine(ISD::UINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 switch (Subtarget.getDarwinDirective()) {
686 case PPC::DIR_E500mc:
695 setPrefFunctionAlignment(4);
696 setPrefLoopAlignment(4);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores do better with aggressive inlining of memcpy and
710 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
722 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
723 /// the desired ByVal argument alignment.
724 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
725 unsigned MaxMaxAlign) {
726 if (MaxAlign == MaxMaxAlign)
728 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
729 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
731 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
733 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
739 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
742 if (EltAlign > MaxAlign)
744 if (MaxAlign == MaxMaxAlign)
750 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
751 /// function arguments in the caller parameter area.
752 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
753 // Darwin passes everything on 4 byte boundary.
754 if (Subtarget.isDarwin())
757 // 16byte and wider vectors are passed on 16byte boundary.
758 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
759 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
760 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
761 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
765 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
767 default: return nullptr;
768 case PPCISD::FSEL: return "PPCISD::FSEL";
769 case PPCISD::FCFID: return "PPCISD::FCFID";
770 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
771 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
772 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
776 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
777 case PPCISD::FRE: return "PPCISD::FRE";
778 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
779 case PPCISD::STFIWX: return "PPCISD::STFIWX";
780 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
781 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
782 case PPCISD::VPERM: return "PPCISD::VPERM";
783 case PPCISD::CMPB: return "PPCISD::CMPB";
784 case PPCISD::Hi: return "PPCISD::Hi";
785 case PPCISD::Lo: return "PPCISD::Lo";
786 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::MTCTR: return "PPCISD::MTCTR";
795 case PPCISD::BCTRL: return "PPCISD::BCTRL";
796 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
797 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
798 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
799 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
800 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
801 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
802 case PPCISD::VCMP: return "PPCISD::VCMP";
803 case PPCISD::VCMPo: return "PPCISD::VCMPo";
804 case PPCISD::LBRX: return "PPCISD::LBRX";
805 case PPCISD::STBRX: return "PPCISD::STBRX";
806 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
807 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
808 case PPCISD::LARX: return "PPCISD::LARX";
809 case PPCISD::STCX: return "PPCISD::STCX";
810 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
811 case PPCISD::BDNZ: return "PPCISD::BDNZ";
812 case PPCISD::BDZ: return "PPCISD::BDZ";
813 case PPCISD::MFFS: return "PPCISD::MFFS";
814 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
815 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
816 case PPCISD::CR6SET: return "PPCISD::CR6SET";
817 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
818 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
819 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
820 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
821 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
822 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
823 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
824 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
825 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
826 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
827 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
828 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
829 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
830 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
831 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
832 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
833 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
834 case PPCISD::SC: return "PPCISD::SC";
838 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
841 return VT.changeVectorElementTypeToInteger();
844 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
845 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
849 //===----------------------------------------------------------------------===//
850 // Node matching predicates, for use by the tblgen matching code.
851 //===----------------------------------------------------------------------===//
853 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
854 static bool isFloatingPointZero(SDValue Op) {
855 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
856 return CFP->getValueAPF().isZero();
857 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
858 // Maybe this has already been legalized into the constant pool?
859 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
860 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
861 return CFP->getValueAPF().isZero();
866 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
867 /// true if Op is undef or if it matches the specified value.
868 static bool isConstantOrUndef(int Op, int Val) {
869 return Op < 0 || Op == Val;
872 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUHUM instruction.
874 /// The ShuffleKind distinguishes between big-endian operations with
875 /// two different inputs (0), either-endian operations with two identical
876 /// inputs (1), and little-endian operantion with two different inputs (2).
877 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
878 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
880 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
881 if (ShuffleKind == 0) {
884 for (unsigned i = 0; i != 16; ++i)
885 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
887 } else if (ShuffleKind == 2) {
890 for (unsigned i = 0; i != 16; ++i)
891 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
893 } else if (ShuffleKind == 1) {
894 unsigned j = IsLE ? 0 : 1;
895 for (unsigned i = 0; i != 8; ++i)
896 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
903 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
904 /// VPKUWUM instruction.
905 /// The ShuffleKind distinguishes between big-endian operations with
906 /// two different inputs (0), either-endian operations with two identical
907 /// inputs (1), and little-endian operantion with two different inputs (2).
908 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
909 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
911 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
912 if (ShuffleKind == 0) {
915 for (unsigned i = 0; i != 16; i += 2)
916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
919 } else if (ShuffleKind == 2) {
922 for (unsigned i = 0; i != 16; i += 2)
923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
926 } else if (ShuffleKind == 1) {
927 unsigned j = IsLE ? 0 : 2;
928 for (unsigned i = 0; i != 8; i += 2)
929 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
931 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
932 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
938 /// isVMerge - Common function, used to match vmrg* shuffles.
940 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned LHSStart, unsigned RHSStart) {
942 if (N->getValueType(0) != MVT::v16i8)
944 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
945 "Unsupported merge size!");
947 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
948 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
949 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
950 LHSStart+j+i*UnitSize) ||
951 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
952 RHSStart+j+i*UnitSize))
958 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
959 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
960 /// The ShuffleKind distinguishes between big-endian merges with two
961 /// different inputs (0), either-endian merges with two identical inputs (1),
962 /// and little-endian merges with two different inputs (2). For the latter,
963 /// the input operands are swapped (see PPCInstrAltivec.td).
964 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
965 unsigned ShuffleKind, SelectionDAG &DAG) {
966 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
967 if (ShuffleKind == 1) // unary
968 return isVMerge(N, UnitSize, 0, 0);
969 else if (ShuffleKind == 2) // swapped
970 return isVMerge(N, UnitSize, 0, 16);
974 if (ShuffleKind == 1) // unary
975 return isVMerge(N, UnitSize, 8, 8);
976 else if (ShuffleKind == 0) // normal
977 return isVMerge(N, UnitSize, 8, 24);
983 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
984 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
985 /// The ShuffleKind distinguishes between big-endian merges with two
986 /// different inputs (0), either-endian merges with two identical inputs (1),
987 /// and little-endian merges with two different inputs (2). For the latter,
988 /// the input operands are swapped (see PPCInstrAltivec.td).
989 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
990 unsigned ShuffleKind, SelectionDAG &DAG) {
991 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
992 if (ShuffleKind == 1) // unary
993 return isVMerge(N, UnitSize, 8, 8);
994 else if (ShuffleKind == 2) // swapped
995 return isVMerge(N, UnitSize, 8, 24);
999 if (ShuffleKind == 1) // unary
1000 return isVMerge(N, UnitSize, 0, 0);
1001 else if (ShuffleKind == 0) // normal
1002 return isVMerge(N, UnitSize, 0, 16);
1009 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1010 /// amount, otherwise return -1.
1011 /// The ShuffleKind distinguishes between big-endian operations with two
1012 /// different inputs (0), either-endian operations with two identical inputs
1013 /// (1), and little-endian operations with two different inputs (2). For the
1014 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1015 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1016 SelectionDAG &DAG) {
1017 if (N->getValueType(0) != MVT::v16i8)
1020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1022 // Find the first non-undef value in the shuffle mask.
1024 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1027 if (i == 16) return -1; // all undef.
1029 // Otherwise, check to see if the rest of the elements are consecutively
1030 // numbered from this value.
1031 unsigned ShiftAmt = SVOp->getMaskElt(i);
1032 if (ShiftAmt < i) return -1;
1035 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1037 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1038 // Check the rest of the elements to see if they are consecutive.
1039 for (++i; i != 16; ++i)
1040 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1042 } else if (ShuffleKind == 1) {
1043 // Check the rest of the elements to see if they are consecutive.
1044 for (++i; i != 16; ++i)
1045 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1050 if (ShuffleKind == 2 && isLE)
1051 ShiftAmt = 16 - ShiftAmt;
1056 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1057 /// specifies a splat of a single element that is suitable for input to
1058 /// VSPLTB/VSPLTH/VSPLTW.
1059 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1060 assert(N->getValueType(0) == MVT::v16i8 &&
1061 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1063 // This is a splat operation if each element of the permute is the same, and
1064 // if the value doesn't reference the second vector.
1065 unsigned ElementBase = N->getMaskElt(0);
1067 // FIXME: Handle UNDEF elements too!
1068 if (ElementBase >= 16)
1071 // Check that the indices are consecutive, in the case of a multi-byte element
1072 // splatted with a v16i8 mask.
1073 for (unsigned i = 1; i != EltSize; ++i)
1074 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1077 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1078 if (N->getMaskElt(i) < 0) continue;
1079 for (unsigned j = 0; j != EltSize; ++j)
1080 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1086 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1088 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1089 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1091 APInt APVal, APUndef;
1095 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1096 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1097 return CFP->getValueAPF().isNegZero();
1102 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1103 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1104 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1105 SelectionDAG &DAG) {
1106 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1107 assert(isSplatShuffleMask(SVOp, EltSize));
1108 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1109 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1111 return SVOp->getMaskElt(0) / EltSize;
1114 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1115 /// by using a vspltis[bhw] instruction of the specified element size, return
1116 /// the constant being splatted. The ByteSize field indicates the number of
1117 /// bytes of each element [124] -> [bhw].
1118 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1119 SDValue OpVal(nullptr, 0);
1121 // If ByteSize of the splat is bigger than the element size of the
1122 // build_vector, then we have a case where we are checking for a splat where
1123 // multiple elements of the buildvector are folded together into a single
1124 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1125 unsigned EltSize = 16/N->getNumOperands();
1126 if (EltSize < ByteSize) {
1127 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1128 SDValue UniquedVals[4];
1129 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1131 // See if all of the elements in the buildvector agree across.
1132 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1133 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1134 // If the element isn't a constant, bail fully out.
1135 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1138 if (!UniquedVals[i&(Multiple-1)].getNode())
1139 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1140 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1141 return SDValue(); // no match.
1144 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1145 // either constant or undef values that are identical for each chunk. See
1146 // if these chunks can form into a larger vspltis*.
1148 // Check to see if all of the leading entries are either 0 or -1. If
1149 // neither, then this won't fit into the immediate field.
1150 bool LeadingZero = true;
1151 bool LeadingOnes = true;
1152 for (unsigned i = 0; i != Multiple-1; ++i) {
1153 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1155 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1156 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1158 // Finally, check the least significant entry.
1160 if (!UniquedVals[Multiple-1].getNode())
1161 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1162 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1164 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1167 if (!UniquedVals[Multiple-1].getNode())
1168 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1169 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1170 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1171 return DAG.getTargetConstant(Val, MVT::i32);
1177 // Check to see if this buildvec has a single non-undef value in its elements.
1178 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1179 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1180 if (!OpVal.getNode())
1181 OpVal = N->getOperand(i);
1182 else if (OpVal != N->getOperand(i))
1186 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1188 unsigned ValSizeInBytes = EltSize;
1190 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1191 Value = CN->getZExtValue();
1192 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1193 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1194 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1197 // If the splat value is larger than the element value, then we can never do
1198 // this splat. The only case that we could fit the replicated bits into our
1199 // immediate field for would be zero, and we prefer to use vxor for it.
1200 if (ValSizeInBytes < ByteSize) return SDValue();
1202 // If the element value is larger than the splat value, cut it in half and
1203 // check to see if the two halves are equal. Continue doing this until we
1204 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1205 while (ValSizeInBytes > ByteSize) {
1206 ValSizeInBytes >>= 1;
1208 // If the top half equals the bottom half, we're still ok.
1209 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1210 (Value & ((1 << (8*ValSizeInBytes))-1)))
1214 // Properly sign extend the value.
1215 int MaskVal = SignExtend32(Value, ByteSize * 8);
1217 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1218 if (MaskVal == 0) return SDValue();
1220 // Finally, if this value fits in a 5 bit sext field, return it
1221 if (SignExtend32<5>(MaskVal) == MaskVal)
1222 return DAG.getTargetConstant(MaskVal, MVT::i32);
1226 //===----------------------------------------------------------------------===//
1227 // Addressing Mode Selection
1228 //===----------------------------------------------------------------------===//
1230 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1231 /// or 64-bit immediate, and if the value can be accurately represented as a
1232 /// sign extension from a 16-bit value. If so, this returns true and the
1234 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1235 if (!isa<ConstantSDNode>(N))
1238 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1239 if (N->getValueType(0) == MVT::i32)
1240 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1242 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1244 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1245 return isIntS16Immediate(Op.getNode(), Imm);
1249 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1250 /// can be represented as an indexed [r+r] operation. Returns false if it
1251 /// can be more efficiently represented with [r+imm].
1252 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1254 SelectionDAG &DAG) const {
1256 if (N.getOpcode() == ISD::ADD) {
1257 if (isIntS16Immediate(N.getOperand(1), imm))
1258 return false; // r+i
1259 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1260 return false; // r+i
1262 Base = N.getOperand(0);
1263 Index = N.getOperand(1);
1265 } else if (N.getOpcode() == ISD::OR) {
1266 if (isIntS16Immediate(N.getOperand(1), imm))
1267 return false; // r+i can fold it if we can.
1269 // If this is an or of disjoint bitfields, we can codegen this as an add
1270 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1272 APInt LHSKnownZero, LHSKnownOne;
1273 APInt RHSKnownZero, RHSKnownOne;
1274 DAG.computeKnownBits(N.getOperand(0),
1275 LHSKnownZero, LHSKnownOne);
1277 if (LHSKnownZero.getBoolValue()) {
1278 DAG.computeKnownBits(N.getOperand(1),
1279 RHSKnownZero, RHSKnownOne);
1280 // If all of the bits are known zero on the LHS or RHS, the add won't
1282 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1283 Base = N.getOperand(0);
1284 Index = N.getOperand(1);
1293 // If we happen to be doing an i64 load or store into a stack slot that has
1294 // less than a 4-byte alignment, then the frame-index elimination may need to
1295 // use an indexed load or store instruction (because the offset may not be a
1296 // multiple of 4). The extra register needed to hold the offset comes from the
1297 // register scavenger, and it is possible that the scavenger will need to use
1298 // an emergency spill slot. As a result, we need to make sure that a spill slot
1299 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1301 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1302 // FIXME: This does not handle the LWA case.
1306 // NOTE: We'll exclude negative FIs here, which come from argument
1307 // lowering, because there are no known test cases triggering this problem
1308 // using packed structures (or similar). We can remove this exclusion if
1309 // we find such a test case. The reason why this is so test-case driven is
1310 // because this entire 'fixup' is only to prevent crashes (from the
1311 // register scavenger) on not-really-valid inputs. For example, if we have:
1313 // %b = bitcast i1* %a to i64*
1314 // store i64* a, i64 b
1315 // then the store should really be marked as 'align 1', but is not. If it
1316 // were marked as 'align 1' then the indexed form would have been
1317 // instruction-selected initially, and the problem this 'fixup' is preventing
1318 // won't happen regardless.
1322 MachineFunction &MF = DAG.getMachineFunction();
1323 MachineFrameInfo *MFI = MF.getFrameInfo();
1325 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1329 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1330 FuncInfo->setHasNonRISpills();
1333 /// Returns true if the address N can be represented by a base register plus
1334 /// a signed 16-bit displacement [r+imm], and if it is not better
1335 /// represented as reg+reg. If Aligned is true, only accept displacements
1336 /// suitable for STD and friends, i.e. multiples of 4.
1337 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1340 bool Aligned) const {
1341 // FIXME dl should come from parent load or store, not from address
1343 // If this can be more profitably realized as r+r, fail.
1344 if (SelectAddressRegReg(N, Disp, Base, DAG))
1347 if (N.getOpcode() == ISD::ADD) {
1349 if (isIntS16Immediate(N.getOperand(1), imm) &&
1350 (!Aligned || (imm & 3) == 0)) {
1351 Disp = DAG.getTargetConstant(imm, N.getValueType());
1352 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1353 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1354 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1356 Base = N.getOperand(0);
1358 return true; // [r+i]
1359 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1360 // Match LOAD (ADD (X, Lo(G))).
1361 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1362 && "Cannot handle constant offsets yet!");
1363 Disp = N.getOperand(1).getOperand(0); // The global address.
1364 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1365 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1366 Disp.getOpcode() == ISD::TargetConstantPool ||
1367 Disp.getOpcode() == ISD::TargetJumpTable);
1368 Base = N.getOperand(0);
1369 return true; // [&g+r]
1371 } else if (N.getOpcode() == ISD::OR) {
1373 if (isIntS16Immediate(N.getOperand(1), imm) &&
1374 (!Aligned || (imm & 3) == 0)) {
1375 // If this is an or of disjoint bitfields, we can codegen this as an add
1376 // (for better address arithmetic) if the LHS and RHS of the OR are
1377 // provably disjoint.
1378 APInt LHSKnownZero, LHSKnownOne;
1379 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1381 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1382 // If all of the bits are known zero on the LHS or RHS, the add won't
1384 if (FrameIndexSDNode *FI =
1385 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1386 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1387 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1389 Base = N.getOperand(0);
1391 Disp = DAG.getTargetConstant(imm, N.getValueType());
1395 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1396 // Loading from a constant address.
1398 // If this address fits entirely in a 16-bit sext immediate field, codegen
1401 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1402 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1403 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 CN->getValueType(0));
1408 // Handle 32-bit sext immediates with LIS + addr mode.
1409 if ((CN->getValueType(0) == MVT::i32 ||
1410 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1411 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1412 int Addr = (int)CN->getZExtValue();
1414 // Otherwise, break this down into an LIS + disp.
1415 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1417 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1418 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1419 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1424 Disp = DAG.getTargetConstant(0, getPointerTy());
1425 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1426 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1427 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1430 return true; // [r+0]
1433 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1434 /// represented as an indexed [r+r] operation.
1435 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1437 SelectionDAG &DAG) const {
1438 // Check to see if we can easily represent this as an [r+r] address. This
1439 // will fail if it thinks that the address is more profitably represented as
1440 // reg+imm, e.g. where imm = 0.
1441 if (SelectAddressRegReg(N, Base, Index, DAG))
1444 // If the operand is an addition, always emit this as [r+r], since this is
1445 // better (for code size, and execution, as the memop does the add for free)
1446 // than emitting an explicit add.
1447 if (N.getOpcode() == ISD::ADD) {
1448 Base = N.getOperand(0);
1449 Index = N.getOperand(1);
1453 // Otherwise, do it the hard way, using R0 as the base register.
1454 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1460 /// getPreIndexedAddressParts - returns true by value, base pointer and
1461 /// offset pointer and addressing mode by reference if the node's address
1462 /// can be legally represented as pre-indexed load / store address.
1463 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1465 ISD::MemIndexedMode &AM,
1466 SelectionDAG &DAG) const {
1467 if (DisablePPCPreinc) return false;
1473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1474 Ptr = LD->getBasePtr();
1475 VT = LD->getMemoryVT();
1476 Alignment = LD->getAlignment();
1477 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1478 Ptr = ST->getBasePtr();
1479 VT = ST->getMemoryVT();
1480 Alignment = ST->getAlignment();
1485 // PowerPC doesn't have preinc load/store instructions for vectors.
1489 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1491 // Common code will reject creating a pre-inc form if the base pointer
1492 // is a frame index, or if N is a store and the base pointer is either
1493 // the same as or a predecessor of the value being stored. Check for
1494 // those situations here, and try with swapped Base/Offset instead.
1497 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1500 SDValue Val = cast<StoreSDNode>(N)->getValue();
1501 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1506 std::swap(Base, Offset);
1512 // LDU/STU can only handle immediates that are a multiple of 4.
1513 if (VT != MVT::i64) {
1514 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1517 // LDU/STU need an address with at least 4-byte alignment.
1521 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1525 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1526 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1527 // sext i32 to i64 when addr mode is r+i.
1528 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1529 LD->getExtensionType() == ISD::SEXTLOAD &&
1530 isa<ConstantSDNode>(Offset))
1538 //===----------------------------------------------------------------------===//
1539 // LowerOperation implementation
1540 //===----------------------------------------------------------------------===//
1542 /// GetLabelAccessInfo - Return true if we should reference labels using a
1543 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1544 static bool GetLabelAccessInfo(const TargetMachine &TM,
1545 const PPCSubtarget &Subtarget,
1546 unsigned &HiOpFlags, unsigned &LoOpFlags,
1547 const GlobalValue *GV = nullptr) {
1548 HiOpFlags = PPCII::MO_HA;
1549 LoOpFlags = PPCII::MO_LO;
1551 // Don't use the pic base if not in PIC relocation model.
1552 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1555 HiOpFlags |= PPCII::MO_PIC_FLAG;
1556 LoOpFlags |= PPCII::MO_PIC_FLAG;
1559 // If this is a reference to a global value that requires a non-lazy-ptr, make
1560 // sure that instruction lowering adds it.
1561 if (GV && Subtarget.hasLazyResolverStub(GV, TM)) {
1562 HiOpFlags |= PPCII::MO_NLP_FLAG;
1563 LoOpFlags |= PPCII::MO_NLP_FLAG;
1565 if (GV->hasHiddenVisibility()) {
1566 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1567 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1574 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1575 SelectionDAG &DAG) {
1576 EVT PtrVT = HiPart.getValueType();
1577 SDValue Zero = DAG.getConstant(0, PtrVT);
1580 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1581 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1583 // With PIC, the first instruction is actually "GR+hi(&G)".
1585 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1586 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1588 // Generate non-pic code that has direct accesses to the constant pool.
1589 // The address of the global is just (hi(&g)+lo(&g)).
1590 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1593 static void setUsesTOCBasePtr(MachineFunction &MF) {
1594 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1595 FuncInfo->setUsesTOCBasePtr();
1598 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1599 setUsesTOCBasePtr(DAG.getMachineFunction());
1602 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1603 SelectionDAG &DAG) const {
1604 EVT PtrVT = Op.getValueType();
1605 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1606 const Constant *C = CP->getConstVal();
1608 // 64-bit SVR4 ABI code is always position-independent.
1609 // The actual address of the GlobalValue is stored in the TOC.
1610 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1611 setUsesTOCBasePtr(DAG);
1612 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1613 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1614 DAG.getRegister(PPC::X2, MVT::i64));
1617 unsigned MOHiFlag, MOLoFlag;
1619 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1621 if (isPIC && Subtarget.isSVR4ABI()) {
1622 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1623 PPCII::MO_PIC_FLAG);
1625 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1626 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1630 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1632 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1633 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1636 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1637 EVT PtrVT = Op.getValueType();
1638 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1640 // 64-bit SVR4 ABI code is always position-independent.
1641 // The actual address of the GlobalValue is stored in the TOC.
1642 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1643 setUsesTOCBasePtr(DAG);
1644 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1645 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1646 DAG.getRegister(PPC::X2, MVT::i64));
1649 unsigned MOHiFlag, MOLoFlag;
1651 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1653 if (isPIC && Subtarget.isSVR4ABI()) {
1654 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1655 PPCII::MO_PIC_FLAG);
1657 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1658 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1661 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1662 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1663 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1666 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1667 SelectionDAG &DAG) const {
1668 EVT PtrVT = Op.getValueType();
1669 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1670 const BlockAddress *BA = BASDN->getBlockAddress();
1672 // 64-bit SVR4 ABI code is always position-independent.
1673 // The actual BlockAddress is stored in the TOC.
1674 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1675 setUsesTOCBasePtr(DAG);
1676 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1677 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1678 DAG.getRegister(PPC::X2, MVT::i64));
1681 unsigned MOHiFlag, MOLoFlag;
1683 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1684 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1685 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1686 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1689 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1690 SelectionDAG &DAG) const {
1692 // FIXME: TLS addresses currently use medium model code sequences,
1693 // which is the most useful form. Eventually support for small and
1694 // large models could be added if users need it, at the cost of
1695 // additional complexity.
1696 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1698 const GlobalValue *GV = GA->getGlobal();
1699 EVT PtrVT = getPointerTy();
1700 bool is64bit = Subtarget.isPPC64();
1701 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1702 PICLevel::Level picLevel = M->getPICLevel();
1704 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1706 if (Model == TLSModel::LocalExec) {
1707 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1708 PPCII::MO_TPREL_HA);
1709 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1710 PPCII::MO_TPREL_LO);
1711 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1712 is64bit ? MVT::i64 : MVT::i32);
1713 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1714 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1717 if (Model == TLSModel::InitialExec) {
1718 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1719 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1723 setUsesTOCBasePtr(DAG);
1724 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1725 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1726 PtrVT, GOTReg, TGA);
1728 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1729 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1730 PtrVT, TGA, GOTPtr);
1731 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1734 if (Model == TLSModel::GeneralDynamic) {
1735 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1738 setUsesTOCBasePtr(DAG);
1739 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1740 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1743 if (picLevel == PICLevel::Small)
1744 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1746 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1748 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl,
1749 PtrVT, GOTPtr, TGA);
1750 return DAG.getNode(PPCISD::GET_TLS_ADDR, dl, PtrVT, GOTEntry, TGA);
1753 if (Model == TLSModel::LocalDynamic) {
1754 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1757 setUsesTOCBasePtr(DAG);
1758 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1759 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1762 if (picLevel == PICLevel::Small)
1763 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1765 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1767 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1769 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1770 PtrVT, GOTEntry, TGA);
1771 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
1772 PtrVT, TLSAddr, TGA);
1773 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1776 llvm_unreachable("Unknown TLS model!");
1779 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1780 SelectionDAG &DAG) const {
1781 EVT PtrVT = Op.getValueType();
1782 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1784 const GlobalValue *GV = GSDN->getGlobal();
1786 // 64-bit SVR4 ABI code is always position-independent.
1787 // The actual address of the GlobalValue is stored in the TOC.
1788 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1789 setUsesTOCBasePtr(DAG);
1790 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1791 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1792 DAG.getRegister(PPC::X2, MVT::i64));
1795 unsigned MOHiFlag, MOLoFlag;
1797 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
1799 if (isPIC && Subtarget.isSVR4ABI()) {
1800 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1802 PPCII::MO_PIC_FLAG);
1803 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1804 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1808 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1810 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1812 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1814 // If the global reference is actually to a non-lazy-pointer, we have to do an
1815 // extra load to get the address of the global.
1816 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1817 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1818 false, false, false, 0);
1822 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1823 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1826 if (Op.getValueType() == MVT::v2i64) {
1827 // When the operands themselves are v2i64 values, we need to do something
1828 // special because VSX has no underlying comparison operations for these.
1829 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1830 // Equality can be handled by casting to the legal type for Altivec
1831 // comparisons, everything else needs to be expanded.
1832 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1833 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1834 DAG.getSetCC(dl, MVT::v4i32,
1835 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1836 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1843 // We handle most of these in the usual way.
1847 // If we're comparing for equality to zero, expose the fact that this is
1848 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1849 // fold the new nodes.
1850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1851 if (C->isNullValue() && CC == ISD::SETEQ) {
1852 EVT VT = Op.getOperand(0).getValueType();
1853 SDValue Zext = Op.getOperand(0);
1854 if (VT.bitsLT(MVT::i32)) {
1856 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1858 unsigned Log2b = Log2_32(VT.getSizeInBits());
1859 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1860 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1861 DAG.getConstant(Log2b, MVT::i32));
1862 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1864 // Leave comparisons against 0 and -1 alone for now, since they're usually
1865 // optimized. FIXME: revisit this when we can custom lower all setcc
1867 if (C->isAllOnesValue() || C->isNullValue())
1871 // If we have an integer seteq/setne, turn it into a compare against zero
1872 // by xor'ing the rhs with the lhs, which is faster than setting a
1873 // condition register, reading it back out, and masking the correct bit. The
1874 // normal approach here uses sub to do this instead of xor. Using xor exposes
1875 // the result to other bit-twiddling opportunities.
1876 EVT LHSVT = Op.getOperand(0).getValueType();
1877 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1878 EVT VT = Op.getValueType();
1879 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1881 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1886 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1887 const PPCSubtarget &Subtarget) const {
1888 SDNode *Node = Op.getNode();
1889 EVT VT = Node->getValueType(0);
1890 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1891 SDValue InChain = Node->getOperand(0);
1892 SDValue VAListPtr = Node->getOperand(1);
1893 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1896 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1899 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1900 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1901 false, false, false, 0);
1902 InChain = GprIndex.getValue(1);
1904 if (VT == MVT::i64) {
1905 // Check if GprIndex is even
1906 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1907 DAG.getConstant(1, MVT::i32));
1908 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1909 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1910 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1911 DAG.getConstant(1, MVT::i32));
1912 // Align GprIndex to be even if it isn't
1913 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1917 // fpr index is 1 byte after gpr
1918 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1919 DAG.getConstant(1, MVT::i32));
1922 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1923 FprPtr, MachinePointerInfo(SV), MVT::i8,
1924 false, false, false, 0);
1925 InChain = FprIndex.getValue(1);
1927 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1928 DAG.getConstant(8, MVT::i32));
1930 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1931 DAG.getConstant(4, MVT::i32));
1934 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1935 MachinePointerInfo(), false, false,
1937 InChain = OverflowArea.getValue(1);
1939 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1940 MachinePointerInfo(), false, false,
1942 InChain = RegSaveArea.getValue(1);
1944 // select overflow_area if index > 8
1945 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1946 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1948 // adjustment constant gpr_index * 4/8
1949 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1950 VT.isInteger() ? GprIndex : FprIndex,
1951 DAG.getConstant(VT.isInteger() ? 4 : 8,
1954 // OurReg = RegSaveArea + RegConstant
1955 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1958 // Floating types are 32 bytes into RegSaveArea
1959 if (VT.isFloatingPoint())
1960 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1961 DAG.getConstant(32, MVT::i32));
1963 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1964 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1965 VT.isInteger() ? GprIndex : FprIndex,
1966 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1969 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1970 VT.isInteger() ? VAListPtr : FprPtr,
1971 MachinePointerInfo(SV),
1972 MVT::i8, false, false, 0);
1974 // determine if we should load from reg_save_area or overflow_area
1975 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1977 // increase overflow_area by 4/8 if gpr/fpr > 8
1978 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1979 DAG.getConstant(VT.isInteger() ? 4 : 8,
1982 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1985 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1987 MachinePointerInfo(),
1988 MVT::i32, false, false, 0);
1990 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1991 false, false, false, 0);
1994 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1995 const PPCSubtarget &Subtarget) const {
1996 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1998 // We have to copy the entire va_list struct:
1999 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2000 return DAG.getMemcpy(Op.getOperand(0), Op,
2001 Op.getOperand(1), Op.getOperand(2),
2002 DAG.getConstant(12, MVT::i32), 8, false, true,
2003 MachinePointerInfo(), MachinePointerInfo());
2006 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2007 SelectionDAG &DAG) const {
2008 return Op.getOperand(0);
2011 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2012 SelectionDAG &DAG) const {
2013 SDValue Chain = Op.getOperand(0);
2014 SDValue Trmp = Op.getOperand(1); // trampoline
2015 SDValue FPtr = Op.getOperand(2); // nested function
2016 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2019 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2020 bool isPPC64 = (PtrVT == MVT::i64);
2022 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2025 TargetLowering::ArgListTy Args;
2026 TargetLowering::ArgListEntry Entry;
2028 Entry.Ty = IntPtrTy;
2029 Entry.Node = Trmp; Args.push_back(Entry);
2031 // TrampSize == (isPPC64 ? 48 : 40);
2032 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2033 isPPC64 ? MVT::i64 : MVT::i32);
2034 Args.push_back(Entry);
2036 Entry.Node = FPtr; Args.push_back(Entry);
2037 Entry.Node = Nest; Args.push_back(Entry);
2039 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2040 TargetLowering::CallLoweringInfo CLI(DAG);
2041 CLI.setDebugLoc(dl).setChain(Chain)
2042 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2043 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2044 std::move(Args), 0);
2046 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2047 return CallResult.second;
2050 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2051 const PPCSubtarget &Subtarget) const {
2052 MachineFunction &MF = DAG.getMachineFunction();
2053 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2057 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2058 // vastart just stores the address of the VarArgsFrameIndex slot into the
2059 // memory location argument.
2060 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2061 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2062 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2063 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2064 MachinePointerInfo(SV),
2068 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2069 // We suppose the given va_list is already allocated.
2072 // char gpr; /* index into the array of 8 GPRs
2073 // * stored in the register save area
2074 // * gpr=0 corresponds to r3,
2075 // * gpr=1 to r4, etc.
2077 // char fpr; /* index into the array of 8 FPRs
2078 // * stored in the register save area
2079 // * fpr=0 corresponds to f1,
2080 // * fpr=1 to f2, etc.
2082 // char *overflow_arg_area;
2083 // /* location on stack that holds
2084 // * the next overflow argument
2086 // char *reg_save_area;
2087 // /* where r3:r10 and f1:f8 (if saved)
2093 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2094 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2097 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2099 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2101 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2104 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2105 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2107 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2108 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2110 uint64_t FPROffset = 1;
2111 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2113 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2115 // Store first byte : number of int regs
2116 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2118 MachinePointerInfo(SV),
2119 MVT::i8, false, false, 0);
2120 uint64_t nextOffset = FPROffset;
2121 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2124 // Store second byte : number of float regs
2125 SDValue secondStore =
2126 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2127 MachinePointerInfo(SV, nextOffset), MVT::i8,
2129 nextOffset += StackOffset;
2130 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2132 // Store second word : arguments given on stack
2133 SDValue thirdStore =
2134 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2135 MachinePointerInfo(SV, nextOffset),
2137 nextOffset += FrameOffset;
2138 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2140 // Store third word : arguments given in registers
2141 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2142 MachinePointerInfo(SV, nextOffset),
2147 #include "PPCGenCallingConv.inc"
2149 // Function whose sole purpose is to kill compiler warnings
2150 // stemming from unused functions included from PPCGenCallingConv.inc.
2151 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2152 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2155 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2156 CCValAssign::LocInfo &LocInfo,
2157 ISD::ArgFlagsTy &ArgFlags,
2162 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2164 CCValAssign::LocInfo &LocInfo,
2165 ISD::ArgFlagsTy &ArgFlags,
2167 static const MCPhysReg ArgRegs[] = {
2168 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2169 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2171 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2173 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2175 // Skip one register if the first unallocated register has an even register
2176 // number and there are still argument registers available which have not been
2177 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2178 // need to skip a register if RegNum is odd.
2179 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2180 State.AllocateReg(ArgRegs[RegNum]);
2183 // Always return false here, as this function only makes sure that the first
2184 // unallocated register has an odd register number and does not actually
2185 // allocate a register for the current argument.
2189 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2191 CCValAssign::LocInfo &LocInfo,
2192 ISD::ArgFlagsTy &ArgFlags,
2194 static const MCPhysReg ArgRegs[] = {
2195 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2199 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2201 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2203 // If there is only one Floating-point register left we need to put both f64
2204 // values of a split ppc_fp128 value on the stack.
2205 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2206 State.AllocateReg(ArgRegs[RegNum]);
2209 // Always return false here, as this function only makes sure that the two f64
2210 // values a ppc_fp128 value is split into are both passed in registers or both
2211 // passed on the stack and does not actually allocate a register for the
2212 // current argument.
2216 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2218 static const MCPhysReg *GetFPR() {
2219 static const MCPhysReg FPR[] = {
2220 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2221 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2227 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2229 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2230 unsigned PtrByteSize) {
2231 unsigned ArgSize = ArgVT.getStoreSize();
2232 if (Flags.isByVal())
2233 ArgSize = Flags.getByValSize();
2235 // Round up to multiples of the pointer size, except for array members,
2236 // which are always packed.
2237 if (!Flags.isInConsecutiveRegs())
2238 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2243 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2245 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2246 ISD::ArgFlagsTy Flags,
2247 unsigned PtrByteSize) {
2248 unsigned Align = PtrByteSize;
2250 // Altivec parameters are padded to a 16 byte boundary.
2251 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2252 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2253 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2256 // ByVal parameters are aligned as requested.
2257 if (Flags.isByVal()) {
2258 unsigned BVAlign = Flags.getByValAlign();
2259 if (BVAlign > PtrByteSize) {
2260 if (BVAlign % PtrByteSize != 0)
2262 "ByVal alignment is not a multiple of the pointer size");
2268 // Array members are always packed to their original alignment.
2269 if (Flags.isInConsecutiveRegs()) {
2270 // If the array member was split into multiple registers, the first
2271 // needs to be aligned to the size of the full type. (Except for
2272 // ppcf128, which is only aligned as its f64 components.)
2273 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2274 Align = OrigVT.getStoreSize();
2276 Align = ArgVT.getStoreSize();
2282 /// CalculateStackSlotUsed - Return whether this argument will use its
2283 /// stack slot (instead of being passed in registers). ArgOffset,
2284 /// AvailableFPRs, and AvailableVRs must hold the current argument
2285 /// position, and will be updated to account for this argument.
2286 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2287 ISD::ArgFlagsTy Flags,
2288 unsigned PtrByteSize,
2289 unsigned LinkageSize,
2290 unsigned ParamAreaSize,
2291 unsigned &ArgOffset,
2292 unsigned &AvailableFPRs,
2293 unsigned &AvailableVRs) {
2294 bool UseMemory = false;
2296 // Respect alignment of argument on the stack.
2298 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2299 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2300 // If there's no space left in the argument save area, we must
2301 // use memory (this check also catches zero-sized arguments).
2302 if (ArgOffset >= LinkageSize + ParamAreaSize)
2305 // Allocate argument on the stack.
2306 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2307 if (Flags.isInConsecutiveRegsLast())
2308 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2309 // If we overran the argument save area, we must use memory
2310 // (this check catches arguments passed partially in memory)
2311 if (ArgOffset > LinkageSize + ParamAreaSize)
2314 // However, if the argument is actually passed in an FPR or a VR,
2315 // we don't use memory after all.
2316 if (!Flags.isByVal()) {
2317 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2318 if (AvailableFPRs > 0) {
2322 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2323 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2324 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2325 if (AvailableVRs > 0) {
2334 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2335 /// ensure minimum alignment required for target.
2336 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2337 unsigned NumBytes) {
2338 unsigned TargetAlign = Lowering->getStackAlignment();
2339 unsigned AlignMask = TargetAlign - 1;
2340 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2345 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2346 CallingConv::ID CallConv, bool isVarArg,
2347 const SmallVectorImpl<ISD::InputArg>
2349 SDLoc dl, SelectionDAG &DAG,
2350 SmallVectorImpl<SDValue> &InVals)
2352 if (Subtarget.isSVR4ABI()) {
2353 if (Subtarget.isPPC64())
2354 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2357 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2360 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2366 PPCTargetLowering::LowerFormalArguments_32SVR4(
2368 CallingConv::ID CallConv, bool isVarArg,
2369 const SmallVectorImpl<ISD::InputArg>
2371 SDLoc dl, SelectionDAG &DAG,
2372 SmallVectorImpl<SDValue> &InVals) const {
2374 // 32-bit SVR4 ABI Stack Frame Layout:
2375 // +-----------------------------------+
2376 // +--> | Back chain |
2377 // | +-----------------------------------+
2378 // | | Floating-point register save area |
2379 // | +-----------------------------------+
2380 // | | General register save area |
2381 // | +-----------------------------------+
2382 // | | CR save word |
2383 // | +-----------------------------------+
2384 // | | VRSAVE save word |
2385 // | +-----------------------------------+
2386 // | | Alignment padding |
2387 // | +-----------------------------------+
2388 // | | Vector register save area |
2389 // | +-----------------------------------+
2390 // | | Local variable space |
2391 // | +-----------------------------------+
2392 // | | Parameter list area |
2393 // | +-----------------------------------+
2394 // | | LR save word |
2395 // | +-----------------------------------+
2396 // SP--> +--- | Back chain |
2397 // +-----------------------------------+
2400 // System V Application Binary Interface PowerPC Processor Supplement
2401 // AltiVec Technology Programming Interface Manual
2403 MachineFunction &MF = DAG.getMachineFunction();
2404 MachineFrameInfo *MFI = MF.getFrameInfo();
2405 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2407 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2408 // Potential tail calls could cause overwriting of argument stack slots.
2409 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2410 (CallConv == CallingConv::Fast));
2411 unsigned PtrByteSize = 4;
2413 // Assign locations to all of the incoming arguments.
2414 SmallVector<CCValAssign, 16> ArgLocs;
2415 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2418 // Reserve space for the linkage area on the stack.
2419 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2420 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2422 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2424 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2425 CCValAssign &VA = ArgLocs[i];
2427 // Arguments stored in registers.
2428 if (VA.isRegLoc()) {
2429 const TargetRegisterClass *RC;
2430 EVT ValVT = VA.getValVT();
2432 switch (ValVT.getSimpleVT().SimpleTy) {
2434 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2437 RC = &PPC::GPRCRegClass;
2440 RC = &PPC::F4RCRegClass;
2443 if (Subtarget.hasVSX())
2444 RC = &PPC::VSFRCRegClass;
2446 RC = &PPC::F8RCRegClass;
2452 RC = &PPC::VRRCRegClass;
2456 RC = &PPC::VSHRCRegClass;
2460 // Transform the arguments stored in physical registers into virtual ones.
2461 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2462 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2463 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2465 if (ValVT == MVT::i1)
2466 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2468 InVals.push_back(ArgValue);
2470 // Argument stored in memory.
2471 assert(VA.isMemLoc());
2473 unsigned ArgSize = VA.getLocVT().getStoreSize();
2474 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2477 // Create load nodes to retrieve arguments from the stack.
2478 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2479 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2480 MachinePointerInfo(),
2481 false, false, false, 0));
2485 // Assign locations to all of the incoming aggregate by value arguments.
2486 // Aggregates passed by value are stored in the local variable space of the
2487 // caller's stack frame, right above the parameter list area.
2488 SmallVector<CCValAssign, 16> ByValArgLocs;
2489 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2490 ByValArgLocs, *DAG.getContext());
2492 // Reserve stack space for the allocations in CCInfo.
2493 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2495 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2497 // Area that is at least reserved in the caller of this function.
2498 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2499 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2501 // Set the size that is at least reserved in caller of this function. Tail
2502 // call optimized function's reserved stack space needs to be aligned so that
2503 // taking the difference between two stack areas will result in an aligned
2506 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2507 FuncInfo->setMinReservedArea(MinReservedArea);
2509 SmallVector<SDValue, 8> MemOps;
2511 // If the function takes variable number of arguments, make a frame index for
2512 // the start of the first vararg value... for expansion of llvm.va_start.
2514 static const MCPhysReg GPArgRegs[] = {
2515 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2516 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2518 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2520 static const MCPhysReg FPArgRegs[] = {
2521 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2524 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2525 if (DisablePPCFloatInVariadic)
2528 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2530 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2533 // Make room for NumGPArgRegs and NumFPArgRegs.
2534 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2535 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2537 FuncInfo->setVarArgsStackOffset(
2538 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2539 CCInfo.getNextStackOffset(), true));
2541 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2542 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2544 // The fixed integer arguments of a variadic function are stored to the
2545 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2546 // the result of va_next.
2547 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2548 // Get an existing live-in vreg, or add a new one.
2549 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2551 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2553 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2554 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2555 MachinePointerInfo(), false, false, 0);
2556 MemOps.push_back(Store);
2557 // Increment the address by four for the next argument to store
2558 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2559 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2562 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2564 // The double arguments are stored to the VarArgsFrameIndex
2566 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2567 // Get an existing live-in vreg, or add a new one.
2568 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2570 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2572 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2573 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2574 MachinePointerInfo(), false, false, 0);
2575 MemOps.push_back(Store);
2576 // Increment the address by eight for the next argument to store
2577 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2579 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2583 if (!MemOps.empty())
2584 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2589 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2590 // value to MVT::i64 and then truncate to the correct register size.
2592 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2593 SelectionDAG &DAG, SDValue ArgVal,
2596 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2597 DAG.getValueType(ObjectVT));
2598 else if (Flags.isZExt())
2599 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2600 DAG.getValueType(ObjectVT));
2602 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2606 PPCTargetLowering::LowerFormalArguments_64SVR4(
2608 CallingConv::ID CallConv, bool isVarArg,
2609 const SmallVectorImpl<ISD::InputArg>
2611 SDLoc dl, SelectionDAG &DAG,
2612 SmallVectorImpl<SDValue> &InVals) const {
2613 // TODO: add description of PPC stack frame format, or at least some docs.
2615 bool isELFv2ABI = Subtarget.isELFv2ABI();
2616 bool isLittleEndian = Subtarget.isLittleEndian();
2617 MachineFunction &MF = DAG.getMachineFunction();
2618 MachineFrameInfo *MFI = MF.getFrameInfo();
2619 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2621 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2622 "fastcc not supported on varargs functions");
2624 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2625 // Potential tail calls could cause overwriting of argument stack slots.
2626 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2627 (CallConv == CallingConv::Fast));
2628 unsigned PtrByteSize = 8;
2630 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2633 static const MCPhysReg GPR[] = {
2634 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2635 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2638 static const MCPhysReg *FPR = GetFPR();
2640 static const MCPhysReg VR[] = {
2641 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2642 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2644 static const MCPhysReg VSRH[] = {
2645 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2646 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2649 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2650 const unsigned Num_FPR_Regs = 13;
2651 const unsigned Num_VR_Regs = array_lengthof(VR);
2653 // Do a first pass over the arguments to determine whether the ABI
2654 // guarantees that our caller has allocated the parameter save area
2655 // on its stack frame. In the ELFv1 ABI, this is always the case;
2656 // in the ELFv2 ABI, it is true if this is a vararg function or if
2657 // any parameter is located in a stack slot.
2659 bool HasParameterArea = !isELFv2ABI || isVarArg;
2660 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2661 unsigned NumBytes = LinkageSize;
2662 unsigned AvailableFPRs = Num_FPR_Regs;
2663 unsigned AvailableVRs = Num_VR_Regs;
2664 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2665 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2666 PtrByteSize, LinkageSize, ParamAreaSize,
2667 NumBytes, AvailableFPRs, AvailableVRs))
2668 HasParameterArea = true;
2670 // Add DAG nodes to load the arguments or copy them out of registers. On
2671 // entry to a function on PPC, the arguments start after the linkage area,
2672 // although the first ones are often in registers.
2674 unsigned ArgOffset = LinkageSize;
2675 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2676 SmallVector<SDValue, 8> MemOps;
2677 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2678 unsigned CurArgIdx = 0;
2679 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2681 bool needsLoad = false;
2682 EVT ObjectVT = Ins[ArgNo].VT;
2683 EVT OrigVT = Ins[ArgNo].ArgVT;
2684 unsigned ObjSize = ObjectVT.getStoreSize();
2685 unsigned ArgSize = ObjSize;
2686 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2687 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2688 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2690 // We re-align the argument offset for each argument, except when using the
2691 // fast calling convention, when we need to make sure we do that only when
2692 // we'll actually use a stack slot.
2693 unsigned CurArgOffset, Align;
2694 auto ComputeArgOffset = [&]() {
2695 /* Respect alignment of argument on the stack. */
2696 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2697 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2698 CurArgOffset = ArgOffset;
2701 if (CallConv != CallingConv::Fast) {
2704 /* Compute GPR index associated with argument offset. */
2705 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2706 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2709 // FIXME the codegen can be much improved in some cases.
2710 // We do not have to keep everything in memory.
2711 if (Flags.isByVal()) {
2712 if (CallConv == CallingConv::Fast)
2715 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2716 ObjSize = Flags.getByValSize();
2717 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2718 // Empty aggregate parameters do not take up registers. Examples:
2722 // etc. However, we have to provide a place-holder in InVals, so
2723 // pretend we have an 8-byte item at the current address for that
2726 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2727 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2728 InVals.push_back(FIN);
2732 // Create a stack object covering all stack doublewords occupied
2733 // by the argument. If the argument is (fully or partially) on
2734 // the stack, or if the argument is fully in registers but the
2735 // caller has allocated the parameter save anyway, we can refer
2736 // directly to the caller's stack frame. Otherwise, create a
2737 // local copy in our own frame.
2739 if (HasParameterArea ||
2740 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2741 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2743 FI = MFI->CreateStackObject(ArgSize, Align, false);
2744 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2746 // Handle aggregates smaller than 8 bytes.
2747 if (ObjSize < PtrByteSize) {
2748 // The value of the object is its address, which differs from the
2749 // address of the enclosing doubleword on big-endian systems.
2751 if (!isLittleEndian) {
2752 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2753 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2755 InVals.push_back(Arg);
2757 if (GPR_idx != Num_GPR_Regs) {
2758 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2759 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2762 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2763 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2764 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2765 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2766 MachinePointerInfo(FuncArg),
2767 ObjType, false, false, 0);
2769 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2770 // store the whole register as-is to the parameter save area
2772 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2773 MachinePointerInfo(FuncArg),
2777 MemOps.push_back(Store);
2779 // Whether we copied from a register or not, advance the offset
2780 // into the parameter save area by a full doubleword.
2781 ArgOffset += PtrByteSize;
2785 // The value of the object is its address, which is the address of
2786 // its first stack doubleword.
2787 InVals.push_back(FIN);
2789 // Store whatever pieces of the object are in registers to memory.
2790 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2791 if (GPR_idx == Num_GPR_Regs)
2794 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2795 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2798 SDValue Off = DAG.getConstant(j, PtrVT);
2799 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2801 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2802 MachinePointerInfo(FuncArg, j),
2804 MemOps.push_back(Store);
2807 ArgOffset += ArgSize;
2811 switch (ObjectVT.getSimpleVT().SimpleTy) {
2812 default: llvm_unreachable("Unhandled argument type!");
2816 // These can be scalar arguments or elements of an integer array type
2817 // passed directly. Clang may use those instead of "byval" aggregate
2818 // types to avoid forcing arguments to memory unnecessarily.
2819 if (GPR_idx != Num_GPR_Regs) {
2820 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2821 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2823 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2824 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2825 // value to MVT::i64 and then truncate to the correct register size.
2826 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2828 if (CallConv == CallingConv::Fast)
2832 ArgSize = PtrByteSize;
2834 if (CallConv != CallingConv::Fast || needsLoad)
2840 // These can be scalar arguments or elements of a float array type
2841 // passed directly. The latter are used to implement ELFv2 homogenous
2842 // float aggregates.
2843 if (FPR_idx != Num_FPR_Regs) {
2846 if (ObjectVT == MVT::f32)
2847 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2849 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
2850 ? &PPC::VSFRCRegClass
2851 : &PPC::F8RCRegClass);
2853 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2855 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2856 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
2857 // once we support fp <-> gpr moves.
2859 // This can only ever happen in the presence of f32 array types,
2860 // since otherwise we never run out of FPRs before running out
2862 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2863 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2865 if (ObjectVT == MVT::f32) {
2866 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2867 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2868 DAG.getConstant(32, MVT::i32));
2869 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2872 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2874 if (CallConv == CallingConv::Fast)
2880 // When passing an array of floats, the array occupies consecutive
2881 // space in the argument area; only round up to the next doubleword
2882 // at the end of the array. Otherwise, each float takes 8 bytes.
2883 if (CallConv != CallingConv::Fast || needsLoad) {
2884 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2885 ArgOffset += ArgSize;
2886 if (Flags.isInConsecutiveRegsLast())
2887 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2896 // These can be scalar arguments or elements of a vector array type
2897 // passed directly. The latter are used to implement ELFv2 homogenous
2898 // vector aggregates.
2899 if (VR_idx != Num_VR_Regs) {
2900 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2901 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2902 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2903 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2906 if (CallConv == CallingConv::Fast)
2911 if (CallConv != CallingConv::Fast || needsLoad)
2916 // We need to load the argument to a virtual register if we determined
2917 // above that we ran out of physical registers of the appropriate type.
2919 if (ObjSize < ArgSize && !isLittleEndian)
2920 CurArgOffset += ArgSize - ObjSize;
2921 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2922 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2923 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2924 false, false, false, 0);
2927 InVals.push_back(ArgVal);
2930 // Area that is at least reserved in the caller of this function.
2931 unsigned MinReservedArea;
2932 if (HasParameterArea)
2933 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2935 MinReservedArea = LinkageSize;
2937 // Set the size that is at least reserved in caller of this function. Tail
2938 // call optimized functions' reserved stack space needs to be aligned so that
2939 // taking the difference between two stack areas will result in an aligned
2942 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2943 FuncInfo->setMinReservedArea(MinReservedArea);
2945 // If the function takes variable number of arguments, make a frame index for
2946 // the start of the first vararg value... for expansion of llvm.va_start.
2948 int Depth = ArgOffset;
2950 FuncInfo->setVarArgsFrameIndex(
2951 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2952 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2954 // If this function is vararg, store any remaining integer argument regs
2955 // to their spots on the stack so that they may be loaded by deferencing the
2956 // result of va_next.
2957 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2958 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2959 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2960 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2961 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2962 MachinePointerInfo(), false, false, 0);
2963 MemOps.push_back(Store);
2964 // Increment the address by four for the next argument to store
2965 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2966 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2970 if (!MemOps.empty())
2971 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2977 PPCTargetLowering::LowerFormalArguments_Darwin(
2979 CallingConv::ID CallConv, bool isVarArg,
2980 const SmallVectorImpl<ISD::InputArg>
2982 SDLoc dl, SelectionDAG &DAG,
2983 SmallVectorImpl<SDValue> &InVals) const {
2984 // TODO: add description of PPC stack frame format, or at least some docs.
2986 MachineFunction &MF = DAG.getMachineFunction();
2987 MachineFrameInfo *MFI = MF.getFrameInfo();
2988 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2990 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2991 bool isPPC64 = PtrVT == MVT::i64;
2992 // Potential tail calls could cause overwriting of argument stack slots.
2993 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2994 (CallConv == CallingConv::Fast));
2995 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2997 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2999 unsigned ArgOffset = LinkageSize;
3000 // Area that is at least reserved in caller of this function.
3001 unsigned MinReservedArea = ArgOffset;
3003 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3004 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3005 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3007 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3008 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3009 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3012 static const MCPhysReg *FPR = GetFPR();
3014 static const MCPhysReg VR[] = {
3015 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3016 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3019 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3020 const unsigned Num_FPR_Regs = 13;
3021 const unsigned Num_VR_Regs = array_lengthof( VR);
3023 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3025 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3027 // In 32-bit non-varargs functions, the stack space for vectors is after the
3028 // stack space for non-vectors. We do not use this space unless we have
3029 // too many vectors to fit in registers, something that only occurs in
3030 // constructed examples:), but we have to walk the arglist to figure
3031 // that out...for the pathological case, compute VecArgOffset as the
3032 // start of the vector parameter area. Computing VecArgOffset is the
3033 // entire point of the following loop.
3034 unsigned VecArgOffset = ArgOffset;
3035 if (!isVarArg && !isPPC64) {
3036 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3038 EVT ObjectVT = Ins[ArgNo].VT;
3039 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3041 if (Flags.isByVal()) {
3042 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3043 unsigned ObjSize = Flags.getByValSize();
3045 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3046 VecArgOffset += ArgSize;
3050 switch(ObjectVT.getSimpleVT().SimpleTy) {
3051 default: llvm_unreachable("Unhandled argument type!");
3057 case MVT::i64: // PPC64
3059 // FIXME: We are guaranteed to be !isPPC64 at this point.
3060 // Does MVT::i64 apply?
3067 // Nothing to do, we're only looking at Nonvector args here.
3072 // We've found where the vector parameter area in memory is. Skip the
3073 // first 12 parameters; these don't use that memory.
3074 VecArgOffset = ((VecArgOffset+15)/16)*16;
3075 VecArgOffset += 12*16;
3077 // Add DAG nodes to load the arguments or copy them out of registers. On
3078 // entry to a function on PPC, the arguments start after the linkage area,
3079 // although the first ones are often in registers.
3081 SmallVector<SDValue, 8> MemOps;
3082 unsigned nAltivecParamsAtEnd = 0;
3083 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3084 unsigned CurArgIdx = 0;
3085 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3087 bool needsLoad = false;
3088 EVT ObjectVT = Ins[ArgNo].VT;
3089 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3090 unsigned ArgSize = ObjSize;
3091 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3092 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3093 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3095 unsigned CurArgOffset = ArgOffset;
3097 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3098 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3099 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3100 if (isVarArg || isPPC64) {
3101 MinReservedArea = ((MinReservedArea+15)/16)*16;
3102 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3105 } else nAltivecParamsAtEnd++;
3107 // Calculate min reserved area.
3108 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3112 // FIXME the codegen can be much improved in some cases.
3113 // We do not have to keep everything in memory.
3114 if (Flags.isByVal()) {
3115 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3116 ObjSize = Flags.getByValSize();
3117 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3118 // Objects of size 1 and 2 are right justified, everything else is
3119 // left justified. This means the memory address is adjusted forwards.
3120 if (ObjSize==1 || ObjSize==2) {
3121 CurArgOffset = CurArgOffset + (4 - ObjSize);
3123 // The value of the object is its address.
3124 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3125 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3126 InVals.push_back(FIN);
3127 if (ObjSize==1 || ObjSize==2) {
3128 if (GPR_idx != Num_GPR_Regs) {
3131 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3133 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3134 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3135 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3136 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3137 MachinePointerInfo(FuncArg),
3138 ObjType, false, false, 0);
3139 MemOps.push_back(Store);
3143 ArgOffset += PtrByteSize;
3147 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3148 // Store whatever pieces of the object are in registers
3149 // to memory. ArgOffset will be the address of the beginning
3151 if (GPR_idx != Num_GPR_Regs) {
3154 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3156 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3157 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3158 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3159 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3160 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3161 MachinePointerInfo(FuncArg, j),
3163 MemOps.push_back(Store);
3165 ArgOffset += PtrByteSize;
3167 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3174 switch (ObjectVT.getSimpleVT().SimpleTy) {
3175 default: llvm_unreachable("Unhandled argument type!");
3179 if (GPR_idx != Num_GPR_Regs) {
3180 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3181 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3183 if (ObjectVT == MVT::i1)
3184 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3189 ArgSize = PtrByteSize;
3191 // All int arguments reserve stack space in the Darwin ABI.
3192 ArgOffset += PtrByteSize;
3196 case MVT::i64: // PPC64
3197 if (GPR_idx != Num_GPR_Regs) {
3198 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3199 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3201 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3202 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3203 // value to MVT::i64 and then truncate to the correct register size.
3204 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3209 ArgSize = PtrByteSize;
3211 // All int arguments reserve stack space in the Darwin ABI.
3217 // Every 4 bytes of argument space consumes one of the GPRs available for
3218 // argument passing.
3219 if (GPR_idx != Num_GPR_Regs) {
3221 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3224 if (FPR_idx != Num_FPR_Regs) {
3227 if (ObjectVT == MVT::f32)
3228 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3230 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3232 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3238 // All FP arguments reserve stack space in the Darwin ABI.
3239 ArgOffset += isPPC64 ? 8 : ObjSize;
3245 // Note that vector arguments in registers don't reserve stack space,
3246 // except in varargs functions.
3247 if (VR_idx != Num_VR_Regs) {
3248 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3249 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3251 while ((ArgOffset % 16) != 0) {
3252 ArgOffset += PtrByteSize;
3253 if (GPR_idx != Num_GPR_Regs)
3257 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3261 if (!isVarArg && !isPPC64) {
3262 // Vectors go after all the nonvectors.
3263 CurArgOffset = VecArgOffset;
3266 // Vectors are aligned.
3267 ArgOffset = ((ArgOffset+15)/16)*16;
3268 CurArgOffset = ArgOffset;
3276 // We need to load the argument to a virtual register if we determined above
3277 // that we ran out of physical registers of the appropriate type.
3279 int FI = MFI->CreateFixedObject(ObjSize,
3280 CurArgOffset + (ArgSize - ObjSize),
3282 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3283 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3284 false, false, false, 0);
3287 InVals.push_back(ArgVal);
3290 // Allow for Altivec parameters at the end, if needed.
3291 if (nAltivecParamsAtEnd) {
3292 MinReservedArea = ((MinReservedArea+15)/16)*16;
3293 MinReservedArea += 16*nAltivecParamsAtEnd;
3296 // Area that is at least reserved in the caller of this function.
3297 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3299 // Set the size that is at least reserved in caller of this function. Tail
3300 // call optimized functions' reserved stack space needs to be aligned so that
3301 // taking the difference between two stack areas will result in an aligned
3304 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3305 FuncInfo->setMinReservedArea(MinReservedArea);
3307 // If the function takes variable number of arguments, make a frame index for
3308 // the start of the first vararg value... for expansion of llvm.va_start.
3310 int Depth = ArgOffset;
3312 FuncInfo->setVarArgsFrameIndex(
3313 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3315 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3317 // If this function is vararg, store any remaining integer argument regs
3318 // to their spots on the stack so that they may be loaded by deferencing the
3319 // result of va_next.
3320 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3324 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3326 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3328 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3329 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3330 MachinePointerInfo(), false, false, 0);
3331 MemOps.push_back(Store);
3332 // Increment the address by four for the next argument to store
3333 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3334 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3338 if (!MemOps.empty())
3339 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3344 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3345 /// adjusted to accommodate the arguments for the tailcall.
3346 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3347 unsigned ParamSize) {
3349 if (!isTailCall) return 0;
3351 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3352 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3353 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3354 // Remember only if the new adjustement is bigger.
3355 if (SPDiff < FI->getTailCallSPDelta())
3356 FI->setTailCallSPDelta(SPDiff);
3361 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3362 /// for tail call optimization. Targets which want to do tail call
3363 /// optimization should implement this function.
3365 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3366 CallingConv::ID CalleeCC,
3368 const SmallVectorImpl<ISD::InputArg> &Ins,
3369 SelectionDAG& DAG) const {
3370 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3373 // Variable argument functions are not supported.
3377 MachineFunction &MF = DAG.getMachineFunction();
3378 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3379 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3380 // Functions containing by val parameters are not supported.
3381 for (unsigned i = 0; i != Ins.size(); i++) {
3382 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3383 if (Flags.isByVal()) return false;
3386 // Non-PIC/GOT tail calls are supported.
3387 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3390 // At the moment we can only do local tail calls (in same module, hidden
3391 // or protected) if we are generating PIC.
3392 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3393 return G->getGlobal()->hasHiddenVisibility()
3394 || G->getGlobal()->hasProtectedVisibility();
3400 /// isCallCompatibleAddress - Return the immediate to use if the specified
3401 /// 32-bit value is representable in the immediate field of a BxA instruction.
3402 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3404 if (!C) return nullptr;
3406 int Addr = C->getZExtValue();
3407 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3408 SignExtend32<26>(Addr) != Addr)
3409 return nullptr; // Top 6 bits have to be sext of immediate.
3411 return DAG.getConstant((int)C->getZExtValue() >> 2,
3412 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3417 struct TailCallArgumentInfo {
3422 TailCallArgumentInfo() : FrameIdx(0) {}
3427 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3429 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3431 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3432 SmallVectorImpl<SDValue> &MemOpChains,
3434 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3435 SDValue Arg = TailCallArgs[i].Arg;
3436 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3437 int FI = TailCallArgs[i].FrameIdx;
3438 // Store relative to framepointer.
3439 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3440 MachinePointerInfo::getFixedStack(FI),
3445 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3446 /// the appropriate stack slot for the tail call optimized function call.
3447 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3448 MachineFunction &MF,
3457 // Calculate the new stack slot for the return address.
3458 int SlotSize = isPPC64 ? 8 : 4;
3459 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3461 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3462 NewRetAddrLoc, true);
3463 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3464 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3465 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3466 MachinePointerInfo::getFixedStack(NewRetAddr),
3469 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3470 // slot as the FP is never overwritten.
3473 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3474 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3476 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3477 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3478 MachinePointerInfo::getFixedStack(NewFPIdx),
3485 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3486 /// the position of the argument.
3488 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3489 SDValue Arg, int SPDiff, unsigned ArgOffset,
3490 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3491 int Offset = ArgOffset + SPDiff;
3492 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3493 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3494 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3495 SDValue FIN = DAG.getFrameIndex(FI, VT);
3496 TailCallArgumentInfo Info;
3498 Info.FrameIdxOp = FIN;
3500 TailCallArguments.push_back(Info);
3503 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3504 /// stack slot. Returns the chain as result and the loaded frame pointers in
3505 /// LROpOut/FPOpout. Used when tail calling.
3506 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3514 // Load the LR and FP stack slot for later adjusting.
3515 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3516 LROpOut = getReturnAddrFrameIndex(DAG);
3517 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3518 false, false, false, 0);
3519 Chain = SDValue(LROpOut.getNode(), 1);
3521 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3522 // slot as the FP is never overwritten.
3524 FPOpOut = getFramePointerFrameIndex(DAG);
3525 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3526 false, false, false, 0);
3527 Chain = SDValue(FPOpOut.getNode(), 1);
3533 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3534 /// by "Src" to address "Dst" of size "Size". Alignment information is
3535 /// specified by the specific parameter attribute. The copy will be passed as
3536 /// a byval function parameter.
3537 /// Sometimes what we are copying is the end of a larger object, the part that
3538 /// does not fit in registers.
3540 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3541 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3543 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3544 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3545 false, false, MachinePointerInfo(),
3546 MachinePointerInfo());
3549 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3552 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3553 SDValue Arg, SDValue PtrOff, int SPDiff,
3554 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3555 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3556 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3558 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3563 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3565 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3566 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3567 DAG.getConstant(ArgOffset, PtrVT));
3569 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3570 MachinePointerInfo(), false, false, 0));
3571 // Calculate and remember argument location.
3572 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3577 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3578 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3579 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3580 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3581 MachineFunction &MF = DAG.getMachineFunction();
3583 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3584 // might overwrite each other in case of tail call optimization.
3585 SmallVector<SDValue, 8> MemOpChains2;
3586 // Do not flag preceding copytoreg stuff together with the following stuff.
3588 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3590 if (!MemOpChains2.empty())
3591 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3593 // Store the return address to the appropriate stack slot.
3594 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3595 isPPC64, isDarwinABI, dl);
3597 // Emit callseq_end just before tailcall node.
3598 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3599 DAG.getIntPtrConstant(0, true), InFlag, dl);
3600 InFlag = Chain.getValue(1);
3603 // Is this global address that of a function that can be called by name? (as
3604 // opposed to something that must hold a descriptor for an indirect call).
3605 static bool isFunctionGlobalAddress(SDValue Callee) {
3606 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3607 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3608 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3611 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3618 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3619 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3620 bool isTailCall, bool IsPatchPoint,
3621 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3622 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3623 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3625 bool isPPC64 = Subtarget.isPPC64();
3626 bool isSVR4ABI = Subtarget.isSVR4ABI();
3627 bool isELFv2ABI = Subtarget.isELFv2ABI();
3629 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3630 NodeTys.push_back(MVT::Other); // Returns a chain
3631 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3633 unsigned CallOpc = PPCISD::CALL;
3635 bool needIndirectCall = true;
3636 if (!isSVR4ABI || !isPPC64)
3637 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3638 // If this is an absolute destination address, use the munged value.
3639 Callee = SDValue(Dest, 0);
3640 needIndirectCall = false;
3643 if (isFunctionGlobalAddress(Callee)) {
3644 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3645 // A call to a TLS address is actually an indirect call to a
3646 // thread-specific pointer.
3647 unsigned OpFlags = 0;
3648 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3649 (Subtarget.getTargetTriple().isMacOSX() &&
3650 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3651 (G->getGlobal()->isDeclaration() ||
3652 G->getGlobal()->isWeakForLinker())) ||
3653 (Subtarget.isTargetELF() && !isPPC64 &&
3654 !G->getGlobal()->hasLocalLinkage() &&
3655 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3656 // PC-relative references to external symbols should go through $stub,
3657 // unless we're building with the leopard linker or later, which
3658 // automatically synthesizes these stubs.
3659 OpFlags = PPCII::MO_PLT_OR_STUB;
3662 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3663 // every direct call is) turn it into a TargetGlobalAddress /
3664 // TargetExternalSymbol node so that legalize doesn't hack it.
3665 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3666 Callee.getValueType(), 0, OpFlags);
3667 needIndirectCall = false;
3670 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3671 unsigned char OpFlags = 0;
3673 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3674 (Subtarget.getTargetTriple().isMacOSX() &&
3675 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3676 (Subtarget.isTargetELF() && !isPPC64 &&
3677 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3678 // PC-relative references to external symbols should go through $stub,
3679 // unless we're building with the leopard linker or later, which
3680 // automatically synthesizes these stubs.
3681 OpFlags = PPCII::MO_PLT_OR_STUB;
3684 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3686 needIndirectCall = false;
3690 // We'll form an invalid direct call when lowering a patchpoint; the full
3691 // sequence for an indirect call is complicated, and many of the
3692 // instructions introduced might have side effects (and, thus, can't be
3693 // removed later). The call itself will be removed as soon as the
3694 // argument/return lowering is complete, so the fact that it has the wrong
3695 // kind of operands should not really matter.
3696 needIndirectCall = false;
3699 if (needIndirectCall) {
3700 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3701 // to do the call, we can't use PPCISD::CALL.
3702 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3704 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3705 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3706 // entry point, but to the function descriptor (the function entry point
3707 // address is part of the function descriptor though).
3708 // The function descriptor is a three doubleword structure with the
3709 // following fields: function entry point, TOC base address and
3710 // environment pointer.
3711 // Thus for a call through a function pointer, the following actions need
3713 // 1. Save the TOC of the caller in the TOC save area of its stack
3714 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3715 // 2. Load the address of the function entry point from the function
3717 // 3. Load the TOC of the callee from the function descriptor into r2.
3718 // 4. Load the environment pointer from the function descriptor into
3720 // 5. Branch to the function entry point address.
3721 // 6. On return of the callee, the TOC of the caller needs to be
3722 // restored (this is done in FinishCall()).
3724 // The loads are scheduled at the beginning of the call sequence, and the
3725 // register copies are flagged together to ensure that no other
3726 // operations can be scheduled in between. E.g. without flagging the
3727 // copies together, a TOC access in the caller could be scheduled between
3728 // the assignment of the callee TOC and the branch to the callee, which
3729 // results in the TOC access going through the TOC of the callee instead
3730 // of going through the TOC of the caller, which leads to incorrect code.
3732 // Load the address of the function entry point from the function
3734 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3735 if (LDChain.getValueType() == MVT::Glue)
3736 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3738 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3740 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3741 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3742 false, false, LoadsInv, 8);
3744 // Load environment pointer into r11.
3745 SDValue PtrOff = DAG.getIntPtrConstant(16);
3746 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3747 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3748 MPI.getWithOffset(16), false, false,
3751 SDValue TOCOff = DAG.getIntPtrConstant(8);
3752 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3753 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3754 MPI.getWithOffset(8), false, false,
3757 setUsesTOCBasePtr(DAG);
3758 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3760 Chain = TOCVal.getValue(0);
3761 InFlag = TOCVal.getValue(1);
3763 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3766 Chain = EnvVal.getValue(0);
3767 InFlag = EnvVal.getValue(1);
3769 MTCTROps[0] = Chain;
3770 MTCTROps[1] = LoadFuncPtr;
3771 MTCTROps[2] = InFlag;
3774 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3775 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3776 InFlag = Chain.getValue(1);
3779 NodeTys.push_back(MVT::Other);
3780 NodeTys.push_back(MVT::Glue);
3781 Ops.push_back(Chain);
3782 CallOpc = PPCISD::BCTRL;
3783 Callee.setNode(nullptr);
3784 // Add use of X11 (holding environment pointer)
3785 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3786 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3787 // Add CTR register as callee so a bctr can be emitted later.
3789 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3792 // If this is a direct call, pass the chain and the callee.
3793 if (Callee.getNode()) {
3794 Ops.push_back(Chain);
3795 Ops.push_back(Callee);
3797 // If this is a tail call add stack pointer delta.
3799 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3801 // Add argument registers to the end of the list so that they are known live
3803 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3804 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3805 RegsToPass[i].second.getValueType()));
3807 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
3809 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
3810 setUsesTOCBasePtr(DAG);
3811 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3818 bool isLocalCall(const SDValue &Callee)
3820 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3821 return !G->getGlobal()->isDeclaration() &&
3822 !G->getGlobal()->isWeakForLinker();
3827 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3828 CallingConv::ID CallConv, bool isVarArg,
3829 const SmallVectorImpl<ISD::InputArg> &Ins,
3830 SDLoc dl, SelectionDAG &DAG,
3831 SmallVectorImpl<SDValue> &InVals) const {
3833 SmallVector<CCValAssign, 16> RVLocs;
3834 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3836 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3838 // Copy all of the result registers out of their specified physreg.
3839 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3840 CCValAssign &VA = RVLocs[i];
3841 assert(VA.isRegLoc() && "Can only return in registers!");
3843 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3844 VA.getLocReg(), VA.getLocVT(), InFlag);
3845 Chain = Val.getValue(1);
3846 InFlag = Val.getValue(2);
3848 switch (VA.getLocInfo()) {
3849 default: llvm_unreachable("Unknown loc info!");
3850 case CCValAssign::Full: break;
3851 case CCValAssign::AExt:
3852 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3854 case CCValAssign::ZExt:
3855 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3856 DAG.getValueType(VA.getValVT()));
3857 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3859 case CCValAssign::SExt:
3860 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3861 DAG.getValueType(VA.getValVT()));
3862 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3866 InVals.push_back(Val);
3873 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3874 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3876 SmallVector<std::pair<unsigned, SDValue>, 8>
3878 SDValue InFlag, SDValue Chain,
3879 SDValue CallSeqStart, SDValue &Callee,
3880 int SPDiff, unsigned NumBytes,
3881 const SmallVectorImpl<ISD::InputArg> &Ins,
3882 SmallVectorImpl<SDValue> &InVals,
3883 ImmutableCallSite *CS) const {
3885 bool isELFv2ABI = Subtarget.isELFv2ABI();
3886 std::vector<EVT> NodeTys;
3887 SmallVector<SDValue, 8> Ops;
3888 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3889 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3890 Ops, NodeTys, CS, Subtarget);
3892 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3893 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3894 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3896 // When performing tail call optimization the callee pops its arguments off
3897 // the stack. Account for this here so these bytes can be pushed back on in
3898 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3899 int BytesCalleePops =
3900 (CallConv == CallingConv::Fast &&
3901 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3903 // Add a register mask operand representing the call-preserved registers.
3904 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3905 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3906 assert(Mask && "Missing call preserved mask for calling convention");
3907 Ops.push_back(DAG.getRegisterMask(Mask));
3909 if (InFlag.getNode())
3910 Ops.push_back(InFlag);
3914 assert(((Callee.getOpcode() == ISD::Register &&
3915 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3916 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3917 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3918 isa<ConstantSDNode>(Callee)) &&
3919 "Expecting an global address, external symbol, absolute value or register");
3921 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3924 // Add a NOP immediately after the branch instruction when using the 64-bit
3925 // SVR4 ABI. At link time, if caller and callee are in a different module and
3926 // thus have a different TOC, the call will be replaced with a call to a stub
3927 // function which saves the current TOC, loads the TOC of the callee and
3928 // branches to the callee. The NOP will be replaced with a load instruction
3929 // which restores the TOC of the caller from the TOC save slot of the current
3930 // stack frame. If caller and callee belong to the same module (and have the
3931 // same TOC), the NOP will remain unchanged.
3933 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3935 if (CallOpc == PPCISD::BCTRL) {
3936 // This is a call through a function pointer.
3937 // Restore the caller TOC from the save area into R2.
3938 // See PrepareCall() for more information about calls through function
3939 // pointers in the 64-bit SVR4 ABI.
3940 // We are using a target-specific load with r2 hard coded, because the
3941 // result of a target-independent load would never go directly into r2,
3942 // since r2 is a reserved register (which prevents the register allocator
3943 // from allocating it), resulting in an additional register being
3944 // allocated and an unnecessary move instruction being generated.
3945 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3947 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3948 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3949 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3950 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3951 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3953 // The address needs to go after the chain input but before the flag (or
3954 // any other variadic arguments).
3955 Ops.insert(std::next(Ops.begin()), AddTOC);
3956 } else if ((CallOpc == PPCISD::CALL) &&
3957 (!isLocalCall(Callee) ||
3958 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
3959 // Otherwise insert NOP for non-local calls.
3960 CallOpc = PPCISD::CALL_NOP;
3963 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3964 InFlag = Chain.getValue(1);
3966 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3967 DAG.getIntPtrConstant(BytesCalleePops, true),
3970 InFlag = Chain.getValue(1);
3972 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3973 Ins, dl, DAG, InVals);
3977 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3978 SmallVectorImpl<SDValue> &InVals) const {
3979 SelectionDAG &DAG = CLI.DAG;
3981 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3982 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3983 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3984 SDValue Chain = CLI.Chain;
3985 SDValue Callee = CLI.Callee;
3986 bool &isTailCall = CLI.IsTailCall;
3987 CallingConv::ID CallConv = CLI.CallConv;
3988 bool isVarArg = CLI.IsVarArg;
3989 bool IsPatchPoint = CLI.IsPatchPoint;
3990 ImmutableCallSite *CS = CLI.CS;
3993 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3996 if (!isTailCall && CS && CS->isMustTailCall())
3997 report_fatal_error("failed to perform tail call elimination on a call "
3998 "site marked musttail");
4000 if (Subtarget.isSVR4ABI()) {
4001 if (Subtarget.isPPC64())
4002 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4003 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4004 dl, DAG, InVals, CS);
4006 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4007 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4008 dl, DAG, InVals, CS);
4011 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4012 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4013 dl, DAG, InVals, CS);
4017 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4018 CallingConv::ID CallConv, bool isVarArg,
4019 bool isTailCall, bool IsPatchPoint,
4020 const SmallVectorImpl<ISD::OutputArg> &Outs,
4021 const SmallVectorImpl<SDValue> &OutVals,
4022 const SmallVectorImpl<ISD::InputArg> &Ins,
4023 SDLoc dl, SelectionDAG &DAG,
4024 SmallVectorImpl<SDValue> &InVals,
4025 ImmutableCallSite *CS) const {
4026 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4027 // of the 32-bit SVR4 ABI stack frame layout.
4029 assert((CallConv == CallingConv::C ||
4030 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4032 unsigned PtrByteSize = 4;
4034 MachineFunction &MF = DAG.getMachineFunction();
4036 // Mark this function as potentially containing a function that contains a
4037 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4038 // and restoring the callers stack pointer in this functions epilog. This is
4039 // done because by tail calling the called function might overwrite the value
4040 // in this function's (MF) stack pointer stack slot 0(SP).
4041 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4042 CallConv == CallingConv::Fast)
4043 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4045 // Count how many bytes are to be pushed on the stack, including the linkage
4046 // area, parameter list area and the part of the local variable space which
4047 // contains copies of aggregates which are passed by value.
4049 // Assign locations to all of the outgoing arguments.
4050 SmallVector<CCValAssign, 16> ArgLocs;
4051 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4054 // Reserve space for the linkage area on the stack.
4055 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4059 // Handle fixed and variable vector arguments differently.
4060 // Fixed vector arguments go into registers as long as registers are
4061 // available. Variable vector arguments always go into memory.
4062 unsigned NumArgs = Outs.size();
4064 for (unsigned i = 0; i != NumArgs; ++i) {
4065 MVT ArgVT = Outs[i].VT;
4066 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4069 if (Outs[i].IsFixed) {
4070 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4073 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4079 errs() << "Call operand #" << i << " has unhandled type "
4080 << EVT(ArgVT).getEVTString() << "\n";
4082 llvm_unreachable(nullptr);
4086 // All arguments are treated the same.
4087 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4090 // Assign locations to all of the outgoing aggregate by value arguments.
4091 SmallVector<CCValAssign, 16> ByValArgLocs;
4092 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4093 ByValArgLocs, *DAG.getContext());
4095 // Reserve stack space for the allocations in CCInfo.
4096 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4098 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4100 // Size of the linkage area, parameter list area and the part of the local
4101 // space variable where copies of aggregates which are passed by value are
4103 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4105 // Calculate by how many bytes the stack has to be adjusted in case of tail
4106 // call optimization.
4107 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4109 // Adjust the stack pointer for the new arguments...
4110 // These operations are automatically eliminated by the prolog/epilog pass
4111 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4113 SDValue CallSeqStart = Chain;
4115 // Load the return address and frame pointer so it can be moved somewhere else
4118 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4121 // Set up a copy of the stack pointer for use loading and storing any
4122 // arguments that may not fit in the registers available for argument
4124 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4126 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4127 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4128 SmallVector<SDValue, 8> MemOpChains;
4130 bool seenFloatArg = false;
4131 // Walk the register/memloc assignments, inserting copies/loads.
4132 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4135 CCValAssign &VA = ArgLocs[i];
4136 SDValue Arg = OutVals[i];
4137 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4139 if (Flags.isByVal()) {
4140 // Argument is an aggregate which is passed by value, thus we need to
4141 // create a copy of it in the local variable space of the current stack
4142 // frame (which is the stack frame of the caller) and pass the address of
4143 // this copy to the callee.
4144 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4145 CCValAssign &ByValVA = ByValArgLocs[j++];
4146 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4148 // Memory reserved in the local variable space of the callers stack frame.
4149 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4151 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4152 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4154 // Create a copy of the argument in the local area of the current
4156 SDValue MemcpyCall =
4157 CreateCopyOfByValArgument(Arg, PtrOff,
4158 CallSeqStart.getNode()->getOperand(0),
4161 // This must go outside the CALLSEQ_START..END.
4162 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4163 CallSeqStart.getNode()->getOperand(1),
4165 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4166 NewCallSeqStart.getNode());
4167 Chain = CallSeqStart = NewCallSeqStart;
4169 // Pass the address of the aggregate copy on the stack either in a
4170 // physical register or in the parameter list area of the current stack
4171 // frame to the callee.
4175 if (VA.isRegLoc()) {
4176 if (Arg.getValueType() == MVT::i1)
4177 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4179 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4180 // Put argument in a physical register.
4181 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4183 // Put argument in the parameter list area of the current stack frame.
4184 assert(VA.isMemLoc());
4185 unsigned LocMemOffset = VA.getLocMemOffset();
4188 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4189 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4191 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4192 MachinePointerInfo(),
4195 // Calculate and remember argument location.
4196 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4202 if (!MemOpChains.empty())
4203 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4205 // Build a sequence of copy-to-reg nodes chained together with token chain
4206 // and flag operands which copy the outgoing args into the appropriate regs.
4208 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4209 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4210 RegsToPass[i].second, InFlag);
4211 InFlag = Chain.getValue(1);
4214 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4217 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4218 SDValue Ops[] = { Chain, InFlag };
4220 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4221 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4223 InFlag = Chain.getValue(1);
4227 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4228 false, TailCallArguments);
4230 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4231 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4232 NumBytes, Ins, InVals, CS);
4235 // Copy an argument into memory, being careful to do this outside the
4236 // call sequence for the call to which the argument belongs.
4238 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4239 SDValue CallSeqStart,
4240 ISD::ArgFlagsTy Flags,
4243 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4244 CallSeqStart.getNode()->getOperand(0),
4246 // The MEMCPY must go outside the CALLSEQ_START..END.
4247 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4248 CallSeqStart.getNode()->getOperand(1),
4250 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4251 NewCallSeqStart.getNode());
4252 return NewCallSeqStart;
4256 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4257 CallingConv::ID CallConv, bool isVarArg,
4258 bool isTailCall, bool IsPatchPoint,
4259 const SmallVectorImpl<ISD::OutputArg> &Outs,
4260 const SmallVectorImpl<SDValue> &OutVals,
4261 const SmallVectorImpl<ISD::InputArg> &Ins,
4262 SDLoc dl, SelectionDAG &DAG,
4263 SmallVectorImpl<SDValue> &InVals,
4264 ImmutableCallSite *CS) const {
4266 bool isELFv2ABI = Subtarget.isELFv2ABI();
4267 bool isLittleEndian = Subtarget.isLittleEndian();
4268 unsigned NumOps = Outs.size();
4270 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4271 unsigned PtrByteSize = 8;
4273 MachineFunction &MF = DAG.getMachineFunction();
4275 // Mark this function as potentially containing a function that contains a
4276 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4277 // and restoring the callers stack pointer in this functions epilog. This is
4278 // done because by tail calling the called function might overwrite the value
4279 // in this function's (MF) stack pointer stack slot 0(SP).
4280 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4281 CallConv == CallingConv::Fast)
4282 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4284 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4285 "fastcc not supported on varargs functions");
4287 // Count how many bytes are to be pushed on the stack, including the linkage
4288 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4289 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4290 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4291 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4293 unsigned NumBytes = LinkageSize;
4294 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4296 static const MCPhysReg GPR[] = {
4297 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4298 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4300 static const MCPhysReg *FPR = GetFPR();
4302 static const MCPhysReg VR[] = {
4303 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4304 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4306 static const MCPhysReg VSRH[] = {
4307 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4308 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4311 const unsigned NumGPRs = array_lengthof(GPR);
4312 const unsigned NumFPRs = 13;
4313 const unsigned NumVRs = array_lengthof(VR);
4315 // When using the fast calling convention, we don't provide backing for
4316 // arguments that will be in registers.
4317 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4319 // Add up all the space actually used.
4320 for (unsigned i = 0; i != NumOps; ++i) {
4321 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4322 EVT ArgVT = Outs[i].VT;
4323 EVT OrigVT = Outs[i].ArgVT;
4325 if (CallConv == CallingConv::Fast) {
4326 if (Flags.isByVal())
4327 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4329 switch (ArgVT.getSimpleVT().SimpleTy) {
4330 default: llvm_unreachable("Unexpected ValueType for argument!");
4334 if (++NumGPRsUsed <= NumGPRs)
4339 if (++NumFPRsUsed <= NumFPRs)
4348 if (++NumVRsUsed <= NumVRs)
4354 /* Respect alignment of argument on the stack. */
4356 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4357 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4359 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4360 if (Flags.isInConsecutiveRegsLast())
4361 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4364 unsigned NumBytesActuallyUsed = NumBytes;
4366 // The prolog code of the callee may store up to 8 GPR argument registers to
4367 // the stack, allowing va_start to index over them in memory if its varargs.
4368 // Because we cannot tell if this is needed on the caller side, we have to
4369 // conservatively assume that it is needed. As such, make sure we have at
4370 // least enough stack space for the caller to store the 8 GPRs.
4371 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4372 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4374 // Tail call needs the stack to be aligned.
4375 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4376 CallConv == CallingConv::Fast)
4377 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4379 // Calculate by how many bytes the stack has to be adjusted in case of tail
4380 // call optimization.
4381 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4383 // To protect arguments on the stack from being clobbered in a tail call,
4384 // force all the loads to happen before doing any other lowering.
4386 Chain = DAG.getStackArgumentTokenFactor(Chain);
4388 // Adjust the stack pointer for the new arguments...
4389 // These operations are automatically eliminated by the prolog/epilog pass
4390 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4392 SDValue CallSeqStart = Chain;
4394 // Load the return address and frame pointer so it can be move somewhere else
4397 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4400 // Set up a copy of the stack pointer for use loading and storing any
4401 // arguments that may not fit in the registers available for argument
4403 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4405 // Figure out which arguments are going to go in registers, and which in
4406 // memory. Also, if this is a vararg function, floating point operations
4407 // must be stored to our stack, and loaded into integer regs as well, if
4408 // any integer regs are available for argument passing.
4409 unsigned ArgOffset = LinkageSize;
4411 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4412 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4414 SmallVector<SDValue, 8> MemOpChains;
4415 for (unsigned i = 0; i != NumOps; ++i) {
4416 SDValue Arg = OutVals[i];
4417 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4418 EVT ArgVT = Outs[i].VT;
4419 EVT OrigVT = Outs[i].ArgVT;
4421 // PtrOff will be used to store the current argument to the stack if a
4422 // register cannot be found for it.
4425 // We re-align the argument offset for each argument, except when using the
4426 // fast calling convention, when we need to make sure we do that only when
4427 // we'll actually use a stack slot.
4428 auto ComputePtrOff = [&]() {
4429 /* Respect alignment of argument on the stack. */
4431 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4432 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4434 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4436 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4439 if (CallConv != CallingConv::Fast) {
4442 /* Compute GPR index associated with argument offset. */
4443 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4444 GPR_idx = std::min(GPR_idx, NumGPRs);
4447 // Promote integers to 64-bit values.
4448 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4449 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4450 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4451 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4454 // FIXME memcpy is used way more than necessary. Correctness first.
4455 // Note: "by value" is code for passing a structure by value, not
4457 if (Flags.isByVal()) {
4458 // Note: Size includes alignment padding, so
4459 // struct x { short a; char b; }
4460 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4461 // These are the proper values we need for right-justifying the
4462 // aggregate in a parameter register.
4463 unsigned Size = Flags.getByValSize();
4465 // An empty aggregate parameter takes up no storage and no
4470 if (CallConv == CallingConv::Fast)
4473 // All aggregates smaller than 8 bytes must be passed right-justified.
4474 if (Size==1 || Size==2 || Size==4) {
4475 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4476 if (GPR_idx != NumGPRs) {
4477 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4478 MachinePointerInfo(), VT,
4479 false, false, false, 0);
4480 MemOpChains.push_back(Load.getValue(1));
4481 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4483 ArgOffset += PtrByteSize;
4488 if (GPR_idx == NumGPRs && Size < 8) {
4489 SDValue AddPtr = PtrOff;
4490 if (!isLittleEndian) {
4491 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4492 PtrOff.getValueType());
4493 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4495 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4498 ArgOffset += PtrByteSize;
4501 // Copy entire object into memory. There are cases where gcc-generated
4502 // code assumes it is there, even if it could be put entirely into
4503 // registers. (This is not what the doc says.)
4505 // FIXME: The above statement is likely due to a misunderstanding of the
4506 // documents. All arguments must be copied into the parameter area BY
4507 // THE CALLEE in the event that the callee takes the address of any
4508 // formal argument. That has not yet been implemented. However, it is
4509 // reasonable to use the stack area as a staging area for the register
4512 // Skip this for small aggregates, as we will use the same slot for a
4513 // right-justified copy, below.
4515 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4519 // When a register is available, pass a small aggregate right-justified.
4520 if (Size < 8 && GPR_idx != NumGPRs) {
4521 // The easiest way to get this right-justified in a register
4522 // is to copy the structure into the rightmost portion of a
4523 // local variable slot, then load the whole slot into the
4525 // FIXME: The memcpy seems to produce pretty awful code for
4526 // small aggregates, particularly for packed ones.
4527 // FIXME: It would be preferable to use the slot in the
4528 // parameter save area instead of a new local variable.
4529 SDValue AddPtr = PtrOff;
4530 if (!isLittleEndian) {
4531 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4532 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4534 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4538 // Load the slot into the register.
4539 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4540 MachinePointerInfo(),
4541 false, false, false, 0);
4542 MemOpChains.push_back(Load.getValue(1));
4543 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4545 // Done with this argument.
4546 ArgOffset += PtrByteSize;
4550 // For aggregates larger than PtrByteSize, copy the pieces of the
4551 // object that fit into registers from the parameter save area.
4552 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4553 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4554 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4555 if (GPR_idx != NumGPRs) {
4556 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4557 MachinePointerInfo(),
4558 false, false, false, 0);
4559 MemOpChains.push_back(Load.getValue(1));
4560 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4561 ArgOffset += PtrByteSize;
4563 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4570 switch (Arg.getSimpleValueType().SimpleTy) {
4571 default: llvm_unreachable("Unexpected ValueType for argument!");
4575 // These can be scalar arguments or elements of an integer array type
4576 // passed directly. Clang may use those instead of "byval" aggregate
4577 // types to avoid forcing arguments to memory unnecessarily.
4578 if (GPR_idx != NumGPRs) {
4579 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4581 if (CallConv == CallingConv::Fast)
4584 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4585 true, isTailCall, false, MemOpChains,
4586 TailCallArguments, dl);
4587 if (CallConv == CallingConv::Fast)
4588 ArgOffset += PtrByteSize;
4590 if (CallConv != CallingConv::Fast)
4591 ArgOffset += PtrByteSize;
4595 // These can be scalar arguments or elements of a float array type
4596 // passed directly. The latter are used to implement ELFv2 homogenous
4597 // float aggregates.
4599 // Named arguments go into FPRs first, and once they overflow, the
4600 // remaining arguments go into GPRs and then the parameter save area.
4601 // Unnamed arguments for vararg functions always go to GPRs and
4602 // then the parameter save area. For now, put all arguments to vararg
4603 // routines always in both locations (FPR *and* GPR or stack slot).
4604 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4605 bool NeededLoad = false;
4607 // First load the argument into the next available FPR.
4608 if (FPR_idx != NumFPRs)
4609 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4611 // Next, load the argument into GPR or stack slot if needed.
4612 if (!NeedGPROrStack)
4614 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4615 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4616 // once we support fp <-> gpr moves.
4618 // In the non-vararg case, this can only ever happen in the
4619 // presence of f32 array types, since otherwise we never run
4620 // out of FPRs before running out of GPRs.
4623 // Double values are always passed in a single GPR.
4624 if (Arg.getValueType() != MVT::f32) {
4625 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4627 // Non-array float values are extended and passed in a GPR.
4628 } else if (!Flags.isInConsecutiveRegs()) {
4629 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4630 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4632 // If we have an array of floats, we collect every odd element
4633 // together with its predecessor into one GPR.
4634 } else if (ArgOffset % PtrByteSize != 0) {
4636 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4637 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4638 if (!isLittleEndian)
4640 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4642 // The final element, if even, goes into the first half of a GPR.
4643 } else if (Flags.isInConsecutiveRegsLast()) {
4644 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4645 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4646 if (!isLittleEndian)
4647 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4648 DAG.getConstant(32, MVT::i32));
4650 // Non-final even elements are skipped; they will be handled
4651 // together the with subsequent argument on the next go-around.
4655 if (ArgVal.getNode())
4656 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4658 if (CallConv == CallingConv::Fast)
4661 // Single-precision floating-point values are mapped to the
4662 // second (rightmost) word of the stack doubleword.
4663 if (Arg.getValueType() == MVT::f32 &&
4664 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4665 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4666 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4669 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4670 true, isTailCall, false, MemOpChains,
4671 TailCallArguments, dl);
4675 // When passing an array of floats, the array occupies consecutive
4676 // space in the argument area; only round up to the next doubleword
4677 // at the end of the array. Otherwise, each float takes 8 bytes.
4678 if (CallConv != CallingConv::Fast || NeededLoad) {
4679 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4680 Flags.isInConsecutiveRegs()) ? 4 : 8;
4681 if (Flags.isInConsecutiveRegsLast())
4682 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4692 // These can be scalar arguments or elements of a vector array type
4693 // passed directly. The latter are used to implement ELFv2 homogenous
4694 // vector aggregates.
4696 // For a varargs call, named arguments go into VRs or on the stack as
4697 // usual; unnamed arguments always go to the stack or the corresponding
4698 // GPRs when within range. For now, we always put the value in both
4699 // locations (or even all three).
4701 // We could elide this store in the case where the object fits
4702 // entirely in R registers. Maybe later.
4703 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4704 MachinePointerInfo(), false, false, 0);
4705 MemOpChains.push_back(Store);
4706 if (VR_idx != NumVRs) {
4707 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4708 MachinePointerInfo(),
4709 false, false, false, 0);
4710 MemOpChains.push_back(Load.getValue(1));
4712 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4713 Arg.getSimpleValueType() == MVT::v2i64) ?
4714 VSRH[VR_idx] : VR[VR_idx];
4717 RegsToPass.push_back(std::make_pair(VReg, Load));
4720 for (unsigned i=0; i<16; i+=PtrByteSize) {
4721 if (GPR_idx == NumGPRs)
4723 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4724 DAG.getConstant(i, PtrVT));
4725 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4726 false, false, false, 0);
4727 MemOpChains.push_back(Load.getValue(1));
4728 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4733 // Non-varargs Altivec params go into VRs or on the stack.
4734 if (VR_idx != NumVRs) {
4735 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4736 Arg.getSimpleValueType() == MVT::v2i64) ?
4737 VSRH[VR_idx] : VR[VR_idx];
4740 RegsToPass.push_back(std::make_pair(VReg, Arg));
4742 if (CallConv == CallingConv::Fast)
4745 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4746 true, isTailCall, true, MemOpChains,
4747 TailCallArguments, dl);
4748 if (CallConv == CallingConv::Fast)
4752 if (CallConv != CallingConv::Fast)
4758 assert(NumBytesActuallyUsed == ArgOffset);
4759 (void)NumBytesActuallyUsed;
4761 if (!MemOpChains.empty())
4762 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4764 // Check if this is an indirect call (MTCTR/BCTRL).
4765 // See PrepareCall() for more information about calls through function
4766 // pointers in the 64-bit SVR4 ABI.
4767 if (!isTailCall && !IsPatchPoint &&
4768 !isFunctionGlobalAddress(Callee) &&
4769 !isa<ExternalSymbolSDNode>(Callee)) {
4770 // Load r2 into a virtual register and store it to the TOC save area.
4771 setUsesTOCBasePtr(DAG);
4772 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4773 // TOC save area offset.
4774 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4775 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4776 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4777 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4778 MachinePointerInfo::getStack(TOCSaveOffset),
4780 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4781 // This does not mean the MTCTR instruction must use R12; it's easier
4782 // to model this as an extra parameter, so do that.
4783 if (isELFv2ABI && !IsPatchPoint)
4784 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4787 // Build a sequence of copy-to-reg nodes chained together with token chain
4788 // and flag operands which copy the outgoing args into the appropriate regs.
4790 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4791 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4792 RegsToPass[i].second, InFlag);
4793 InFlag = Chain.getValue(1);
4797 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4798 FPOp, true, TailCallArguments);
4800 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4801 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4802 NumBytes, Ins, InVals, CS);
4806 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4807 CallingConv::ID CallConv, bool isVarArg,
4808 bool isTailCall, bool IsPatchPoint,
4809 const SmallVectorImpl<ISD::OutputArg> &Outs,
4810 const SmallVectorImpl<SDValue> &OutVals,
4811 const SmallVectorImpl<ISD::InputArg> &Ins,
4812 SDLoc dl, SelectionDAG &DAG,
4813 SmallVectorImpl<SDValue> &InVals,
4814 ImmutableCallSite *CS) const {
4816 unsigned NumOps = Outs.size();
4818 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4819 bool isPPC64 = PtrVT == MVT::i64;
4820 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4822 MachineFunction &MF = DAG.getMachineFunction();
4824 // Mark this function as potentially containing a function that contains a
4825 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4826 // and restoring the callers stack pointer in this functions epilog. This is
4827 // done because by tail calling the called function might overwrite the value
4828 // in this function's (MF) stack pointer stack slot 0(SP).
4829 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4830 CallConv == CallingConv::Fast)
4831 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4833 // Count how many bytes are to be pushed on the stack, including the linkage
4834 // area, and parameter passing area. We start with 24/48 bytes, which is
4835 // prereserved space for [SP][CR][LR][3 x unused].
4836 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4838 unsigned NumBytes = LinkageSize;
4840 // Add up all the space actually used.
4841 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4842 // they all go in registers, but we must reserve stack space for them for
4843 // possible use by the caller. In varargs or 64-bit calls, parameters are
4844 // assigned stack space in order, with padding so Altivec parameters are
4846 unsigned nAltivecParamsAtEnd = 0;
4847 for (unsigned i = 0; i != NumOps; ++i) {
4848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4849 EVT ArgVT = Outs[i].VT;
4850 // Varargs Altivec parameters are padded to a 16 byte boundary.
4851 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4852 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4853 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4854 if (!isVarArg && !isPPC64) {
4855 // Non-varargs Altivec parameters go after all the non-Altivec
4856 // parameters; handle those later so we know how much padding we need.
4857 nAltivecParamsAtEnd++;
4860 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4861 NumBytes = ((NumBytes+15)/16)*16;
4863 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4866 // Allow for Altivec parameters at the end, if needed.
4867 if (nAltivecParamsAtEnd) {
4868 NumBytes = ((NumBytes+15)/16)*16;
4869 NumBytes += 16*nAltivecParamsAtEnd;
4872 // The prolog code of the callee may store up to 8 GPR argument registers to
4873 // the stack, allowing va_start to index over them in memory if its varargs.
4874 // Because we cannot tell if this is needed on the caller side, we have to
4875 // conservatively assume that it is needed. As such, make sure we have at
4876 // least enough stack space for the caller to store the 8 GPRs.
4877 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4879 // Tail call needs the stack to be aligned.
4880 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4881 CallConv == CallingConv::Fast)
4882 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4884 // Calculate by how many bytes the stack has to be adjusted in case of tail
4885 // call optimization.
4886 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4888 // To protect arguments on the stack from being clobbered in a tail call,
4889 // force all the loads to happen before doing any other lowering.
4891 Chain = DAG.getStackArgumentTokenFactor(Chain);
4893 // Adjust the stack pointer for the new arguments...
4894 // These operations are automatically eliminated by the prolog/epilog pass
4895 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4897 SDValue CallSeqStart = Chain;
4899 // Load the return address and frame pointer so it can be move somewhere else
4902 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4905 // Set up a copy of the stack pointer for use loading and storing any
4906 // arguments that may not fit in the registers available for argument
4910 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4912 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4914 // Figure out which arguments are going to go in registers, and which in
4915 // memory. Also, if this is a vararg function, floating point operations
4916 // must be stored to our stack, and loaded into integer regs as well, if
4917 // any integer regs are available for argument passing.
4918 unsigned ArgOffset = LinkageSize;
4919 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4921 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4922 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4923 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4925 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4926 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4927 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4929 static const MCPhysReg *FPR = GetFPR();
4931 static const MCPhysReg VR[] = {
4932 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4933 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4935 const unsigned NumGPRs = array_lengthof(GPR_32);
4936 const unsigned NumFPRs = 13;
4937 const unsigned NumVRs = array_lengthof(VR);
4939 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4941 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4942 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4944 SmallVector<SDValue, 8> MemOpChains;
4945 for (unsigned i = 0; i != NumOps; ++i) {
4946 SDValue Arg = OutVals[i];
4947 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4949 // PtrOff will be used to store the current argument to the stack if a
4950 // register cannot be found for it.
4953 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4955 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4957 // On PPC64, promote integers to 64-bit values.
4958 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4959 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4960 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4961 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4964 // FIXME memcpy is used way more than necessary. Correctness first.
4965 // Note: "by value" is code for passing a structure by value, not
4967 if (Flags.isByVal()) {
4968 unsigned Size = Flags.getByValSize();
4969 // Very small objects are passed right-justified. Everything else is
4970 // passed left-justified.
4971 if (Size==1 || Size==2) {
4972 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4973 if (GPR_idx != NumGPRs) {
4974 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4975 MachinePointerInfo(), VT,
4976 false, false, false, 0);
4977 MemOpChains.push_back(Load.getValue(1));
4978 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4980 ArgOffset += PtrByteSize;
4982 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4983 PtrOff.getValueType());
4984 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4985 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4988 ArgOffset += PtrByteSize;
4992 // Copy entire object into memory. There are cases where gcc-generated
4993 // code assumes it is there, even if it could be put entirely into
4994 // registers. (This is not what the doc says.)
4995 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4999 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5000 // copy the pieces of the object that fit into registers from the
5001 // parameter save area.
5002 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5003 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5004 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5005 if (GPR_idx != NumGPRs) {
5006 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5007 MachinePointerInfo(),
5008 false, false, false, 0);
5009 MemOpChains.push_back(Load.getValue(1));
5010 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5011 ArgOffset += PtrByteSize;
5013 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5020 switch (Arg.getSimpleValueType().SimpleTy) {
5021 default: llvm_unreachable("Unexpected ValueType for argument!");
5025 if (GPR_idx != NumGPRs) {
5026 if (Arg.getValueType() == MVT::i1)
5027 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5029 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5031 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5032 isPPC64, isTailCall, false, MemOpChains,
5033 TailCallArguments, dl);
5035 ArgOffset += PtrByteSize;
5039 if (FPR_idx != NumFPRs) {
5040 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5043 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5044 MachinePointerInfo(), false, false, 0);
5045 MemOpChains.push_back(Store);
5047 // Float varargs are always shadowed in available integer registers
5048 if (GPR_idx != NumGPRs) {
5049 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5050 MachinePointerInfo(), false, false,
5052 MemOpChains.push_back(Load.getValue(1));
5053 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5055 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5056 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5057 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5058 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5059 MachinePointerInfo(),
5060 false, false, false, 0);
5061 MemOpChains.push_back(Load.getValue(1));
5062 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5065 // If we have any FPRs remaining, we may also have GPRs remaining.
5066 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5068 if (GPR_idx != NumGPRs)
5070 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5071 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5075 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5076 isPPC64, isTailCall, false, MemOpChains,
5077 TailCallArguments, dl);
5081 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5088 // These go aligned on the stack, or in the corresponding R registers
5089 // when within range. The Darwin PPC ABI doc claims they also go in
5090 // V registers; in fact gcc does this only for arguments that are
5091 // prototyped, not for those that match the ... We do it for all
5092 // arguments, seems to work.
5093 while (ArgOffset % 16 !=0) {
5094 ArgOffset += PtrByteSize;
5095 if (GPR_idx != NumGPRs)
5098 // We could elide this store in the case where the object fits
5099 // entirely in R registers. Maybe later.
5100 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5101 DAG.getConstant(ArgOffset, PtrVT));
5102 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5103 MachinePointerInfo(), false, false, 0);
5104 MemOpChains.push_back(Store);
5105 if (VR_idx != NumVRs) {
5106 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5107 MachinePointerInfo(),
5108 false, false, false, 0);
5109 MemOpChains.push_back(Load.getValue(1));
5110 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5113 for (unsigned i=0; i<16; i+=PtrByteSize) {
5114 if (GPR_idx == NumGPRs)
5116 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5117 DAG.getConstant(i, PtrVT));
5118 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5119 false, false, false, 0);
5120 MemOpChains.push_back(Load.getValue(1));
5121 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5126 // Non-varargs Altivec params generally go in registers, but have
5127 // stack space allocated at the end.
5128 if (VR_idx != NumVRs) {
5129 // Doesn't have GPR space allocated.
5130 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5131 } else if (nAltivecParamsAtEnd==0) {
5132 // We are emitting Altivec params in order.
5133 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5134 isPPC64, isTailCall, true, MemOpChains,
5135 TailCallArguments, dl);
5141 // If all Altivec parameters fit in registers, as they usually do,
5142 // they get stack space following the non-Altivec parameters. We
5143 // don't track this here because nobody below needs it.
5144 // If there are more Altivec parameters than fit in registers emit
5146 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5148 // Offset is aligned; skip 1st 12 params which go in V registers.
5149 ArgOffset = ((ArgOffset+15)/16)*16;
5151 for (unsigned i = 0; i != NumOps; ++i) {
5152 SDValue Arg = OutVals[i];
5153 EVT ArgType = Outs[i].VT;
5154 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5155 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5158 // We are emitting Altivec params in order.
5159 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5160 isPPC64, isTailCall, true, MemOpChains,
5161 TailCallArguments, dl);
5168 if (!MemOpChains.empty())
5169 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5171 // On Darwin, R12 must contain the address of an indirect callee. This does
5172 // not mean the MTCTR instruction must use R12; it's easier to model this as
5173 // an extra parameter, so do that.
5175 !isFunctionGlobalAddress(Callee) &&
5176 !isa<ExternalSymbolSDNode>(Callee) &&
5177 !isBLACompatibleAddress(Callee, DAG))
5178 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5179 PPC::R12), Callee));
5181 // Build a sequence of copy-to-reg nodes chained together with token chain
5182 // and flag operands which copy the outgoing args into the appropriate regs.
5184 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5185 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5186 RegsToPass[i].second, InFlag);
5187 InFlag = Chain.getValue(1);
5191 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5192 FPOp, true, TailCallArguments);
5194 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5195 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5196 NumBytes, Ins, InVals, CS);
5200 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5201 MachineFunction &MF, bool isVarArg,
5202 const SmallVectorImpl<ISD::OutputArg> &Outs,
5203 LLVMContext &Context) const {
5204 SmallVector<CCValAssign, 16> RVLocs;
5205 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5206 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5210 PPCTargetLowering::LowerReturn(SDValue Chain,
5211 CallingConv::ID CallConv, bool isVarArg,
5212 const SmallVectorImpl<ISD::OutputArg> &Outs,
5213 const SmallVectorImpl<SDValue> &OutVals,
5214 SDLoc dl, SelectionDAG &DAG) const {
5216 SmallVector<CCValAssign, 16> RVLocs;
5217 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5219 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5222 SmallVector<SDValue, 4> RetOps(1, Chain);
5224 // Copy the result values into the output registers.
5225 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5226 CCValAssign &VA = RVLocs[i];
5227 assert(VA.isRegLoc() && "Can only return in registers!");
5229 SDValue Arg = OutVals[i];
5231 switch (VA.getLocInfo()) {
5232 default: llvm_unreachable("Unknown loc info!");
5233 case CCValAssign::Full: break;
5234 case CCValAssign::AExt:
5235 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5237 case CCValAssign::ZExt:
5238 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5240 case CCValAssign::SExt:
5241 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5245 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5246 Flag = Chain.getValue(1);
5247 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5250 RetOps[0] = Chain; // Update chain.
5252 // Add the flag if we have it.
5254 RetOps.push_back(Flag);
5256 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5259 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5260 const PPCSubtarget &Subtarget) const {
5261 // When we pop the dynamic allocation we need to restore the SP link.
5264 // Get the corect type for pointers.
5265 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5267 // Construct the stack pointer operand.
5268 bool isPPC64 = Subtarget.isPPC64();
5269 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5270 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5272 // Get the operands for the STACKRESTORE.
5273 SDValue Chain = Op.getOperand(0);
5274 SDValue SaveSP = Op.getOperand(1);
5276 // Load the old link SP.
5277 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5278 MachinePointerInfo(),
5279 false, false, false, 0);
5281 // Restore the stack pointer.
5282 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5284 // Store the old link SP.
5285 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5292 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5293 MachineFunction &MF = DAG.getMachineFunction();
5294 bool isPPC64 = Subtarget.isPPC64();
5295 bool isDarwinABI = Subtarget.isDarwinABI();
5296 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5298 // Get current frame pointer save index. The users of this index will be
5299 // primarily DYNALLOC instructions.
5300 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5301 int RASI = FI->getReturnAddrSaveIndex();
5303 // If the frame pointer save index hasn't been defined yet.
5305 // Find out what the fix offset of the frame pointer save area.
5306 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5307 // Allocate the frame index for frame pointer save area.
5308 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5310 FI->setReturnAddrSaveIndex(RASI);
5312 return DAG.getFrameIndex(RASI, PtrVT);
5316 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5317 MachineFunction &MF = DAG.getMachineFunction();
5318 bool isPPC64 = Subtarget.isPPC64();
5319 bool isDarwinABI = Subtarget.isDarwinABI();
5320 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5322 // Get current frame pointer save index. The users of this index will be
5323 // primarily DYNALLOC instructions.
5324 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5325 int FPSI = FI->getFramePointerSaveIndex();
5327 // If the frame pointer save index hasn't been defined yet.
5329 // Find out what the fix offset of the frame pointer save area.
5330 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5333 // Allocate the frame index for frame pointer save area.
5334 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5336 FI->setFramePointerSaveIndex(FPSI);
5338 return DAG.getFrameIndex(FPSI, PtrVT);
5341 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5343 const PPCSubtarget &Subtarget) const {
5345 SDValue Chain = Op.getOperand(0);
5346 SDValue Size = Op.getOperand(1);
5349 // Get the corect type for pointers.
5350 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5352 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5353 DAG.getConstant(0, PtrVT), Size);
5354 // Construct a node for the frame pointer save index.
5355 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5356 // Build a DYNALLOC node.
5357 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5358 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5359 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5362 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5363 SelectionDAG &DAG) const {
5365 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5366 DAG.getVTList(MVT::i32, MVT::Other),
5367 Op.getOperand(0), Op.getOperand(1));
5370 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5371 SelectionDAG &DAG) const {
5373 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5374 Op.getOperand(0), Op.getOperand(1));
5377 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5378 assert(Op.getValueType() == MVT::i1 &&
5379 "Custom lowering only for i1 loads");
5381 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5384 LoadSDNode *LD = cast<LoadSDNode>(Op);
5386 SDValue Chain = LD->getChain();
5387 SDValue BasePtr = LD->getBasePtr();
5388 MachineMemOperand *MMO = LD->getMemOperand();
5390 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5391 BasePtr, MVT::i8, MMO);
5392 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5394 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5395 return DAG.getMergeValues(Ops, dl);
5398 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5399 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5400 "Custom lowering only for i1 stores");
5402 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5405 StoreSDNode *ST = cast<StoreSDNode>(Op);
5407 SDValue Chain = ST->getChain();
5408 SDValue BasePtr = ST->getBasePtr();
5409 SDValue Value = ST->getValue();
5410 MachineMemOperand *MMO = ST->getMemOperand();
5412 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5413 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5416 // FIXME: Remove this once the ANDI glue bug is fixed:
5417 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5418 assert(Op.getValueType() == MVT::i1 &&
5419 "Custom lowering only for i1 results");
5422 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5426 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5428 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5429 // Not FP? Not a fsel.
5430 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5431 !Op.getOperand(2).getValueType().isFloatingPoint())
5434 // We might be able to do better than this under some circumstances, but in
5435 // general, fsel-based lowering of select is a finite-math-only optimization.
5436 // For more information, see section F.3 of the 2.06 ISA specification.
5437 if (!DAG.getTarget().Options.NoInfsFPMath ||
5438 !DAG.getTarget().Options.NoNaNsFPMath)
5441 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5443 EVT ResVT = Op.getValueType();
5444 EVT CmpVT = Op.getOperand(0).getValueType();
5445 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5446 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5449 // If the RHS of the comparison is a 0.0, we don't need to do the
5450 // subtraction at all.
5452 if (isFloatingPointZero(RHS))
5454 default: break; // SETUO etc aren't handled by fsel.
5458 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5459 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5460 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5461 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5462 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5463 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5464 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5467 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5470 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5471 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5472 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5475 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5478 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5479 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5480 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5481 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5486 default: break; // SETUO etc aren't handled by fsel.
5490 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5491 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5492 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5493 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5494 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5495 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5496 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5497 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5500 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5501 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5502 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5503 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5506 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5507 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5508 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5509 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5512 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5513 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5514 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5515 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5518 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5519 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5520 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5521 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5526 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5529 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5530 SDValue Src = Op.getOperand(0);
5531 if (Src.getValueType() == MVT::f32)
5532 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5535 switch (Op.getSimpleValueType().SimpleTy) {
5536 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5539 Op.getOpcode() == ISD::FP_TO_SINT
5541 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5545 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5546 "i64 FP_TO_UINT is supported only with FPCVT");
5547 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5553 // Convert the FP value to an int value through memory.
5554 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5555 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5556 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5557 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5558 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5560 // Emit a store to the stack slot.
5563 MachineFunction &MF = DAG.getMachineFunction();
5564 MachineMemOperand *MMO =
5565 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5566 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5567 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5568 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5570 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5571 MPI, false, false, 0);
5573 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5575 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5576 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5577 DAG.getConstant(4, FIPtr.getValueType()));
5578 MPI = MPI.getWithOffset(4);
5586 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5589 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5591 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5592 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5596 // We're trying to insert a regular store, S, and then a load, L. If the
5597 // incoming value, O, is a load, we might just be able to have our load use the
5598 // address used by O. However, we don't know if anything else will store to
5599 // that address before we can load from it. To prevent this situation, we need
5600 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5601 // the same chain operand as O, we create a token factor from the chain results
5602 // of O and L, and we replace all uses of O's chain result with that token
5603 // factor (see spliceIntoChain below for this last part).
5604 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5607 ISD::LoadExtType ET) const {
5609 if (ET == ISD::NON_EXTLOAD &&
5610 (Op.getOpcode() == ISD::FP_TO_UINT ||
5611 Op.getOpcode() == ISD::FP_TO_SINT) &&
5612 isOperationLegalOrCustom(Op.getOpcode(),
5613 Op.getOperand(0).getValueType())) {
5615 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5619 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5620 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5621 LD->isNonTemporal())
5623 if (LD->getMemoryVT() != MemVT)
5626 RLI.Ptr = LD->getBasePtr();
5627 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5628 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5629 "Non-pre-inc AM on PPC?");
5630 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5634 RLI.Chain = LD->getChain();
5635 RLI.MPI = LD->getPointerInfo();
5636 RLI.IsInvariant = LD->isInvariant();
5637 RLI.Alignment = LD->getAlignment();
5638 RLI.AAInfo = LD->getAAInfo();
5639 RLI.Ranges = LD->getRanges();
5641 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5645 // Given the head of the old chain, ResChain, insert a token factor containing
5646 // it and NewResChain, and make users of ResChain now be users of that token
5648 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5649 SDValue NewResChain,
5650 SelectionDAG &DAG) const {
5654 SDLoc dl(NewResChain);
5656 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5657 NewResChain, DAG.getUNDEF(MVT::Other));
5658 assert(TF.getNode() != NewResChain.getNode() &&
5659 "A new TF really is required here");
5661 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5662 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5665 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5666 SelectionDAG &DAG) const {
5668 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5669 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5672 if (Op.getOperand(0).getValueType() == MVT::i1)
5673 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5674 DAG.getConstantFP(1.0, Op.getValueType()),
5675 DAG.getConstantFP(0.0, Op.getValueType()));
5677 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5678 "UINT_TO_FP is supported only with FPCVT");
5680 // If we have FCFIDS, then use it when converting to single-precision.
5681 // Otherwise, convert to double-precision and then round.
5682 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5683 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
5685 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
5687 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
5691 if (Op.getOperand(0).getValueType() == MVT::i64) {
5692 SDValue SINT = Op.getOperand(0);
5693 // When converting to single-precision, we actually need to convert
5694 // to double-precision first and then round to single-precision.
5695 // To avoid double-rounding effects during that operation, we have
5696 // to prepare the input operand. Bits that might be truncated when
5697 // converting to double-precision are replaced by a bit that won't
5698 // be lost at this stage, but is below the single-precision rounding
5701 // However, if -enable-unsafe-fp-math is in effect, accept double
5702 // rounding to avoid the extra overhead.
5703 if (Op.getValueType() == MVT::f32 &&
5704 !Subtarget.hasFPCVT() &&
5705 !DAG.getTarget().Options.UnsafeFPMath) {
5707 // Twiddle input to make sure the low 11 bits are zero. (If this
5708 // is the case, we are guaranteed the value will fit into the 53 bit
5709 // mantissa of an IEEE double-precision value without rounding.)
5710 // If any of those low 11 bits were not zero originally, make sure
5711 // bit 12 (value 2048) is set instead, so that the final rounding
5712 // to single-precision gets the correct result.
5713 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5714 SINT, DAG.getConstant(2047, MVT::i64));
5715 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5716 Round, DAG.getConstant(2047, MVT::i64));
5717 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5718 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5719 Round, DAG.getConstant(-2048, MVT::i64));
5721 // However, we cannot use that value unconditionally: if the magnitude
5722 // of the input value is small, the bit-twiddling we did above might
5723 // end up visibly changing the output. Fortunately, in that case, we
5724 // don't need to twiddle bits since the original input will convert
5725 // exactly to double-precision floating-point already. Therefore,
5726 // construct a conditional to use the original value if the top 11
5727 // bits are all sign-bit copies, and use the rounded value computed
5729 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5730 SINT, DAG.getConstant(53, MVT::i32));
5731 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5732 Cond, DAG.getConstant(1, MVT::i64));
5733 Cond = DAG.getSetCC(dl, MVT::i32,
5734 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5736 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5742 MachineFunction &MF = DAG.getMachineFunction();
5743 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5744 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5745 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5747 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5748 } else if (Subtarget.hasLFIWAX() &&
5749 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5750 MachineMemOperand *MMO =
5751 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5752 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5753 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5754 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5755 DAG.getVTList(MVT::f64, MVT::Other),
5756 Ops, MVT::i32, MMO);
5757 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5758 } else if (Subtarget.hasFPCVT() &&
5759 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5760 MachineMemOperand *MMO =
5761 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5762 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5763 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5764 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5765 DAG.getVTList(MVT::f64, MVT::Other),
5766 Ops, MVT::i32, MMO);
5767 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5768 } else if (((Subtarget.hasLFIWAX() &&
5769 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5770 (Subtarget.hasFPCVT() &&
5771 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5772 SINT.getOperand(0).getValueType() == MVT::i32) {
5773 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5774 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5776 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5777 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5780 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5781 MachinePointerInfo::getFixedStack(FrameIdx),
5784 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5785 "Expected an i32 store");
5789 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5792 MachineMemOperand *MMO =
5793 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5794 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5795 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5796 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5797 PPCISD::LFIWZX : PPCISD::LFIWAX,
5798 dl, DAG.getVTList(MVT::f64, MVT::Other),
5799 Ops, MVT::i32, MMO);
5801 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5803 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5805 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5806 FP = DAG.getNode(ISD::FP_ROUND, dl,
5807 MVT::f32, FP, DAG.getIntPtrConstant(0));
5811 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5812 "Unhandled INT_TO_FP type in custom expander!");
5813 // Since we only generate this in 64-bit mode, we can take advantage of
5814 // 64-bit registers. In particular, sign extend the input value into the
5815 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5816 // then lfd it and fcfid it.
5817 MachineFunction &MF = DAG.getMachineFunction();
5818 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5822 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5825 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5827 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5828 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5830 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5831 MachinePointerInfo::getFixedStack(FrameIdx),
5834 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5835 "Expected an i32 store");
5839 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5843 MachineMemOperand *MMO =
5844 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5845 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5846 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5847 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5848 PPCISD::LFIWZX : PPCISD::LFIWAX,
5849 dl, DAG.getVTList(MVT::f64, MVT::Other),
5850 Ops, MVT::i32, MMO);
5852 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5854 assert(Subtarget.isPPC64() &&
5855 "i32->FP without LFIWAX supported only on PPC64");
5857 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5858 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5860 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5863 // STD the extended value into the stack slot.
5864 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5865 MachinePointerInfo::getFixedStack(FrameIdx),
5868 // Load the value as a double.
5869 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5870 MachinePointerInfo::getFixedStack(FrameIdx),
5871 false, false, false, 0);
5874 // FCFID it and return it.
5875 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5876 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5877 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5881 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5882 SelectionDAG &DAG) const {
5885 The rounding mode is in bits 30:31 of FPSR, and has the following
5892 FLT_ROUNDS, on the other hand, expects the following:
5899 To perform the conversion, we do:
5900 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5903 MachineFunction &MF = DAG.getMachineFunction();
5904 EVT VT = Op.getValueType();
5905 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5907 // Save FP Control Word to register
5909 MVT::f64, // return register
5910 MVT::Glue // unused in this context
5912 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5914 // Save FP register to stack slot
5915 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5916 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5917 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5918 StackSlot, MachinePointerInfo(), false, false,0);
5920 // Load FP Control Word from low 32 bits of stack slot.
5921 SDValue Four = DAG.getConstant(4, PtrVT);
5922 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5923 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5924 false, false, false, 0);
5926 // Transform as necessary
5928 DAG.getNode(ISD::AND, dl, MVT::i32,
5929 CWD, DAG.getConstant(3, MVT::i32));
5931 DAG.getNode(ISD::SRL, dl, MVT::i32,
5932 DAG.getNode(ISD::AND, dl, MVT::i32,
5933 DAG.getNode(ISD::XOR, dl, MVT::i32,
5934 CWD, DAG.getConstant(3, MVT::i32)),
5935 DAG.getConstant(3, MVT::i32)),
5936 DAG.getConstant(1, MVT::i32));
5939 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5941 return DAG.getNode((VT.getSizeInBits() < 16 ?
5942 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5945 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5946 EVT VT = Op.getValueType();
5947 unsigned BitWidth = VT.getSizeInBits();
5949 assert(Op.getNumOperands() == 3 &&
5950 VT == Op.getOperand(1).getValueType() &&
5953 // Expand into a bunch of logical ops. Note that these ops
5954 // depend on the PPC behavior for oversized shift amounts.
5955 SDValue Lo = Op.getOperand(0);
5956 SDValue Hi = Op.getOperand(1);
5957 SDValue Amt = Op.getOperand(2);
5958 EVT AmtVT = Amt.getValueType();
5960 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5961 DAG.getConstant(BitWidth, AmtVT), Amt);
5962 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5963 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5964 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5965 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5966 DAG.getConstant(-BitWidth, AmtVT));
5967 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5968 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5969 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5970 SDValue OutOps[] = { OutLo, OutHi };
5971 return DAG.getMergeValues(OutOps, dl);
5974 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5975 EVT VT = Op.getValueType();
5977 unsigned BitWidth = VT.getSizeInBits();
5978 assert(Op.getNumOperands() == 3 &&
5979 VT == Op.getOperand(1).getValueType() &&
5982 // Expand into a bunch of logical ops. Note that these ops
5983 // depend on the PPC behavior for oversized shift amounts.
5984 SDValue Lo = Op.getOperand(0);
5985 SDValue Hi = Op.getOperand(1);
5986 SDValue Amt = Op.getOperand(2);
5987 EVT AmtVT = Amt.getValueType();
5989 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5990 DAG.getConstant(BitWidth, AmtVT), Amt);
5991 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5992 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5993 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5994 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5995 DAG.getConstant(-BitWidth, AmtVT));
5996 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5997 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5998 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5999 SDValue OutOps[] = { OutLo, OutHi };
6000 return DAG.getMergeValues(OutOps, dl);
6003 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6005 EVT VT = Op.getValueType();
6006 unsigned BitWidth = VT.getSizeInBits();
6007 assert(Op.getNumOperands() == 3 &&
6008 VT == Op.getOperand(1).getValueType() &&
6011 // Expand into a bunch of logical ops, followed by a select_cc.
6012 SDValue Lo = Op.getOperand(0);
6013 SDValue Hi = Op.getOperand(1);
6014 SDValue Amt = Op.getOperand(2);
6015 EVT AmtVT = Amt.getValueType();
6017 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6018 DAG.getConstant(BitWidth, AmtVT), Amt);
6019 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6020 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6021 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6022 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6023 DAG.getConstant(-BitWidth, AmtVT));
6024 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6025 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6026 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6027 Tmp4, Tmp6, ISD::SETLE);
6028 SDValue OutOps[] = { OutLo, OutHi };
6029 return DAG.getMergeValues(OutOps, dl);
6032 //===----------------------------------------------------------------------===//
6033 // Vector related lowering.
6036 /// BuildSplatI - Build a canonical splati of Val with an element size of
6037 /// SplatSize. Cast the result to VT.
6038 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6039 SelectionDAG &DAG, SDLoc dl) {
6040 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6042 static const EVT VTys[] = { // canonical VT to use for each size.
6043 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6046 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6048 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6052 EVT CanonicalVT = VTys[SplatSize-1];
6054 // Build a canonical splat for this value.
6055 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6056 SmallVector<SDValue, 8> Ops;
6057 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6058 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6059 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6062 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6063 /// specified intrinsic ID.
6064 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6065 SelectionDAG &DAG, SDLoc dl,
6066 EVT DestVT = MVT::Other) {
6067 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6068 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6069 DAG.getConstant(IID, MVT::i32), Op);
6072 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6073 /// specified intrinsic ID.
6074 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6075 SelectionDAG &DAG, SDLoc dl,
6076 EVT DestVT = MVT::Other) {
6077 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6078 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6079 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6082 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6083 /// specified intrinsic ID.
6084 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6085 SDValue Op2, SelectionDAG &DAG,
6086 SDLoc dl, EVT DestVT = MVT::Other) {
6087 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6088 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6089 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6093 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6094 /// amount. The result has the specified value type.
6095 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6096 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6097 // Force LHS/RHS to be the right type.
6098 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6099 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6102 for (unsigned i = 0; i != 16; ++i)
6104 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6105 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6108 // If this is a case we can't handle, return null and let the default
6109 // expansion code take care of it. If we CAN select this case, and if it
6110 // selects to a single instruction, return Op. Otherwise, if we can codegen
6111 // this case more efficiently than a constant pool load, lower it to the
6112 // sequence of ops that should be used.
6113 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6114 SelectionDAG &DAG) const {
6116 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6117 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6119 // Check if this is a splat of a constant value.
6120 APInt APSplatBits, APSplatUndef;
6121 unsigned SplatBitSize;
6123 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6124 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6127 unsigned SplatBits = APSplatBits.getZExtValue();
6128 unsigned SplatUndef = APSplatUndef.getZExtValue();
6129 unsigned SplatSize = SplatBitSize / 8;
6131 // First, handle single instruction cases.
6134 if (SplatBits == 0) {
6135 // Canonicalize all zero vectors to be v4i32.
6136 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6137 SDValue Z = DAG.getConstant(0, MVT::i32);
6138 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6139 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6144 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6145 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6147 if (SextVal >= -16 && SextVal <= 15)
6148 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6151 // Two instruction sequences.
6153 // If this value is in the range [-32,30] and is even, use:
6154 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6155 // If this value is in the range [17,31] and is odd, use:
6156 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6157 // If this value is in the range [-31,-17] and is odd, use:
6158 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6159 // Note the last two are three-instruction sequences.
6160 if (SextVal >= -32 && SextVal <= 31) {
6161 // To avoid having these optimizations undone by constant folding,
6162 // we convert to a pseudo that will be expanded later into one of
6164 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6165 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6166 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6167 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6168 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6169 if (VT == Op.getValueType())
6172 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6175 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6176 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6178 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6179 // Make -1 and vspltisw -1:
6180 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6182 // Make the VSLW intrinsic, computing 0x8000_0000.
6183 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6186 // xor by OnesV to invert it.
6187 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6188 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6191 // The remaining cases assume either big endian element order or
6192 // a splat-size that equates to the element size of the vector
6193 // to be built. An example that doesn't work for little endian is
6194 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6195 // and a vector element size of 16 bits. The code below will
6196 // produce the vector in big endian element order, which for little
6197 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6199 // For now, just avoid these optimizations in that case.
6200 // FIXME: Develop correct optimizations for LE with mismatched
6201 // splat and element sizes.
6203 if (Subtarget.isLittleEndian() &&
6204 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6207 // Check to see if this is a wide variety of vsplti*, binop self cases.
6208 static const signed char SplatCsts[] = {
6209 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6210 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6213 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6214 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6215 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6216 int i = SplatCsts[idx];
6218 // Figure out what shift amount will be used by altivec if shifted by i in
6220 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6222 // vsplti + shl self.
6223 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6224 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6225 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6226 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6227 Intrinsic::ppc_altivec_vslw
6229 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6230 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6233 // vsplti + srl self.
6234 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6235 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6236 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6237 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6238 Intrinsic::ppc_altivec_vsrw
6240 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6241 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6244 // vsplti + sra self.
6245 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6246 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6247 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6248 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6249 Intrinsic::ppc_altivec_vsraw
6251 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6252 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6255 // vsplti + rol self.
6256 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6257 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6258 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6259 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6260 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6261 Intrinsic::ppc_altivec_vrlw
6263 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6264 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6267 // t = vsplti c, result = vsldoi t, t, 1
6268 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6269 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6270 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6272 // t = vsplti c, result = vsldoi t, t, 2
6273 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6274 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6275 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6277 // t = vsplti c, result = vsldoi t, t, 3
6278 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6279 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6280 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6287 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6288 /// the specified operations to build the shuffle.
6289 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6290 SDValue RHS, SelectionDAG &DAG,
6292 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6293 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6294 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6297 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6309 if (OpNum == OP_COPY) {
6310 if (LHSID == (1*9+2)*9+3) return LHS;
6311 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6315 SDValue OpLHS, OpRHS;
6316 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6317 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6321 default: llvm_unreachable("Unknown i32 permute!");
6323 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6324 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6325 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6326 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6329 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6330 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6331 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6332 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6335 for (unsigned i = 0; i != 16; ++i)
6336 ShufIdxs[i] = (i&3)+0;
6339 for (unsigned i = 0; i != 16; ++i)
6340 ShufIdxs[i] = (i&3)+4;
6343 for (unsigned i = 0; i != 16; ++i)
6344 ShufIdxs[i] = (i&3)+8;
6347 for (unsigned i = 0; i != 16; ++i)
6348 ShufIdxs[i] = (i&3)+12;
6351 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6353 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6355 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6357 EVT VT = OpLHS.getValueType();
6358 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6359 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6360 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6361 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6364 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6365 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6366 /// return the code it can be lowered into. Worst case, it can always be
6367 /// lowered into a vperm.
6368 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6369 SelectionDAG &DAG) const {
6371 SDValue V1 = Op.getOperand(0);
6372 SDValue V2 = Op.getOperand(1);
6373 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6374 EVT VT = Op.getValueType();
6375 bool isLittleEndian = Subtarget.isLittleEndian();
6377 // Cases that are handled by instructions that take permute immediates
6378 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6379 // selected by the instruction selector.
6380 if (V2.getOpcode() == ISD::UNDEF) {
6381 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6382 PPC::isSplatShuffleMask(SVOp, 2) ||
6383 PPC::isSplatShuffleMask(SVOp, 4) ||
6384 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6385 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6386 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6387 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6388 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6389 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6390 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6391 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6392 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6397 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6398 // and produce a fixed permutation. If any of these match, do not lower to
6400 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6401 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6402 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6403 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6404 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6405 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6406 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6407 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6408 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6409 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6412 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6413 // perfect shuffle table to emit an optimal matching sequence.
6414 ArrayRef<int> PermMask = SVOp->getMask();
6416 unsigned PFIndexes[4];
6417 bool isFourElementShuffle = true;
6418 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6419 unsigned EltNo = 8; // Start out undef.
6420 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6421 if (PermMask[i*4+j] < 0)
6422 continue; // Undef, ignore it.
6424 unsigned ByteSource = PermMask[i*4+j];
6425 if ((ByteSource & 3) != j) {
6426 isFourElementShuffle = false;
6431 EltNo = ByteSource/4;
6432 } else if (EltNo != ByteSource/4) {
6433 isFourElementShuffle = false;
6437 PFIndexes[i] = EltNo;
6440 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6441 // perfect shuffle vector to determine if it is cost effective to do this as
6442 // discrete instructions, or whether we should use a vperm.
6443 // For now, we skip this for little endian until such time as we have a
6444 // little-endian perfect shuffle table.
6445 if (isFourElementShuffle && !isLittleEndian) {
6446 // Compute the index in the perfect shuffle table.
6447 unsigned PFTableIndex =
6448 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6450 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6451 unsigned Cost = (PFEntry >> 30);
6453 // Determining when to avoid vperm is tricky. Many things affect the cost
6454 // of vperm, particularly how many times the perm mask needs to be computed.
6455 // For example, if the perm mask can be hoisted out of a loop or is already
6456 // used (perhaps because there are multiple permutes with the same shuffle
6457 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6458 // the loop requires an extra register.
6460 // As a compromise, we only emit discrete instructions if the shuffle can be
6461 // generated in 3 or fewer operations. When we have loop information
6462 // available, if this block is within a loop, we should avoid using vperm
6463 // for 3-operation perms and use a constant pool load instead.
6465 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6468 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6469 // vector that will get spilled to the constant pool.
6470 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6472 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6473 // that it is in input element units, not in bytes. Convert now.
6475 // For little endian, the order of the input vectors is reversed, and
6476 // the permutation mask is complemented with respect to 31. This is
6477 // necessary to produce proper semantics with the big-endian-biased vperm
6479 EVT EltVT = V1.getValueType().getVectorElementType();
6480 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6482 SmallVector<SDValue, 16> ResultMask;
6483 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6484 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6486 for (unsigned j = 0; j != BytesPerElement; ++j)
6488 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6491 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6495 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6498 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6501 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6505 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6506 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6507 /// information about the intrinsic.
6508 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6510 unsigned IntrinsicID =
6511 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6514 switch (IntrinsicID) {
6515 default: return false;
6516 // Comparison predicates.
6517 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6518 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6519 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6520 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6521 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6522 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6523 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6524 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6525 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6526 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6527 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6528 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6529 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6531 // Normal Comparisons.
6532 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6533 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6534 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6535 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6536 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6537 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6538 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6539 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6540 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6541 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6542 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6543 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6544 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6549 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6550 /// lower, do it, otherwise return null.
6551 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6552 SelectionDAG &DAG) const {
6553 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6554 // opcode number of the comparison.
6558 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6559 return SDValue(); // Don't custom lower most intrinsics.
6561 // If this is a non-dot comparison, make the VCMP node and we are done.
6563 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6564 Op.getOperand(1), Op.getOperand(2),
6565 DAG.getConstant(CompareOpc, MVT::i32));
6566 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6569 // Create the PPCISD altivec 'dot' comparison node.
6571 Op.getOperand(2), // LHS
6572 Op.getOperand(3), // RHS
6573 DAG.getConstant(CompareOpc, MVT::i32)
6575 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6576 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6578 // Now that we have the comparison, emit a copy from the CR to a GPR.
6579 // This is flagged to the above dot comparison.
6580 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6581 DAG.getRegister(PPC::CR6, MVT::i32),
6582 CompNode.getValue(1));
6584 // Unpack the result based on how the target uses it.
6585 unsigned BitNo; // Bit # of CR6.
6586 bool InvertBit; // Invert result?
6587 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6588 default: // Can't happen, don't crash on invalid number though.
6589 case 0: // Return the value of the EQ bit of CR6.
6590 BitNo = 0; InvertBit = false;
6592 case 1: // Return the inverted value of the EQ bit of CR6.
6593 BitNo = 0; InvertBit = true;
6595 case 2: // Return the value of the LT bit of CR6.
6596 BitNo = 2; InvertBit = false;
6598 case 3: // Return the inverted value of the LT bit of CR6.
6599 BitNo = 2; InvertBit = true;
6603 // Shift the bit into the low position.
6604 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6605 DAG.getConstant(8-(3-BitNo), MVT::i32));
6607 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6608 DAG.getConstant(1, MVT::i32));
6610 // If we are supposed to, toggle the bit.
6612 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6613 DAG.getConstant(1, MVT::i32));
6617 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6618 SelectionDAG &DAG) const {
6620 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6621 // instructions), but for smaller types, we need to first extend up to v2i32
6622 // before doing going farther.
6623 if (Op.getValueType() == MVT::v2i64) {
6624 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6625 if (ExtVT != MVT::v2i32) {
6626 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6627 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6628 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6629 ExtVT.getVectorElementType(), 4)));
6630 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6631 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6632 DAG.getValueType(MVT::v2i32));
6641 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6642 SelectionDAG &DAG) const {
6644 // Create a stack slot that is 16-byte aligned.
6645 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6646 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6647 EVT PtrVT = getPointerTy();
6648 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6650 // Store the input value into Value#0 of the stack slot.
6651 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6652 Op.getOperand(0), FIdx, MachinePointerInfo(),
6655 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6656 false, false, false, 0);
6659 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6661 if (Op.getValueType() == MVT::v4i32) {
6662 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6664 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6665 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6667 SDValue RHSSwap = // = vrlw RHS, 16
6668 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6670 // Shrinkify inputs to v8i16.
6671 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6672 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6673 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6675 // Low parts multiplied together, generating 32-bit results (we ignore the
6677 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6678 LHS, RHS, DAG, dl, MVT::v4i32);
6680 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6681 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6682 // Shift the high parts up 16 bits.
6683 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6685 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6686 } else if (Op.getValueType() == MVT::v8i16) {
6687 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6689 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6691 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6692 LHS, RHS, Zero, DAG, dl);
6693 } else if (Op.getValueType() == MVT::v16i8) {
6694 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6695 bool isLittleEndian = Subtarget.isLittleEndian();
6697 // Multiply the even 8-bit parts, producing 16-bit sums.
6698 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6699 LHS, RHS, DAG, dl, MVT::v8i16);
6700 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6702 // Multiply the odd 8-bit parts, producing 16-bit sums.
6703 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6704 LHS, RHS, DAG, dl, MVT::v8i16);
6705 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6707 // Merge the results together. Because vmuleub and vmuloub are
6708 // instructions with a big-endian bias, we must reverse the
6709 // element numbering and reverse the meaning of "odd" and "even"
6710 // when generating little endian code.
6712 for (unsigned i = 0; i != 8; ++i) {
6713 if (isLittleEndian) {
6715 Ops[i*2+1] = 2*i+16;
6718 Ops[i*2+1] = 2*i+1+16;
6722 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6724 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6726 llvm_unreachable("Unknown mul to lower!");
6730 /// LowerOperation - Provide custom lowering hooks for some operations.
6732 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6733 switch (Op.getOpcode()) {
6734 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6735 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6736 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6737 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6738 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6739 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6740 case ISD::SETCC: return LowerSETCC(Op, DAG);
6741 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6742 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6744 return LowerVASTART(Op, DAG, Subtarget);
6747 return LowerVAARG(Op, DAG, Subtarget);
6750 return LowerVACOPY(Op, DAG, Subtarget);
6752 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6753 case ISD::DYNAMIC_STACKALLOC:
6754 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6756 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6757 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6759 case ISD::LOAD: return LowerLOAD(Op, DAG);
6760 case ISD::STORE: return LowerSTORE(Op, DAG);
6761 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6762 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6763 case ISD::FP_TO_UINT:
6764 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6766 case ISD::UINT_TO_FP:
6767 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6768 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6770 // Lower 64-bit shifts.
6771 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6772 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6773 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6775 // Vector-related lowering.
6776 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6777 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6778 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6779 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6780 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6781 case ISD::MUL: return LowerMUL(Op, DAG);
6783 // For counter-based loop handling.
6784 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6786 // Frame & Return address.
6787 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6788 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6792 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6793 SmallVectorImpl<SDValue>&Results,
6794 SelectionDAG &DAG) const {
6796 switch (N->getOpcode()) {
6798 llvm_unreachable("Do not know how to custom type legalize this operation!");
6799 case ISD::READCYCLECOUNTER: {
6800 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6801 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6803 Results.push_back(RTB);
6804 Results.push_back(RTB.getValue(1));
6805 Results.push_back(RTB.getValue(2));
6808 case ISD::INTRINSIC_W_CHAIN: {
6809 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6810 Intrinsic::ppc_is_decremented_ctr_nonzero)
6813 assert(N->getValueType(0) == MVT::i1 &&
6814 "Unexpected result type for CTR decrement intrinsic");
6815 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6816 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6817 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6820 Results.push_back(NewInt);
6821 Results.push_back(NewInt.getValue(1));
6825 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
6828 EVT VT = N->getValueType(0);
6830 if (VT == MVT::i64) {
6831 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6833 Results.push_back(NewNode);
6834 Results.push_back(NewNode.getValue(1));
6838 case ISD::FP_ROUND_INREG: {
6839 assert(N->getValueType(0) == MVT::ppcf128);
6840 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6841 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6842 MVT::f64, N->getOperand(0),
6843 DAG.getIntPtrConstant(0));
6844 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6845 MVT::f64, N->getOperand(0),
6846 DAG.getIntPtrConstant(1));
6848 // Add the two halves of the long double in round-to-zero mode.
6849 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6851 // We know the low half is about to be thrown away, so just use something
6853 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6857 case ISD::FP_TO_SINT:
6858 // LowerFP_TO_INT() can only handle f32 and f64.
6859 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6861 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6867 //===----------------------------------------------------------------------===//
6868 // Other Lowering Code
6869 //===----------------------------------------------------------------------===//
6871 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6872 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6873 Function *Func = Intrinsic::getDeclaration(M, Id);
6874 return Builder.CreateCall(Func);
6877 // The mappings for emitLeading/TrailingFence is taken from
6878 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6879 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6880 AtomicOrdering Ord, bool IsStore,
6881 bool IsLoad) const {
6882 if (Ord == SequentiallyConsistent)
6883 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6884 else if (isAtLeastRelease(Ord))
6885 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6890 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6891 AtomicOrdering Ord, bool IsStore,
6892 bool IsLoad) const {
6893 if (IsLoad && isAtLeastAcquire(Ord))
6894 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6895 // FIXME: this is too conservative, a dependent branch + isync is enough.
6896 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6897 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6898 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6904 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6905 bool is64bit, unsigned BinOpcode) const {
6906 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6907 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6909 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6910 MachineFunction *F = BB->getParent();
6911 MachineFunction::iterator It = BB;
6914 unsigned dest = MI->getOperand(0).getReg();
6915 unsigned ptrA = MI->getOperand(1).getReg();
6916 unsigned ptrB = MI->getOperand(2).getReg();
6917 unsigned incr = MI->getOperand(3).getReg();
6918 DebugLoc dl = MI->getDebugLoc();
6920 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6921 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6922 F->insert(It, loopMBB);
6923 F->insert(It, exitMBB);
6924 exitMBB->splice(exitMBB->begin(), BB,
6925 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6926 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6928 MachineRegisterInfo &RegInfo = F->getRegInfo();
6929 unsigned TmpReg = (!BinOpcode) ? incr :
6930 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6931 : &PPC::GPRCRegClass);
6935 // fallthrough --> loopMBB
6936 BB->addSuccessor(loopMBB);
6939 // l[wd]arx dest, ptr
6940 // add r0, dest, incr
6941 // st[wd]cx. r0, ptr
6943 // fallthrough --> exitMBB
6945 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6946 .addReg(ptrA).addReg(ptrB);
6948 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6949 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6950 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6951 BuildMI(BB, dl, TII->get(PPC::BCC))
6952 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6953 BB->addSuccessor(loopMBB);
6954 BB->addSuccessor(exitMBB);
6963 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6964 MachineBasicBlock *BB,
6965 bool is8bit, // operation
6966 unsigned BinOpcode) const {
6967 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6968 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
6969 // In 64 bit mode we have to use 64 bits for addresses, even though the
6970 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6971 // registers without caring whether they're 32 or 64, but here we're
6972 // doing actual arithmetic on the addresses.
6973 bool is64bit = Subtarget.isPPC64();
6974 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6976 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6977 MachineFunction *F = BB->getParent();
6978 MachineFunction::iterator It = BB;
6981 unsigned dest = MI->getOperand(0).getReg();
6982 unsigned ptrA = MI->getOperand(1).getReg();
6983 unsigned ptrB = MI->getOperand(2).getReg();
6984 unsigned incr = MI->getOperand(3).getReg();
6985 DebugLoc dl = MI->getDebugLoc();
6987 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6988 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6989 F->insert(It, loopMBB);
6990 F->insert(It, exitMBB);
6991 exitMBB->splice(exitMBB->begin(), BB,
6992 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6993 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6995 MachineRegisterInfo &RegInfo = F->getRegInfo();
6996 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6997 : &PPC::GPRCRegClass;
6998 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6999 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7000 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7001 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7002 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7003 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7004 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7005 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7006 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7007 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7008 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7010 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7014 // fallthrough --> loopMBB
7015 BB->addSuccessor(loopMBB);
7017 // The 4-byte load must be aligned, while a char or short may be
7018 // anywhere in the word. Hence all this nasty bookkeeping code.
7019 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7020 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7021 // xori shift, shift1, 24 [16]
7022 // rlwinm ptr, ptr1, 0, 0, 29
7023 // slw incr2, incr, shift
7024 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7025 // slw mask, mask2, shift
7027 // lwarx tmpDest, ptr
7028 // add tmp, tmpDest, incr2
7029 // andc tmp2, tmpDest, mask
7030 // and tmp3, tmp, mask
7031 // or tmp4, tmp3, tmp2
7034 // fallthrough --> exitMBB
7035 // srw dest, tmpDest, shift
7036 if (ptrA != ZeroReg) {
7037 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7038 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7039 .addReg(ptrA).addReg(ptrB);
7043 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7044 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7045 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7046 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7048 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7049 .addReg(Ptr1Reg).addImm(0).addImm(61);
7051 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7052 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7053 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7054 .addReg(incr).addReg(ShiftReg);
7056 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7058 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7059 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7061 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7062 .addReg(Mask2Reg).addReg(ShiftReg);
7065 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7066 .addReg(ZeroReg).addReg(PtrReg);
7068 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7069 .addReg(Incr2Reg).addReg(TmpDestReg);
7070 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7071 .addReg(TmpDestReg).addReg(MaskReg);
7072 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7073 .addReg(TmpReg).addReg(MaskReg);
7074 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7075 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7076 BuildMI(BB, dl, TII->get(PPC::STWCX))
7077 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7078 BuildMI(BB, dl, TII->get(PPC::BCC))
7079 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7080 BB->addSuccessor(loopMBB);
7081 BB->addSuccessor(exitMBB);
7086 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7091 llvm::MachineBasicBlock*
7092 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7093 MachineBasicBlock *MBB) const {
7094 DebugLoc DL = MI->getDebugLoc();
7095 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7097 MachineFunction *MF = MBB->getParent();
7098 MachineRegisterInfo &MRI = MF->getRegInfo();
7100 const BasicBlock *BB = MBB->getBasicBlock();
7101 MachineFunction::iterator I = MBB;
7105 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7106 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7108 unsigned DstReg = MI->getOperand(0).getReg();
7109 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7110 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7111 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7112 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7114 MVT PVT = getPointerTy();
7115 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7116 "Invalid Pointer Size!");
7117 // For v = setjmp(buf), we generate
7120 // SjLjSetup mainMBB
7126 // buf[LabelOffset] = LR
7130 // v = phi(main, restore)
7133 MachineBasicBlock *thisMBB = MBB;
7134 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7135 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7136 MF->insert(I, mainMBB);
7137 MF->insert(I, sinkMBB);
7139 MachineInstrBuilder MIB;
7141 // Transfer the remainder of BB and its successor edges to sinkMBB.
7142 sinkMBB->splice(sinkMBB->begin(), MBB,
7143 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7144 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7146 // Note that the structure of the jmp_buf used here is not compatible
7147 // with that used by libc, and is not designed to be. Specifically, it
7148 // stores only those 'reserved' registers that LLVM does not otherwise
7149 // understand how to spill. Also, by convention, by the time this
7150 // intrinsic is called, Clang has already stored the frame address in the
7151 // first slot of the buffer and stack address in the third. Following the
7152 // X86 target code, we'll store the jump address in the second slot. We also
7153 // need to save the TOC pointer (R2) to handle jumps between shared
7154 // libraries, and that will be stored in the fourth slot. The thread
7155 // identifier (R13) is not affected.
7158 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7159 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7160 const int64_t BPOffset = 4 * PVT.getStoreSize();
7162 // Prepare IP either in reg.
7163 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7164 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7165 unsigned BufReg = MI->getOperand(1).getReg();
7167 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7168 setUsesTOCBasePtr(*MBB->getParent());
7169 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7173 MIB.setMemRefs(MMOBegin, MMOEnd);
7176 // Naked functions never have a base pointer, and so we use r1. For all
7177 // other functions, this decision must be delayed until during PEI.
7179 if (MF->getFunction()->getAttributes().hasAttribute(
7180 AttributeSet::FunctionIndex, Attribute::Naked))
7181 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7183 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7185 MIB = BuildMI(*thisMBB, MI, DL,
7186 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7190 MIB.setMemRefs(MMOBegin, MMOEnd);
7193 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7194 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
7195 MIB.addRegMask(TRI->getNoPreservedMask());
7197 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7199 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7201 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7203 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7204 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7209 BuildMI(mainMBB, DL,
7210 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7213 if (Subtarget.isPPC64()) {
7214 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7216 .addImm(LabelOffset)
7219 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7221 .addImm(LabelOffset)
7225 MIB.setMemRefs(MMOBegin, MMOEnd);
7227 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7228 mainMBB->addSuccessor(sinkMBB);
7231 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7232 TII->get(PPC::PHI), DstReg)
7233 .addReg(mainDstReg).addMBB(mainMBB)
7234 .addReg(restoreDstReg).addMBB(thisMBB);
7236 MI->eraseFromParent();
7241 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7242 MachineBasicBlock *MBB) const {
7243 DebugLoc DL = MI->getDebugLoc();
7244 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7246 MachineFunction *MF = MBB->getParent();
7247 MachineRegisterInfo &MRI = MF->getRegInfo();
7250 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7251 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7253 MVT PVT = getPointerTy();
7254 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7255 "Invalid Pointer Size!");
7257 const TargetRegisterClass *RC =
7258 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7259 unsigned Tmp = MRI.createVirtualRegister(RC);
7260 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7261 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7262 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7266 : (Subtarget.isSVR4ABI() &&
7267 MF->getTarget().getRelocationModel() == Reloc::PIC_
7271 MachineInstrBuilder MIB;
7273 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7274 const int64_t SPOffset = 2 * PVT.getStoreSize();
7275 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7276 const int64_t BPOffset = 4 * PVT.getStoreSize();
7278 unsigned BufReg = MI->getOperand(0).getReg();
7280 // Reload FP (the jumped-to function may not have had a
7281 // frame pointer, and if so, then its r31 will be restored
7283 if (PVT == MVT::i64) {
7284 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7288 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7292 MIB.setMemRefs(MMOBegin, MMOEnd);
7295 if (PVT == MVT::i64) {
7296 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7297 .addImm(LabelOffset)
7300 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7301 .addImm(LabelOffset)
7304 MIB.setMemRefs(MMOBegin, MMOEnd);
7307 if (PVT == MVT::i64) {
7308 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7312 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7316 MIB.setMemRefs(MMOBegin, MMOEnd);
7319 if (PVT == MVT::i64) {
7320 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7324 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7328 MIB.setMemRefs(MMOBegin, MMOEnd);
7331 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7332 setUsesTOCBasePtr(*MBB->getParent());
7333 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7337 MIB.setMemRefs(MMOBegin, MMOEnd);
7341 BuildMI(*MBB, MI, DL,
7342 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7343 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7345 MI->eraseFromParent();
7350 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7351 MachineBasicBlock *BB) const {
7352 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7353 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7354 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
7355 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
7356 // Call lowering should have added an r2 operand to indicate a dependence
7357 // on the TOC base pointer value. It can't however, because there is no
7358 // way to mark the dependence as implicit there, and so the stackmap code
7359 // will confuse it with a regular operand. Instead, add the dependence
7361 setUsesTOCBasePtr(*BB->getParent());
7362 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
7365 return emitPatchPoint(MI, BB);
7368 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7369 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7370 return emitEHSjLjSetJmp(MI, BB);
7371 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7372 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7373 return emitEHSjLjLongJmp(MI, BB);
7376 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7378 // To "insert" these instructions we actually have to insert their
7379 // control-flow patterns.
7380 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7381 MachineFunction::iterator It = BB;
7384 MachineFunction *F = BB->getParent();
7386 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7387 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7388 MI->getOpcode() == PPC::SELECT_I4 ||
7389 MI->getOpcode() == PPC::SELECT_I8)) {
7390 SmallVector<MachineOperand, 2> Cond;
7391 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7392 MI->getOpcode() == PPC::SELECT_CC_I8)
7393 Cond.push_back(MI->getOperand(4));
7395 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7396 Cond.push_back(MI->getOperand(1));
7398 DebugLoc dl = MI->getDebugLoc();
7399 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7400 Cond, MI->getOperand(2).getReg(),
7401 MI->getOperand(3).getReg());
7402 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7403 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7404 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7405 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7406 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7407 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7408 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7409 MI->getOpcode() == PPC::SELECT_I4 ||
7410 MI->getOpcode() == PPC::SELECT_I8 ||
7411 MI->getOpcode() == PPC::SELECT_F4 ||
7412 MI->getOpcode() == PPC::SELECT_F8 ||
7413 MI->getOpcode() == PPC::SELECT_VRRC ||
7414 MI->getOpcode() == PPC::SELECT_VSFRC ||
7415 MI->getOpcode() == PPC::SELECT_VSRC) {
7416 // The incoming instruction knows the destination vreg to set, the
7417 // condition code register to branch on, the true/false values to
7418 // select between, and a branch opcode to use.
7423 // cmpTY ccX, r1, r2
7425 // fallthrough --> copy0MBB
7426 MachineBasicBlock *thisMBB = BB;
7427 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7428 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7429 DebugLoc dl = MI->getDebugLoc();
7430 F->insert(It, copy0MBB);
7431 F->insert(It, sinkMBB);
7433 // Transfer the remainder of BB and its successor edges to sinkMBB.
7434 sinkMBB->splice(sinkMBB->begin(), BB,
7435 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7436 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7438 // Next, add the true and fallthrough blocks as its successors.
7439 BB->addSuccessor(copy0MBB);
7440 BB->addSuccessor(sinkMBB);
7442 if (MI->getOpcode() == PPC::SELECT_I4 ||
7443 MI->getOpcode() == PPC::SELECT_I8 ||
7444 MI->getOpcode() == PPC::SELECT_F4 ||
7445 MI->getOpcode() == PPC::SELECT_F8 ||
7446 MI->getOpcode() == PPC::SELECT_VRRC ||
7447 MI->getOpcode() == PPC::SELECT_VSFRC ||
7448 MI->getOpcode() == PPC::SELECT_VSRC) {
7449 BuildMI(BB, dl, TII->get(PPC::BC))
7450 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7452 unsigned SelectPred = MI->getOperand(4).getImm();
7453 BuildMI(BB, dl, TII->get(PPC::BCC))
7454 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7458 // %FalseValue = ...
7459 // # fallthrough to sinkMBB
7462 // Update machine-CFG edges
7463 BB->addSuccessor(sinkMBB);
7466 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7469 BuildMI(*BB, BB->begin(), dl,
7470 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7471 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7472 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7473 } else if (MI->getOpcode() == PPC::ReadTB) {
7474 // To read the 64-bit time-base register on a 32-bit target, we read the
7475 // two halves. Should the counter have wrapped while it was being read, we
7476 // need to try again.
7479 // mfspr Rx,TBU # load from TBU
7480 // mfspr Ry,TB # load from TB
7481 // mfspr Rz,TBU # load from TBU
7482 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7483 // bne readLoop # branch if they're not equal
7486 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7487 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7488 DebugLoc dl = MI->getDebugLoc();
7489 F->insert(It, readMBB);
7490 F->insert(It, sinkMBB);
7492 // Transfer the remainder of BB and its successor edges to sinkMBB.
7493 sinkMBB->splice(sinkMBB->begin(), BB,
7494 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7495 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7497 BB->addSuccessor(readMBB);
7500 MachineRegisterInfo &RegInfo = F->getRegInfo();
7501 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7502 unsigned LoReg = MI->getOperand(0).getReg();
7503 unsigned HiReg = MI->getOperand(1).getReg();
7505 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7506 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7507 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7509 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7511 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7512 .addReg(HiReg).addReg(ReadAgainReg);
7513 BuildMI(BB, dl, TII->get(PPC::BCC))
7514 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7516 BB->addSuccessor(readMBB);
7517 BB->addSuccessor(sinkMBB);
7519 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7520 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7521 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7522 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7523 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7524 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7525 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7526 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7528 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7529 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7530 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7531 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7532 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7533 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7534 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7535 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7537 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7538 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7539 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7540 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7541 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7542 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7543 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7544 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7546 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7547 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7548 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7549 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7550 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7551 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7552 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7553 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7555 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7556 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7557 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7558 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7559 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7560 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7561 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7562 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7564 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7565 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7566 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7567 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7569 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7571 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7573 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7574 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7575 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7576 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7577 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7578 BB = EmitAtomicBinary(MI, BB, false, 0);
7579 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7580 BB = EmitAtomicBinary(MI, BB, true, 0);
7582 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7583 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7584 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7586 unsigned dest = MI->getOperand(0).getReg();
7587 unsigned ptrA = MI->getOperand(1).getReg();
7588 unsigned ptrB = MI->getOperand(2).getReg();
7589 unsigned oldval = MI->getOperand(3).getReg();
7590 unsigned newval = MI->getOperand(4).getReg();
7591 DebugLoc dl = MI->getDebugLoc();
7593 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7594 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7595 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7596 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7597 F->insert(It, loop1MBB);
7598 F->insert(It, loop2MBB);
7599 F->insert(It, midMBB);
7600 F->insert(It, exitMBB);
7601 exitMBB->splice(exitMBB->begin(), BB,
7602 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7603 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7607 // fallthrough --> loopMBB
7608 BB->addSuccessor(loop1MBB);
7611 // l[wd]arx dest, ptr
7612 // cmp[wd] dest, oldval
7615 // st[wd]cx. newval, ptr
7619 // st[wd]cx. dest, ptr
7622 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7623 .addReg(ptrA).addReg(ptrB);
7624 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7625 .addReg(oldval).addReg(dest);
7626 BuildMI(BB, dl, TII->get(PPC::BCC))
7627 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7628 BB->addSuccessor(loop2MBB);
7629 BB->addSuccessor(midMBB);
7632 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7633 .addReg(newval).addReg(ptrA).addReg(ptrB);
7634 BuildMI(BB, dl, TII->get(PPC::BCC))
7635 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7636 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7637 BB->addSuccessor(loop1MBB);
7638 BB->addSuccessor(exitMBB);
7641 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7642 .addReg(dest).addReg(ptrA).addReg(ptrB);
7643 BB->addSuccessor(exitMBB);
7648 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7649 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7650 // We must use 64-bit registers for addresses when targeting 64-bit,
7651 // since we're actually doing arithmetic on them. Other registers
7653 bool is64bit = Subtarget.isPPC64();
7654 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7656 unsigned dest = MI->getOperand(0).getReg();
7657 unsigned ptrA = MI->getOperand(1).getReg();
7658 unsigned ptrB = MI->getOperand(2).getReg();
7659 unsigned oldval = MI->getOperand(3).getReg();
7660 unsigned newval = MI->getOperand(4).getReg();
7661 DebugLoc dl = MI->getDebugLoc();
7663 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7664 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7665 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7666 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7667 F->insert(It, loop1MBB);
7668 F->insert(It, loop2MBB);
7669 F->insert(It, midMBB);
7670 F->insert(It, exitMBB);
7671 exitMBB->splice(exitMBB->begin(), BB,
7672 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7673 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7675 MachineRegisterInfo &RegInfo = F->getRegInfo();
7676 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7677 : &PPC::GPRCRegClass;
7678 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7679 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7680 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7681 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7682 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7683 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7684 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7685 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7686 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7687 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7688 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7689 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7690 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7692 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7693 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7696 // fallthrough --> loopMBB
7697 BB->addSuccessor(loop1MBB);
7699 // The 4-byte load must be aligned, while a char or short may be
7700 // anywhere in the word. Hence all this nasty bookkeeping code.
7701 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7702 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7703 // xori shift, shift1, 24 [16]
7704 // rlwinm ptr, ptr1, 0, 0, 29
7705 // slw newval2, newval, shift
7706 // slw oldval2, oldval,shift
7707 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7708 // slw mask, mask2, shift
7709 // and newval3, newval2, mask
7710 // and oldval3, oldval2, mask
7712 // lwarx tmpDest, ptr
7713 // and tmp, tmpDest, mask
7714 // cmpw tmp, oldval3
7717 // andc tmp2, tmpDest, mask
7718 // or tmp4, tmp2, newval3
7723 // stwcx. tmpDest, ptr
7725 // srw dest, tmpDest, shift
7726 if (ptrA != ZeroReg) {
7727 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7728 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7729 .addReg(ptrA).addReg(ptrB);
7733 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7734 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7735 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7736 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7738 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7739 .addReg(Ptr1Reg).addImm(0).addImm(61);
7741 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7742 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7743 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7744 .addReg(newval).addReg(ShiftReg);
7745 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7746 .addReg(oldval).addReg(ShiftReg);
7748 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7750 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7751 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7752 .addReg(Mask3Reg).addImm(65535);
7754 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7755 .addReg(Mask2Reg).addReg(ShiftReg);
7756 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7757 .addReg(NewVal2Reg).addReg(MaskReg);
7758 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7759 .addReg(OldVal2Reg).addReg(MaskReg);
7762 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7763 .addReg(ZeroReg).addReg(PtrReg);
7764 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7765 .addReg(TmpDestReg).addReg(MaskReg);
7766 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7767 .addReg(TmpReg).addReg(OldVal3Reg);
7768 BuildMI(BB, dl, TII->get(PPC::BCC))
7769 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7770 BB->addSuccessor(loop2MBB);
7771 BB->addSuccessor(midMBB);
7774 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7775 .addReg(TmpDestReg).addReg(MaskReg);
7776 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7777 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7778 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7779 .addReg(ZeroReg).addReg(PtrReg);
7780 BuildMI(BB, dl, TII->get(PPC::BCC))
7781 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7782 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7783 BB->addSuccessor(loop1MBB);
7784 BB->addSuccessor(exitMBB);
7787 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7788 .addReg(ZeroReg).addReg(PtrReg);
7789 BB->addSuccessor(exitMBB);
7794 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7796 } else if (MI->getOpcode() == PPC::FADDrtz) {
7797 // This pseudo performs an FADD with rounding mode temporarily forced
7798 // to round-to-zero. We emit this via custom inserter since the FPSCR
7799 // is not modeled at the SelectionDAG level.
7800 unsigned Dest = MI->getOperand(0).getReg();
7801 unsigned Src1 = MI->getOperand(1).getReg();
7802 unsigned Src2 = MI->getOperand(2).getReg();
7803 DebugLoc dl = MI->getDebugLoc();
7805 MachineRegisterInfo &RegInfo = F->getRegInfo();
7806 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7808 // Save FPSCR value.
7809 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7811 // Set rounding mode to round-to-zero.
7812 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7813 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7815 // Perform addition.
7816 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7818 // Restore FPSCR value.
7819 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7820 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7821 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7822 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7823 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7824 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7825 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7826 PPC::ANDIo8 : PPC::ANDIo;
7827 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7828 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7830 MachineRegisterInfo &RegInfo = F->getRegInfo();
7831 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7832 &PPC::GPRCRegClass :
7833 &PPC::G8RCRegClass);
7835 DebugLoc dl = MI->getDebugLoc();
7836 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7837 .addReg(MI->getOperand(1).getReg()).addImm(1);
7838 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7839 MI->getOperand(0).getReg())
7840 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7842 llvm_unreachable("Unexpected instr type to insert");
7845 MI->eraseFromParent(); // The pseudo instruction is gone now.
7849 //===----------------------------------------------------------------------===//
7850 // Target Optimization Hooks
7851 //===----------------------------------------------------------------------===//
7853 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7854 DAGCombinerInfo &DCI,
7855 unsigned &RefinementSteps,
7856 bool &UseOneConstNR) const {
7857 EVT VT = Operand.getValueType();
7858 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7859 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7860 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7861 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7862 // Convergence is quadratic, so we essentially double the number of digits
7863 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7864 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7865 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7866 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7867 if (VT.getScalarType() == MVT::f64)
7869 UseOneConstNR = true;
7870 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7875 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7876 DAGCombinerInfo &DCI,
7877 unsigned &RefinementSteps) const {
7878 EVT VT = Operand.getValueType();
7879 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7880 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7881 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7882 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7883 // Convergence is quadratic, so we essentially double the number of digits
7884 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7885 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7886 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7887 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7888 if (VT.getScalarType() == MVT::f64)
7890 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7895 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7896 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7897 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7898 // enabled for division), this functionality is redundant with the default
7899 // combiner logic (once the division -> reciprocal/multiply transformation
7900 // has taken place). As a result, this matters more for older cores than for
7903 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7904 // reciprocal if there are two or more FDIVs (for embedded cores with only
7905 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7906 switch (Subtarget.getDarwinDirective()) {
7908 return NumUsers > 2;
7911 case PPC::DIR_E500mc:
7912 case PPC::DIR_E5500:
7913 return NumUsers > 1;
7917 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7918 unsigned Bytes, int Dist,
7919 SelectionDAG &DAG) {
7920 if (VT.getSizeInBits() / 8 != Bytes)
7923 SDValue BaseLoc = Base->getBasePtr();
7924 if (Loc.getOpcode() == ISD::FrameIndex) {
7925 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7927 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7928 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7929 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7930 int FS = MFI->getObjectSize(FI);
7931 int BFS = MFI->getObjectSize(BFI);
7932 if (FS != BFS || FS != (int)Bytes) return false;
7933 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7937 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7938 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7941 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7942 const GlobalValue *GV1 = nullptr;
7943 const GlobalValue *GV2 = nullptr;
7944 int64_t Offset1 = 0;
7945 int64_t Offset2 = 0;
7946 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7947 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7948 if (isGA1 && isGA2 && GV1 == GV2)
7949 return Offset1 == (Offset2 + Dist*Bytes);
7953 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7954 // not enforce equality of the chain operands.
7955 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7956 unsigned Bytes, int Dist,
7957 SelectionDAG &DAG) {
7958 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7959 EVT VT = LS->getMemoryVT();
7960 SDValue Loc = LS->getBasePtr();
7961 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7964 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7966 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7967 default: return false;
7968 case Intrinsic::ppc_altivec_lvx:
7969 case Intrinsic::ppc_altivec_lvxl:
7970 case Intrinsic::ppc_vsx_lxvw4x:
7973 case Intrinsic::ppc_vsx_lxvd2x:
7976 case Intrinsic::ppc_altivec_lvebx:
7979 case Intrinsic::ppc_altivec_lvehx:
7982 case Intrinsic::ppc_altivec_lvewx:
7987 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7990 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7992 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7993 default: return false;
7994 case Intrinsic::ppc_altivec_stvx:
7995 case Intrinsic::ppc_altivec_stvxl:
7996 case Intrinsic::ppc_vsx_stxvw4x:
7999 case Intrinsic::ppc_vsx_stxvd2x:
8002 case Intrinsic::ppc_altivec_stvebx:
8005 case Intrinsic::ppc_altivec_stvehx:
8008 case Intrinsic::ppc_altivec_stvewx:
8013 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8019 // Return true is there is a nearyby consecutive load to the one provided
8020 // (regardless of alignment). We search up and down the chain, looking though
8021 // token factors and other loads (but nothing else). As a result, a true result
8022 // indicates that it is safe to create a new consecutive load adjacent to the
8024 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8025 SDValue Chain = LD->getChain();
8026 EVT VT = LD->getMemoryVT();
8028 SmallSet<SDNode *, 16> LoadRoots;
8029 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8030 SmallSet<SDNode *, 16> Visited;
8032 // First, search up the chain, branching to follow all token-factor operands.
8033 // If we find a consecutive load, then we're done, otherwise, record all
8034 // nodes just above the top-level loads and token factors.
8035 while (!Queue.empty()) {
8036 SDNode *ChainNext = Queue.pop_back_val();
8037 if (!Visited.insert(ChainNext).second)
8040 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8041 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8044 if (!Visited.count(ChainLD->getChain().getNode()))
8045 Queue.push_back(ChainLD->getChain().getNode());
8046 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8047 for (const SDUse &O : ChainNext->ops())
8048 if (!Visited.count(O.getNode()))
8049 Queue.push_back(O.getNode());
8051 LoadRoots.insert(ChainNext);
8054 // Second, search down the chain, starting from the top-level nodes recorded
8055 // in the first phase. These top-level nodes are the nodes just above all
8056 // loads and token factors. Starting with their uses, recursively look though
8057 // all loads (just the chain uses) and token factors to find a consecutive
8062 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8063 IE = LoadRoots.end(); I != IE; ++I) {
8064 Queue.push_back(*I);
8066 while (!Queue.empty()) {
8067 SDNode *LoadRoot = Queue.pop_back_val();
8068 if (!Visited.insert(LoadRoot).second)
8071 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8072 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8075 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8076 UE = LoadRoot->use_end(); UI != UE; ++UI)
8077 if (((isa<MemSDNode>(*UI) &&
8078 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8079 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8080 Queue.push_back(*UI);
8087 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8088 DAGCombinerInfo &DCI) const {
8089 SelectionDAG &DAG = DCI.DAG;
8092 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
8093 // If we're tracking CR bits, we need to be careful that we don't have:
8094 // trunc(binary-ops(zext(x), zext(y)))
8096 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8097 // such that we're unnecessarily moving things into GPRs when it would be
8098 // better to keep them in CR bits.
8100 // Note that trunc here can be an actual i1 trunc, or can be the effective
8101 // truncation that comes from a setcc or select_cc.
8102 if (N->getOpcode() == ISD::TRUNCATE &&
8103 N->getValueType(0) != MVT::i1)
8106 if (N->getOperand(0).getValueType() != MVT::i32 &&
8107 N->getOperand(0).getValueType() != MVT::i64)
8110 if (N->getOpcode() == ISD::SETCC ||
8111 N->getOpcode() == ISD::SELECT_CC) {
8112 // If we're looking at a comparison, then we need to make sure that the
8113 // high bits (all except for the first) don't matter the result.
8115 cast<CondCodeSDNode>(N->getOperand(
8116 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8117 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8119 if (ISD::isSignedIntSetCC(CC)) {
8120 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8121 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8123 } else if (ISD::isUnsignedIntSetCC(CC)) {
8124 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8125 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8126 !DAG.MaskedValueIsZero(N->getOperand(1),
8127 APInt::getHighBitsSet(OpBits, OpBits-1)))
8130 // This is neither a signed nor an unsigned comparison, just make sure
8131 // that the high bits are equal.
8132 APInt Op1Zero, Op1One;
8133 APInt Op2Zero, Op2One;
8134 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8135 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8137 // We don't really care about what is known about the first bit (if
8138 // anything), so clear it in all masks prior to comparing them.
8139 Op1Zero.clearBit(0); Op1One.clearBit(0);
8140 Op2Zero.clearBit(0); Op2One.clearBit(0);
8142 if (Op1Zero != Op2Zero || Op1One != Op2One)
8147 // We now know that the higher-order bits are irrelevant, we just need to
8148 // make sure that all of the intermediate operations are bit operations, and
8149 // all inputs are extensions.
8150 if (N->getOperand(0).getOpcode() != ISD::AND &&
8151 N->getOperand(0).getOpcode() != ISD::OR &&
8152 N->getOperand(0).getOpcode() != ISD::XOR &&
8153 N->getOperand(0).getOpcode() != ISD::SELECT &&
8154 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8155 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8156 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8157 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8158 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8161 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8162 N->getOperand(1).getOpcode() != ISD::AND &&
8163 N->getOperand(1).getOpcode() != ISD::OR &&
8164 N->getOperand(1).getOpcode() != ISD::XOR &&
8165 N->getOperand(1).getOpcode() != ISD::SELECT &&
8166 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8167 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8168 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8169 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8170 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8173 SmallVector<SDValue, 4> Inputs;
8174 SmallVector<SDValue, 8> BinOps, PromOps;
8175 SmallPtrSet<SDNode *, 16> Visited;
8177 for (unsigned i = 0; i < 2; ++i) {
8178 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8179 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8180 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8181 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8182 isa<ConstantSDNode>(N->getOperand(i)))
8183 Inputs.push_back(N->getOperand(i));
8185 BinOps.push_back(N->getOperand(i));
8187 if (N->getOpcode() == ISD::TRUNCATE)
8191 // Visit all inputs, collect all binary operations (and, or, xor and
8192 // select) that are all fed by extensions.
8193 while (!BinOps.empty()) {
8194 SDValue BinOp = BinOps.back();
8197 if (!Visited.insert(BinOp.getNode()).second)
8200 PromOps.push_back(BinOp);
8202 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8203 // The condition of the select is not promoted.
8204 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8206 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8209 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8210 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8211 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8212 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8213 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8214 Inputs.push_back(BinOp.getOperand(i));
8215 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8216 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8217 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8218 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8219 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8220 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8221 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8222 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8223 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8224 BinOps.push_back(BinOp.getOperand(i));
8226 // We have an input that is not an extension or another binary
8227 // operation; we'll abort this transformation.
8233 // Make sure that this is a self-contained cluster of operations (which
8234 // is not quite the same thing as saying that everything has only one
8236 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8237 if (isa<ConstantSDNode>(Inputs[i]))
8240 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8241 UE = Inputs[i].getNode()->use_end();
8244 if (User != N && !Visited.count(User))
8247 // Make sure that we're not going to promote the non-output-value
8248 // operand(s) or SELECT or SELECT_CC.
8249 // FIXME: Although we could sometimes handle this, and it does occur in
8250 // practice that one of the condition inputs to the select is also one of
8251 // the outputs, we currently can't deal with this.
8252 if (User->getOpcode() == ISD::SELECT) {
8253 if (User->getOperand(0) == Inputs[i])
8255 } else if (User->getOpcode() == ISD::SELECT_CC) {
8256 if (User->getOperand(0) == Inputs[i] ||
8257 User->getOperand(1) == Inputs[i])
8263 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8264 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8265 UE = PromOps[i].getNode()->use_end();
8268 if (User != N && !Visited.count(User))
8271 // Make sure that we're not going to promote the non-output-value
8272 // operand(s) or SELECT or SELECT_CC.
8273 // FIXME: Although we could sometimes handle this, and it does occur in
8274 // practice that one of the condition inputs to the select is also one of
8275 // the outputs, we currently can't deal with this.
8276 if (User->getOpcode() == ISD::SELECT) {
8277 if (User->getOperand(0) == PromOps[i])
8279 } else if (User->getOpcode() == ISD::SELECT_CC) {
8280 if (User->getOperand(0) == PromOps[i] ||
8281 User->getOperand(1) == PromOps[i])
8287 // Replace all inputs with the extension operand.
8288 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8289 // Constants may have users outside the cluster of to-be-promoted nodes,
8290 // and so we need to replace those as we do the promotions.
8291 if (isa<ConstantSDNode>(Inputs[i]))
8294 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8297 // Replace all operations (these are all the same, but have a different
8298 // (i1) return type). DAG.getNode will validate that the types of
8299 // a binary operator match, so go through the list in reverse so that
8300 // we've likely promoted both operands first. Any intermediate truncations or
8301 // extensions disappear.
8302 while (!PromOps.empty()) {
8303 SDValue PromOp = PromOps.back();
8306 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8307 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8308 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8309 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8310 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8311 PromOp.getOperand(0).getValueType() != MVT::i1) {
8312 // The operand is not yet ready (see comment below).
8313 PromOps.insert(PromOps.begin(), PromOp);
8317 SDValue RepValue = PromOp.getOperand(0);
8318 if (isa<ConstantSDNode>(RepValue))
8319 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8321 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8326 switch (PromOp.getOpcode()) {
8327 default: C = 0; break;
8328 case ISD::SELECT: C = 1; break;
8329 case ISD::SELECT_CC: C = 2; break;
8332 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8333 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8334 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8335 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8336 // The to-be-promoted operands of this node have not yet been
8337 // promoted (this should be rare because we're going through the
8338 // list backward, but if one of the operands has several users in
8339 // this cluster of to-be-promoted nodes, it is possible).
8340 PromOps.insert(PromOps.begin(), PromOp);
8344 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8345 PromOp.getNode()->op_end());
8347 // If there are any constant inputs, make sure they're replaced now.
8348 for (unsigned i = 0; i < 2; ++i)
8349 if (isa<ConstantSDNode>(Ops[C+i]))
8350 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8352 DAG.ReplaceAllUsesOfValueWith(PromOp,
8353 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8356 // Now we're left with the initial truncation itself.
8357 if (N->getOpcode() == ISD::TRUNCATE)
8358 return N->getOperand(0);
8360 // Otherwise, this is a comparison. The operands to be compared have just
8361 // changed type (to i1), but everything else is the same.
8362 return SDValue(N, 0);
8365 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8366 DAGCombinerInfo &DCI) const {
8367 SelectionDAG &DAG = DCI.DAG;
8370 // If we're tracking CR bits, we need to be careful that we don't have:
8371 // zext(binary-ops(trunc(x), trunc(y)))
8373 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8374 // such that we're unnecessarily moving things into CR bits that can more
8375 // efficiently stay in GPRs. Note that if we're not certain that the high
8376 // bits are set as required by the final extension, we still may need to do
8377 // some masking to get the proper behavior.
8379 // This same functionality is important on PPC64 when dealing with
8380 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8381 // the return values of functions. Because it is so similar, it is handled
8384 if (N->getValueType(0) != MVT::i32 &&
8385 N->getValueType(0) != MVT::i64)
8388 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
8389 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
8392 if (N->getOperand(0).getOpcode() != ISD::AND &&
8393 N->getOperand(0).getOpcode() != ISD::OR &&
8394 N->getOperand(0).getOpcode() != ISD::XOR &&
8395 N->getOperand(0).getOpcode() != ISD::SELECT &&
8396 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8399 SmallVector<SDValue, 4> Inputs;
8400 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8401 SmallPtrSet<SDNode *, 16> Visited;
8403 // Visit all inputs, collect all binary operations (and, or, xor and
8404 // select) that are all fed by truncations.
8405 while (!BinOps.empty()) {
8406 SDValue BinOp = BinOps.back();
8409 if (!Visited.insert(BinOp.getNode()).second)
8412 PromOps.push_back(BinOp);
8414 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8415 // The condition of the select is not promoted.
8416 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8418 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8421 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8422 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8423 Inputs.push_back(BinOp.getOperand(i));
8424 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8425 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8426 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8427 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8428 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8429 BinOps.push_back(BinOp.getOperand(i));
8431 // We have an input that is not a truncation or another binary
8432 // operation; we'll abort this transformation.
8438 // The operands of a select that must be truncated when the select is
8439 // promoted because the operand is actually part of the to-be-promoted set.
8440 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8442 // Make sure that this is a self-contained cluster of operations (which
8443 // is not quite the same thing as saying that everything has only one
8445 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8446 if (isa<ConstantSDNode>(Inputs[i]))
8449 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8450 UE = Inputs[i].getNode()->use_end();
8453 if (User != N && !Visited.count(User))
8456 // If we're going to promote the non-output-value operand(s) or SELECT or
8457 // SELECT_CC, record them for truncation.
8458 if (User->getOpcode() == ISD::SELECT) {
8459 if (User->getOperand(0) == Inputs[i])
8460 SelectTruncOp[0].insert(std::make_pair(User,
8461 User->getOperand(0).getValueType()));
8462 } else if (User->getOpcode() == ISD::SELECT_CC) {
8463 if (User->getOperand(0) == Inputs[i])
8464 SelectTruncOp[0].insert(std::make_pair(User,
8465 User->getOperand(0).getValueType()));
8466 if (User->getOperand(1) == Inputs[i])
8467 SelectTruncOp[1].insert(std::make_pair(User,
8468 User->getOperand(1).getValueType()));
8473 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8474 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8475 UE = PromOps[i].getNode()->use_end();
8478 if (User != N && !Visited.count(User))
8481 // If we're going to promote the non-output-value operand(s) or SELECT or
8482 // SELECT_CC, record them for truncation.
8483 if (User->getOpcode() == ISD::SELECT) {
8484 if (User->getOperand(0) == PromOps[i])
8485 SelectTruncOp[0].insert(std::make_pair(User,
8486 User->getOperand(0).getValueType()));
8487 } else if (User->getOpcode() == ISD::SELECT_CC) {
8488 if (User->getOperand(0) == PromOps[i])
8489 SelectTruncOp[0].insert(std::make_pair(User,
8490 User->getOperand(0).getValueType()));
8491 if (User->getOperand(1) == PromOps[i])
8492 SelectTruncOp[1].insert(std::make_pair(User,
8493 User->getOperand(1).getValueType()));
8498 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8499 bool ReallyNeedsExt = false;
8500 if (N->getOpcode() != ISD::ANY_EXTEND) {
8501 // If all of the inputs are not already sign/zero extended, then
8502 // we'll still need to do that at the end.
8503 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8504 if (isa<ConstantSDNode>(Inputs[i]))
8508 Inputs[i].getOperand(0).getValueSizeInBits();
8509 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8511 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8512 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8513 APInt::getHighBitsSet(OpBits,
8514 OpBits-PromBits))) ||
8515 (N->getOpcode() == ISD::SIGN_EXTEND &&
8516 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8517 (OpBits-(PromBits-1)))) {
8518 ReallyNeedsExt = true;
8524 // Replace all inputs, either with the truncation operand, or a
8525 // truncation or extension to the final output type.
8526 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8527 // Constant inputs need to be replaced with the to-be-promoted nodes that
8528 // use them because they might have users outside of the cluster of
8530 if (isa<ConstantSDNode>(Inputs[i]))
8533 SDValue InSrc = Inputs[i].getOperand(0);
8534 if (Inputs[i].getValueType() == N->getValueType(0))
8535 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8536 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8537 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8538 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8539 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8540 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8541 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8543 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8544 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8547 // Replace all operations (these are all the same, but have a different
8548 // (promoted) return type). DAG.getNode will validate that the types of
8549 // a binary operator match, so go through the list in reverse so that
8550 // we've likely promoted both operands first.
8551 while (!PromOps.empty()) {
8552 SDValue PromOp = PromOps.back();
8556 switch (PromOp.getOpcode()) {
8557 default: C = 0; break;
8558 case ISD::SELECT: C = 1; break;
8559 case ISD::SELECT_CC: C = 2; break;
8562 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8563 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8564 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8565 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8566 // The to-be-promoted operands of this node have not yet been
8567 // promoted (this should be rare because we're going through the
8568 // list backward, but if one of the operands has several users in
8569 // this cluster of to-be-promoted nodes, it is possible).
8570 PromOps.insert(PromOps.begin(), PromOp);
8574 // For SELECT and SELECT_CC nodes, we do a similar check for any
8575 // to-be-promoted comparison inputs.
8576 if (PromOp.getOpcode() == ISD::SELECT ||
8577 PromOp.getOpcode() == ISD::SELECT_CC) {
8578 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8579 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8580 (SelectTruncOp[1].count(PromOp.getNode()) &&
8581 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8582 PromOps.insert(PromOps.begin(), PromOp);
8587 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8588 PromOp.getNode()->op_end());
8590 // If this node has constant inputs, then they'll need to be promoted here.
8591 for (unsigned i = 0; i < 2; ++i) {
8592 if (!isa<ConstantSDNode>(Ops[C+i]))
8594 if (Ops[C+i].getValueType() == N->getValueType(0))
8597 if (N->getOpcode() == ISD::SIGN_EXTEND)
8598 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8599 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8600 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8602 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8605 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8606 // truncate them again to the original value type.
8607 if (PromOp.getOpcode() == ISD::SELECT ||
8608 PromOp.getOpcode() == ISD::SELECT_CC) {
8609 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8610 if (SI0 != SelectTruncOp[0].end())
8611 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8612 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8613 if (SI1 != SelectTruncOp[1].end())
8614 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8617 DAG.ReplaceAllUsesOfValueWith(PromOp,
8618 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8621 // Now we're left with the initial extension itself.
8622 if (!ReallyNeedsExt)
8623 return N->getOperand(0);
8625 // To zero extend, just mask off everything except for the first bit (in the
8627 if (N->getOpcode() == ISD::ZERO_EXTEND)
8628 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8629 DAG.getConstant(APInt::getLowBitsSet(
8630 N->getValueSizeInBits(0), PromBits),
8631 N->getValueType(0)));
8633 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8634 "Invalid extension type");
8635 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8637 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8638 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8639 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8640 N->getOperand(0), ShiftCst), ShiftCst);
8643 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8644 DAGCombinerInfo &DCI) const {
8645 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8646 N->getOpcode() == ISD::UINT_TO_FP) &&
8647 "Need an int -> FP conversion node here");
8649 if (!Subtarget.has64BitSupport())
8652 SelectionDAG &DAG = DCI.DAG;
8656 // Don't handle ppc_fp128 here or i1 conversions.
8657 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8659 if (Op.getOperand(0).getValueType() == MVT::i1)
8662 // For i32 intermediate values, unfortunately, the conversion functions
8663 // leave the upper 32 bits of the value are undefined. Within the set of
8664 // scalar instructions, we have no method for zero- or sign-extending the
8665 // value. Thus, we cannot handle i32 intermediate values here.
8666 if (Op.getOperand(0).getValueType() == MVT::i32)
8669 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8670 "UINT_TO_FP is supported only with FPCVT");
8672 // If we have FCFIDS, then use it when converting to single-precision.
8673 // Otherwise, convert to double-precision and then round.
8674 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8675 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
8677 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
8679 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
8683 // If we're converting from a float, to an int, and back to a float again,
8684 // then we don't need the store/load pair at all.
8685 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8686 Subtarget.hasFPCVT()) ||
8687 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8688 SDValue Src = Op.getOperand(0).getOperand(0);
8689 if (Src.getValueType() == MVT::f32) {
8690 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8691 DCI.AddToWorklist(Src.getNode());
8695 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8698 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8699 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8701 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8702 FP = DAG.getNode(ISD::FP_ROUND, dl,
8703 MVT::f32, FP, DAG.getIntPtrConstant(0));
8704 DCI.AddToWorklist(FP.getNode());
8713 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8714 // builtins) into loads with swaps.
8715 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8716 DAGCombinerInfo &DCI) const {
8717 SelectionDAG &DAG = DCI.DAG;
8721 MachineMemOperand *MMO;
8723 switch (N->getOpcode()) {
8725 llvm_unreachable("Unexpected opcode for little endian VSX load");
8727 LoadSDNode *LD = cast<LoadSDNode>(N);
8728 Chain = LD->getChain();
8729 Base = LD->getBasePtr();
8730 MMO = LD->getMemOperand();
8731 // If the MMO suggests this isn't a load of a full vector, leave
8732 // things alone. For a built-in, we have to make the change for
8733 // correctness, so if there is a size problem that will be a bug.
8734 if (MMO->getSize() < 16)
8738 case ISD::INTRINSIC_W_CHAIN: {
8739 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8740 Chain = Intrin->getChain();
8741 Base = Intrin->getBasePtr();
8742 MMO = Intrin->getMemOperand();
8747 MVT VecTy = N->getValueType(0).getSimpleVT();
8748 SDValue LoadOps[] = { Chain, Base };
8749 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8750 DAG.getVTList(VecTy, MVT::Other),
8751 LoadOps, VecTy, MMO);
8752 DCI.AddToWorklist(Load.getNode());
8753 Chain = Load.getValue(1);
8754 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8755 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8756 DCI.AddToWorklist(Swap.getNode());
8760 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8761 // builtins) into stores with swaps.
8762 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8763 DAGCombinerInfo &DCI) const {
8764 SelectionDAG &DAG = DCI.DAG;
8769 MachineMemOperand *MMO;
8771 switch (N->getOpcode()) {
8773 llvm_unreachable("Unexpected opcode for little endian VSX store");
8775 StoreSDNode *ST = cast<StoreSDNode>(N);
8776 Chain = ST->getChain();
8777 Base = ST->getBasePtr();
8778 MMO = ST->getMemOperand();
8780 // If the MMO suggests this isn't a store of a full vector, leave
8781 // things alone. For a built-in, we have to make the change for
8782 // correctness, so if there is a size problem that will be a bug.
8783 if (MMO->getSize() < 16)
8787 case ISD::INTRINSIC_VOID: {
8788 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8789 Chain = Intrin->getChain();
8790 // Intrin->getBasePtr() oddly does not get what we want.
8791 Base = Intrin->getOperand(3);
8792 MMO = Intrin->getMemOperand();
8798 SDValue Src = N->getOperand(SrcOpnd);
8799 MVT VecTy = Src.getValueType().getSimpleVT();
8800 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8801 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8802 DCI.AddToWorklist(Swap.getNode());
8803 Chain = Swap.getValue(1);
8804 SDValue StoreOps[] = { Chain, Swap, Base };
8805 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8806 DAG.getVTList(MVT::Other),
8807 StoreOps, VecTy, MMO);
8808 DCI.AddToWorklist(Store.getNode());
8812 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8813 DAGCombinerInfo &DCI) const {
8814 SelectionDAG &DAG = DCI.DAG;
8816 switch (N->getOpcode()) {
8819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8820 if (C->isNullValue()) // 0 << V -> 0.
8821 return N->getOperand(0);
8825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8826 if (C->isNullValue()) // 0 >>u V -> 0.
8827 return N->getOperand(0);
8831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8832 if (C->isNullValue() || // 0 >>s V -> 0.
8833 C->isAllOnesValue()) // -1 >>s V -> -1.
8834 return N->getOperand(0);
8837 case ISD::SIGN_EXTEND:
8838 case ISD::ZERO_EXTEND:
8839 case ISD::ANY_EXTEND:
8840 return DAGCombineExtBoolTrunc(N, DCI);
8843 case ISD::SELECT_CC:
8844 return DAGCombineTruncBoolExt(N, DCI);
8845 case ISD::SINT_TO_FP:
8846 case ISD::UINT_TO_FP:
8847 return combineFPToIntToFP(N, DCI);
8849 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8850 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
8851 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8852 N->getOperand(1).getValueType() == MVT::i32 &&
8853 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8854 SDValue Val = N->getOperand(1).getOperand(0);
8855 if (Val.getValueType() == MVT::f32) {
8856 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8857 DCI.AddToWorklist(Val.getNode());
8859 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8860 DCI.AddToWorklist(Val.getNode());
8863 N->getOperand(0), Val, N->getOperand(2),
8864 DAG.getValueType(N->getOperand(1).getValueType())
8867 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8868 DAG.getVTList(MVT::Other), Ops,
8869 cast<StoreSDNode>(N)->getMemoryVT(),
8870 cast<StoreSDNode>(N)->getMemOperand());
8871 DCI.AddToWorklist(Val.getNode());
8875 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8876 if (cast<StoreSDNode>(N)->isUnindexed() &&
8877 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8878 N->getOperand(1).getNode()->hasOneUse() &&
8879 (N->getOperand(1).getValueType() == MVT::i32 ||
8880 N->getOperand(1).getValueType() == MVT::i16 ||
8881 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
8882 N->getOperand(1).getValueType() == MVT::i64))) {
8883 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8884 // Do an any-extend to 32-bits if this is a half-word input.
8885 if (BSwapOp.getValueType() == MVT::i16)
8886 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8889 N->getOperand(0), BSwapOp, N->getOperand(2),
8890 DAG.getValueType(N->getOperand(1).getValueType())
8893 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8894 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8895 cast<StoreSDNode>(N)->getMemOperand());
8898 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8899 EVT VT = N->getOperand(1).getValueType();
8900 if (VT.isSimple()) {
8901 MVT StoreVT = VT.getSimpleVT();
8902 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8903 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8904 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8905 return expandVSXStoreForLE(N, DCI);
8910 LoadSDNode *LD = cast<LoadSDNode>(N);
8911 EVT VT = LD->getValueType(0);
8913 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8914 if (VT.isSimple()) {
8915 MVT LoadVT = VT.getSimpleVT();
8916 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
8917 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8918 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8919 return expandVSXLoadForLE(N, DCI);
8922 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8923 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8924 if (ISD::isNON_EXTLoad(N) && VT.isVector() && Subtarget.hasAltivec() &&
8925 // P8 and later hardware should just use LOAD.
8926 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8927 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8928 LD->getAlignment() < ABIAlignment) {
8929 // This is a type-legal unaligned Altivec load.
8930 SDValue Chain = LD->getChain();
8931 SDValue Ptr = LD->getBasePtr();
8932 bool isLittleEndian = Subtarget.isLittleEndian();
8934 // This implements the loading of unaligned vectors as described in
8935 // the venerable Apple Velocity Engine overview. Specifically:
8936 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8937 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8939 // The general idea is to expand a sequence of one or more unaligned
8940 // loads into an alignment-based permutation-control instruction (lvsl
8941 // or lvsr), a series of regular vector loads (which always truncate
8942 // their input address to an aligned address), and a series of
8943 // permutations. The results of these permutations are the requested
8944 // loaded values. The trick is that the last "extra" load is not taken
8945 // from the address you might suspect (sizeof(vector) bytes after the
8946 // last requested load), but rather sizeof(vector) - 1 bytes after the
8947 // last requested vector. The point of this is to avoid a page fault if
8948 // the base address happened to be aligned. This works because if the
8949 // base address is aligned, then adding less than a full vector length
8950 // will cause the last vector in the sequence to be (re)loaded.
8951 // Otherwise, the next vector will be fetched as you might suspect was
8954 // We might be able to reuse the permutation generation from
8955 // a different base address offset from this one by an aligned amount.
8956 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8957 // optimization later.
8958 Intrinsic::ID Intr = (isLittleEndian ?
8959 Intrinsic::ppc_altivec_lvsr :
8960 Intrinsic::ppc_altivec_lvsl);
8961 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8963 // Create the new MMO for the new base load. It is like the original MMO,
8964 // but represents an area in memory almost twice the vector size centered
8965 // on the original address. If the address is unaligned, we might start
8966 // reading up to (sizeof(vector)-1) bytes below the address of the
8967 // original unaligned load.
8968 MachineFunction &MF = DAG.getMachineFunction();
8969 MachineMemOperand *BaseMMO =
8970 MF.getMachineMemOperand(LD->getMemOperand(),
8971 -LD->getMemoryVT().getStoreSize()+1,
8972 2*LD->getMemoryVT().getStoreSize()-1);
8974 // Create the new base load.
8975 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8977 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8979 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8980 DAG.getVTList(MVT::v4i32, MVT::Other),
8981 BaseLoadOps, MVT::v4i32, BaseMMO);
8983 // Note that the value of IncOffset (which is provided to the next
8984 // load's pointer info offset value, and thus used to calculate the
8985 // alignment), and the value of IncValue (which is actually used to
8986 // increment the pointer value) are different! This is because we
8987 // require the next load to appear to be aligned, even though it
8988 // is actually offset from the base pointer by a lesser amount.
8989 int IncOffset = VT.getSizeInBits() / 8;
8990 int IncValue = IncOffset;
8992 // Walk (both up and down) the chain looking for another load at the real
8993 // (aligned) offset (the alignment of the other load does not matter in
8994 // this case). If found, then do not use the offset reduction trick, as
8995 // that will prevent the loads from being later combined (as they would
8996 // otherwise be duplicates).
8997 if (!findConsecutiveLoad(LD, DAG))
9000 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9001 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9003 MachineMemOperand *ExtraMMO =
9004 MF.getMachineMemOperand(LD->getMemOperand(),
9005 1, 2*LD->getMemoryVT().getStoreSize()-1);
9006 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9008 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9009 DAG.getVTList(MVT::v4i32, MVT::Other),
9010 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9012 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9013 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9015 // Because vperm has a big-endian bias, we must reverse the order
9016 // of the input vectors and complement the permute control vector
9017 // when generating little endian code. We have already handled the
9018 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9019 // and ExtraLoad here.
9022 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9023 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9025 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9026 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9028 if (VT != MVT::v4i32)
9029 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9031 // The output of the permutation is our loaded result, the TokenFactor is
9033 DCI.CombineTo(N, Perm, TF);
9034 return SDValue(N, 0);
9038 case ISD::INTRINSIC_WO_CHAIN: {
9039 bool isLittleEndian = Subtarget.isLittleEndian();
9040 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
9041 : Intrinsic::ppc_altivec_lvsl);
9042 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9043 N->getOperand(1)->getOpcode() == ISD::ADD) {
9044 SDValue Add = N->getOperand(1);
9046 if (DAG.MaskedValueIsZero(
9048 APInt::getAllOnesValue(4 /* 16 byte alignment */)
9050 Add.getValueType().getScalarType().getSizeInBits()))) {
9051 SDNode *BasePtr = Add->getOperand(0).getNode();
9052 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9053 UE = BasePtr->use_end();
9055 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9056 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9058 // We've found another LVSL/LVSR, and this address is an aligned
9059 // multiple of that one. The results will be the same, so use the
9060 // one we've just found instead.
9062 return SDValue(*UI, 0);
9070 case ISD::INTRINSIC_W_CHAIN: {
9071 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9072 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9073 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9076 case Intrinsic::ppc_vsx_lxvw4x:
9077 case Intrinsic::ppc_vsx_lxvd2x:
9078 return expandVSXLoadForLE(N, DCI);
9083 case ISD::INTRINSIC_VOID: {
9084 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9085 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
9086 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9089 case Intrinsic::ppc_vsx_stxvw4x:
9090 case Intrinsic::ppc_vsx_stxvd2x:
9091 return expandVSXStoreForLE(N, DCI);
9097 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9098 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9099 N->getOperand(0).hasOneUse() &&
9100 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9101 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9102 N->getValueType(0) == MVT::i64))) {
9103 SDValue Load = N->getOperand(0);
9104 LoadSDNode *LD = cast<LoadSDNode>(Load);
9105 // Create the byte-swapping load.
9107 LD->getChain(), // Chain
9108 LD->getBasePtr(), // Ptr
9109 DAG.getValueType(N->getValueType(0)) // VT
9112 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9113 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9114 MVT::i64 : MVT::i32, MVT::Other),
9115 Ops, LD->getMemoryVT(), LD->getMemOperand());
9117 // If this is an i16 load, insert the truncate.
9118 SDValue ResVal = BSLoad;
9119 if (N->getValueType(0) == MVT::i16)
9120 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9122 // First, combine the bswap away. This makes the value produced by the
9124 DCI.CombineTo(N, ResVal);
9126 // Next, combine the load away, we give it a bogus result value but a real
9127 // chain result. The result value is dead because the bswap is dead.
9128 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9130 // Return N so it doesn't get rechecked!
9131 return SDValue(N, 0);
9135 case PPCISD::VCMP: {
9136 // If a VCMPo node already exists with exactly the same operands as this
9137 // node, use its result instead of this node (VCMPo computes both a CR6 and
9138 // a normal output).
9140 if (!N->getOperand(0).hasOneUse() &&
9141 !N->getOperand(1).hasOneUse() &&
9142 !N->getOperand(2).hasOneUse()) {
9144 // Scan all of the users of the LHS, looking for VCMPo's that match.
9145 SDNode *VCMPoNode = nullptr;
9147 SDNode *LHSN = N->getOperand(0).getNode();
9148 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9150 if (UI->getOpcode() == PPCISD::VCMPo &&
9151 UI->getOperand(1) == N->getOperand(1) &&
9152 UI->getOperand(2) == N->getOperand(2) &&
9153 UI->getOperand(0) == N->getOperand(0)) {
9158 // If there is no VCMPo node, or if the flag value has a single use, don't
9160 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9163 // Look at the (necessarily single) use of the flag value. If it has a
9164 // chain, this transformation is more complex. Note that multiple things
9165 // could use the value result, which we should ignore.
9166 SDNode *FlagUser = nullptr;
9167 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9168 FlagUser == nullptr; ++UI) {
9169 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9171 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9172 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9179 // If the user is a MFOCRF instruction, we know this is safe.
9180 // Otherwise we give up for right now.
9181 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9182 return SDValue(VCMPoNode, 0);
9187 SDValue Cond = N->getOperand(1);
9188 SDValue Target = N->getOperand(2);
9190 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9191 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9192 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9194 // We now need to make the intrinsic dead (it cannot be instruction
9196 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9197 assert(Cond.getNode()->hasOneUse() &&
9198 "Counter decrement has more than one use");
9200 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9201 N->getOperand(0), Target);
9206 // If this is a branch on an altivec predicate comparison, lower this so
9207 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9208 // lowering is done pre-legalize, because the legalizer lowers the predicate
9209 // compare down to code that is difficult to reassemble.
9210 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9211 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9213 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9214 // value. If so, pass-through the AND to get to the intrinsic.
9215 if (LHS.getOpcode() == ISD::AND &&
9216 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9217 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9218 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9219 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9220 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9222 LHS = LHS.getOperand(0);
9224 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9225 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9226 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9227 isa<ConstantSDNode>(RHS)) {
9228 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9229 "Counter decrement comparison is not EQ or NE");
9231 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9232 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9233 (CC == ISD::SETNE && !Val);
9235 // We now need to make the intrinsic dead (it cannot be instruction
9237 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9238 assert(LHS.getNode()->hasOneUse() &&
9239 "Counter decrement has more than one use");
9241 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9242 N->getOperand(0), N->getOperand(4));
9248 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9249 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9250 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9251 assert(isDot && "Can't compare against a vector result!");
9253 // If this is a comparison against something other than 0/1, then we know
9254 // that the condition is never/always true.
9255 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9256 if (Val != 0 && Val != 1) {
9257 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9258 return N->getOperand(0);
9259 // Always !=, turn it into an unconditional branch.
9260 return DAG.getNode(ISD::BR, dl, MVT::Other,
9261 N->getOperand(0), N->getOperand(4));
9264 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9266 // Create the PPCISD altivec 'dot' comparison node.
9268 LHS.getOperand(2), // LHS of compare
9269 LHS.getOperand(3), // RHS of compare
9270 DAG.getConstant(CompareOpc, MVT::i32)
9272 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9273 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9275 // Unpack the result based on how the target uses it.
9276 PPC::Predicate CompOpc;
9277 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9278 default: // Can't happen, don't crash on invalid number though.
9279 case 0: // Branch on the value of the EQ bit of CR6.
9280 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9282 case 1: // Branch on the inverted value of the EQ bit of CR6.
9283 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9285 case 2: // Branch on the value of the LT bit of CR6.
9286 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9288 case 3: // Branch on the inverted value of the LT bit of CR6.
9289 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9293 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9294 DAG.getConstant(CompOpc, MVT::i32),
9295 DAG.getRegister(PPC::CR6, MVT::i32),
9296 N->getOperand(4), CompNode.getValue(1));
9306 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9308 std::vector<SDNode *> *Created) const {
9309 // fold (sdiv X, pow2)
9310 EVT VT = N->getValueType(0);
9311 if (VT == MVT::i64 && !Subtarget.isPPC64())
9313 if ((VT != MVT::i32 && VT != MVT::i64) ||
9314 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9318 SDValue N0 = N->getOperand(0);
9320 bool IsNegPow2 = (-Divisor).isPowerOf2();
9321 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9322 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9324 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9326 Created->push_back(Op.getNode());
9329 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9331 Created->push_back(Op.getNode());
9337 //===----------------------------------------------------------------------===//
9338 // Inline Assembly Support
9339 //===----------------------------------------------------------------------===//
9341 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9344 const SelectionDAG &DAG,
9345 unsigned Depth) const {
9346 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9347 switch (Op.getOpcode()) {
9349 case PPCISD::LBRX: {
9350 // lhbrx is known to have the top bits cleared out.
9351 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9352 KnownZero = 0xFFFF0000;
9355 case ISD::INTRINSIC_WO_CHAIN: {
9356 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9358 case Intrinsic::ppc_altivec_vcmpbfp_p:
9359 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9360 case Intrinsic::ppc_altivec_vcmpequb_p:
9361 case Intrinsic::ppc_altivec_vcmpequh_p:
9362 case Intrinsic::ppc_altivec_vcmpequw_p:
9363 case Intrinsic::ppc_altivec_vcmpgefp_p:
9364 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9365 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9366 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9367 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9368 case Intrinsic::ppc_altivec_vcmpgtub_p:
9369 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9370 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9371 KnownZero = ~1U; // All bits but the low one are known to be zero.
9378 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9379 switch (Subtarget.getDarwinDirective()) {
9384 case PPC::DIR_PWR5X:
9386 case PPC::DIR_PWR6X:
9388 case PPC::DIR_PWR8: {
9392 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
9394 // For small loops (between 5 and 8 instructions), align to a 32-byte
9395 // boundary so that the entire loop fits in one instruction-cache line.
9396 uint64_t LoopSize = 0;
9397 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9398 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9399 LoopSize += TII->GetInstSizeInBytes(J);
9401 if (LoopSize > 16 && LoopSize <= 32)
9408 return TargetLowering::getPrefLoopAlignment(ML);
9411 /// getConstraintType - Given a constraint, return the type of
9412 /// constraint it is for this target.
9413 PPCTargetLowering::ConstraintType
9414 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9415 if (Constraint.size() == 1) {
9416 switch (Constraint[0]) {
9423 return C_RegisterClass;
9425 // FIXME: While Z does indicate a memory constraint, it specifically
9426 // indicates an r+r address (used in conjunction with the 'y' modifier
9427 // in the replacement string). Currently, we're forcing the base
9428 // register to be r0 in the asm printer (which is interpreted as zero)
9429 // and forming the complete address in the second register. This is
9433 } else if (Constraint == "wc") { // individual CR bits.
9434 return C_RegisterClass;
9435 } else if (Constraint == "wa" || Constraint == "wd" ||
9436 Constraint == "wf" || Constraint == "ws") {
9437 return C_RegisterClass; // VSX registers.
9439 return TargetLowering::getConstraintType(Constraint);
9442 /// Examine constraint type and operand type and determine a weight value.
9443 /// This object must already have been set up with the operand type
9444 /// and the current alternative constraint selected.
9445 TargetLowering::ConstraintWeight
9446 PPCTargetLowering::getSingleConstraintMatchWeight(
9447 AsmOperandInfo &info, const char *constraint) const {
9448 ConstraintWeight weight = CW_Invalid;
9449 Value *CallOperandVal = info.CallOperandVal;
9450 // If we don't have a value, we can't do a match,
9451 // but allow it at the lowest weight.
9452 if (!CallOperandVal)
9454 Type *type = CallOperandVal->getType();
9456 // Look at the constraint type.
9457 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9458 return CW_Register; // an individual CR bit.
9459 else if ((StringRef(constraint) == "wa" ||
9460 StringRef(constraint) == "wd" ||
9461 StringRef(constraint) == "wf") &&
9464 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9467 switch (*constraint) {
9469 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9472 if (type->isIntegerTy())
9473 weight = CW_Register;
9476 if (type->isFloatTy())
9477 weight = CW_Register;
9480 if (type->isDoubleTy())
9481 weight = CW_Register;
9484 if (type->isVectorTy())
9485 weight = CW_Register;
9488 weight = CW_Register;
9497 std::pair<unsigned, const TargetRegisterClass*>
9498 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9500 if (Constraint.size() == 1) {
9501 // GCC RS6000 Constraint Letters
9502 switch (Constraint[0]) {
9504 if (VT == MVT::i64 && Subtarget.isPPC64())
9505 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9506 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9508 if (VT == MVT::i64 && Subtarget.isPPC64())
9509 return std::make_pair(0U, &PPC::G8RCRegClass);
9510 return std::make_pair(0U, &PPC::GPRCRegClass);
9512 if (VT == MVT::f32 || VT == MVT::i32)
9513 return std::make_pair(0U, &PPC::F4RCRegClass);
9514 if (VT == MVT::f64 || VT == MVT::i64)
9515 return std::make_pair(0U, &PPC::F8RCRegClass);
9518 return std::make_pair(0U, &PPC::VRRCRegClass);
9520 return std::make_pair(0U, &PPC::CRRCRegClass);
9522 } else if (Constraint == "wc") { // an individual CR bit.
9523 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9524 } else if (Constraint == "wa" || Constraint == "wd" ||
9525 Constraint == "wf") {
9526 return std::make_pair(0U, &PPC::VSRCRegClass);
9527 } else if (Constraint == "ws") {
9528 return std::make_pair(0U, &PPC::VSFRCRegClass);
9531 std::pair<unsigned, const TargetRegisterClass*> R =
9532 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9534 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9535 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9536 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9538 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9539 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9540 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9541 PPC::GPRCRegClass.contains(R.first)) {
9542 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
9543 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9544 PPC::sub_32, &PPC::G8RCRegClass),
9545 &PPC::G8RCRegClass);
9548 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9549 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9551 R.second = &PPC::CRRCRegClass;
9558 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9559 /// vector. If it is invalid, don't add anything to Ops.
9560 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9561 std::string &Constraint,
9562 std::vector<SDValue>&Ops,
9563 SelectionDAG &DAG) const {
9566 // Only support length 1 constraints.
9567 if (Constraint.length() > 1) return;
9569 char Letter = Constraint[0];
9580 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9581 if (!CST) return; // Must be an immediate to match.
9582 int64_t Value = CST->getSExtValue();
9583 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9584 // numbers are printed as such.
9586 default: llvm_unreachable("Unknown constraint letter!");
9587 case 'I': // "I" is a signed 16-bit constant.
9588 if (isInt<16>(Value))
9589 Result = DAG.getTargetConstant(Value, TCVT);
9591 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9592 if (isShiftedUInt<16, 16>(Value))
9593 Result = DAG.getTargetConstant(Value, TCVT);
9595 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9596 if (isShiftedInt<16, 16>(Value))
9597 Result = DAG.getTargetConstant(Value, TCVT);
9599 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9600 if (isUInt<16>(Value))
9601 Result = DAG.getTargetConstant(Value, TCVT);
9603 case 'M': // "M" is a constant that is greater than 31.
9605 Result = DAG.getTargetConstant(Value, TCVT);
9607 case 'N': // "N" is a positive constant that is an exact power of two.
9608 if (Value > 0 && isPowerOf2_64(Value))
9609 Result = DAG.getTargetConstant(Value, TCVT);
9611 case 'O': // "O" is the constant zero.
9613 Result = DAG.getTargetConstant(Value, TCVT);
9615 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9616 if (isInt<16>(-Value))
9617 Result = DAG.getTargetConstant(Value, TCVT);
9624 if (Result.getNode()) {
9625 Ops.push_back(Result);
9629 // Handle standard constraint letters.
9630 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9633 // isLegalAddressingMode - Return true if the addressing mode represented
9634 // by AM is legal for this target, for a load/store of the specified type.
9635 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9637 // FIXME: PPC does not allow r+i addressing modes for vectors!
9639 // PPC allows a sign-extended 16-bit immediate field.
9640 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9643 // No global is ever allowed as a base.
9647 // PPC only support r+r,
9649 case 0: // "r+i" or just "i", depending on HasBaseReg.
9652 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9654 // Otherwise we have r+r or r+i.
9657 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9659 // Allow 2*r as r+r.
9662 // No other scales are supported.
9669 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9670 SelectionDAG &DAG) const {
9671 MachineFunction &MF = DAG.getMachineFunction();
9672 MachineFrameInfo *MFI = MF.getFrameInfo();
9673 MFI->setReturnAddressIsTaken(true);
9675 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9679 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9681 // Make sure the function does not optimize away the store of the RA to
9683 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9684 FuncInfo->setLRStoreRequired();
9685 bool isPPC64 = Subtarget.isPPC64();
9686 bool isDarwinABI = Subtarget.isDarwinABI();
9689 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9692 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9693 isPPC64? MVT::i64 : MVT::i32);
9694 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9695 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9697 MachinePointerInfo(), false, false, false, 0);
9700 // Just load the return address off the stack.
9701 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9702 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9703 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9706 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9707 SelectionDAG &DAG) const {
9709 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9711 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9712 bool isPPC64 = PtrVT == MVT::i64;
9714 MachineFunction &MF = DAG.getMachineFunction();
9715 MachineFrameInfo *MFI = MF.getFrameInfo();
9716 MFI->setFrameAddressIsTaken(true);
9718 // Naked functions never have a frame pointer, and so we use r1. For all
9719 // other functions, this decision must be delayed until during PEI.
9721 if (MF.getFunction()->getAttributes().hasAttribute(
9722 AttributeSet::FunctionIndex, Attribute::Naked))
9723 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9725 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9727 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9730 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9731 FrameAddr, MachinePointerInfo(), false, false,
9736 // FIXME? Maybe this could be a TableGen attribute on some registers and
9737 // this table could be generated automatically from RegInfo.
9738 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9740 bool isPPC64 = Subtarget.isPPC64();
9741 bool isDarwinABI = Subtarget.isDarwinABI();
9743 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9744 (!isPPC64 && VT != MVT::i32))
9745 report_fatal_error("Invalid register global variable type");
9747 bool is64Bit = isPPC64 && VT == MVT::i64;
9748 unsigned Reg = StringSwitch<unsigned>(RegName)
9749 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9750 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
9751 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9752 (is64Bit ? PPC::X13 : PPC::R13))
9757 report_fatal_error("Invalid register name global variable");
9761 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9762 // The PowerPC target isn't yet aware of offsets.
9766 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9768 unsigned Intrinsic) const {
9770 switch (Intrinsic) {
9771 case Intrinsic::ppc_altivec_lvx:
9772 case Intrinsic::ppc_altivec_lvxl:
9773 case Intrinsic::ppc_altivec_lvebx:
9774 case Intrinsic::ppc_altivec_lvehx:
9775 case Intrinsic::ppc_altivec_lvewx:
9776 case Intrinsic::ppc_vsx_lxvd2x:
9777 case Intrinsic::ppc_vsx_lxvw4x: {
9779 switch (Intrinsic) {
9780 case Intrinsic::ppc_altivec_lvebx:
9783 case Intrinsic::ppc_altivec_lvehx:
9786 case Intrinsic::ppc_altivec_lvewx:
9789 case Intrinsic::ppc_vsx_lxvd2x:
9797 Info.opc = ISD::INTRINSIC_W_CHAIN;
9799 Info.ptrVal = I.getArgOperand(0);
9800 Info.offset = -VT.getStoreSize()+1;
9801 Info.size = 2*VT.getStoreSize()-1;
9804 Info.readMem = true;
9805 Info.writeMem = false;
9808 case Intrinsic::ppc_altivec_stvx:
9809 case Intrinsic::ppc_altivec_stvxl:
9810 case Intrinsic::ppc_altivec_stvebx:
9811 case Intrinsic::ppc_altivec_stvehx:
9812 case Intrinsic::ppc_altivec_stvewx:
9813 case Intrinsic::ppc_vsx_stxvd2x:
9814 case Intrinsic::ppc_vsx_stxvw4x: {
9816 switch (Intrinsic) {
9817 case Intrinsic::ppc_altivec_stvebx:
9820 case Intrinsic::ppc_altivec_stvehx:
9823 case Intrinsic::ppc_altivec_stvewx:
9826 case Intrinsic::ppc_vsx_stxvd2x:
9834 Info.opc = ISD::INTRINSIC_VOID;
9836 Info.ptrVal = I.getArgOperand(1);
9837 Info.offset = -VT.getStoreSize()+1;
9838 Info.size = 2*VT.getStoreSize()-1;
9841 Info.readMem = false;
9842 Info.writeMem = true;
9852 /// getOptimalMemOpType - Returns the target specific optimal type for load
9853 /// and store operations as a result of memset, memcpy, and memmove
9854 /// lowering. If DstAlign is zero that means it's safe to destination
9855 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9856 /// means there isn't a need to check it against alignment requirement,
9857 /// probably because the source does not need to be loaded. If 'IsMemset' is
9858 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9859 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9860 /// source is constant so it does not need to be loaded.
9861 /// It returns EVT::Other if the type should be determined using generic
9862 /// target-independent logic.
9863 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9864 unsigned DstAlign, unsigned SrcAlign,
9865 bool IsMemset, bool ZeroMemset,
9867 MachineFunction &MF) const {
9868 if (Subtarget.isPPC64()) {
9875 /// \brief Returns true if it is beneficial to convert a load of a constant
9876 /// to just the constant itself.
9877 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9879 assert(Ty->isIntegerTy());
9881 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9882 if (BitSize == 0 || BitSize > 64)
9887 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9888 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9890 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9891 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9892 return NumBits1 == 64 && NumBits2 == 32;
9895 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9896 if (!VT1.isInteger() || !VT2.isInteger())
9898 unsigned NumBits1 = VT1.getSizeInBits();
9899 unsigned NumBits2 = VT2.getSizeInBits();
9900 return NumBits1 == 64 && NumBits2 == 32;
9903 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9904 // Generally speaking, zexts are not free, but they are free when they can be
9905 // folded with other operations.
9906 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9907 EVT MemVT = LD->getMemoryVT();
9908 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9909 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9910 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9911 LD->getExtensionType() == ISD::ZEXTLOAD))
9915 // FIXME: Add other cases...
9916 // - 32-bit shifts with a zext to i64
9917 // - zext after ctlz, bswap, etc.
9918 // - zext after and by a constant mask
9920 return TargetLowering::isZExtFree(Val, VT2);
9923 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9924 assert(VT.isFloatingPoint());
9928 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9929 return isInt<16>(Imm) || isUInt<16>(Imm);
9932 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9933 return isInt<16>(Imm) || isUInt<16>(Imm);
9936 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9940 if (DisablePPCUnaligned)
9943 // PowerPC supports unaligned memory access for simple non-vector types.
9944 // Although accessing unaligned addresses is not as efficient as accessing
9945 // aligned addresses, it is generally more efficient than manual expansion,
9946 // and generally only traps for software emulation when crossing page
9952 if (VT.getSimpleVT().isVector()) {
9953 if (Subtarget.hasVSX()) {
9954 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9955 VT != MVT::v4f32 && VT != MVT::v4i32)
9962 if (VT == MVT::ppcf128)
9971 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9972 VT = VT.getScalarType();
9977 switch (VT.getSimpleVT().SimpleTy) {
9989 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
9990 // LR is a callee-save register, but we must treat it as clobbered by any call
9991 // site. Hence we include LR in the scratch registers, which are in turn added
9992 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
9993 // to CTR, which is used by any indirect call.
9994 static const MCPhysReg ScratchRegs[] = {
9995 PPC::X12, PPC::LR8, PPC::CTR8, 0
10002 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10003 EVT VT , unsigned DefinedValues) const {
10004 if (VT == MVT::v2i64)
10007 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10010 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10011 if (DisableILPPref || Subtarget.enableMachineScheduler())
10012 return TargetLowering::getSchedulingPreference(N);
10017 // Create a fast isel object.
10019 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10020 const TargetLibraryInfo *LibInfo) const {
10021 return PPC::createFastISel(FuncInfo, LibInfo);