1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD , VT, Legal);
407 setOperationAction(ISD::SUB , VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::STORE, VT, Promote);
435 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
437 // No other operations are legal.
438 setOperationAction(ISD::MUL , VT, Expand);
439 setOperationAction(ISD::SDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UDIV, VT, Expand);
442 setOperationAction(ISD::UREM, VT, Expand);
443 setOperationAction(ISD::FDIV, VT, Expand);
444 setOperationAction(ISD::FREM, VT, Expand);
445 setOperationAction(ISD::FNEG, VT, Expand);
446 setOperationAction(ISD::FSQRT, VT, Expand);
447 setOperationAction(ISD::FLOG, VT, Expand);
448 setOperationAction(ISD::FLOG10, VT, Expand);
449 setOperationAction(ISD::FLOG2, VT, Expand);
450 setOperationAction(ISD::FEXP, VT, Expand);
451 setOperationAction(ISD::FEXP2, VT, Expand);
452 setOperationAction(ISD::FSIN, VT, Expand);
453 setOperationAction(ISD::FCOS, VT, Expand);
454 setOperationAction(ISD::FABS, VT, Expand);
455 setOperationAction(ISD::FPOWI, VT, Expand);
456 setOperationAction(ISD::FFLOOR, VT, Expand);
457 setOperationAction(ISD::FCEIL, VT, Expand);
458 setOperationAction(ISD::FTRUNC, VT, Expand);
459 setOperationAction(ISD::FRINT, VT, Expand);
460 setOperationAction(ISD::FNEARBYINT, VT, Expand);
461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
463 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
464 setOperationAction(ISD::MULHU, VT, Expand);
465 setOperationAction(ISD::MULHS, VT, Expand);
466 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
468 setOperationAction(ISD::UDIVREM, VT, Expand);
469 setOperationAction(ISD::SDIVREM, VT, Expand);
470 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
471 setOperationAction(ISD::FPOW, VT, Expand);
472 setOperationAction(ISD::BSWAP, VT, Expand);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::CTTZ, VT, Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::VSELECT, VT, Expand);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
479 for (MVT InnerVT : MVT::vector_valuetypes()) {
480 setTruncStoreAction(VT, InnerVT, Expand);
481 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
483 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
521 if (Subtarget.hasP8Altivec())
522 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
524 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
526 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
527 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
537 // Altivec does not contain unordered floating-point compare instructions
538 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
539 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
543 if (Subtarget.hasVSX()) {
544 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
545 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
548 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
549 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
550 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
551 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
553 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
555 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
556 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
558 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
559 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
561 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
562 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
563 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
564 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
565 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
567 // Share the Altivec comparison restrictions.
568 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
571 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
573 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
574 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
576 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
578 if (Subtarget.hasP8Vector())
579 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
581 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
583 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
584 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
586 if (Subtarget.hasP8Altivec()) {
587 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
588 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
589 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
591 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
594 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
595 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
596 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
598 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
600 // VSX v2i64 only supports non-arithmetic operations.
601 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
602 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
605 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
606 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
607 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
608 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
610 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
612 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
613 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
614 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
615 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
617 // Vector operation legalization checks the result type of
618 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
619 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
621 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
622 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
624 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
627 if (Subtarget.hasP8Altivec()) {
628 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
629 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
633 if (Subtarget.hasQPX()) {
634 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
635 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
636 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
637 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
640 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
642 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
643 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
645 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
646 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
648 if (!Subtarget.useCRBits())
649 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
650 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
652 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
653 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
654 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
655 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
656 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
657 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
660 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
661 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
663 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
664 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
665 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
667 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
668 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
669 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
671 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
672 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
673 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
674 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
675 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
676 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
677 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
679 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
680 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
682 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
683 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
685 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
687 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
688 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
689 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
690 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
692 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
693 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
695 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
696 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
698 if (!Subtarget.useCRBits())
699 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
700 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
703 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
704 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
705 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
706 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
708 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
711 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
713 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
714 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
715 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
717 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
718 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
719 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
720 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
721 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
722 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
723 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
725 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
726 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
728 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
729 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
731 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
733 setOperationAction(ISD::AND , MVT::v4i1, Legal);
734 setOperationAction(ISD::OR , MVT::v4i1, Legal);
735 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
737 if (!Subtarget.useCRBits())
738 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
739 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
741 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
742 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
745 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
746 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
748 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
750 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
752 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
753 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
755 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
757 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
758 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
759 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
760 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
762 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
763 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
764 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
765 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
767 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
768 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
770 // These need to set FE_INEXACT, and so cannot be vectorized here.
771 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
772 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
774 if (TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
776 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
782 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
784 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
785 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
789 if (Subtarget.has64BitSupport())
790 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
792 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
795 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
796 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
799 setBooleanContents(ZeroOrOneBooleanContent);
801 if (Subtarget.hasAltivec()) {
802 // Altivec instructions set fields to all zeros or all ones.
803 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
807 // These libcalls are not available in 32-bit.
808 setLibcallName(RTLIB::SHL_I128, nullptr);
809 setLibcallName(RTLIB::SRL_I128, nullptr);
810 setLibcallName(RTLIB::SRA_I128, nullptr);
814 setStackPointerRegisterToSaveRestore(PPC::X1);
815 setExceptionPointerRegister(PPC::X3);
816 setExceptionSelectorRegister(PPC::X4);
818 setStackPointerRegisterToSaveRestore(PPC::R1);
819 setExceptionPointerRegister(PPC::R3);
820 setExceptionSelectorRegister(PPC::R4);
823 // We have target-specific dag combine patterns for the following nodes:
824 setTargetDAGCombine(ISD::SINT_TO_FP);
825 if (Subtarget.hasFPCVT())
826 setTargetDAGCombine(ISD::UINT_TO_FP);
827 setTargetDAGCombine(ISD::LOAD);
828 setTargetDAGCombine(ISD::STORE);
829 setTargetDAGCombine(ISD::BR_CC);
830 if (Subtarget.useCRBits())
831 setTargetDAGCombine(ISD::BRCOND);
832 setTargetDAGCombine(ISD::BSWAP);
833 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
834 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
835 setTargetDAGCombine(ISD::INTRINSIC_VOID);
837 setTargetDAGCombine(ISD::SIGN_EXTEND);
838 setTargetDAGCombine(ISD::ZERO_EXTEND);
839 setTargetDAGCombine(ISD::ANY_EXTEND);
841 if (Subtarget.useCRBits()) {
842 setTargetDAGCombine(ISD::TRUNCATE);
843 setTargetDAGCombine(ISD::SETCC);
844 setTargetDAGCombine(ISD::SELECT_CC);
847 // Use reciprocal estimates.
848 if (TM.Options.UnsafeFPMath) {
849 setTargetDAGCombine(ISD::FDIV);
850 setTargetDAGCombine(ISD::FSQRT);
853 // Darwin long double math library functions have $LDBL128 appended.
854 if (Subtarget.isDarwin()) {
855 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
856 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
857 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
858 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
859 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
860 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
861 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
862 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
863 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
864 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
867 // With 32 condition bits, we don't need to sink (and duplicate) compares
868 // aggressively in CodeGenPrep.
869 if (Subtarget.useCRBits()) {
870 setHasMultipleConditionRegisters();
871 setJumpIsExpensive();
874 setMinFunctionAlignment(2);
875 if (Subtarget.isDarwin())
876 setPrefFunctionAlignment(4);
878 switch (Subtarget.getDarwinDirective()) {
882 case PPC::DIR_E500mc:
891 setPrefFunctionAlignment(4);
892 setPrefLoopAlignment(4);
896 setInsertFencesForAtomic(true);
898 if (Subtarget.enableMachineScheduler())
899 setSchedulingPreference(Sched::Source);
901 setSchedulingPreference(Sched::Hybrid);
903 computeRegisterProperties(STI.getRegisterInfo());
905 // The Freescale cores do better with aggressive inlining of memcpy and
906 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
907 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
908 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
909 MaxStoresPerMemset = 32;
910 MaxStoresPerMemsetOptSize = 16;
911 MaxStoresPerMemcpy = 32;
912 MaxStoresPerMemcpyOptSize = 8;
913 MaxStoresPerMemmove = 32;
914 MaxStoresPerMemmoveOptSize = 8;
915 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
916 // The A2 also benefits from (very) aggressive inlining of memcpy and
917 // friends. The overhead of a the function call, even when warm, can be
918 // over one hundred cycles.
919 MaxStoresPerMemset = 128;
920 MaxStoresPerMemcpy = 128;
921 MaxStoresPerMemmove = 128;
925 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
926 /// the desired ByVal argument alignment.
927 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
928 unsigned MaxMaxAlign) {
929 if (MaxAlign == MaxMaxAlign)
931 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
932 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
934 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
936 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
937 unsigned EltAlign = 0;
938 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
939 if (EltAlign > MaxAlign)
941 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
942 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
943 unsigned EltAlign = 0;
944 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
945 if (EltAlign > MaxAlign)
947 if (MaxAlign == MaxMaxAlign)
953 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
954 /// function arguments in the caller parameter area.
955 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
956 const DataLayout &DL) const {
957 // Darwin passes everything on 4 byte boundary.
958 if (Subtarget.isDarwin())
961 // 16byte and wider vectors are passed on 16byte boundary.
962 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
963 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
964 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
965 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
969 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
970 switch ((PPCISD::NodeType)Opcode) {
971 case PPCISD::FIRST_NUMBER: break;
972 case PPCISD::FSEL: return "PPCISD::FSEL";
973 case PPCISD::FCFID: return "PPCISD::FCFID";
974 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
975 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
976 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
977 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
978 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
979 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
980 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
981 case PPCISD::FRE: return "PPCISD::FRE";
982 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
983 case PPCISD::STFIWX: return "PPCISD::STFIWX";
984 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
985 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
986 case PPCISD::VPERM: return "PPCISD::VPERM";
987 case PPCISD::CMPB: return "PPCISD::CMPB";
988 case PPCISD::Hi: return "PPCISD::Hi";
989 case PPCISD::Lo: return "PPCISD::Lo";
990 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
991 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
992 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
993 case PPCISD::SRL: return "PPCISD::SRL";
994 case PPCISD::SRA: return "PPCISD::SRA";
995 case PPCISD::SHL: return "PPCISD::SHL";
996 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
997 case PPCISD::CALL: return "PPCISD::CALL";
998 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
999 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1000 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1001 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1002 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1003 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1004 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1005 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1006 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1007 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1008 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1009 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1010 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1011 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1012 case PPCISD::VCMP: return "PPCISD::VCMP";
1013 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1014 case PPCISD::LBRX: return "PPCISD::LBRX";
1015 case PPCISD::STBRX: return "PPCISD::STBRX";
1016 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1017 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1018 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1019 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1020 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1021 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1022 case PPCISD::BDZ: return "PPCISD::BDZ";
1023 case PPCISD::MFFS: return "PPCISD::MFFS";
1024 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1025 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1026 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1027 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1028 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1029 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1030 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1031 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1032 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1033 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1034 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1035 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1036 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1037 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1038 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1039 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1040 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1041 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1042 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1043 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1044 case PPCISD::SC: return "PPCISD::SC";
1045 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1046 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1047 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1048 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1049 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1050 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1051 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1052 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1053 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1054 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1059 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1062 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1064 if (Subtarget.hasQPX())
1065 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1067 return VT.changeVectorElementTypeToInteger();
1070 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1071 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1075 //===----------------------------------------------------------------------===//
1076 // Node matching predicates, for use by the tblgen matching code.
1077 //===----------------------------------------------------------------------===//
1079 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1080 static bool isFloatingPointZero(SDValue Op) {
1081 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1082 return CFP->getValueAPF().isZero();
1083 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1084 // Maybe this has already been legalized into the constant pool?
1085 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1086 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1087 return CFP->getValueAPF().isZero();
1092 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1093 /// true if Op is undef or if it matches the specified value.
1094 static bool isConstantOrUndef(int Op, int Val) {
1095 return Op < 0 || Op == Val;
1098 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1099 /// VPKUHUM instruction.
1100 /// The ShuffleKind distinguishes between big-endian operations with
1101 /// two different inputs (0), either-endian operations with two identical
1102 /// inputs (1), and little-endian operations with two different inputs (2).
1103 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1104 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1105 SelectionDAG &DAG) {
1106 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1107 if (ShuffleKind == 0) {
1110 for (unsigned i = 0; i != 16; ++i)
1111 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1113 } else if (ShuffleKind == 2) {
1116 for (unsigned i = 0; i != 16; ++i)
1117 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1119 } else if (ShuffleKind == 1) {
1120 unsigned j = IsLE ? 0 : 1;
1121 for (unsigned i = 0; i != 8; ++i)
1122 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1123 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1129 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1130 /// VPKUWUM instruction.
1131 /// The ShuffleKind distinguishes between big-endian operations with
1132 /// two different inputs (0), either-endian operations with two identical
1133 /// inputs (1), and little-endian operations with two different inputs (2).
1134 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1135 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1136 SelectionDAG &DAG) {
1137 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1138 if (ShuffleKind == 0) {
1141 for (unsigned i = 0; i != 16; i += 2)
1142 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1143 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1145 } else if (ShuffleKind == 2) {
1148 for (unsigned i = 0; i != 16; i += 2)
1149 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1150 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1152 } else if (ShuffleKind == 1) {
1153 unsigned j = IsLE ? 0 : 2;
1154 for (unsigned i = 0; i != 8; i += 2)
1155 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1156 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1157 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1158 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1164 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1165 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1166 /// current subtarget.
1168 /// The ShuffleKind distinguishes between big-endian operations with
1169 /// two different inputs (0), either-endian operations with two identical
1170 /// inputs (1), and little-endian operations with two different inputs (2).
1171 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1172 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1173 SelectionDAG &DAG) {
1174 const PPCSubtarget& Subtarget =
1175 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1176 if (!Subtarget.hasP8Vector())
1179 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1180 if (ShuffleKind == 0) {
1183 for (unsigned i = 0; i != 16; i += 4)
1184 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1185 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1186 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1187 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1189 } else if (ShuffleKind == 2) {
1192 for (unsigned i = 0; i != 16; i += 4)
1193 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1194 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1195 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1196 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1198 } else if (ShuffleKind == 1) {
1199 unsigned j = IsLE ? 0 : 4;
1200 for (unsigned i = 0; i != 8; i += 4)
1201 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1202 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1203 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1204 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1205 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1206 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1207 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1208 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1214 /// isVMerge - Common function, used to match vmrg* shuffles.
1216 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1217 unsigned LHSStart, unsigned RHSStart) {
1218 if (N->getValueType(0) != MVT::v16i8)
1220 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1221 "Unsupported merge size!");
1223 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1224 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1225 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1226 LHSStart+j+i*UnitSize) ||
1227 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1228 RHSStart+j+i*UnitSize))
1234 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1235 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1236 /// The ShuffleKind distinguishes between big-endian merges with two
1237 /// different inputs (0), either-endian merges with two identical inputs (1),
1238 /// and little-endian merges with two different inputs (2). For the latter,
1239 /// the input operands are swapped (see PPCInstrAltivec.td).
1240 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1241 unsigned ShuffleKind, SelectionDAG &DAG) {
1242 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1243 if (ShuffleKind == 1) // unary
1244 return isVMerge(N, UnitSize, 0, 0);
1245 else if (ShuffleKind == 2) // swapped
1246 return isVMerge(N, UnitSize, 0, 16);
1250 if (ShuffleKind == 1) // unary
1251 return isVMerge(N, UnitSize, 8, 8);
1252 else if (ShuffleKind == 0) // normal
1253 return isVMerge(N, UnitSize, 8, 24);
1259 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1260 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1261 /// The ShuffleKind distinguishes between big-endian merges with two
1262 /// different inputs (0), either-endian merges with two identical inputs (1),
1263 /// and little-endian merges with two different inputs (2). For the latter,
1264 /// the input operands are swapped (see PPCInstrAltivec.td).
1265 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1266 unsigned ShuffleKind, SelectionDAG &DAG) {
1267 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1268 if (ShuffleKind == 1) // unary
1269 return isVMerge(N, UnitSize, 8, 8);
1270 else if (ShuffleKind == 2) // swapped
1271 return isVMerge(N, UnitSize, 8, 24);
1275 if (ShuffleKind == 1) // unary
1276 return isVMerge(N, UnitSize, 0, 0);
1277 else if (ShuffleKind == 0) // normal
1278 return isVMerge(N, UnitSize, 0, 16);
1285 * \brief Common function used to match vmrgew and vmrgow shuffles
1287 * The indexOffset determines whether to look for even or odd words in
1288 * the shuffle mask. This is based on the of the endianness of the target
1291 * - Use offset of 0 to check for odd elements
1292 * - Use offset of 4 to check for even elements
1294 * - Use offset of 0 to check for even elements
1295 * - Use offset of 4 to check for odd elements
1296 * A detailed description of the vector element ordering for little endian and
1297 * big endian can be found at
1298 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1299 * Targeting your applications - what little endian and big endian IBM XL C/C++
1300 * compiler differences mean to you
1302 * The mask to the shuffle vector instruction specifies the indices of the
1303 * elements from the two input vectors to place in the result. The elements are
1304 * numbered in array-access order, starting with the first vector. These vectors
1305 * are always of type v16i8, thus each vector will contain 16 elements of size
1306 * 8. More info on the shuffle vector can be found in the
1307 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1308 * Language Reference.
1310 * The RHSStartValue indicates whether the same input vectors are used (unary)
1311 * or two different input vectors are used, based on the following:
1312 * - If the instruction uses the same vector for both inputs, the range of the
1313 * indices will be 0 to 15. In this case, the RHSStart value passed should
1315 * - If the instruction has two different vectors then the range of the
1316 * indices will be 0 to 31. In this case, the RHSStart value passed should
1317 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1318 * to 31 specify elements in the second vector).
1320 * \param[in] N The shuffle vector SD Node to analyze
1321 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1322 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1323 * vector to the shuffle_vector instruction
1324 * \return true iff this shuffle vector represents an even or odd word merge
1326 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1327 unsigned RHSStartValue) {
1328 if (N->getValueType(0) != MVT::v16i8)
1331 for (unsigned i = 0; i < 2; ++i)
1332 for (unsigned j = 0; j < 4; ++j)
1333 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1334 i*RHSStartValue+j+IndexOffset) ||
1335 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1336 i*RHSStartValue+j+IndexOffset+8))
1342 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1343 * vmrgow instructions.
1345 * \param[in] N The shuffle vector SD Node to analyze
1346 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1347 * \param[in] ShuffleKind Identify the type of merge:
1348 * - 0 = big-endian merge with two different inputs;
1349 * - 1 = either-endian merge with two identical inputs;
1350 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1351 * little-endian merges).
1352 * \param[in] DAG The current SelectionDAG
1353 * \return true iff this shuffle mask
1355 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1356 unsigned ShuffleKind, SelectionDAG &DAG) {
1357 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1358 unsigned indexOffset = CheckEven ? 4 : 0;
1359 if (ShuffleKind == 1) // Unary
1360 return isVMerge(N, indexOffset, 0);
1361 else if (ShuffleKind == 2) // swapped
1362 return isVMerge(N, indexOffset, 16);
1367 unsigned indexOffset = CheckEven ? 0 : 4;
1368 if (ShuffleKind == 1) // Unary
1369 return isVMerge(N, indexOffset, 0);
1370 else if (ShuffleKind == 0) // Normal
1371 return isVMerge(N, indexOffset, 16);
1378 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1379 /// amount, otherwise return -1.
1380 /// The ShuffleKind distinguishes between big-endian operations with two
1381 /// different inputs (0), either-endian operations with two identical inputs
1382 /// (1), and little-endian operations with two different inputs (2). For the
1383 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1384 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1385 SelectionDAG &DAG) {
1386 if (N->getValueType(0) != MVT::v16i8)
1389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1391 // Find the first non-undef value in the shuffle mask.
1393 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1396 if (i == 16) return -1; // all undef.
1398 // Otherwise, check to see if the rest of the elements are consecutively
1399 // numbered from this value.
1400 unsigned ShiftAmt = SVOp->getMaskElt(i);
1401 if (ShiftAmt < i) return -1;
1404 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1406 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1407 // Check the rest of the elements to see if they are consecutive.
1408 for (++i; i != 16; ++i)
1409 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1411 } else if (ShuffleKind == 1) {
1412 // Check the rest of the elements to see if they are consecutive.
1413 for (++i; i != 16; ++i)
1414 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1419 if (ShuffleKind == 2 && isLE)
1420 ShiftAmt = 16 - ShiftAmt;
1425 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1426 /// specifies a splat of a single element that is suitable for input to
1427 /// VSPLTB/VSPLTH/VSPLTW.
1428 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1429 assert(N->getValueType(0) == MVT::v16i8 &&
1430 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1432 // This is a splat operation if each element of the permute is the same, and
1433 // if the value doesn't reference the second vector.
1434 unsigned ElementBase = N->getMaskElt(0);
1436 // FIXME: Handle UNDEF elements too!
1437 if (ElementBase >= 16)
1440 // Check that the indices are consecutive, in the case of a multi-byte element
1441 // splatted with a v16i8 mask.
1442 for (unsigned i = 1; i != EltSize; ++i)
1443 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1446 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1447 if (N->getMaskElt(i) < 0) continue;
1448 for (unsigned j = 0; j != EltSize; ++j)
1449 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1455 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1456 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1457 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1458 SelectionDAG &DAG) {
1459 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1460 assert(isSplatShuffleMask(SVOp, EltSize));
1461 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1462 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1464 return SVOp->getMaskElt(0) / EltSize;
1467 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1468 /// by using a vspltis[bhw] instruction of the specified element size, return
1469 /// the constant being splatted. The ByteSize field indicates the number of
1470 /// bytes of each element [124] -> [bhw].
1471 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1472 SDValue OpVal(nullptr, 0);
1474 // If ByteSize of the splat is bigger than the element size of the
1475 // build_vector, then we have a case where we are checking for a splat where
1476 // multiple elements of the buildvector are folded together into a single
1477 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1478 unsigned EltSize = 16/N->getNumOperands();
1479 if (EltSize < ByteSize) {
1480 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1481 SDValue UniquedVals[4];
1482 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1484 // See if all of the elements in the buildvector agree across.
1485 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1486 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1487 // If the element isn't a constant, bail fully out.
1488 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1491 if (!UniquedVals[i&(Multiple-1)].getNode())
1492 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1493 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1494 return SDValue(); // no match.
1497 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1498 // either constant or undef values that are identical for each chunk. See
1499 // if these chunks can form into a larger vspltis*.
1501 // Check to see if all of the leading entries are either 0 or -1. If
1502 // neither, then this won't fit into the immediate field.
1503 bool LeadingZero = true;
1504 bool LeadingOnes = true;
1505 for (unsigned i = 0; i != Multiple-1; ++i) {
1506 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1508 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1509 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1511 // Finally, check the least significant entry.
1513 if (!UniquedVals[Multiple-1].getNode())
1514 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1515 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1516 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1517 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1520 if (!UniquedVals[Multiple-1].getNode())
1521 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1522 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1523 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1524 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1530 // Check to see if this buildvec has a single non-undef value in its elements.
1531 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1532 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1533 if (!OpVal.getNode())
1534 OpVal = N->getOperand(i);
1535 else if (OpVal != N->getOperand(i))
1539 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1541 unsigned ValSizeInBytes = EltSize;
1543 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1544 Value = CN->getZExtValue();
1545 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1546 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1547 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1550 // If the splat value is larger than the element value, then we can never do
1551 // this splat. The only case that we could fit the replicated bits into our
1552 // immediate field for would be zero, and we prefer to use vxor for it.
1553 if (ValSizeInBytes < ByteSize) return SDValue();
1555 // If the element value is larger than the splat value, check if it consists
1556 // of a repeated bit pattern of size ByteSize.
1557 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1560 // Properly sign extend the value.
1561 int MaskVal = SignExtend32(Value, ByteSize * 8);
1563 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1564 if (MaskVal == 0) return SDValue();
1566 // Finally, if this value fits in a 5 bit sext field, return it
1567 if (SignExtend32<5>(MaskVal) == MaskVal)
1568 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1572 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1573 /// amount, otherwise return -1.
1574 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1575 EVT VT = N->getValueType(0);
1576 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1579 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1581 // Find the first non-undef value in the shuffle mask.
1583 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1586 if (i == 4) return -1; // all undef.
1588 // Otherwise, check to see if the rest of the elements are consecutively
1589 // numbered from this value.
1590 unsigned ShiftAmt = SVOp->getMaskElt(i);
1591 if (ShiftAmt < i) return -1;
1594 // Check the rest of the elements to see if they are consecutive.
1595 for (++i; i != 4; ++i)
1596 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1602 //===----------------------------------------------------------------------===//
1603 // Addressing Mode Selection
1604 //===----------------------------------------------------------------------===//
1606 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1607 /// or 64-bit immediate, and if the value can be accurately represented as a
1608 /// sign extension from a 16-bit value. If so, this returns true and the
1610 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1611 if (!isa<ConstantSDNode>(N))
1614 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1615 if (N->getValueType(0) == MVT::i32)
1616 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1618 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1620 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1621 return isIntS16Immediate(Op.getNode(), Imm);
1625 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1626 /// can be represented as an indexed [r+r] operation. Returns false if it
1627 /// can be more efficiently represented with [r+imm].
1628 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1630 SelectionDAG &DAG) const {
1632 if (N.getOpcode() == ISD::ADD) {
1633 if (isIntS16Immediate(N.getOperand(1), imm))
1634 return false; // r+i
1635 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1636 return false; // r+i
1638 Base = N.getOperand(0);
1639 Index = N.getOperand(1);
1641 } else if (N.getOpcode() == ISD::OR) {
1642 if (isIntS16Immediate(N.getOperand(1), imm))
1643 return false; // r+i can fold it if we can.
1645 // If this is an or of disjoint bitfields, we can codegen this as an add
1646 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1648 APInt LHSKnownZero, LHSKnownOne;
1649 APInt RHSKnownZero, RHSKnownOne;
1650 DAG.computeKnownBits(N.getOperand(0),
1651 LHSKnownZero, LHSKnownOne);
1653 if (LHSKnownZero.getBoolValue()) {
1654 DAG.computeKnownBits(N.getOperand(1),
1655 RHSKnownZero, RHSKnownOne);
1656 // If all of the bits are known zero on the LHS or RHS, the add won't
1658 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1659 Base = N.getOperand(0);
1660 Index = N.getOperand(1);
1669 // If we happen to be doing an i64 load or store into a stack slot that has
1670 // less than a 4-byte alignment, then the frame-index elimination may need to
1671 // use an indexed load or store instruction (because the offset may not be a
1672 // multiple of 4). The extra register needed to hold the offset comes from the
1673 // register scavenger, and it is possible that the scavenger will need to use
1674 // an emergency spill slot. As a result, we need to make sure that a spill slot
1675 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1677 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1678 // FIXME: This does not handle the LWA case.
1682 // NOTE: We'll exclude negative FIs here, which come from argument
1683 // lowering, because there are no known test cases triggering this problem
1684 // using packed structures (or similar). We can remove this exclusion if
1685 // we find such a test case. The reason why this is so test-case driven is
1686 // because this entire 'fixup' is only to prevent crashes (from the
1687 // register scavenger) on not-really-valid inputs. For example, if we have:
1689 // %b = bitcast i1* %a to i64*
1690 // store i64* a, i64 b
1691 // then the store should really be marked as 'align 1', but is not. If it
1692 // were marked as 'align 1' then the indexed form would have been
1693 // instruction-selected initially, and the problem this 'fixup' is preventing
1694 // won't happen regardless.
1698 MachineFunction &MF = DAG.getMachineFunction();
1699 MachineFrameInfo *MFI = MF.getFrameInfo();
1701 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1705 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1706 FuncInfo->setHasNonRISpills();
1709 /// Returns true if the address N can be represented by a base register plus
1710 /// a signed 16-bit displacement [r+imm], and if it is not better
1711 /// represented as reg+reg. If Aligned is true, only accept displacements
1712 /// suitable for STD and friends, i.e. multiples of 4.
1713 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1716 bool Aligned) const {
1717 // FIXME dl should come from parent load or store, not from address
1719 // If this can be more profitably realized as r+r, fail.
1720 if (SelectAddressRegReg(N, Disp, Base, DAG))
1723 if (N.getOpcode() == ISD::ADD) {
1725 if (isIntS16Immediate(N.getOperand(1), imm) &&
1726 (!Aligned || (imm & 3) == 0)) {
1727 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1728 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1729 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1730 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1732 Base = N.getOperand(0);
1734 return true; // [r+i]
1735 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1736 // Match LOAD (ADD (X, Lo(G))).
1737 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1738 && "Cannot handle constant offsets yet!");
1739 Disp = N.getOperand(1).getOperand(0); // The global address.
1740 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1741 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1742 Disp.getOpcode() == ISD::TargetConstantPool ||
1743 Disp.getOpcode() == ISD::TargetJumpTable);
1744 Base = N.getOperand(0);
1745 return true; // [&g+r]
1747 } else if (N.getOpcode() == ISD::OR) {
1749 if (isIntS16Immediate(N.getOperand(1), imm) &&
1750 (!Aligned || (imm & 3) == 0)) {
1751 // If this is an or of disjoint bitfields, we can codegen this as an add
1752 // (for better address arithmetic) if the LHS and RHS of the OR are
1753 // provably disjoint.
1754 APInt LHSKnownZero, LHSKnownOne;
1755 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1757 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1758 // If all of the bits are known zero on the LHS or RHS, the add won't
1760 if (FrameIndexSDNode *FI =
1761 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1762 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1763 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1765 Base = N.getOperand(0);
1767 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1771 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1772 // Loading from a constant address.
1774 // If this address fits entirely in a 16-bit sext immediate field, codegen
1777 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1778 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1779 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1780 CN->getValueType(0));
1784 // Handle 32-bit sext immediates with LIS + addr mode.
1785 if ((CN->getValueType(0) == MVT::i32 ||
1786 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1787 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1788 int Addr = (int)CN->getZExtValue();
1790 // Otherwise, break this down into an LIS + disp.
1791 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1793 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1795 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1796 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1801 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1802 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1803 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1804 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1807 return true; // [r+0]
1810 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1811 /// represented as an indexed [r+r] operation.
1812 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1814 SelectionDAG &DAG) const {
1815 // Check to see if we can easily represent this as an [r+r] address. This
1816 // will fail if it thinks that the address is more profitably represented as
1817 // reg+imm, e.g. where imm = 0.
1818 if (SelectAddressRegReg(N, Base, Index, DAG))
1821 // If the operand is an addition, always emit this as [r+r], since this is
1822 // better (for code size, and execution, as the memop does the add for free)
1823 // than emitting an explicit add.
1824 if (N.getOpcode() == ISD::ADD) {
1825 Base = N.getOperand(0);
1826 Index = N.getOperand(1);
1830 // Otherwise, do it the hard way, using R0 as the base register.
1831 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1837 /// getPreIndexedAddressParts - returns true by value, base pointer and
1838 /// offset pointer and addressing mode by reference if the node's address
1839 /// can be legally represented as pre-indexed load / store address.
1840 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1842 ISD::MemIndexedMode &AM,
1843 SelectionDAG &DAG) const {
1844 if (DisablePPCPreinc) return false;
1850 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1851 Ptr = LD->getBasePtr();
1852 VT = LD->getMemoryVT();
1853 Alignment = LD->getAlignment();
1854 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1855 Ptr = ST->getBasePtr();
1856 VT = ST->getMemoryVT();
1857 Alignment = ST->getAlignment();
1862 // PowerPC doesn't have preinc load/store instructions for vectors (except
1863 // for QPX, which does have preinc r+r forms).
1864 if (VT.isVector()) {
1865 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1867 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1873 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1875 // Common code will reject creating a pre-inc form if the base pointer
1876 // is a frame index, or if N is a store and the base pointer is either
1877 // the same as or a predecessor of the value being stored. Check for
1878 // those situations here, and try with swapped Base/Offset instead.
1881 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1884 SDValue Val = cast<StoreSDNode>(N)->getValue();
1885 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1890 std::swap(Base, Offset);
1896 // LDU/STU can only handle immediates that are a multiple of 4.
1897 if (VT != MVT::i64) {
1898 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1901 // LDU/STU need an address with at least 4-byte alignment.
1905 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1909 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1910 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1911 // sext i32 to i64 when addr mode is r+i.
1912 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1913 LD->getExtensionType() == ISD::SEXTLOAD &&
1914 isa<ConstantSDNode>(Offset))
1922 //===----------------------------------------------------------------------===//
1923 // LowerOperation implementation
1924 //===----------------------------------------------------------------------===//
1926 /// GetLabelAccessInfo - Return true if we should reference labels using a
1927 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1928 static bool GetLabelAccessInfo(const TargetMachine &TM,
1929 const PPCSubtarget &Subtarget,
1930 unsigned &HiOpFlags, unsigned &LoOpFlags,
1931 const GlobalValue *GV = nullptr) {
1932 HiOpFlags = PPCII::MO_HA;
1933 LoOpFlags = PPCII::MO_LO;
1935 // Don't use the pic base if not in PIC relocation model.
1936 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1939 HiOpFlags |= PPCII::MO_PIC_FLAG;
1940 LoOpFlags |= PPCII::MO_PIC_FLAG;
1943 // If this is a reference to a global value that requires a non-lazy-ptr, make
1944 // sure that instruction lowering adds it.
1945 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1946 HiOpFlags |= PPCII::MO_NLP_FLAG;
1947 LoOpFlags |= PPCII::MO_NLP_FLAG;
1949 if (GV->hasHiddenVisibility()) {
1950 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1951 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1958 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1959 SelectionDAG &DAG) {
1961 EVT PtrVT = HiPart.getValueType();
1962 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1964 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1965 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1967 // With PIC, the first instruction is actually "GR+hi(&G)".
1969 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1970 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1972 // Generate non-pic code that has direct accesses to the constant pool.
1973 // The address of the global is just (hi(&g)+lo(&g)).
1974 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1977 static void setUsesTOCBasePtr(MachineFunction &MF) {
1978 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1979 FuncInfo->setUsesTOCBasePtr();
1982 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1983 setUsesTOCBasePtr(DAG.getMachineFunction());
1986 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
1988 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1989 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
1990 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
1992 SDValue Ops[] = { GA, Reg };
1993 return DAG.getMemIntrinsicNode(PPCISD::TOC_ENTRY, dl,
1994 DAG.getVTList(VT, MVT::Other), Ops, VT,
1995 MachinePointerInfo::getGOT(), 0, false, true,
1999 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2000 SelectionDAG &DAG) const {
2001 EVT PtrVT = Op.getValueType();
2002 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2003 const Constant *C = CP->getConstVal();
2005 // 64-bit SVR4 ABI code is always position-independent.
2006 // The actual address of the GlobalValue is stored in the TOC.
2007 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2008 setUsesTOCBasePtr(DAG);
2009 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2010 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2013 unsigned MOHiFlag, MOLoFlag;
2015 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2017 if (isPIC && Subtarget.isSVR4ABI()) {
2018 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2019 PPCII::MO_PIC_FLAG);
2020 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2024 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2026 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2027 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2030 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2031 EVT PtrVT = Op.getValueType();
2032 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2034 // 64-bit SVR4 ABI code is always position-independent.
2035 // The actual address of the GlobalValue is stored in the TOC.
2036 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2037 setUsesTOCBasePtr(DAG);
2038 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2039 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2042 unsigned MOHiFlag, MOLoFlag;
2044 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2046 if (isPIC && Subtarget.isSVR4ABI()) {
2047 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2048 PPCII::MO_PIC_FLAG);
2049 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2052 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2053 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2054 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2057 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2058 SelectionDAG &DAG) const {
2059 EVT PtrVT = Op.getValueType();
2060 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2061 const BlockAddress *BA = BASDN->getBlockAddress();
2063 // 64-bit SVR4 ABI code is always position-independent.
2064 // The actual BlockAddress is stored in the TOC.
2065 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2066 setUsesTOCBasePtr(DAG);
2067 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2068 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2071 unsigned MOHiFlag, MOLoFlag;
2073 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2074 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2075 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2076 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2079 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2080 SelectionDAG &DAG) const {
2082 // FIXME: TLS addresses currently use medium model code sequences,
2083 // which is the most useful form. Eventually support for small and
2084 // large models could be added if users need it, at the cost of
2085 // additional complexity.
2086 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2088 const GlobalValue *GV = GA->getGlobal();
2089 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2090 bool is64bit = Subtarget.isPPC64();
2091 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2092 PICLevel::Level picLevel = M->getPICLevel();
2094 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2096 if (Model == TLSModel::LocalExec) {
2097 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2098 PPCII::MO_TPREL_HA);
2099 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2100 PPCII::MO_TPREL_LO);
2101 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2102 is64bit ? MVT::i64 : MVT::i32);
2103 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2104 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2107 if (Model == TLSModel::InitialExec) {
2108 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2109 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2113 setUsesTOCBasePtr(DAG);
2114 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2115 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2116 PtrVT, GOTReg, TGA);
2118 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2119 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2120 PtrVT, TGA, GOTPtr);
2121 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2124 if (Model == TLSModel::GeneralDynamic) {
2125 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2128 setUsesTOCBasePtr(DAG);
2129 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2130 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2133 if (picLevel == PICLevel::Small)
2134 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2136 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2138 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2142 if (Model == TLSModel::LocalDynamic) {
2143 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2146 setUsesTOCBasePtr(DAG);
2147 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2148 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2151 if (picLevel == PICLevel::Small)
2152 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2154 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2156 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2157 PtrVT, GOTPtr, TGA, TGA);
2158 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2159 PtrVT, TLSAddr, TGA);
2160 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2163 llvm_unreachable("Unknown TLS model!");
2166 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2167 SelectionDAG &DAG) const {
2168 EVT PtrVT = Op.getValueType();
2169 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2171 const GlobalValue *GV = GSDN->getGlobal();
2173 // 64-bit SVR4 ABI code is always position-independent.
2174 // The actual address of the GlobalValue is stored in the TOC.
2175 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2176 setUsesTOCBasePtr(DAG);
2177 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2178 return getTOCEntry(DAG, DL, true, GA);
2181 unsigned MOHiFlag, MOLoFlag;
2183 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2185 if (isPIC && Subtarget.isSVR4ABI()) {
2186 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2188 PPCII::MO_PIC_FLAG);
2189 return getTOCEntry(DAG, DL, false, GA);
2193 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2195 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2197 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2199 // If the global reference is actually to a non-lazy-pointer, we have to do an
2200 // extra load to get the address of the global.
2201 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2202 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2203 false, false, false, 0);
2207 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2208 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2211 if (Op.getValueType() == MVT::v2i64) {
2212 // When the operands themselves are v2i64 values, we need to do something
2213 // special because VSX has no underlying comparison operations for these.
2214 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2215 // Equality can be handled by casting to the legal type for Altivec
2216 // comparisons, everything else needs to be expanded.
2217 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2218 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2219 DAG.getSetCC(dl, MVT::v4i32,
2220 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2221 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2228 // We handle most of these in the usual way.
2232 // If we're comparing for equality to zero, expose the fact that this is
2233 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2234 // fold the new nodes.
2235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2236 if (C->isNullValue() && CC == ISD::SETEQ) {
2237 EVT VT = Op.getOperand(0).getValueType();
2238 SDValue Zext = Op.getOperand(0);
2239 if (VT.bitsLT(MVT::i32)) {
2241 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2243 unsigned Log2b = Log2_32(VT.getSizeInBits());
2244 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2245 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2246 DAG.getConstant(Log2b, dl, MVT::i32));
2247 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2249 // Leave comparisons against 0 and -1 alone for now, since they're usually
2250 // optimized. FIXME: revisit this when we can custom lower all setcc
2252 if (C->isAllOnesValue() || C->isNullValue())
2256 // If we have an integer seteq/setne, turn it into a compare against zero
2257 // by xor'ing the rhs with the lhs, which is faster than setting a
2258 // condition register, reading it back out, and masking the correct bit. The
2259 // normal approach here uses sub to do this instead of xor. Using xor exposes
2260 // the result to other bit-twiddling opportunities.
2261 EVT LHSVT = Op.getOperand(0).getValueType();
2262 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2263 EVT VT = Op.getValueType();
2264 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2266 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2271 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2272 const PPCSubtarget &Subtarget) const {
2273 SDNode *Node = Op.getNode();
2274 EVT VT = Node->getValueType(0);
2275 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2276 SDValue InChain = Node->getOperand(0);
2277 SDValue VAListPtr = Node->getOperand(1);
2278 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2281 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2284 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2285 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2286 false, false, false, 0);
2287 InChain = GprIndex.getValue(1);
2289 if (VT == MVT::i64) {
2290 // Check if GprIndex is even
2291 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2292 DAG.getConstant(1, dl, MVT::i32));
2293 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2294 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2295 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2296 DAG.getConstant(1, dl, MVT::i32));
2297 // Align GprIndex to be even if it isn't
2298 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2302 // fpr index is 1 byte after gpr
2303 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2304 DAG.getConstant(1, dl, MVT::i32));
2307 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2308 FprPtr, MachinePointerInfo(SV), MVT::i8,
2309 false, false, false, 0);
2310 InChain = FprIndex.getValue(1);
2312 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2313 DAG.getConstant(8, dl, MVT::i32));
2315 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2316 DAG.getConstant(4, dl, MVT::i32));
2319 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2320 MachinePointerInfo(), false, false,
2322 InChain = OverflowArea.getValue(1);
2324 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2325 MachinePointerInfo(), false, false,
2327 InChain = RegSaveArea.getValue(1);
2329 // select overflow_area if index > 8
2330 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2331 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2333 // adjustment constant gpr_index * 4/8
2334 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2335 VT.isInteger() ? GprIndex : FprIndex,
2336 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2339 // OurReg = RegSaveArea + RegConstant
2340 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2343 // Floating types are 32 bytes into RegSaveArea
2344 if (VT.isFloatingPoint())
2345 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2346 DAG.getConstant(32, dl, MVT::i32));
2348 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2349 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2350 VT.isInteger() ? GprIndex : FprIndex,
2351 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2354 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2355 VT.isInteger() ? VAListPtr : FprPtr,
2356 MachinePointerInfo(SV),
2357 MVT::i8, false, false, 0);
2359 // determine if we should load from reg_save_area or overflow_area
2360 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2362 // increase overflow_area by 4/8 if gpr/fpr > 8
2363 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2364 DAG.getConstant(VT.isInteger() ? 4 : 8,
2367 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2370 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2372 MachinePointerInfo(),
2373 MVT::i32, false, false, 0);
2375 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2376 false, false, false, 0);
2379 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2380 const PPCSubtarget &Subtarget) const {
2381 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2383 // We have to copy the entire va_list struct:
2384 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2385 return DAG.getMemcpy(Op.getOperand(0), Op,
2386 Op.getOperand(1), Op.getOperand(2),
2387 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2388 false, MachinePointerInfo(), MachinePointerInfo());
2391 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2392 SelectionDAG &DAG) const {
2393 return Op.getOperand(0);
2396 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2397 SelectionDAG &DAG) const {
2398 SDValue Chain = Op.getOperand(0);
2399 SDValue Trmp = Op.getOperand(1); // trampoline
2400 SDValue FPtr = Op.getOperand(2); // nested function
2401 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2404 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2405 bool isPPC64 = (PtrVT == MVT::i64);
2407 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2410 TargetLowering::ArgListTy Args;
2411 TargetLowering::ArgListEntry Entry;
2413 Entry.Ty = IntPtrTy;
2414 Entry.Node = Trmp; Args.push_back(Entry);
2416 // TrampSize == (isPPC64 ? 48 : 40);
2417 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2418 isPPC64 ? MVT::i64 : MVT::i32);
2419 Args.push_back(Entry);
2421 Entry.Node = FPtr; Args.push_back(Entry);
2422 Entry.Node = Nest; Args.push_back(Entry);
2424 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2425 TargetLowering::CallLoweringInfo CLI(DAG);
2426 CLI.setDebugLoc(dl).setChain(Chain)
2427 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2428 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2429 std::move(Args), 0);
2431 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2432 return CallResult.second;
2435 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2436 const PPCSubtarget &Subtarget) const {
2437 MachineFunction &MF = DAG.getMachineFunction();
2438 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2442 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2443 // vastart just stores the address of the VarArgsFrameIndex slot into the
2444 // memory location argument.
2445 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2446 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2447 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2448 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2449 MachinePointerInfo(SV),
2453 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2454 // We suppose the given va_list is already allocated.
2457 // char gpr; /* index into the array of 8 GPRs
2458 // * stored in the register save area
2459 // * gpr=0 corresponds to r3,
2460 // * gpr=1 to r4, etc.
2462 // char fpr; /* index into the array of 8 FPRs
2463 // * stored in the register save area
2464 // * fpr=0 corresponds to f1,
2465 // * fpr=1 to f2, etc.
2467 // char *overflow_arg_area;
2468 // /* location on stack that holds
2469 // * the next overflow argument
2471 // char *reg_save_area;
2472 // /* where r3:r10 and f1:f8 (if saved)
2478 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2479 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2481 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2483 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2485 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2488 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2489 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2491 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2492 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2494 uint64_t FPROffset = 1;
2495 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2497 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2499 // Store first byte : number of int regs
2500 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2502 MachinePointerInfo(SV),
2503 MVT::i8, false, false, 0);
2504 uint64_t nextOffset = FPROffset;
2505 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2508 // Store second byte : number of float regs
2509 SDValue secondStore =
2510 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2511 MachinePointerInfo(SV, nextOffset), MVT::i8,
2513 nextOffset += StackOffset;
2514 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2516 // Store second word : arguments given on stack
2517 SDValue thirdStore =
2518 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2519 MachinePointerInfo(SV, nextOffset),
2521 nextOffset += FrameOffset;
2522 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2524 // Store third word : arguments given in registers
2525 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2526 MachinePointerInfo(SV, nextOffset),
2531 #include "PPCGenCallingConv.inc"
2533 // Function whose sole purpose is to kill compiler warnings
2534 // stemming from unused functions included from PPCGenCallingConv.inc.
2535 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2536 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2539 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2540 CCValAssign::LocInfo &LocInfo,
2541 ISD::ArgFlagsTy &ArgFlags,
2546 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2548 CCValAssign::LocInfo &LocInfo,
2549 ISD::ArgFlagsTy &ArgFlags,
2551 static const MCPhysReg ArgRegs[] = {
2552 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2553 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2555 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2557 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2559 // Skip one register if the first unallocated register has an even register
2560 // number and there are still argument registers available which have not been
2561 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2562 // need to skip a register if RegNum is odd.
2563 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2564 State.AllocateReg(ArgRegs[RegNum]);
2567 // Always return false here, as this function only makes sure that the first
2568 // unallocated register has an odd register number and does not actually
2569 // allocate a register for the current argument.
2573 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2575 CCValAssign::LocInfo &LocInfo,
2576 ISD::ArgFlagsTy &ArgFlags,
2578 static const MCPhysReg ArgRegs[] = {
2579 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2583 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2585 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2587 // If there is only one Floating-point register left we need to put both f64
2588 // values of a split ppc_fp128 value on the stack.
2589 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2590 State.AllocateReg(ArgRegs[RegNum]);
2593 // Always return false here, as this function only makes sure that the two f64
2594 // values a ppc_fp128 value is split into are both passed in registers or both
2595 // passed on the stack and does not actually allocate a register for the
2596 // current argument.
2600 /// FPR - The set of FP registers that should be allocated for arguments,
2602 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2603 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2604 PPC::F11, PPC::F12, PPC::F13};
2606 /// QFPR - The set of QPX registers that should be allocated for arguments.
2607 static const MCPhysReg QFPR[] = {
2608 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2609 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2611 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2613 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2614 unsigned PtrByteSize) {
2615 unsigned ArgSize = ArgVT.getStoreSize();
2616 if (Flags.isByVal())
2617 ArgSize = Flags.getByValSize();
2619 // Round up to multiples of the pointer size, except for array members,
2620 // which are always packed.
2621 if (!Flags.isInConsecutiveRegs())
2622 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2627 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2629 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2630 ISD::ArgFlagsTy Flags,
2631 unsigned PtrByteSize) {
2632 unsigned Align = PtrByteSize;
2634 // Altivec parameters are padded to a 16 byte boundary.
2635 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2636 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2637 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2638 ArgVT == MVT::v1i128)
2640 // QPX vector types stored in double-precision are padded to a 32 byte
2642 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2645 // ByVal parameters are aligned as requested.
2646 if (Flags.isByVal()) {
2647 unsigned BVAlign = Flags.getByValAlign();
2648 if (BVAlign > PtrByteSize) {
2649 if (BVAlign % PtrByteSize != 0)
2651 "ByVal alignment is not a multiple of the pointer size");
2657 // Array members are always packed to their original alignment.
2658 if (Flags.isInConsecutiveRegs()) {
2659 // If the array member was split into multiple registers, the first
2660 // needs to be aligned to the size of the full type. (Except for
2661 // ppcf128, which is only aligned as its f64 components.)
2662 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2663 Align = OrigVT.getStoreSize();
2665 Align = ArgVT.getStoreSize();
2671 /// CalculateStackSlotUsed - Return whether this argument will use its
2672 /// stack slot (instead of being passed in registers). ArgOffset,
2673 /// AvailableFPRs, and AvailableVRs must hold the current argument
2674 /// position, and will be updated to account for this argument.
2675 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2676 ISD::ArgFlagsTy Flags,
2677 unsigned PtrByteSize,
2678 unsigned LinkageSize,
2679 unsigned ParamAreaSize,
2680 unsigned &ArgOffset,
2681 unsigned &AvailableFPRs,
2682 unsigned &AvailableVRs, bool HasQPX) {
2683 bool UseMemory = false;
2685 // Respect alignment of argument on the stack.
2687 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2688 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2689 // If there's no space left in the argument save area, we must
2690 // use memory (this check also catches zero-sized arguments).
2691 if (ArgOffset >= LinkageSize + ParamAreaSize)
2694 // Allocate argument on the stack.
2695 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2696 if (Flags.isInConsecutiveRegsLast())
2697 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2698 // If we overran the argument save area, we must use memory
2699 // (this check catches arguments passed partially in memory)
2700 if (ArgOffset > LinkageSize + ParamAreaSize)
2703 // However, if the argument is actually passed in an FPR or a VR,
2704 // we don't use memory after all.
2705 if (!Flags.isByVal()) {
2706 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2707 // QPX registers overlap with the scalar FP registers.
2708 (HasQPX && (ArgVT == MVT::v4f32 ||
2709 ArgVT == MVT::v4f64 ||
2710 ArgVT == MVT::v4i1)))
2711 if (AvailableFPRs > 0) {
2715 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2716 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2717 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2718 ArgVT == MVT::v1i128)
2719 if (AvailableVRs > 0) {
2728 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2729 /// ensure minimum alignment required for target.
2730 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2731 unsigned NumBytes) {
2732 unsigned TargetAlign = Lowering->getStackAlignment();
2733 unsigned AlignMask = TargetAlign - 1;
2734 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2739 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2740 CallingConv::ID CallConv, bool isVarArg,
2741 const SmallVectorImpl<ISD::InputArg>
2743 SDLoc dl, SelectionDAG &DAG,
2744 SmallVectorImpl<SDValue> &InVals)
2746 if (Subtarget.isSVR4ABI()) {
2747 if (Subtarget.isPPC64())
2748 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2751 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2754 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2760 PPCTargetLowering::LowerFormalArguments_32SVR4(
2762 CallingConv::ID CallConv, bool isVarArg,
2763 const SmallVectorImpl<ISD::InputArg>
2765 SDLoc dl, SelectionDAG &DAG,
2766 SmallVectorImpl<SDValue> &InVals) const {
2768 // 32-bit SVR4 ABI Stack Frame Layout:
2769 // +-----------------------------------+
2770 // +--> | Back chain |
2771 // | +-----------------------------------+
2772 // | | Floating-point register save area |
2773 // | +-----------------------------------+
2774 // | | General register save area |
2775 // | +-----------------------------------+
2776 // | | CR save word |
2777 // | +-----------------------------------+
2778 // | | VRSAVE save word |
2779 // | +-----------------------------------+
2780 // | | Alignment padding |
2781 // | +-----------------------------------+
2782 // | | Vector register save area |
2783 // | +-----------------------------------+
2784 // | | Local variable space |
2785 // | +-----------------------------------+
2786 // | | Parameter list area |
2787 // | +-----------------------------------+
2788 // | | LR save word |
2789 // | +-----------------------------------+
2790 // SP--> +--- | Back chain |
2791 // +-----------------------------------+
2794 // System V Application Binary Interface PowerPC Processor Supplement
2795 // AltiVec Technology Programming Interface Manual
2797 MachineFunction &MF = DAG.getMachineFunction();
2798 MachineFrameInfo *MFI = MF.getFrameInfo();
2799 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2801 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2802 // Potential tail calls could cause overwriting of argument stack slots.
2803 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2804 (CallConv == CallingConv::Fast));
2805 unsigned PtrByteSize = 4;
2807 // Assign locations to all of the incoming arguments.
2808 SmallVector<CCValAssign, 16> ArgLocs;
2809 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2812 // Reserve space for the linkage area on the stack.
2813 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2814 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2816 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2818 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2819 CCValAssign &VA = ArgLocs[i];
2821 // Arguments stored in registers.
2822 if (VA.isRegLoc()) {
2823 const TargetRegisterClass *RC;
2824 EVT ValVT = VA.getValVT();
2826 switch (ValVT.getSimpleVT().SimpleTy) {
2828 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2831 RC = &PPC::GPRCRegClass;
2834 if (Subtarget.hasP8Vector())
2835 RC = &PPC::VSSRCRegClass;
2837 RC = &PPC::F4RCRegClass;
2840 if (Subtarget.hasVSX())
2841 RC = &PPC::VSFRCRegClass;
2843 RC = &PPC::F8RCRegClass;
2848 RC = &PPC::VRRCRegClass;
2851 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2855 RC = &PPC::VSHRCRegClass;
2858 RC = &PPC::QFRCRegClass;
2861 RC = &PPC::QBRCRegClass;
2865 // Transform the arguments stored in physical registers into virtual ones.
2866 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2867 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2868 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2870 if (ValVT == MVT::i1)
2871 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2873 InVals.push_back(ArgValue);
2875 // Argument stored in memory.
2876 assert(VA.isMemLoc());
2878 unsigned ArgSize = VA.getLocVT().getStoreSize();
2879 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2882 // Create load nodes to retrieve arguments from the stack.
2883 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2884 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2885 MachinePointerInfo(),
2886 false, false, false, 0));
2890 // Assign locations to all of the incoming aggregate by value arguments.
2891 // Aggregates passed by value are stored in the local variable space of the
2892 // caller's stack frame, right above the parameter list area.
2893 SmallVector<CCValAssign, 16> ByValArgLocs;
2894 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2895 ByValArgLocs, *DAG.getContext());
2897 // Reserve stack space for the allocations in CCInfo.
2898 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2900 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2902 // Area that is at least reserved in the caller of this function.
2903 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2904 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2906 // Set the size that is at least reserved in caller of this function. Tail
2907 // call optimized function's reserved stack space needs to be aligned so that
2908 // taking the difference between two stack areas will result in an aligned
2911 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2912 FuncInfo->setMinReservedArea(MinReservedArea);
2914 SmallVector<SDValue, 8> MemOps;
2916 // If the function takes variable number of arguments, make a frame index for
2917 // the start of the first vararg value... for expansion of llvm.va_start.
2919 static const MCPhysReg GPArgRegs[] = {
2920 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2921 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2923 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2925 static const MCPhysReg FPArgRegs[] = {
2926 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2929 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2930 if (DisablePPCFloatInVariadic)
2933 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2934 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2936 // Make room for NumGPArgRegs and NumFPArgRegs.
2937 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2938 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2940 FuncInfo->setVarArgsStackOffset(
2941 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2942 CCInfo.getNextStackOffset(), true));
2944 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2945 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2947 // The fixed integer arguments of a variadic function are stored to the
2948 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2949 // the result of va_next.
2950 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2951 // Get an existing live-in vreg, or add a new one.
2952 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2954 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2956 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2957 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2958 MachinePointerInfo(), false, false, 0);
2959 MemOps.push_back(Store);
2960 // Increment the address by four for the next argument to store
2961 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2962 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2965 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2967 // The double arguments are stored to the VarArgsFrameIndex
2969 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2970 // Get an existing live-in vreg, or add a new one.
2971 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2973 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2975 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2976 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2977 MachinePointerInfo(), false, false, 0);
2978 MemOps.push_back(Store);
2979 // Increment the address by eight for the next argument to store
2980 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2982 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2986 if (!MemOps.empty())
2987 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2992 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2993 // value to MVT::i64 and then truncate to the correct register size.
2995 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2996 SelectionDAG &DAG, SDValue ArgVal,
2999 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3000 DAG.getValueType(ObjectVT));
3001 else if (Flags.isZExt())
3002 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3003 DAG.getValueType(ObjectVT));
3005 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3009 PPCTargetLowering::LowerFormalArguments_64SVR4(
3011 CallingConv::ID CallConv, bool isVarArg,
3012 const SmallVectorImpl<ISD::InputArg>
3014 SDLoc dl, SelectionDAG &DAG,
3015 SmallVectorImpl<SDValue> &InVals) const {
3016 // TODO: add description of PPC stack frame format, or at least some docs.
3018 bool isELFv2ABI = Subtarget.isELFv2ABI();
3019 bool isLittleEndian = Subtarget.isLittleEndian();
3020 MachineFunction &MF = DAG.getMachineFunction();
3021 MachineFrameInfo *MFI = MF.getFrameInfo();
3022 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3024 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3025 "fastcc not supported on varargs functions");
3027 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3028 // Potential tail calls could cause overwriting of argument stack slots.
3029 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3030 (CallConv == CallingConv::Fast));
3031 unsigned PtrByteSize = 8;
3032 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3034 static const MCPhysReg GPR[] = {
3035 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3036 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3038 static const MCPhysReg VR[] = {
3039 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3040 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3042 static const MCPhysReg VSRH[] = {
3043 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3044 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3047 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3048 const unsigned Num_FPR_Regs = 13;
3049 const unsigned Num_VR_Regs = array_lengthof(VR);
3050 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3052 // Do a first pass over the arguments to determine whether the ABI
3053 // guarantees that our caller has allocated the parameter save area
3054 // on its stack frame. In the ELFv1 ABI, this is always the case;
3055 // in the ELFv2 ABI, it is true if this is a vararg function or if
3056 // any parameter is located in a stack slot.
3058 bool HasParameterArea = !isELFv2ABI || isVarArg;
3059 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3060 unsigned NumBytes = LinkageSize;
3061 unsigned AvailableFPRs = Num_FPR_Regs;
3062 unsigned AvailableVRs = Num_VR_Regs;
3063 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
3064 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3065 PtrByteSize, LinkageSize, ParamAreaSize,
3066 NumBytes, AvailableFPRs, AvailableVRs,
3067 Subtarget.hasQPX()))
3068 HasParameterArea = true;
3070 // Add DAG nodes to load the arguments or copy them out of registers. On
3071 // entry to a function on PPC, the arguments start after the linkage area,
3072 // although the first ones are often in registers.
3074 unsigned ArgOffset = LinkageSize;
3075 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3076 unsigned &QFPR_idx = FPR_idx;
3077 SmallVector<SDValue, 8> MemOps;
3078 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3079 unsigned CurArgIdx = 0;
3080 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3082 bool needsLoad = false;
3083 EVT ObjectVT = Ins[ArgNo].VT;
3084 EVT OrigVT = Ins[ArgNo].ArgVT;
3085 unsigned ObjSize = ObjectVT.getStoreSize();
3086 unsigned ArgSize = ObjSize;
3087 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3088 if (Ins[ArgNo].isOrigArg()) {
3089 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3090 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3092 // We re-align the argument offset for each argument, except when using the
3093 // fast calling convention, when we need to make sure we do that only when
3094 // we'll actually use a stack slot.
3095 unsigned CurArgOffset, Align;
3096 auto ComputeArgOffset = [&]() {
3097 /* Respect alignment of argument on the stack. */
3098 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3099 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3100 CurArgOffset = ArgOffset;
3103 if (CallConv != CallingConv::Fast) {
3106 /* Compute GPR index associated with argument offset. */
3107 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3108 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3111 // FIXME the codegen can be much improved in some cases.
3112 // We do not have to keep everything in memory.
3113 if (Flags.isByVal()) {
3114 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3116 if (CallConv == CallingConv::Fast)
3119 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3120 ObjSize = Flags.getByValSize();
3121 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3122 // Empty aggregate parameters do not take up registers. Examples:
3126 // etc. However, we have to provide a place-holder in InVals, so
3127 // pretend we have an 8-byte item at the current address for that
3130 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3131 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3132 InVals.push_back(FIN);
3136 // Create a stack object covering all stack doublewords occupied
3137 // by the argument. If the argument is (fully or partially) on
3138 // the stack, or if the argument is fully in registers but the
3139 // caller has allocated the parameter save anyway, we can refer
3140 // directly to the caller's stack frame. Otherwise, create a
3141 // local copy in our own frame.
3143 if (HasParameterArea ||
3144 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3145 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3147 FI = MFI->CreateStackObject(ArgSize, Align, false);
3148 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3150 // Handle aggregates smaller than 8 bytes.
3151 if (ObjSize < PtrByteSize) {
3152 // The value of the object is its address, which differs from the
3153 // address of the enclosing doubleword on big-endian systems.
3155 if (!isLittleEndian) {
3156 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3157 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3159 InVals.push_back(Arg);
3161 if (GPR_idx != Num_GPR_Regs) {
3162 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3163 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3166 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3167 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3168 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3169 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3170 MachinePointerInfo(FuncArg),
3171 ObjType, false, false, 0);
3173 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3174 // store the whole register as-is to the parameter save area
3176 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3177 MachinePointerInfo(FuncArg),
3181 MemOps.push_back(Store);
3183 // Whether we copied from a register or not, advance the offset
3184 // into the parameter save area by a full doubleword.
3185 ArgOffset += PtrByteSize;
3189 // The value of the object is its address, which is the address of
3190 // its first stack doubleword.
3191 InVals.push_back(FIN);
3193 // Store whatever pieces of the object are in registers to memory.
3194 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3195 if (GPR_idx == Num_GPR_Regs)
3198 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3199 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3202 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3203 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3205 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3206 MachinePointerInfo(FuncArg, j),
3208 MemOps.push_back(Store);
3211 ArgOffset += ArgSize;
3215 switch (ObjectVT.getSimpleVT().SimpleTy) {
3216 default: llvm_unreachable("Unhandled argument type!");
3220 // These can be scalar arguments or elements of an integer array type
3221 // passed directly. Clang may use those instead of "byval" aggregate
3222 // types to avoid forcing arguments to memory unnecessarily.
3223 if (GPR_idx != Num_GPR_Regs) {
3224 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3225 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3227 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3228 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3229 // value to MVT::i64 and then truncate to the correct register size.
3230 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3232 if (CallConv == CallingConv::Fast)
3236 ArgSize = PtrByteSize;
3238 if (CallConv != CallingConv::Fast || needsLoad)
3244 // These can be scalar arguments or elements of a float array type
3245 // passed directly. The latter are used to implement ELFv2 homogenous
3246 // float aggregates.
3247 if (FPR_idx != Num_FPR_Regs) {
3250 if (ObjectVT == MVT::f32)
3251 VReg = MF.addLiveIn(FPR[FPR_idx],
3252 Subtarget.hasP8Vector()
3253 ? &PPC::VSSRCRegClass
3254 : &PPC::F4RCRegClass);
3256 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3257 ? &PPC::VSFRCRegClass
3258 : &PPC::F8RCRegClass);
3260 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3262 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3263 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3264 // once we support fp <-> gpr moves.
3266 // This can only ever happen in the presence of f32 array types,
3267 // since otherwise we never run out of FPRs before running out
3269 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3270 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3272 if (ObjectVT == MVT::f32) {
3273 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3274 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3275 DAG.getConstant(32, dl, MVT::i32));
3276 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3279 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3281 if (CallConv == CallingConv::Fast)
3287 // When passing an array of floats, the array occupies consecutive
3288 // space in the argument area; only round up to the next doubleword
3289 // at the end of the array. Otherwise, each float takes 8 bytes.
3290 if (CallConv != CallingConv::Fast || needsLoad) {
3291 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3292 ArgOffset += ArgSize;
3293 if (Flags.isInConsecutiveRegsLast())
3294 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3304 if (!Subtarget.hasQPX()) {
3305 // These can be scalar arguments or elements of a vector array type
3306 // passed directly. The latter are used to implement ELFv2 homogenous
3307 // vector aggregates.
3308 if (VR_idx != Num_VR_Regs) {
3309 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3310 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3311 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3312 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3315 if (CallConv == CallingConv::Fast)
3320 if (CallConv != CallingConv::Fast || needsLoad)
3325 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3326 "Invalid QPX parameter type");
3331 // QPX vectors are treated like their scalar floating-point subregisters
3332 // (except that they're larger).
3333 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3334 if (QFPR_idx != Num_QFPR_Regs) {
3335 const TargetRegisterClass *RC;
3336 switch (ObjectVT.getSimpleVT().SimpleTy) {
3337 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3338 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3339 default: RC = &PPC::QBRCRegClass; break;
3342 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3343 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3346 if (CallConv == CallingConv::Fast)
3350 if (CallConv != CallingConv::Fast || needsLoad)
3355 // We need to load the argument to a virtual register if we determined
3356 // above that we ran out of physical registers of the appropriate type.
3358 if (ObjSize < ArgSize && !isLittleEndian)
3359 CurArgOffset += ArgSize - ObjSize;
3360 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3361 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3362 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3363 false, false, false, 0);
3366 InVals.push_back(ArgVal);
3369 // Area that is at least reserved in the caller of this function.
3370 unsigned MinReservedArea;
3371 if (HasParameterArea)
3372 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3374 MinReservedArea = LinkageSize;
3376 // Set the size that is at least reserved in caller of this function. Tail
3377 // call optimized functions' reserved stack space needs to be aligned so that
3378 // taking the difference between two stack areas will result in an aligned
3381 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3382 FuncInfo->setMinReservedArea(MinReservedArea);
3384 // If the function takes variable number of arguments, make a frame index for
3385 // the start of the first vararg value... for expansion of llvm.va_start.
3387 int Depth = ArgOffset;
3389 FuncInfo->setVarArgsFrameIndex(
3390 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3391 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3393 // If this function is vararg, store any remaining integer argument regs
3394 // to their spots on the stack so that they may be loaded by deferencing the
3395 // result of va_next.
3396 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3397 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3398 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3399 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3400 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3401 MachinePointerInfo(), false, false, 0);
3402 MemOps.push_back(Store);
3403 // Increment the address by four for the next argument to store
3404 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3405 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3409 if (!MemOps.empty())
3410 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3416 PPCTargetLowering::LowerFormalArguments_Darwin(
3418 CallingConv::ID CallConv, bool isVarArg,
3419 const SmallVectorImpl<ISD::InputArg>
3421 SDLoc dl, SelectionDAG &DAG,
3422 SmallVectorImpl<SDValue> &InVals) const {
3423 // TODO: add description of PPC stack frame format, or at least some docs.
3425 MachineFunction &MF = DAG.getMachineFunction();
3426 MachineFrameInfo *MFI = MF.getFrameInfo();
3427 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3429 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3430 bool isPPC64 = PtrVT == MVT::i64;
3431 // Potential tail calls could cause overwriting of argument stack slots.
3432 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3433 (CallConv == CallingConv::Fast));
3434 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3435 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3436 unsigned ArgOffset = LinkageSize;
3437 // Area that is at least reserved in caller of this function.
3438 unsigned MinReservedArea = ArgOffset;
3440 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3441 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3442 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3444 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3445 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3446 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3448 static const MCPhysReg VR[] = {
3449 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3450 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3453 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3454 const unsigned Num_FPR_Regs = 13;
3455 const unsigned Num_VR_Regs = array_lengthof( VR);
3457 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3459 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3461 // In 32-bit non-varargs functions, the stack space for vectors is after the
3462 // stack space for non-vectors. We do not use this space unless we have
3463 // too many vectors to fit in registers, something that only occurs in
3464 // constructed examples:), but we have to walk the arglist to figure
3465 // that out...for the pathological case, compute VecArgOffset as the
3466 // start of the vector parameter area. Computing VecArgOffset is the
3467 // entire point of the following loop.
3468 unsigned VecArgOffset = ArgOffset;
3469 if (!isVarArg && !isPPC64) {
3470 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3472 EVT ObjectVT = Ins[ArgNo].VT;
3473 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3475 if (Flags.isByVal()) {
3476 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3477 unsigned ObjSize = Flags.getByValSize();
3479 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3480 VecArgOffset += ArgSize;
3484 switch(ObjectVT.getSimpleVT().SimpleTy) {
3485 default: llvm_unreachable("Unhandled argument type!");
3491 case MVT::i64: // PPC64
3493 // FIXME: We are guaranteed to be !isPPC64 at this point.
3494 // Does MVT::i64 apply?
3501 // Nothing to do, we're only looking at Nonvector args here.
3506 // We've found where the vector parameter area in memory is. Skip the
3507 // first 12 parameters; these don't use that memory.
3508 VecArgOffset = ((VecArgOffset+15)/16)*16;
3509 VecArgOffset += 12*16;
3511 // Add DAG nodes to load the arguments or copy them out of registers. On
3512 // entry to a function on PPC, the arguments start after the linkage area,
3513 // although the first ones are often in registers.
3515 SmallVector<SDValue, 8> MemOps;
3516 unsigned nAltivecParamsAtEnd = 0;
3517 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3518 unsigned CurArgIdx = 0;
3519 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3521 bool needsLoad = false;
3522 EVT ObjectVT = Ins[ArgNo].VT;
3523 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3524 unsigned ArgSize = ObjSize;
3525 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3526 if (Ins[ArgNo].isOrigArg()) {
3527 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3528 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3530 unsigned CurArgOffset = ArgOffset;
3532 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3533 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3534 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3535 if (isVarArg || isPPC64) {
3536 MinReservedArea = ((MinReservedArea+15)/16)*16;
3537 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3540 } else nAltivecParamsAtEnd++;
3542 // Calculate min reserved area.
3543 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3547 // FIXME the codegen can be much improved in some cases.
3548 // We do not have to keep everything in memory.
3549 if (Flags.isByVal()) {
3550 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3552 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3553 ObjSize = Flags.getByValSize();
3554 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3555 // Objects of size 1 and 2 are right justified, everything else is
3556 // left justified. This means the memory address is adjusted forwards.
3557 if (ObjSize==1 || ObjSize==2) {
3558 CurArgOffset = CurArgOffset + (4 - ObjSize);
3560 // The value of the object is its address.
3561 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3562 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3563 InVals.push_back(FIN);
3564 if (ObjSize==1 || ObjSize==2) {
3565 if (GPR_idx != Num_GPR_Regs) {
3568 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3570 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3571 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3572 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3573 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3574 MachinePointerInfo(FuncArg),
3575 ObjType, false, false, 0);
3576 MemOps.push_back(Store);
3580 ArgOffset += PtrByteSize;
3584 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3585 // Store whatever pieces of the object are in registers
3586 // to memory. ArgOffset will be the address of the beginning
3588 if (GPR_idx != Num_GPR_Regs) {
3591 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3593 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3594 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3595 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3596 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3597 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3598 MachinePointerInfo(FuncArg, j),
3600 MemOps.push_back(Store);
3602 ArgOffset += PtrByteSize;
3604 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3611 switch (ObjectVT.getSimpleVT().SimpleTy) {
3612 default: llvm_unreachable("Unhandled argument type!");
3616 if (GPR_idx != Num_GPR_Regs) {
3617 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3618 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3620 if (ObjectVT == MVT::i1)
3621 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3626 ArgSize = PtrByteSize;
3628 // All int arguments reserve stack space in the Darwin ABI.
3629 ArgOffset += PtrByteSize;
3633 case MVT::i64: // PPC64
3634 if (GPR_idx != Num_GPR_Regs) {
3635 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3636 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3638 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3639 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3640 // value to MVT::i64 and then truncate to the correct register size.
3641 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3646 ArgSize = PtrByteSize;
3648 // All int arguments reserve stack space in the Darwin ABI.
3654 // Every 4 bytes of argument space consumes one of the GPRs available for
3655 // argument passing.
3656 if (GPR_idx != Num_GPR_Regs) {
3658 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3661 if (FPR_idx != Num_FPR_Regs) {
3664 if (ObjectVT == MVT::f32)
3665 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3667 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3669 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3675 // All FP arguments reserve stack space in the Darwin ABI.
3676 ArgOffset += isPPC64 ? 8 : ObjSize;
3682 // Note that vector arguments in registers don't reserve stack space,
3683 // except in varargs functions.
3684 if (VR_idx != Num_VR_Regs) {
3685 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3686 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3688 while ((ArgOffset % 16) != 0) {
3689 ArgOffset += PtrByteSize;
3690 if (GPR_idx != Num_GPR_Regs)
3694 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3698 if (!isVarArg && !isPPC64) {
3699 // Vectors go after all the nonvectors.
3700 CurArgOffset = VecArgOffset;
3703 // Vectors are aligned.
3704 ArgOffset = ((ArgOffset+15)/16)*16;
3705 CurArgOffset = ArgOffset;
3713 // We need to load the argument to a virtual register if we determined above
3714 // that we ran out of physical registers of the appropriate type.
3716 int FI = MFI->CreateFixedObject(ObjSize,
3717 CurArgOffset + (ArgSize - ObjSize),
3719 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3720 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3721 false, false, false, 0);
3724 InVals.push_back(ArgVal);
3727 // Allow for Altivec parameters at the end, if needed.
3728 if (nAltivecParamsAtEnd) {
3729 MinReservedArea = ((MinReservedArea+15)/16)*16;
3730 MinReservedArea += 16*nAltivecParamsAtEnd;
3733 // Area that is at least reserved in the caller of this function.
3734 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3736 // Set the size that is at least reserved in caller of this function. Tail
3737 // call optimized functions' reserved stack space needs to be aligned so that
3738 // taking the difference between two stack areas will result in an aligned
3741 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3742 FuncInfo->setMinReservedArea(MinReservedArea);
3744 // If the function takes variable number of arguments, make a frame index for
3745 // the start of the first vararg value... for expansion of llvm.va_start.
3747 int Depth = ArgOffset;
3749 FuncInfo->setVarArgsFrameIndex(
3750 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3752 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3754 // If this function is vararg, store any remaining integer argument regs
3755 // to their spots on the stack so that they may be loaded by deferencing the
3756 // result of va_next.
3757 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3761 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3763 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3765 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3766 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3767 MachinePointerInfo(), false, false, 0);
3768 MemOps.push_back(Store);
3769 // Increment the address by four for the next argument to store
3770 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3771 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3775 if (!MemOps.empty())
3776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3781 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3782 /// adjusted to accommodate the arguments for the tailcall.
3783 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3784 unsigned ParamSize) {
3786 if (!isTailCall) return 0;
3788 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3789 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3790 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3791 // Remember only if the new adjustement is bigger.
3792 if (SPDiff < FI->getTailCallSPDelta())
3793 FI->setTailCallSPDelta(SPDiff);
3798 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3799 /// for tail call optimization. Targets which want to do tail call
3800 /// optimization should implement this function.
3802 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3803 CallingConv::ID CalleeCC,
3805 const SmallVectorImpl<ISD::InputArg> &Ins,
3806 SelectionDAG& DAG) const {
3807 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3810 // Variable argument functions are not supported.
3814 MachineFunction &MF = DAG.getMachineFunction();
3815 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3816 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3817 // Functions containing by val parameters are not supported.
3818 for (unsigned i = 0; i != Ins.size(); i++) {
3819 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3820 if (Flags.isByVal()) return false;
3823 // Non-PIC/GOT tail calls are supported.
3824 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3827 // At the moment we can only do local tail calls (in same module, hidden
3828 // or protected) if we are generating PIC.
3829 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3830 return G->getGlobal()->hasHiddenVisibility()
3831 || G->getGlobal()->hasProtectedVisibility();
3837 /// isCallCompatibleAddress - Return the immediate to use if the specified
3838 /// 32-bit value is representable in the immediate field of a BxA instruction.
3839 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3840 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3841 if (!C) return nullptr;
3843 int Addr = C->getZExtValue();
3844 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3845 SignExtend32<26>(Addr) != Addr)
3846 return nullptr; // Top 6 bits have to be sext of immediate.
3848 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3849 DAG.getTargetLoweringInfo().getPointerTy(
3850 DAG.getDataLayout())).getNode();
3855 struct TailCallArgumentInfo {
3860 TailCallArgumentInfo() : FrameIdx(0) {}
3865 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3867 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3869 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3870 SmallVectorImpl<SDValue> &MemOpChains,
3872 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3873 SDValue Arg = TailCallArgs[i].Arg;
3874 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3875 int FI = TailCallArgs[i].FrameIdx;
3876 // Store relative to framepointer.
3877 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3878 MachinePointerInfo::getFixedStack(FI),
3883 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3884 /// the appropriate stack slot for the tail call optimized function call.
3885 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3886 MachineFunction &MF,
3895 // Calculate the new stack slot for the return address.
3896 int SlotSize = isPPC64 ? 8 : 4;
3897 const PPCFrameLowering *FL =
3898 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3899 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3900 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3901 NewRetAddrLoc, true);
3902 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3903 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3904 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3905 MachinePointerInfo::getFixedStack(NewRetAddr),
3908 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3909 // slot as the FP is never overwritten.
3911 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3912 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3914 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3915 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3916 MachinePointerInfo::getFixedStack(NewFPIdx),
3923 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3924 /// the position of the argument.
3926 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3927 SDValue Arg, int SPDiff, unsigned ArgOffset,
3928 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3929 int Offset = ArgOffset + SPDiff;
3930 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3931 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3932 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3933 SDValue FIN = DAG.getFrameIndex(FI, VT);
3934 TailCallArgumentInfo Info;
3936 Info.FrameIdxOp = FIN;
3938 TailCallArguments.push_back(Info);
3941 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3942 /// stack slot. Returns the chain as result and the loaded frame pointers in
3943 /// LROpOut/FPOpout. Used when tail calling.
3944 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3952 // Load the LR and FP stack slot for later adjusting.
3953 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3954 LROpOut = getReturnAddrFrameIndex(DAG);
3955 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3956 false, false, false, 0);
3957 Chain = SDValue(LROpOut.getNode(), 1);
3959 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3960 // slot as the FP is never overwritten.
3962 FPOpOut = getFramePointerFrameIndex(DAG);
3963 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3964 false, false, false, 0);
3965 Chain = SDValue(FPOpOut.getNode(), 1);
3971 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3972 /// by "Src" to address "Dst" of size "Size". Alignment information is
3973 /// specified by the specific parameter attribute. The copy will be passed as
3974 /// a byval function parameter.
3975 /// Sometimes what we are copying is the end of a larger object, the part that
3976 /// does not fit in registers.
3978 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3979 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3981 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
3982 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3983 false, false, false, MachinePointerInfo(),
3984 MachinePointerInfo());
3987 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3990 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3991 SDValue Arg, SDValue PtrOff, int SPDiff,
3992 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3993 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3994 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3996 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4001 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4003 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4004 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4005 DAG.getConstant(ArgOffset, dl, PtrVT));
4007 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4008 MachinePointerInfo(), false, false, 0));
4009 // Calculate and remember argument location.
4010 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4015 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4016 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4017 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4018 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4019 MachineFunction &MF = DAG.getMachineFunction();
4021 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4022 // might overwrite each other in case of tail call optimization.
4023 SmallVector<SDValue, 8> MemOpChains2;
4024 // Do not flag preceding copytoreg stuff together with the following stuff.
4026 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4028 if (!MemOpChains2.empty())
4029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4031 // Store the return address to the appropriate stack slot.
4032 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4033 isPPC64, isDarwinABI, dl);
4035 // Emit callseq_end just before tailcall node.
4036 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4037 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4038 InFlag = Chain.getValue(1);
4041 // Is this global address that of a function that can be called by name? (as
4042 // opposed to something that must hold a descriptor for an indirect call).
4043 static bool isFunctionGlobalAddress(SDValue Callee) {
4044 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4045 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4046 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4049 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4056 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4057 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4058 bool isTailCall, bool IsPatchPoint,
4059 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4060 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4061 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4063 bool isPPC64 = Subtarget.isPPC64();
4064 bool isSVR4ABI = Subtarget.isSVR4ABI();
4065 bool isELFv2ABI = Subtarget.isELFv2ABI();
4067 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4068 NodeTys.push_back(MVT::Other); // Returns a chain
4069 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4071 unsigned CallOpc = PPCISD::CALL;
4073 bool needIndirectCall = true;
4074 if (!isSVR4ABI || !isPPC64)
4075 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4076 // If this is an absolute destination address, use the munged value.
4077 Callee = SDValue(Dest, 0);
4078 needIndirectCall = false;
4081 if (isFunctionGlobalAddress(Callee)) {
4082 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4083 // A call to a TLS address is actually an indirect call to a
4084 // thread-specific pointer.
4085 unsigned OpFlags = 0;
4086 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4087 (Subtarget.getTargetTriple().isMacOSX() &&
4088 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4089 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4090 (Subtarget.isTargetELF() && !isPPC64 &&
4091 !G->getGlobal()->hasLocalLinkage() &&
4092 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4093 // PC-relative references to external symbols should go through $stub,
4094 // unless we're building with the leopard linker or later, which
4095 // automatically synthesizes these stubs.
4096 OpFlags = PPCII::MO_PLT_OR_STUB;
4099 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4100 // every direct call is) turn it into a TargetGlobalAddress /
4101 // TargetExternalSymbol node so that legalize doesn't hack it.
4102 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4103 Callee.getValueType(), 0, OpFlags);
4104 needIndirectCall = false;
4107 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4108 unsigned char OpFlags = 0;
4110 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4111 (Subtarget.getTargetTriple().isMacOSX() &&
4112 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4113 (Subtarget.isTargetELF() && !isPPC64 &&
4114 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4115 // PC-relative references to external symbols should go through $stub,
4116 // unless we're building with the leopard linker or later, which
4117 // automatically synthesizes these stubs.
4118 OpFlags = PPCII::MO_PLT_OR_STUB;
4121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4123 needIndirectCall = false;
4127 // We'll form an invalid direct call when lowering a patchpoint; the full
4128 // sequence for an indirect call is complicated, and many of the
4129 // instructions introduced might have side effects (and, thus, can't be
4130 // removed later). The call itself will be removed as soon as the
4131 // argument/return lowering is complete, so the fact that it has the wrong
4132 // kind of operands should not really matter.
4133 needIndirectCall = false;
4136 if (needIndirectCall) {
4137 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4138 // to do the call, we can't use PPCISD::CALL.
4139 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4141 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4142 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4143 // entry point, but to the function descriptor (the function entry point
4144 // address is part of the function descriptor though).
4145 // The function descriptor is a three doubleword structure with the
4146 // following fields: function entry point, TOC base address and
4147 // environment pointer.
4148 // Thus for a call through a function pointer, the following actions need
4150 // 1. Save the TOC of the caller in the TOC save area of its stack
4151 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4152 // 2. Load the address of the function entry point from the function
4154 // 3. Load the TOC of the callee from the function descriptor into r2.
4155 // 4. Load the environment pointer from the function descriptor into
4157 // 5. Branch to the function entry point address.
4158 // 6. On return of the callee, the TOC of the caller needs to be
4159 // restored (this is done in FinishCall()).
4161 // The loads are scheduled at the beginning of the call sequence, and the
4162 // register copies are flagged together to ensure that no other
4163 // operations can be scheduled in between. E.g. without flagging the
4164 // copies together, a TOC access in the caller could be scheduled between
4165 // the assignment of the callee TOC and the branch to the callee, which
4166 // results in the TOC access going through the TOC of the callee instead
4167 // of going through the TOC of the caller, which leads to incorrect code.
4169 // Load the address of the function entry point from the function
4171 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4172 if (LDChain.getValueType() == MVT::Glue)
4173 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4175 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4177 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4178 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4179 false, false, LoadsInv, 8);
4181 // Load environment pointer into r11.
4182 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4183 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4184 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4185 MPI.getWithOffset(16), false, false,
4188 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4189 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4190 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4191 MPI.getWithOffset(8), false, false,
4194 setUsesTOCBasePtr(DAG);
4195 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4197 Chain = TOCVal.getValue(0);
4198 InFlag = TOCVal.getValue(1);
4200 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4203 Chain = EnvVal.getValue(0);
4204 InFlag = EnvVal.getValue(1);
4206 MTCTROps[0] = Chain;
4207 MTCTROps[1] = LoadFuncPtr;
4208 MTCTROps[2] = InFlag;
4211 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4212 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4213 InFlag = Chain.getValue(1);
4216 NodeTys.push_back(MVT::Other);
4217 NodeTys.push_back(MVT::Glue);
4218 Ops.push_back(Chain);
4219 CallOpc = PPCISD::BCTRL;
4220 Callee.setNode(nullptr);
4221 // Add use of X11 (holding environment pointer)
4222 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
4223 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4224 // Add CTR register as callee so a bctr can be emitted later.
4226 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4229 // If this is a direct call, pass the chain and the callee.
4230 if (Callee.getNode()) {
4231 Ops.push_back(Chain);
4232 Ops.push_back(Callee);
4234 // If this is a tail call add stack pointer delta.
4236 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4238 // Add argument registers to the end of the list so that they are known live
4240 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4241 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4242 RegsToPass[i].second.getValueType()));
4244 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4246 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4247 setUsesTOCBasePtr(DAG);
4248 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4255 bool isLocalCall(const SDValue &Callee)
4257 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4258 return G->getGlobal()->isStrongDefinitionForLinker();
4263 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4264 CallingConv::ID CallConv, bool isVarArg,
4265 const SmallVectorImpl<ISD::InputArg> &Ins,
4266 SDLoc dl, SelectionDAG &DAG,
4267 SmallVectorImpl<SDValue> &InVals) const {
4269 SmallVector<CCValAssign, 16> RVLocs;
4270 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4272 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4274 // Copy all of the result registers out of their specified physreg.
4275 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4276 CCValAssign &VA = RVLocs[i];
4277 assert(VA.isRegLoc() && "Can only return in registers!");
4279 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4280 VA.getLocReg(), VA.getLocVT(), InFlag);
4281 Chain = Val.getValue(1);
4282 InFlag = Val.getValue(2);
4284 switch (VA.getLocInfo()) {
4285 default: llvm_unreachable("Unknown loc info!");
4286 case CCValAssign::Full: break;
4287 case CCValAssign::AExt:
4288 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4290 case CCValAssign::ZExt:
4291 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4292 DAG.getValueType(VA.getValVT()));
4293 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4295 case CCValAssign::SExt:
4296 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4297 DAG.getValueType(VA.getValVT()));
4298 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4302 InVals.push_back(Val);
4309 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4310 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4312 SmallVector<std::pair<unsigned, SDValue>, 8>
4314 SDValue InFlag, SDValue Chain,
4315 SDValue CallSeqStart, SDValue &Callee,
4316 int SPDiff, unsigned NumBytes,
4317 const SmallVectorImpl<ISD::InputArg> &Ins,
4318 SmallVectorImpl<SDValue> &InVals,
4319 ImmutableCallSite *CS) const {
4321 std::vector<EVT> NodeTys;
4322 SmallVector<SDValue, 8> Ops;
4323 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4324 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
4325 Ops, NodeTys, CS, Subtarget);
4327 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4328 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4329 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4331 // When performing tail call optimization the callee pops its arguments off
4332 // the stack. Account for this here so these bytes can be pushed back on in
4333 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4334 int BytesCalleePops =
4335 (CallConv == CallingConv::Fast &&
4336 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4338 // Add a register mask operand representing the call-preserved registers.
4339 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4340 const uint32_t *Mask =
4341 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4342 assert(Mask && "Missing call preserved mask for calling convention");
4343 Ops.push_back(DAG.getRegisterMask(Mask));
4345 if (InFlag.getNode())
4346 Ops.push_back(InFlag);
4350 assert(((Callee.getOpcode() == ISD::Register &&
4351 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4352 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4353 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4354 isa<ConstantSDNode>(Callee)) &&
4355 "Expecting an global address, external symbol, absolute value or register");
4357 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4358 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4361 // Add a NOP immediately after the branch instruction when using the 64-bit
4362 // SVR4 ABI. At link time, if caller and callee are in a different module and
4363 // thus have a different TOC, the call will be replaced with a call to a stub
4364 // function which saves the current TOC, loads the TOC of the callee and
4365 // branches to the callee. The NOP will be replaced with a load instruction
4366 // which restores the TOC of the caller from the TOC save slot of the current
4367 // stack frame. If caller and callee belong to the same module (and have the
4368 // same TOC), the NOP will remain unchanged.
4370 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4372 if (CallOpc == PPCISD::BCTRL) {
4373 // This is a call through a function pointer.
4374 // Restore the caller TOC from the save area into R2.
4375 // See PrepareCall() for more information about calls through function
4376 // pointers in the 64-bit SVR4 ABI.
4377 // We are using a target-specific load with r2 hard coded, because the
4378 // result of a target-independent load would never go directly into r2,
4379 // since r2 is a reserved register (which prevents the register allocator
4380 // from allocating it), resulting in an additional register being
4381 // allocated and an unnecessary move instruction being generated.
4382 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4384 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4385 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4386 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4387 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4388 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4390 // The address needs to go after the chain input but before the flag (or
4391 // any other variadic arguments).
4392 Ops.insert(std::next(Ops.begin()), AddTOC);
4393 } else if ((CallOpc == PPCISD::CALL) &&
4394 (!isLocalCall(Callee) ||
4395 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4396 // Otherwise insert NOP for non-local calls.
4397 CallOpc = PPCISD::CALL_NOP;
4400 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4401 InFlag = Chain.getValue(1);
4403 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4404 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4407 InFlag = Chain.getValue(1);
4409 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4410 Ins, dl, DAG, InVals);
4414 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4415 SmallVectorImpl<SDValue> &InVals) const {
4416 SelectionDAG &DAG = CLI.DAG;
4418 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4419 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4420 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4421 SDValue Chain = CLI.Chain;
4422 SDValue Callee = CLI.Callee;
4423 bool &isTailCall = CLI.IsTailCall;
4424 CallingConv::ID CallConv = CLI.CallConv;
4425 bool isVarArg = CLI.IsVarArg;
4426 bool IsPatchPoint = CLI.IsPatchPoint;
4427 ImmutableCallSite *CS = CLI.CS;
4430 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4433 if (!isTailCall && CS && CS->isMustTailCall())
4434 report_fatal_error("failed to perform tail call elimination on a call "
4435 "site marked musttail");
4437 if (Subtarget.isSVR4ABI()) {
4438 if (Subtarget.isPPC64())
4439 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4440 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4441 dl, DAG, InVals, CS);
4443 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4444 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4445 dl, DAG, InVals, CS);
4448 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4449 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4450 dl, DAG, InVals, CS);
4454 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4455 CallingConv::ID CallConv, bool isVarArg,
4456 bool isTailCall, bool IsPatchPoint,
4457 const SmallVectorImpl<ISD::OutputArg> &Outs,
4458 const SmallVectorImpl<SDValue> &OutVals,
4459 const SmallVectorImpl<ISD::InputArg> &Ins,
4460 SDLoc dl, SelectionDAG &DAG,
4461 SmallVectorImpl<SDValue> &InVals,
4462 ImmutableCallSite *CS) const {
4463 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4464 // of the 32-bit SVR4 ABI stack frame layout.
4466 assert((CallConv == CallingConv::C ||
4467 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4469 unsigned PtrByteSize = 4;
4471 MachineFunction &MF = DAG.getMachineFunction();
4473 // Mark this function as potentially containing a function that contains a
4474 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4475 // and restoring the callers stack pointer in this functions epilog. This is
4476 // done because by tail calling the called function might overwrite the value
4477 // in this function's (MF) stack pointer stack slot 0(SP).
4478 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4479 CallConv == CallingConv::Fast)
4480 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4482 // Count how many bytes are to be pushed on the stack, including the linkage
4483 // area, parameter list area and the part of the local variable space which
4484 // contains copies of aggregates which are passed by value.
4486 // Assign locations to all of the outgoing arguments.
4487 SmallVector<CCValAssign, 16> ArgLocs;
4488 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4491 // Reserve space for the linkage area on the stack.
4492 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4496 // Handle fixed and variable vector arguments differently.
4497 // Fixed vector arguments go into registers as long as registers are
4498 // available. Variable vector arguments always go into memory.
4499 unsigned NumArgs = Outs.size();
4501 for (unsigned i = 0; i != NumArgs; ++i) {
4502 MVT ArgVT = Outs[i].VT;
4503 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4506 if (Outs[i].IsFixed) {
4507 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4510 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4516 errs() << "Call operand #" << i << " has unhandled type "
4517 << EVT(ArgVT).getEVTString() << "\n";
4519 llvm_unreachable(nullptr);
4523 // All arguments are treated the same.
4524 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4527 // Assign locations to all of the outgoing aggregate by value arguments.
4528 SmallVector<CCValAssign, 16> ByValArgLocs;
4529 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4530 ByValArgLocs, *DAG.getContext());
4532 // Reserve stack space for the allocations in CCInfo.
4533 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4535 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4537 // Size of the linkage area, parameter list area and the part of the local
4538 // space variable where copies of aggregates which are passed by value are
4540 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4542 // Calculate by how many bytes the stack has to be adjusted in case of tail
4543 // call optimization.
4544 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4546 // Adjust the stack pointer for the new arguments...
4547 // These operations are automatically eliminated by the prolog/epilog pass
4548 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4550 SDValue CallSeqStart = Chain;
4552 // Load the return address and frame pointer so it can be moved somewhere else
4555 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4558 // Set up a copy of the stack pointer for use loading and storing any
4559 // arguments that may not fit in the registers available for argument
4561 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4563 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4564 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4565 SmallVector<SDValue, 8> MemOpChains;
4567 bool seenFloatArg = false;
4568 // Walk the register/memloc assignments, inserting copies/loads.
4569 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4572 CCValAssign &VA = ArgLocs[i];
4573 SDValue Arg = OutVals[i];
4574 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4576 if (Flags.isByVal()) {
4577 // Argument is an aggregate which is passed by value, thus we need to
4578 // create a copy of it in the local variable space of the current stack
4579 // frame (which is the stack frame of the caller) and pass the address of
4580 // this copy to the callee.
4581 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4582 CCValAssign &ByValVA = ByValArgLocs[j++];
4583 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4585 // Memory reserved in the local variable space of the callers stack frame.
4586 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4588 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4589 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4592 // Create a copy of the argument in the local area of the current
4594 SDValue MemcpyCall =
4595 CreateCopyOfByValArgument(Arg, PtrOff,
4596 CallSeqStart.getNode()->getOperand(0),
4599 // This must go outside the CALLSEQ_START..END.
4600 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4601 CallSeqStart.getNode()->getOperand(1),
4603 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4604 NewCallSeqStart.getNode());
4605 Chain = CallSeqStart = NewCallSeqStart;
4607 // Pass the address of the aggregate copy on the stack either in a
4608 // physical register or in the parameter list area of the current stack
4609 // frame to the callee.
4613 if (VA.isRegLoc()) {
4614 if (Arg.getValueType() == MVT::i1)
4615 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4617 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4618 // Put argument in a physical register.
4619 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4621 // Put argument in the parameter list area of the current stack frame.
4622 assert(VA.isMemLoc());
4623 unsigned LocMemOffset = VA.getLocMemOffset();
4626 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4627 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4630 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4631 MachinePointerInfo(),
4634 // Calculate and remember argument location.
4635 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4641 if (!MemOpChains.empty())
4642 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4644 // Build a sequence of copy-to-reg nodes chained together with token chain
4645 // and flag operands which copy the outgoing args into the appropriate regs.
4647 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4648 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4649 RegsToPass[i].second, InFlag);
4650 InFlag = Chain.getValue(1);
4653 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4656 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4657 SDValue Ops[] = { Chain, InFlag };
4659 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4660 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4662 InFlag = Chain.getValue(1);
4666 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4667 false, TailCallArguments);
4669 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4670 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4671 NumBytes, Ins, InVals, CS);
4674 // Copy an argument into memory, being careful to do this outside the
4675 // call sequence for the call to which the argument belongs.
4677 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4678 SDValue CallSeqStart,
4679 ISD::ArgFlagsTy Flags,
4682 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4683 CallSeqStart.getNode()->getOperand(0),
4685 // The MEMCPY must go outside the CALLSEQ_START..END.
4686 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4687 CallSeqStart.getNode()->getOperand(1),
4689 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4690 NewCallSeqStart.getNode());
4691 return NewCallSeqStart;
4695 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4696 CallingConv::ID CallConv, bool isVarArg,
4697 bool isTailCall, bool IsPatchPoint,
4698 const SmallVectorImpl<ISD::OutputArg> &Outs,
4699 const SmallVectorImpl<SDValue> &OutVals,
4700 const SmallVectorImpl<ISD::InputArg> &Ins,
4701 SDLoc dl, SelectionDAG &DAG,
4702 SmallVectorImpl<SDValue> &InVals,
4703 ImmutableCallSite *CS) const {
4705 bool isELFv2ABI = Subtarget.isELFv2ABI();
4706 bool isLittleEndian = Subtarget.isLittleEndian();
4707 unsigned NumOps = Outs.size();
4709 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4710 unsigned PtrByteSize = 8;
4712 MachineFunction &MF = DAG.getMachineFunction();
4714 // Mark this function as potentially containing a function that contains a
4715 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4716 // and restoring the callers stack pointer in this functions epilog. This is
4717 // done because by tail calling the called function might overwrite the value
4718 // in this function's (MF) stack pointer stack slot 0(SP).
4719 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4720 CallConv == CallingConv::Fast)
4721 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4723 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4724 "fastcc not supported on varargs functions");
4726 // Count how many bytes are to be pushed on the stack, including the linkage
4727 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4728 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4729 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4730 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4731 unsigned NumBytes = LinkageSize;
4732 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4733 unsigned &QFPR_idx = FPR_idx;
4735 static const MCPhysReg GPR[] = {
4736 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4737 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4739 static const MCPhysReg VR[] = {
4740 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4741 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4743 static const MCPhysReg VSRH[] = {
4744 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4745 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4748 const unsigned NumGPRs = array_lengthof(GPR);
4749 const unsigned NumFPRs = 13;
4750 const unsigned NumVRs = array_lengthof(VR);
4751 const unsigned NumQFPRs = NumFPRs;
4753 // When using the fast calling convention, we don't provide backing for
4754 // arguments that will be in registers.
4755 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4757 // Add up all the space actually used.
4758 for (unsigned i = 0; i != NumOps; ++i) {
4759 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4760 EVT ArgVT = Outs[i].VT;
4761 EVT OrigVT = Outs[i].ArgVT;
4763 if (CallConv == CallingConv::Fast) {
4764 if (Flags.isByVal())
4765 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4767 switch (ArgVT.getSimpleVT().SimpleTy) {
4768 default: llvm_unreachable("Unexpected ValueType for argument!");
4772 if (++NumGPRsUsed <= NumGPRs)
4781 if (++NumVRsUsed <= NumVRs)
4785 // When using QPX, this is handled like a FP register, otherwise, it
4786 // is an Altivec register.
4787 if (Subtarget.hasQPX()) {
4788 if (++NumFPRsUsed <= NumFPRs)
4791 if (++NumVRsUsed <= NumVRs)
4797 case MVT::v4f64: // QPX
4798 case MVT::v4i1: // QPX
4799 if (++NumFPRsUsed <= NumFPRs)
4805 /* Respect alignment of argument on the stack. */
4807 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4808 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4810 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4811 if (Flags.isInConsecutiveRegsLast())
4812 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4815 unsigned NumBytesActuallyUsed = NumBytes;
4817 // The prolog code of the callee may store up to 8 GPR argument registers to
4818 // the stack, allowing va_start to index over them in memory if its varargs.
4819 // Because we cannot tell if this is needed on the caller side, we have to
4820 // conservatively assume that it is needed. As such, make sure we have at
4821 // least enough stack space for the caller to store the 8 GPRs.
4822 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4823 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4825 // Tail call needs the stack to be aligned.
4826 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4827 CallConv == CallingConv::Fast)
4828 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4830 // Calculate by how many bytes the stack has to be adjusted in case of tail
4831 // call optimization.
4832 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4834 // To protect arguments on the stack from being clobbered in a tail call,
4835 // force all the loads to happen before doing any other lowering.
4837 Chain = DAG.getStackArgumentTokenFactor(Chain);
4839 // Adjust the stack pointer for the new arguments...
4840 // These operations are automatically eliminated by the prolog/epilog pass
4841 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4843 SDValue CallSeqStart = Chain;
4845 // Load the return address and frame pointer so it can be move somewhere else
4848 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4851 // Set up a copy of the stack pointer for use loading and storing any
4852 // arguments that may not fit in the registers available for argument
4854 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4856 // Figure out which arguments are going to go in registers, and which in
4857 // memory. Also, if this is a vararg function, floating point operations
4858 // must be stored to our stack, and loaded into integer regs as well, if
4859 // any integer regs are available for argument passing.
4860 unsigned ArgOffset = LinkageSize;
4862 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4863 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4865 SmallVector<SDValue, 8> MemOpChains;
4866 for (unsigned i = 0; i != NumOps; ++i) {
4867 SDValue Arg = OutVals[i];
4868 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4869 EVT ArgVT = Outs[i].VT;
4870 EVT OrigVT = Outs[i].ArgVT;
4872 // PtrOff will be used to store the current argument to the stack if a
4873 // register cannot be found for it.
4876 // We re-align the argument offset for each argument, except when using the
4877 // fast calling convention, when we need to make sure we do that only when
4878 // we'll actually use a stack slot.
4879 auto ComputePtrOff = [&]() {
4880 /* Respect alignment of argument on the stack. */
4882 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4883 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4885 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4887 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4890 if (CallConv != CallingConv::Fast) {
4893 /* Compute GPR index associated with argument offset. */
4894 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4895 GPR_idx = std::min(GPR_idx, NumGPRs);
4898 // Promote integers to 64-bit values.
4899 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4900 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4901 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4902 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4905 // FIXME memcpy is used way more than necessary. Correctness first.
4906 // Note: "by value" is code for passing a structure by value, not
4908 if (Flags.isByVal()) {
4909 // Note: Size includes alignment padding, so
4910 // struct x { short a; char b; }
4911 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4912 // These are the proper values we need for right-justifying the
4913 // aggregate in a parameter register.
4914 unsigned Size = Flags.getByValSize();
4916 // An empty aggregate parameter takes up no storage and no
4921 if (CallConv == CallingConv::Fast)
4924 // All aggregates smaller than 8 bytes must be passed right-justified.
4925 if (Size==1 || Size==2 || Size==4) {
4926 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4927 if (GPR_idx != NumGPRs) {
4928 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4929 MachinePointerInfo(), VT,
4930 false, false, false, 0);
4931 MemOpChains.push_back(Load.getValue(1));
4932 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4934 ArgOffset += PtrByteSize;
4939 if (GPR_idx == NumGPRs && Size < 8) {
4940 SDValue AddPtr = PtrOff;
4941 if (!isLittleEndian) {
4942 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4943 PtrOff.getValueType());
4944 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4946 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4949 ArgOffset += PtrByteSize;
4952 // Copy entire object into memory. There are cases where gcc-generated
4953 // code assumes it is there, even if it could be put entirely into
4954 // registers. (This is not what the doc says.)
4956 // FIXME: The above statement is likely due to a misunderstanding of the
4957 // documents. All arguments must be copied into the parameter area BY
4958 // THE CALLEE in the event that the callee takes the address of any
4959 // formal argument. That has not yet been implemented. However, it is
4960 // reasonable to use the stack area as a staging area for the register
4963 // Skip this for small aggregates, as we will use the same slot for a
4964 // right-justified copy, below.
4966 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4970 // When a register is available, pass a small aggregate right-justified.
4971 if (Size < 8 && GPR_idx != NumGPRs) {
4972 // The easiest way to get this right-justified in a register
4973 // is to copy the structure into the rightmost portion of a
4974 // local variable slot, then load the whole slot into the
4976 // FIXME: The memcpy seems to produce pretty awful code for
4977 // small aggregates, particularly for packed ones.
4978 // FIXME: It would be preferable to use the slot in the
4979 // parameter save area instead of a new local variable.
4980 SDValue AddPtr = PtrOff;
4981 if (!isLittleEndian) {
4982 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
4983 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4985 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4989 // Load the slot into the register.
4990 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4991 MachinePointerInfo(),
4992 false, false, false, 0);
4993 MemOpChains.push_back(Load.getValue(1));
4994 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4996 // Done with this argument.
4997 ArgOffset += PtrByteSize;
5001 // For aggregates larger than PtrByteSize, copy the pieces of the
5002 // object that fit into registers from the parameter save area.
5003 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5004 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5005 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5006 if (GPR_idx != NumGPRs) {
5007 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5008 MachinePointerInfo(),
5009 false, false, false, 0);
5010 MemOpChains.push_back(Load.getValue(1));
5011 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5012 ArgOffset += PtrByteSize;
5014 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5021 switch (Arg.getSimpleValueType().SimpleTy) {
5022 default: llvm_unreachable("Unexpected ValueType for argument!");
5026 // These can be scalar arguments or elements of an integer array type
5027 // passed directly. Clang may use those instead of "byval" aggregate
5028 // types to avoid forcing arguments to memory unnecessarily.
5029 if (GPR_idx != NumGPRs) {
5030 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5032 if (CallConv == CallingConv::Fast)
5035 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5036 true, isTailCall, false, MemOpChains,
5037 TailCallArguments, dl);
5038 if (CallConv == CallingConv::Fast)
5039 ArgOffset += PtrByteSize;
5041 if (CallConv != CallingConv::Fast)
5042 ArgOffset += PtrByteSize;
5046 // These can be scalar arguments or elements of a float array type
5047 // passed directly. The latter are used to implement ELFv2 homogenous
5048 // float aggregates.
5050 // Named arguments go into FPRs first, and once they overflow, the
5051 // remaining arguments go into GPRs and then the parameter save area.
5052 // Unnamed arguments for vararg functions always go to GPRs and
5053 // then the parameter save area. For now, put all arguments to vararg
5054 // routines always in both locations (FPR *and* GPR or stack slot).
5055 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5056 bool NeededLoad = false;
5058 // First load the argument into the next available FPR.
5059 if (FPR_idx != NumFPRs)
5060 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5062 // Next, load the argument into GPR or stack slot if needed.
5063 if (!NeedGPROrStack)
5065 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5066 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5067 // once we support fp <-> gpr moves.
5069 // In the non-vararg case, this can only ever happen in the
5070 // presence of f32 array types, since otherwise we never run
5071 // out of FPRs before running out of GPRs.
5074 // Double values are always passed in a single GPR.
5075 if (Arg.getValueType() != MVT::f32) {
5076 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5078 // Non-array float values are extended and passed in a GPR.
5079 } else if (!Flags.isInConsecutiveRegs()) {
5080 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5081 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5083 // If we have an array of floats, we collect every odd element
5084 // together with its predecessor into one GPR.
5085 } else if (ArgOffset % PtrByteSize != 0) {
5087 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5088 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5089 if (!isLittleEndian)
5091 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5093 // The final element, if even, goes into the first half of a GPR.
5094 } else if (Flags.isInConsecutiveRegsLast()) {
5095 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5096 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5097 if (!isLittleEndian)
5098 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5099 DAG.getConstant(32, dl, MVT::i32));
5101 // Non-final even elements are skipped; they will be handled
5102 // together the with subsequent argument on the next go-around.
5106 if (ArgVal.getNode())
5107 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5109 if (CallConv == CallingConv::Fast)
5112 // Single-precision floating-point values are mapped to the
5113 // second (rightmost) word of the stack doubleword.
5114 if (Arg.getValueType() == MVT::f32 &&
5115 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5116 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5117 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5120 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5121 true, isTailCall, false, MemOpChains,
5122 TailCallArguments, dl);
5126 // When passing an array of floats, the array occupies consecutive
5127 // space in the argument area; only round up to the next doubleword
5128 // at the end of the array. Otherwise, each float takes 8 bytes.
5129 if (CallConv != CallingConv::Fast || NeededLoad) {
5130 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5131 Flags.isInConsecutiveRegs()) ? 4 : 8;
5132 if (Flags.isInConsecutiveRegsLast())
5133 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5144 if (!Subtarget.hasQPX()) {
5145 // These can be scalar arguments or elements of a vector array type
5146 // passed directly. The latter are used to implement ELFv2 homogenous
5147 // vector aggregates.
5149 // For a varargs call, named arguments go into VRs or on the stack as
5150 // usual; unnamed arguments always go to the stack or the corresponding
5151 // GPRs when within range. For now, we always put the value in both
5152 // locations (or even all three).
5154 // We could elide this store in the case where the object fits
5155 // entirely in R registers. Maybe later.
5156 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5157 MachinePointerInfo(), false, false, 0);
5158 MemOpChains.push_back(Store);
5159 if (VR_idx != NumVRs) {
5160 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5161 MachinePointerInfo(),
5162 false, false, false, 0);
5163 MemOpChains.push_back(Load.getValue(1));
5165 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5166 Arg.getSimpleValueType() == MVT::v2i64) ?
5167 VSRH[VR_idx] : VR[VR_idx];
5170 RegsToPass.push_back(std::make_pair(VReg, Load));
5173 for (unsigned i=0; i<16; i+=PtrByteSize) {
5174 if (GPR_idx == NumGPRs)
5176 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5177 DAG.getConstant(i, dl, PtrVT));
5178 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5179 false, false, false, 0);
5180 MemOpChains.push_back(Load.getValue(1));
5181 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5186 // Non-varargs Altivec params go into VRs or on the stack.
5187 if (VR_idx != NumVRs) {
5188 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5189 Arg.getSimpleValueType() == MVT::v2i64) ?
5190 VSRH[VR_idx] : VR[VR_idx];
5193 RegsToPass.push_back(std::make_pair(VReg, Arg));
5195 if (CallConv == CallingConv::Fast)
5198 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5199 true, isTailCall, true, MemOpChains,
5200 TailCallArguments, dl);
5201 if (CallConv == CallingConv::Fast)
5205 if (CallConv != CallingConv::Fast)
5210 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5211 "Invalid QPX parameter type");
5216 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5218 // We could elide this store in the case where the object fits
5219 // entirely in R registers. Maybe later.
5220 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5221 MachinePointerInfo(), false, false, 0);
5222 MemOpChains.push_back(Store);
5223 if (QFPR_idx != NumQFPRs) {
5224 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5225 Store, PtrOff, MachinePointerInfo(),
5226 false, false, false, 0);
5227 MemOpChains.push_back(Load.getValue(1));
5228 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5230 ArgOffset += (IsF32 ? 16 : 32);
5231 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5232 if (GPR_idx == NumGPRs)
5234 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5235 DAG.getConstant(i, dl, PtrVT));
5236 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5237 false, false, false, 0);
5238 MemOpChains.push_back(Load.getValue(1));
5239 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5244 // Non-varargs QPX params go into registers or on the stack.
5245 if (QFPR_idx != NumQFPRs) {
5246 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5248 if (CallConv == CallingConv::Fast)
5251 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5252 true, isTailCall, true, MemOpChains,
5253 TailCallArguments, dl);
5254 if (CallConv == CallingConv::Fast)
5255 ArgOffset += (IsF32 ? 16 : 32);
5258 if (CallConv != CallingConv::Fast)
5259 ArgOffset += (IsF32 ? 16 : 32);
5265 assert(NumBytesActuallyUsed == ArgOffset);
5266 (void)NumBytesActuallyUsed;
5268 if (!MemOpChains.empty())
5269 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5271 // Check if this is an indirect call (MTCTR/BCTRL).
5272 // See PrepareCall() for more information about calls through function
5273 // pointers in the 64-bit SVR4 ABI.
5274 if (!isTailCall && !IsPatchPoint &&
5275 !isFunctionGlobalAddress(Callee) &&
5276 !isa<ExternalSymbolSDNode>(Callee)) {
5277 // Load r2 into a virtual register and store it to the TOC save area.
5278 setUsesTOCBasePtr(DAG);
5279 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5280 // TOC save area offset.
5281 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5282 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5283 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5284 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5285 MachinePointerInfo::getStack(TOCSaveOffset),
5287 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5288 // This does not mean the MTCTR instruction must use R12; it's easier
5289 // to model this as an extra parameter, so do that.
5290 if (isELFv2ABI && !IsPatchPoint)
5291 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5294 // Build a sequence of copy-to-reg nodes chained together with token chain
5295 // and flag operands which copy the outgoing args into the appropriate regs.
5297 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5298 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5299 RegsToPass[i].second, InFlag);
5300 InFlag = Chain.getValue(1);
5304 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5305 FPOp, true, TailCallArguments);
5307 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5308 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5309 NumBytes, Ins, InVals, CS);
5313 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5314 CallingConv::ID CallConv, bool isVarArg,
5315 bool isTailCall, bool IsPatchPoint,
5316 const SmallVectorImpl<ISD::OutputArg> &Outs,
5317 const SmallVectorImpl<SDValue> &OutVals,
5318 const SmallVectorImpl<ISD::InputArg> &Ins,
5319 SDLoc dl, SelectionDAG &DAG,
5320 SmallVectorImpl<SDValue> &InVals,
5321 ImmutableCallSite *CS) const {
5323 unsigned NumOps = Outs.size();
5325 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5326 bool isPPC64 = PtrVT == MVT::i64;
5327 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5329 MachineFunction &MF = DAG.getMachineFunction();
5331 // Mark this function as potentially containing a function that contains a
5332 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5333 // and restoring the callers stack pointer in this functions epilog. This is
5334 // done because by tail calling the called function might overwrite the value
5335 // in this function's (MF) stack pointer stack slot 0(SP).
5336 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5337 CallConv == CallingConv::Fast)
5338 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5340 // Count how many bytes are to be pushed on the stack, including the linkage
5341 // area, and parameter passing area. We start with 24/48 bytes, which is
5342 // prereserved space for [SP][CR][LR][3 x unused].
5343 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5344 unsigned NumBytes = LinkageSize;
5346 // Add up all the space actually used.
5347 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5348 // they all go in registers, but we must reserve stack space for them for
5349 // possible use by the caller. In varargs or 64-bit calls, parameters are
5350 // assigned stack space in order, with padding so Altivec parameters are
5352 unsigned nAltivecParamsAtEnd = 0;
5353 for (unsigned i = 0; i != NumOps; ++i) {
5354 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5355 EVT ArgVT = Outs[i].VT;
5356 // Varargs Altivec parameters are padded to a 16 byte boundary.
5357 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5358 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5359 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5360 if (!isVarArg && !isPPC64) {
5361 // Non-varargs Altivec parameters go after all the non-Altivec
5362 // parameters; handle those later so we know how much padding we need.
5363 nAltivecParamsAtEnd++;
5366 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5367 NumBytes = ((NumBytes+15)/16)*16;
5369 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5372 // Allow for Altivec parameters at the end, if needed.
5373 if (nAltivecParamsAtEnd) {
5374 NumBytes = ((NumBytes+15)/16)*16;
5375 NumBytes += 16*nAltivecParamsAtEnd;
5378 // The prolog code of the callee may store up to 8 GPR argument registers to
5379 // the stack, allowing va_start to index over them in memory if its varargs.
5380 // Because we cannot tell if this is needed on the caller side, we have to
5381 // conservatively assume that it is needed. As such, make sure we have at
5382 // least enough stack space for the caller to store the 8 GPRs.
5383 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5385 // Tail call needs the stack to be aligned.
5386 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5387 CallConv == CallingConv::Fast)
5388 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5390 // Calculate by how many bytes the stack has to be adjusted in case of tail
5391 // call optimization.
5392 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5394 // To protect arguments on the stack from being clobbered in a tail call,
5395 // force all the loads to happen before doing any other lowering.
5397 Chain = DAG.getStackArgumentTokenFactor(Chain);
5399 // Adjust the stack pointer for the new arguments...
5400 // These operations are automatically eliminated by the prolog/epilog pass
5401 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5403 SDValue CallSeqStart = Chain;
5405 // Load the return address and frame pointer so it can be move somewhere else
5408 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5411 // Set up a copy of the stack pointer for use loading and storing any
5412 // arguments that may not fit in the registers available for argument
5416 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5418 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5420 // Figure out which arguments are going to go in registers, and which in
5421 // memory. Also, if this is a vararg function, floating point operations
5422 // must be stored to our stack, and loaded into integer regs as well, if
5423 // any integer regs are available for argument passing.
5424 unsigned ArgOffset = LinkageSize;
5425 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5427 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5428 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5429 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5431 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5432 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5433 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5435 static const MCPhysReg VR[] = {
5436 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5437 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5439 const unsigned NumGPRs = array_lengthof(GPR_32);
5440 const unsigned NumFPRs = 13;
5441 const unsigned NumVRs = array_lengthof(VR);
5443 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5445 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5446 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5448 SmallVector<SDValue, 8> MemOpChains;
5449 for (unsigned i = 0; i != NumOps; ++i) {
5450 SDValue Arg = OutVals[i];
5451 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5453 // PtrOff will be used to store the current argument to the stack if a
5454 // register cannot be found for it.
5457 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5459 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5461 // On PPC64, promote integers to 64-bit values.
5462 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5463 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5464 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5465 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5468 // FIXME memcpy is used way more than necessary. Correctness first.
5469 // Note: "by value" is code for passing a structure by value, not
5471 if (Flags.isByVal()) {
5472 unsigned Size = Flags.getByValSize();
5473 // Very small objects are passed right-justified. Everything else is
5474 // passed left-justified.
5475 if (Size==1 || Size==2) {
5476 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5477 if (GPR_idx != NumGPRs) {
5478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5479 MachinePointerInfo(), VT,
5480 false, false, false, 0);
5481 MemOpChains.push_back(Load.getValue(1));
5482 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5484 ArgOffset += PtrByteSize;
5486 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5487 PtrOff.getValueType());
5488 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5489 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5492 ArgOffset += PtrByteSize;
5496 // Copy entire object into memory. There are cases where gcc-generated
5497 // code assumes it is there, even if it could be put entirely into
5498 // registers. (This is not what the doc says.)
5499 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5503 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5504 // copy the pieces of the object that fit into registers from the
5505 // parameter save area.
5506 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5507 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5508 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5509 if (GPR_idx != NumGPRs) {
5510 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5511 MachinePointerInfo(),
5512 false, false, false, 0);
5513 MemOpChains.push_back(Load.getValue(1));
5514 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5515 ArgOffset += PtrByteSize;
5517 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5524 switch (Arg.getSimpleValueType().SimpleTy) {
5525 default: llvm_unreachable("Unexpected ValueType for argument!");
5529 if (GPR_idx != NumGPRs) {
5530 if (Arg.getValueType() == MVT::i1)
5531 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5533 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5535 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5536 isPPC64, isTailCall, false, MemOpChains,
5537 TailCallArguments, dl);
5539 ArgOffset += PtrByteSize;
5543 if (FPR_idx != NumFPRs) {
5544 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5547 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5548 MachinePointerInfo(), false, false, 0);
5549 MemOpChains.push_back(Store);
5551 // Float varargs are always shadowed in available integer registers
5552 if (GPR_idx != NumGPRs) {
5553 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5554 MachinePointerInfo(), false, false,
5556 MemOpChains.push_back(Load.getValue(1));
5557 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5559 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5560 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5561 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5562 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5563 MachinePointerInfo(),
5564 false, false, false, 0);
5565 MemOpChains.push_back(Load.getValue(1));
5566 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5569 // If we have any FPRs remaining, we may also have GPRs remaining.
5570 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5572 if (GPR_idx != NumGPRs)
5574 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5575 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5579 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5580 isPPC64, isTailCall, false, MemOpChains,
5581 TailCallArguments, dl);
5585 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5592 // These go aligned on the stack, or in the corresponding R registers
5593 // when within range. The Darwin PPC ABI doc claims they also go in
5594 // V registers; in fact gcc does this only for arguments that are
5595 // prototyped, not for those that match the ... We do it for all
5596 // arguments, seems to work.
5597 while (ArgOffset % 16 !=0) {
5598 ArgOffset += PtrByteSize;
5599 if (GPR_idx != NumGPRs)
5602 // We could elide this store in the case where the object fits
5603 // entirely in R registers. Maybe later.
5604 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5605 DAG.getConstant(ArgOffset, dl, PtrVT));
5606 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5607 MachinePointerInfo(), false, false, 0);
5608 MemOpChains.push_back(Store);
5609 if (VR_idx != NumVRs) {
5610 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5611 MachinePointerInfo(),
5612 false, false, false, 0);
5613 MemOpChains.push_back(Load.getValue(1));
5614 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5617 for (unsigned i=0; i<16; i+=PtrByteSize) {
5618 if (GPR_idx == NumGPRs)
5620 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5621 DAG.getConstant(i, dl, PtrVT));
5622 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5623 false, false, false, 0);
5624 MemOpChains.push_back(Load.getValue(1));
5625 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5630 // Non-varargs Altivec params generally go in registers, but have
5631 // stack space allocated at the end.
5632 if (VR_idx != NumVRs) {
5633 // Doesn't have GPR space allocated.
5634 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5635 } else if (nAltivecParamsAtEnd==0) {
5636 // We are emitting Altivec params in order.
5637 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5638 isPPC64, isTailCall, true, MemOpChains,
5639 TailCallArguments, dl);
5645 // If all Altivec parameters fit in registers, as they usually do,
5646 // they get stack space following the non-Altivec parameters. We
5647 // don't track this here because nobody below needs it.
5648 // If there are more Altivec parameters than fit in registers emit
5650 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5652 // Offset is aligned; skip 1st 12 params which go in V registers.
5653 ArgOffset = ((ArgOffset+15)/16)*16;
5655 for (unsigned i = 0; i != NumOps; ++i) {
5656 SDValue Arg = OutVals[i];
5657 EVT ArgType = Outs[i].VT;
5658 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5659 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5662 // We are emitting Altivec params in order.
5663 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5664 isPPC64, isTailCall, true, MemOpChains,
5665 TailCallArguments, dl);
5672 if (!MemOpChains.empty())
5673 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5675 // On Darwin, R12 must contain the address of an indirect callee. This does
5676 // not mean the MTCTR instruction must use R12; it's easier to model this as
5677 // an extra parameter, so do that.
5679 !isFunctionGlobalAddress(Callee) &&
5680 !isa<ExternalSymbolSDNode>(Callee) &&
5681 !isBLACompatibleAddress(Callee, DAG))
5682 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5683 PPC::R12), Callee));
5685 // Build a sequence of copy-to-reg nodes chained together with token chain
5686 // and flag operands which copy the outgoing args into the appropriate regs.
5688 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5689 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5690 RegsToPass[i].second, InFlag);
5691 InFlag = Chain.getValue(1);
5695 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5696 FPOp, true, TailCallArguments);
5698 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5699 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5700 NumBytes, Ins, InVals, CS);
5704 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5705 MachineFunction &MF, bool isVarArg,
5706 const SmallVectorImpl<ISD::OutputArg> &Outs,
5707 LLVMContext &Context) const {
5708 SmallVector<CCValAssign, 16> RVLocs;
5709 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5710 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5714 PPCTargetLowering::LowerReturn(SDValue Chain,
5715 CallingConv::ID CallConv, bool isVarArg,
5716 const SmallVectorImpl<ISD::OutputArg> &Outs,
5717 const SmallVectorImpl<SDValue> &OutVals,
5718 SDLoc dl, SelectionDAG &DAG) const {
5720 SmallVector<CCValAssign, 16> RVLocs;
5721 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5723 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5726 SmallVector<SDValue, 4> RetOps(1, Chain);
5728 // Copy the result values into the output registers.
5729 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5730 CCValAssign &VA = RVLocs[i];
5731 assert(VA.isRegLoc() && "Can only return in registers!");
5733 SDValue Arg = OutVals[i];
5735 switch (VA.getLocInfo()) {
5736 default: llvm_unreachable("Unknown loc info!");
5737 case CCValAssign::Full: break;
5738 case CCValAssign::AExt:
5739 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5741 case CCValAssign::ZExt:
5742 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5744 case CCValAssign::SExt:
5745 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5749 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5750 Flag = Chain.getValue(1);
5751 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5754 RetOps[0] = Chain; // Update chain.
5756 // Add the flag if we have it.
5758 RetOps.push_back(Flag);
5760 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5763 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5764 const PPCSubtarget &Subtarget) const {
5765 // When we pop the dynamic allocation we need to restore the SP link.
5768 // Get the corect type for pointers.
5769 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5771 // Construct the stack pointer operand.
5772 bool isPPC64 = Subtarget.isPPC64();
5773 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5774 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5776 // Get the operands for the STACKRESTORE.
5777 SDValue Chain = Op.getOperand(0);
5778 SDValue SaveSP = Op.getOperand(1);
5780 // Load the old link SP.
5781 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5782 MachinePointerInfo(),
5783 false, false, false, 0);
5785 // Restore the stack pointer.
5786 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5788 // Store the old link SP.
5789 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5796 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5797 MachineFunction &MF = DAG.getMachineFunction();
5798 bool isPPC64 = Subtarget.isPPC64();
5799 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5801 // Get current frame pointer save index. The users of this index will be
5802 // primarily DYNALLOC instructions.
5803 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5804 int RASI = FI->getReturnAddrSaveIndex();
5806 // If the frame pointer save index hasn't been defined yet.
5808 // Find out what the fix offset of the frame pointer save area.
5809 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5810 // Allocate the frame index for frame pointer save area.
5811 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5813 FI->setReturnAddrSaveIndex(RASI);
5815 return DAG.getFrameIndex(RASI, PtrVT);
5819 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5820 MachineFunction &MF = DAG.getMachineFunction();
5821 bool isPPC64 = Subtarget.isPPC64();
5822 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5824 // Get current frame pointer save index. The users of this index will be
5825 // primarily DYNALLOC instructions.
5826 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5827 int FPSI = FI->getFramePointerSaveIndex();
5829 // If the frame pointer save index hasn't been defined yet.
5831 // Find out what the fix offset of the frame pointer save area.
5832 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5833 // Allocate the frame index for frame pointer save area.
5834 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5836 FI->setFramePointerSaveIndex(FPSI);
5838 return DAG.getFrameIndex(FPSI, PtrVT);
5841 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5843 const PPCSubtarget &Subtarget) const {
5845 SDValue Chain = Op.getOperand(0);
5846 SDValue Size = Op.getOperand(1);
5849 // Get the corect type for pointers.
5850 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5852 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5853 DAG.getConstant(0, dl, PtrVT), Size);
5854 // Construct a node for the frame pointer save index.
5855 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5856 // Build a DYNALLOC node.
5857 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5858 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5859 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5862 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5863 SelectionDAG &DAG) const {
5865 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5866 DAG.getVTList(MVT::i32, MVT::Other),
5867 Op.getOperand(0), Op.getOperand(1));
5870 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5871 SelectionDAG &DAG) const {
5873 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5874 Op.getOperand(0), Op.getOperand(1));
5877 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5878 if (Op.getValueType().isVector())
5879 return LowerVectorLoad(Op, DAG);
5881 assert(Op.getValueType() == MVT::i1 &&
5882 "Custom lowering only for i1 loads");
5884 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5887 LoadSDNode *LD = cast<LoadSDNode>(Op);
5889 SDValue Chain = LD->getChain();
5890 SDValue BasePtr = LD->getBasePtr();
5891 MachineMemOperand *MMO = LD->getMemOperand();
5894 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5895 BasePtr, MVT::i8, MMO);
5896 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5898 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5899 return DAG.getMergeValues(Ops, dl);
5902 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5903 if (Op.getOperand(1).getValueType().isVector())
5904 return LowerVectorStore(Op, DAG);
5906 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5907 "Custom lowering only for i1 stores");
5909 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5912 StoreSDNode *ST = cast<StoreSDNode>(Op);
5914 SDValue Chain = ST->getChain();
5915 SDValue BasePtr = ST->getBasePtr();
5916 SDValue Value = ST->getValue();
5917 MachineMemOperand *MMO = ST->getMemOperand();
5919 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5921 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5924 // FIXME: Remove this once the ANDI glue bug is fixed:
5925 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5926 assert(Op.getValueType() == MVT::i1 &&
5927 "Custom lowering only for i1 results");
5930 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5934 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5936 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5937 // Not FP? Not a fsel.
5938 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5939 !Op.getOperand(2).getValueType().isFloatingPoint())
5942 // We might be able to do better than this under some circumstances, but in
5943 // general, fsel-based lowering of select is a finite-math-only optimization.
5944 // For more information, see section F.3 of the 2.06 ISA specification.
5945 if (!DAG.getTarget().Options.NoInfsFPMath ||
5946 !DAG.getTarget().Options.NoNaNsFPMath)
5949 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5951 EVT ResVT = Op.getValueType();
5952 EVT CmpVT = Op.getOperand(0).getValueType();
5953 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5954 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5957 // If the RHS of the comparison is a 0.0, we don't need to do the
5958 // subtraction at all.
5960 if (isFloatingPointZero(RHS))
5962 default: break; // SETUO etc aren't handled by fsel.
5966 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5967 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5968 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5969 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5970 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5971 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5972 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5975 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5978 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5979 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5980 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5983 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5986 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5987 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5988 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5989 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5994 default: break; // SETUO etc aren't handled by fsel.
5998 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5999 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6000 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6001 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6002 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6003 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6004 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6005 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6008 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6009 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6010 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6011 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6014 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6015 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6016 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6017 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6020 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6021 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6022 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6023 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6026 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6027 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6028 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6029 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6034 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6037 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6038 SDValue Src = Op.getOperand(0);
6039 if (Src.getValueType() == MVT::f32)
6040 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6043 switch (Op.getSimpleValueType().SimpleTy) {
6044 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6047 Op.getOpcode() == ISD::FP_TO_SINT
6049 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6053 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6054 "i64 FP_TO_UINT is supported only with FPCVT");
6055 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6061 // Convert the FP value to an int value through memory.
6062 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6063 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6064 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6065 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6066 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
6068 // Emit a store to the stack slot.
6071 MachineFunction &MF = DAG.getMachineFunction();
6072 MachineMemOperand *MMO =
6073 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6074 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6075 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6076 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6078 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6079 MPI, false, false, 0);
6081 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6083 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6084 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6085 DAG.getConstant(4, dl, FIPtr.getValueType()));
6086 MPI = MPI.getWithOffset(4);
6094 /// \brief Custom lowers floating point to integer conversions to use
6095 /// the direct move instructions available in ISA 2.07 to avoid the
6096 /// need for load/store combinations.
6097 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6100 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6101 SDValue Src = Op.getOperand(0);
6103 if (Src.getValueType() == MVT::f32)
6104 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6107 switch (Op.getSimpleValueType().SimpleTy) {
6108 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6111 Op.getOpcode() == ISD::FP_TO_SINT
6113 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6115 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6118 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6119 "i64 FP_TO_UINT is supported only with FPCVT");
6120 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6123 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6129 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6131 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6132 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6135 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6137 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6138 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6142 // We're trying to insert a regular store, S, and then a load, L. If the
6143 // incoming value, O, is a load, we might just be able to have our load use the
6144 // address used by O. However, we don't know if anything else will store to
6145 // that address before we can load from it. To prevent this situation, we need
6146 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6147 // the same chain operand as O, we create a token factor from the chain results
6148 // of O and L, and we replace all uses of O's chain result with that token
6149 // factor (see spliceIntoChain below for this last part).
6150 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6153 ISD::LoadExtType ET) const {
6155 if (ET == ISD::NON_EXTLOAD &&
6156 (Op.getOpcode() == ISD::FP_TO_UINT ||
6157 Op.getOpcode() == ISD::FP_TO_SINT) &&
6158 isOperationLegalOrCustom(Op.getOpcode(),
6159 Op.getOperand(0).getValueType())) {
6161 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6165 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6166 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6167 LD->isNonTemporal())
6169 if (LD->getMemoryVT() != MemVT)
6172 RLI.Ptr = LD->getBasePtr();
6173 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6174 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6175 "Non-pre-inc AM on PPC?");
6176 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6180 RLI.Chain = LD->getChain();
6181 RLI.MPI = LD->getPointerInfo();
6182 RLI.IsInvariant = LD->isInvariant();
6183 RLI.Alignment = LD->getAlignment();
6184 RLI.AAInfo = LD->getAAInfo();
6185 RLI.Ranges = LD->getRanges();
6187 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6191 // Given the head of the old chain, ResChain, insert a token factor containing
6192 // it and NewResChain, and make users of ResChain now be users of that token
6194 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6195 SDValue NewResChain,
6196 SelectionDAG &DAG) const {
6200 SDLoc dl(NewResChain);
6202 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6203 NewResChain, DAG.getUNDEF(MVT::Other));
6204 assert(TF.getNode() != NewResChain.getNode() &&
6205 "A new TF really is required here");
6207 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6208 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6211 /// \brief Custom lowers integer to floating point conversions to use
6212 /// the direct move instructions available in ISA 2.07 to avoid the
6213 /// need for load/store combinations.
6214 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6217 assert((Op.getValueType() == MVT::f32 ||
6218 Op.getValueType() == MVT::f64) &&
6219 "Invalid floating point type as target of conversion");
6220 assert(Subtarget.hasFPCVT() &&
6221 "Int to FP conversions with direct moves require FPCVT");
6223 SDValue Src = Op.getOperand(0);
6224 bool SinglePrec = Op.getValueType() == MVT::f32;
6225 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6226 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6227 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6228 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6231 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6233 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6236 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6237 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6243 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6244 SelectionDAG &DAG) const {
6247 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6248 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6251 SDValue Value = Op.getOperand(0);
6252 // The values are now known to be -1 (false) or 1 (true). To convert this
6253 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6254 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6255 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6257 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6258 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6259 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6261 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6263 if (Op.getValueType() != MVT::v4f64)
6264 Value = DAG.getNode(ISD::FP_ROUND, dl,
6265 Op.getValueType(), Value,
6266 DAG.getIntPtrConstant(1, dl));
6270 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6271 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6274 if (Op.getOperand(0).getValueType() == MVT::i1)
6275 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6276 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6277 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6279 // If we have direct moves, we can do all the conversion, skip the store/load
6280 // however, without FPCVT we can't do most conversions.
6281 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6282 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6284 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6285 "UINT_TO_FP is supported only with FPCVT");
6287 // If we have FCFIDS, then use it when converting to single-precision.
6288 // Otherwise, convert to double-precision and then round.
6289 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6290 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6292 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6294 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6298 if (Op.getOperand(0).getValueType() == MVT::i64) {
6299 SDValue SINT = Op.getOperand(0);
6300 // When converting to single-precision, we actually need to convert
6301 // to double-precision first and then round to single-precision.
6302 // To avoid double-rounding effects during that operation, we have
6303 // to prepare the input operand. Bits that might be truncated when
6304 // converting to double-precision are replaced by a bit that won't
6305 // be lost at this stage, but is below the single-precision rounding
6308 // However, if -enable-unsafe-fp-math is in effect, accept double
6309 // rounding to avoid the extra overhead.
6310 if (Op.getValueType() == MVT::f32 &&
6311 !Subtarget.hasFPCVT() &&
6312 !DAG.getTarget().Options.UnsafeFPMath) {
6314 // Twiddle input to make sure the low 11 bits are zero. (If this
6315 // is the case, we are guaranteed the value will fit into the 53 bit
6316 // mantissa of an IEEE double-precision value without rounding.)
6317 // If any of those low 11 bits were not zero originally, make sure
6318 // bit 12 (value 2048) is set instead, so that the final rounding
6319 // to single-precision gets the correct result.
6320 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6321 SINT, DAG.getConstant(2047, dl, MVT::i64));
6322 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6323 Round, DAG.getConstant(2047, dl, MVT::i64));
6324 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6325 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6326 Round, DAG.getConstant(-2048, dl, MVT::i64));
6328 // However, we cannot use that value unconditionally: if the magnitude
6329 // of the input value is small, the bit-twiddling we did above might
6330 // end up visibly changing the output. Fortunately, in that case, we
6331 // don't need to twiddle bits since the original input will convert
6332 // exactly to double-precision floating-point already. Therefore,
6333 // construct a conditional to use the original value if the top 11
6334 // bits are all sign-bit copies, and use the rounded value computed
6336 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6337 SINT, DAG.getConstant(53, dl, MVT::i32));
6338 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6339 Cond, DAG.getConstant(1, dl, MVT::i64));
6340 Cond = DAG.getSetCC(dl, MVT::i32,
6341 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6343 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6349 MachineFunction &MF = DAG.getMachineFunction();
6350 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6351 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6352 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6354 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6355 } else if (Subtarget.hasLFIWAX() &&
6356 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6357 MachineMemOperand *MMO =
6358 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6359 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6360 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6361 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6362 DAG.getVTList(MVT::f64, MVT::Other),
6363 Ops, MVT::i32, MMO);
6364 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6365 } else if (Subtarget.hasFPCVT() &&
6366 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6367 MachineMemOperand *MMO =
6368 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6369 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6370 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6371 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6372 DAG.getVTList(MVT::f64, MVT::Other),
6373 Ops, MVT::i32, MMO);
6374 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6375 } else if (((Subtarget.hasLFIWAX() &&
6376 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6377 (Subtarget.hasFPCVT() &&
6378 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6379 SINT.getOperand(0).getValueType() == MVT::i32) {
6380 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6381 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6383 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6384 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6387 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6388 MachinePointerInfo::getFixedStack(FrameIdx),
6391 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6392 "Expected an i32 store");
6396 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6399 MachineMemOperand *MMO =
6400 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6401 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6402 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6403 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6404 PPCISD::LFIWZX : PPCISD::LFIWAX,
6405 dl, DAG.getVTList(MVT::f64, MVT::Other),
6406 Ops, MVT::i32, MMO);
6408 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6410 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6412 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6413 FP = DAG.getNode(ISD::FP_ROUND, dl,
6414 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6418 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6419 "Unhandled INT_TO_FP type in custom expander!");
6420 // Since we only generate this in 64-bit mode, we can take advantage of
6421 // 64-bit registers. In particular, sign extend the input value into the
6422 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6423 // then lfd it and fcfid it.
6424 MachineFunction &MF = DAG.getMachineFunction();
6425 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6426 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6429 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6432 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6434 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6435 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6437 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6438 MachinePointerInfo::getFixedStack(FrameIdx),
6441 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6442 "Expected an i32 store");
6446 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6450 MachineMemOperand *MMO =
6451 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6452 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6453 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6454 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6455 PPCISD::LFIWZX : PPCISD::LFIWAX,
6456 dl, DAG.getVTList(MVT::f64, MVT::Other),
6457 Ops, MVT::i32, MMO);
6459 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6461 assert(Subtarget.isPPC64() &&
6462 "i32->FP without LFIWAX supported only on PPC64");
6464 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6465 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6467 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6470 // STD the extended value into the stack slot.
6471 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6472 MachinePointerInfo::getFixedStack(FrameIdx),
6475 // Load the value as a double.
6476 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6477 MachinePointerInfo::getFixedStack(FrameIdx),
6478 false, false, false, 0);
6481 // FCFID it and return it.
6482 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6483 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6484 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6485 DAG.getIntPtrConstant(0, dl));
6489 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6490 SelectionDAG &DAG) const {
6493 The rounding mode is in bits 30:31 of FPSR, and has the following
6500 FLT_ROUNDS, on the other hand, expects the following:
6507 To perform the conversion, we do:
6508 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6511 MachineFunction &MF = DAG.getMachineFunction();
6512 EVT VT = Op.getValueType();
6513 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6515 // Save FP Control Word to register
6517 MVT::f64, // return register
6518 MVT::Glue // unused in this context
6520 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6522 // Save FP register to stack slot
6523 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6524 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6525 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6526 StackSlot, MachinePointerInfo(), false, false,0);
6528 // Load FP Control Word from low 32 bits of stack slot.
6529 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6530 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6531 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6532 false, false, false, 0);
6534 // Transform as necessary
6536 DAG.getNode(ISD::AND, dl, MVT::i32,
6537 CWD, DAG.getConstant(3, dl, MVT::i32));
6539 DAG.getNode(ISD::SRL, dl, MVT::i32,
6540 DAG.getNode(ISD::AND, dl, MVT::i32,
6541 DAG.getNode(ISD::XOR, dl, MVT::i32,
6542 CWD, DAG.getConstant(3, dl, MVT::i32)),
6543 DAG.getConstant(3, dl, MVT::i32)),
6544 DAG.getConstant(1, dl, MVT::i32));
6547 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6549 return DAG.getNode((VT.getSizeInBits() < 16 ?
6550 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6553 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6554 EVT VT = Op.getValueType();
6555 unsigned BitWidth = VT.getSizeInBits();
6557 assert(Op.getNumOperands() == 3 &&
6558 VT == Op.getOperand(1).getValueType() &&
6561 // Expand into a bunch of logical ops. Note that these ops
6562 // depend on the PPC behavior for oversized shift amounts.
6563 SDValue Lo = Op.getOperand(0);
6564 SDValue Hi = Op.getOperand(1);
6565 SDValue Amt = Op.getOperand(2);
6566 EVT AmtVT = Amt.getValueType();
6568 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6569 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6570 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6571 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6572 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6573 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6574 DAG.getConstant(-BitWidth, dl, AmtVT));
6575 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6576 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6577 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6578 SDValue OutOps[] = { OutLo, OutHi };
6579 return DAG.getMergeValues(OutOps, dl);
6582 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6583 EVT VT = Op.getValueType();
6585 unsigned BitWidth = VT.getSizeInBits();
6586 assert(Op.getNumOperands() == 3 &&
6587 VT == Op.getOperand(1).getValueType() &&
6590 // Expand into a bunch of logical ops. Note that these ops
6591 // depend on the PPC behavior for oversized shift amounts.
6592 SDValue Lo = Op.getOperand(0);
6593 SDValue Hi = Op.getOperand(1);
6594 SDValue Amt = Op.getOperand(2);
6595 EVT AmtVT = Amt.getValueType();
6597 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6598 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6599 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6600 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6601 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6602 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6603 DAG.getConstant(-BitWidth, dl, AmtVT));
6604 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6605 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6606 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6607 SDValue OutOps[] = { OutLo, OutHi };
6608 return DAG.getMergeValues(OutOps, dl);
6611 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6613 EVT VT = Op.getValueType();
6614 unsigned BitWidth = VT.getSizeInBits();
6615 assert(Op.getNumOperands() == 3 &&
6616 VT == Op.getOperand(1).getValueType() &&
6619 // Expand into a bunch of logical ops, followed by a select_cc.
6620 SDValue Lo = Op.getOperand(0);
6621 SDValue Hi = Op.getOperand(1);
6622 SDValue Amt = Op.getOperand(2);
6623 EVT AmtVT = Amt.getValueType();
6625 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6626 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6627 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6628 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6629 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6630 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6631 DAG.getConstant(-BitWidth, dl, AmtVT));
6632 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6633 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6634 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6635 Tmp4, Tmp6, ISD::SETLE);
6636 SDValue OutOps[] = { OutLo, OutHi };
6637 return DAG.getMergeValues(OutOps, dl);
6640 //===----------------------------------------------------------------------===//
6641 // Vector related lowering.
6644 /// BuildSplatI - Build a canonical splati of Val with an element size of
6645 /// SplatSize. Cast the result to VT.
6646 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6647 SelectionDAG &DAG, SDLoc dl) {
6648 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6650 static const MVT VTys[] = { // canonical VT to use for each size.
6651 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6654 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6656 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6660 EVT CanonicalVT = VTys[SplatSize-1];
6662 // Build a canonical splat for this value.
6663 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6664 SmallVector<SDValue, 8> Ops;
6665 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6666 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6667 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6670 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6671 /// specified intrinsic ID.
6672 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6673 SelectionDAG &DAG, SDLoc dl,
6674 EVT DestVT = MVT::Other) {
6675 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6676 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6677 DAG.getConstant(IID, dl, MVT::i32), Op);
6680 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6681 /// specified intrinsic ID.
6682 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6683 SelectionDAG &DAG, SDLoc dl,
6684 EVT DestVT = MVT::Other) {
6685 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6686 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6687 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6690 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6691 /// specified intrinsic ID.
6692 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6693 SDValue Op2, SelectionDAG &DAG,
6694 SDLoc dl, EVT DestVT = MVT::Other) {
6695 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6696 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6697 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6701 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6702 /// amount. The result has the specified value type.
6703 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6704 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6705 // Force LHS/RHS to be the right type.
6706 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6707 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6710 for (unsigned i = 0; i != 16; ++i)
6712 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6713 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6716 // If this is a case we can't handle, return null and let the default
6717 // expansion code take care of it. If we CAN select this case, and if it
6718 // selects to a single instruction, return Op. Otherwise, if we can codegen
6719 // this case more efficiently than a constant pool load, lower it to the
6720 // sequence of ops that should be used.
6721 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6722 SelectionDAG &DAG) const {
6724 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6725 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6727 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6728 // We first build an i32 vector, load it into a QPX register,
6729 // then convert it to a floating-point vector and compare it
6730 // to a zero vector to get the boolean result.
6731 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6732 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6733 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6734 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6735 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6737 assert(BVN->getNumOperands() == 4 &&
6738 "BUILD_VECTOR for v4i1 does not have 4 operands");
6740 bool IsConst = true;
6741 for (unsigned i = 0; i < 4; ++i) {
6742 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6743 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6751 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6753 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6755 SmallVector<Constant*, 4> CV(4, NegOne);
6756 for (unsigned i = 0; i < 4; ++i) {
6757 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6758 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6759 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6760 getConstantIntValue()->isZero())
6766 Constant *CP = ConstantVector::get(CV);
6767 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6768 16 /* alignment */);
6770 SmallVector<SDValue, 2> Ops;
6771 Ops.push_back(DAG.getEntryNode());
6772 Ops.push_back(CPIdx);
6774 SmallVector<EVT, 2> ValueVTs;
6775 ValueVTs.push_back(MVT::v4i1);
6776 ValueVTs.push_back(MVT::Other); // chain
6777 SDVTList VTs = DAG.getVTList(ValueVTs);
6779 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6780 dl, VTs, Ops, MVT::v4f32,
6781 MachinePointerInfo::getConstantPool());
6784 SmallVector<SDValue, 4> Stores;
6785 for (unsigned i = 0; i < 4; ++i) {
6786 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6788 unsigned Offset = 4*i;
6789 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6790 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6792 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6793 if (StoreSize > 4) {
6794 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6795 BVN->getOperand(i), Idx,
6796 PtrInfo.getWithOffset(Offset),
6797 MVT::i32, false, false, 0));
6799 SDValue StoreValue = BVN->getOperand(i);
6801 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6803 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6805 PtrInfo.getWithOffset(Offset),
6811 if (!Stores.empty())
6812 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6814 StoreChain = DAG.getEntryNode();
6816 // Now load from v4i32 into the QPX register; this will extend it to
6817 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6818 // is typed as v4f64 because the QPX register integer states are not
6819 // explicitly represented.
6821 SmallVector<SDValue, 2> Ops;
6822 Ops.push_back(StoreChain);
6823 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6824 Ops.push_back(FIdx);
6826 SmallVector<EVT, 2> ValueVTs;
6827 ValueVTs.push_back(MVT::v4f64);
6828 ValueVTs.push_back(MVT::Other); // chain
6829 SDVTList VTs = DAG.getVTList(ValueVTs);
6831 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6832 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6833 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6834 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6837 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6838 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6839 FPZeros, FPZeros, FPZeros, FPZeros);
6841 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6844 // All other QPX vectors are handled by generic code.
6845 if (Subtarget.hasQPX())
6848 // Check if this is a splat of a constant value.
6849 APInt APSplatBits, APSplatUndef;
6850 unsigned SplatBitSize;
6852 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6853 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6857 unsigned SplatBits = APSplatBits.getZExtValue();
6858 unsigned SplatUndef = APSplatUndef.getZExtValue();
6859 unsigned SplatSize = SplatBitSize / 8;
6861 // First, handle single instruction cases.
6864 if (SplatBits == 0) {
6865 // Canonicalize all zero vectors to be v4i32.
6866 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6867 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6868 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6869 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6874 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6875 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6877 if (SextVal >= -16 && SextVal <= 15)
6878 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6881 // Two instruction sequences.
6883 // If this value is in the range [-32,30] and is even, use:
6884 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6885 // If this value is in the range [17,31] and is odd, use:
6886 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6887 // If this value is in the range [-31,-17] and is odd, use:
6888 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6889 // Note the last two are three-instruction sequences.
6890 if (SextVal >= -32 && SextVal <= 31) {
6891 // To avoid having these optimizations undone by constant folding,
6892 // we convert to a pseudo that will be expanded later into one of
6894 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6895 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6896 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6897 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6898 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6899 if (VT == Op.getValueType())
6902 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6905 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6906 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6908 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6909 // Make -1 and vspltisw -1:
6910 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6912 // Make the VSLW intrinsic, computing 0x8000_0000.
6913 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6916 // xor by OnesV to invert it.
6917 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6918 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6921 // Check to see if this is a wide variety of vsplti*, binop self cases.
6922 static const signed char SplatCsts[] = {
6923 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6924 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6927 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6928 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6929 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6930 int i = SplatCsts[idx];
6932 // Figure out what shift amount will be used by altivec if shifted by i in
6934 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6936 // vsplti + shl self.
6937 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6938 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6939 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6940 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6941 Intrinsic::ppc_altivec_vslw
6943 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6944 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6947 // vsplti + srl self.
6948 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6949 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6950 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6951 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6952 Intrinsic::ppc_altivec_vsrw
6954 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6955 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6958 // vsplti + sra self.
6959 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6960 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6961 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6962 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6963 Intrinsic::ppc_altivec_vsraw
6965 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6966 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6969 // vsplti + rol self.
6970 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6971 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6972 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6973 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6974 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6975 Intrinsic::ppc_altivec_vrlw
6977 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6978 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6981 // t = vsplti c, result = vsldoi t, t, 1
6982 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6983 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6984 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6986 // t = vsplti c, result = vsldoi t, t, 2
6987 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6988 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6989 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6991 // t = vsplti c, result = vsldoi t, t, 3
6992 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6993 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6994 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
7001 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7002 /// the specified operations to build the shuffle.
7003 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7004 SDValue RHS, SelectionDAG &DAG,
7006 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7007 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7008 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7011 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7023 if (OpNum == OP_COPY) {
7024 if (LHSID == (1*9+2)*9+3) return LHS;
7025 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7029 SDValue OpLHS, OpRHS;
7030 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7031 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7035 default: llvm_unreachable("Unknown i32 permute!");
7037 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7038 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7039 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7040 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7043 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7044 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7045 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7046 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7049 for (unsigned i = 0; i != 16; ++i)
7050 ShufIdxs[i] = (i&3)+0;
7053 for (unsigned i = 0; i != 16; ++i)
7054 ShufIdxs[i] = (i&3)+4;
7057 for (unsigned i = 0; i != 16; ++i)
7058 ShufIdxs[i] = (i&3)+8;
7061 for (unsigned i = 0; i != 16; ++i)
7062 ShufIdxs[i] = (i&3)+12;
7065 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7067 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7069 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7071 EVT VT = OpLHS.getValueType();
7072 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7073 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7074 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7075 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7078 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7079 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7080 /// return the code it can be lowered into. Worst case, it can always be
7081 /// lowered into a vperm.
7082 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7083 SelectionDAG &DAG) const {
7085 SDValue V1 = Op.getOperand(0);
7086 SDValue V2 = Op.getOperand(1);
7087 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7088 EVT VT = Op.getValueType();
7089 bool isLittleEndian = Subtarget.isLittleEndian();
7091 if (Subtarget.hasQPX()) {
7092 if (VT.getVectorNumElements() != 4)
7095 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7097 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7098 if (AlignIdx != -1) {
7099 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7100 DAG.getConstant(AlignIdx, dl, MVT::i32));
7101 } else if (SVOp->isSplat()) {
7102 int SplatIdx = SVOp->getSplatIndex();
7103 if (SplatIdx >= 4) {
7108 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7111 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7112 DAG.getConstant(SplatIdx, dl, MVT::i32));
7115 // Lower this into a qvgpci/qvfperm pair.
7117 // Compute the qvgpci literal
7119 for (unsigned i = 0; i < 4; ++i) {
7120 int m = SVOp->getMaskElt(i);
7121 unsigned mm = m >= 0 ? (unsigned) m : i;
7122 idx |= mm << (3-i)*3;
7125 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7126 DAG.getConstant(idx, dl, MVT::i32));
7127 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7130 // Cases that are handled by instructions that take permute immediates
7131 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7132 // selected by the instruction selector.
7133 if (V2.getOpcode() == ISD::UNDEF) {
7134 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7135 PPC::isSplatShuffleMask(SVOp, 2) ||
7136 PPC::isSplatShuffleMask(SVOp, 4) ||
7137 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7138 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7139 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7140 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7141 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7142 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7143 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7144 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7145 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7146 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7147 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7148 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
7153 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7154 // and produce a fixed permutation. If any of these match, do not lower to
7156 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7157 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7158 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7159 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7160 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7161 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7162 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7163 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7164 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7165 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7166 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7167 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7168 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
7171 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7172 // perfect shuffle table to emit an optimal matching sequence.
7173 ArrayRef<int> PermMask = SVOp->getMask();
7175 unsigned PFIndexes[4];
7176 bool isFourElementShuffle = true;
7177 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7178 unsigned EltNo = 8; // Start out undef.
7179 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7180 if (PermMask[i*4+j] < 0)
7181 continue; // Undef, ignore it.
7183 unsigned ByteSource = PermMask[i*4+j];
7184 if ((ByteSource & 3) != j) {
7185 isFourElementShuffle = false;
7190 EltNo = ByteSource/4;
7191 } else if (EltNo != ByteSource/4) {
7192 isFourElementShuffle = false;
7196 PFIndexes[i] = EltNo;
7199 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7200 // perfect shuffle vector to determine if it is cost effective to do this as
7201 // discrete instructions, or whether we should use a vperm.
7202 // For now, we skip this for little endian until such time as we have a
7203 // little-endian perfect shuffle table.
7204 if (isFourElementShuffle && !isLittleEndian) {
7205 // Compute the index in the perfect shuffle table.
7206 unsigned PFTableIndex =
7207 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7209 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7210 unsigned Cost = (PFEntry >> 30);
7212 // Determining when to avoid vperm is tricky. Many things affect the cost
7213 // of vperm, particularly how many times the perm mask needs to be computed.
7214 // For example, if the perm mask can be hoisted out of a loop or is already
7215 // used (perhaps because there are multiple permutes with the same shuffle
7216 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7217 // the loop requires an extra register.
7219 // As a compromise, we only emit discrete instructions if the shuffle can be
7220 // generated in 3 or fewer operations. When we have loop information
7221 // available, if this block is within a loop, we should avoid using vperm
7222 // for 3-operation perms and use a constant pool load instead.
7224 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7227 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7228 // vector that will get spilled to the constant pool.
7229 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7231 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7232 // that it is in input element units, not in bytes. Convert now.
7234 // For little endian, the order of the input vectors is reversed, and
7235 // the permutation mask is complemented with respect to 31. This is
7236 // necessary to produce proper semantics with the big-endian-biased vperm
7238 EVT EltVT = V1.getValueType().getVectorElementType();
7239 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7241 SmallVector<SDValue, 16> ResultMask;
7242 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7243 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7245 for (unsigned j = 0; j != BytesPerElement; ++j)
7247 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7250 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7254 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7257 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7260 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7264 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7265 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7266 /// information about the intrinsic.
7267 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7268 bool &isDot, const PPCSubtarget &Subtarget) {
7269 unsigned IntrinsicID =
7270 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7273 switch (IntrinsicID) {
7274 default: return false;
7275 // Comparison predicates.
7276 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7277 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7278 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7279 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7280 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7281 case Intrinsic::ppc_altivec_vcmpequd_p:
7282 if (Subtarget.hasP8Altivec()) {
7290 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7291 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7292 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7293 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7294 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7295 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7296 if (Subtarget.hasP8Altivec()) {
7304 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7305 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7306 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7307 case Intrinsic::ppc_altivec_vcmpgtud_p:
7308 if (Subtarget.hasP8Altivec()) {
7317 // Normal Comparisons.
7318 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7319 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7320 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7321 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7322 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7323 case Intrinsic::ppc_altivec_vcmpequd:
7324 if (Subtarget.hasP8Altivec()) {
7332 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7333 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7334 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7335 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7336 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7337 case Intrinsic::ppc_altivec_vcmpgtsd:
7338 if (Subtarget.hasP8Altivec()) {
7346 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7347 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7348 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7349 case Intrinsic::ppc_altivec_vcmpgtud:
7350 if (Subtarget.hasP8Altivec()) {
7362 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7363 /// lower, do it, otherwise return null.
7364 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7365 SelectionDAG &DAG) const {
7366 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7367 // opcode number of the comparison.
7371 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7372 return SDValue(); // Don't custom lower most intrinsics.
7374 // If this is a non-dot comparison, make the VCMP node and we are done.
7376 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7377 Op.getOperand(1), Op.getOperand(2),
7378 DAG.getConstant(CompareOpc, dl, MVT::i32));
7379 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7382 // Create the PPCISD altivec 'dot' comparison node.
7384 Op.getOperand(2), // LHS
7385 Op.getOperand(3), // RHS
7386 DAG.getConstant(CompareOpc, dl, MVT::i32)
7388 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7389 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7391 // Now that we have the comparison, emit a copy from the CR to a GPR.
7392 // This is flagged to the above dot comparison.
7393 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7394 DAG.getRegister(PPC::CR6, MVT::i32),
7395 CompNode.getValue(1));
7397 // Unpack the result based on how the target uses it.
7398 unsigned BitNo; // Bit # of CR6.
7399 bool InvertBit; // Invert result?
7400 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7401 default: // Can't happen, don't crash on invalid number though.
7402 case 0: // Return the value of the EQ bit of CR6.
7403 BitNo = 0; InvertBit = false;
7405 case 1: // Return the inverted value of the EQ bit of CR6.
7406 BitNo = 0; InvertBit = true;
7408 case 2: // Return the value of the LT bit of CR6.
7409 BitNo = 2; InvertBit = false;
7411 case 3: // Return the inverted value of the LT bit of CR6.
7412 BitNo = 2; InvertBit = true;
7416 // Shift the bit into the low position.
7417 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7418 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7420 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7421 DAG.getConstant(1, dl, MVT::i32));
7423 // If we are supposed to, toggle the bit.
7425 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7426 DAG.getConstant(1, dl, MVT::i32));
7430 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7431 SelectionDAG &DAG) const {
7433 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7434 // instructions), but for smaller types, we need to first extend up to v2i32
7435 // before doing going farther.
7436 if (Op.getValueType() == MVT::v2i64) {
7437 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7438 if (ExtVT != MVT::v2i32) {
7439 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7440 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7441 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7442 ExtVT.getVectorElementType(), 4)));
7443 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7444 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7445 DAG.getValueType(MVT::v2i32));
7454 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7455 SelectionDAG &DAG) const {
7457 // Create a stack slot that is 16-byte aligned.
7458 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7459 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7460 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7461 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7463 // Store the input value into Value#0 of the stack slot.
7464 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7465 Op.getOperand(0), FIdx, MachinePointerInfo(),
7468 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7469 false, false, false, 0);
7472 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7473 SelectionDAG &DAG) const {
7475 SDNode *N = Op.getNode();
7477 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7478 "Unknown extract_vector_elt type");
7480 SDValue Value = N->getOperand(0);
7482 // The first part of this is like the store lowering except that we don't
7483 // need to track the chain.
7485 // The values are now known to be -1 (false) or 1 (true). To convert this
7486 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7487 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7488 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7490 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7491 // understand how to form the extending load.
7492 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7493 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7494 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7496 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7498 // Now convert to an integer and store.
7499 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7500 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7503 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7504 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7505 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7506 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7507 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7509 SDValue StoreChain = DAG.getEntryNode();
7510 SmallVector<SDValue, 2> Ops;
7511 Ops.push_back(StoreChain);
7512 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7513 Ops.push_back(Value);
7514 Ops.push_back(FIdx);
7516 SmallVector<EVT, 2> ValueVTs;
7517 ValueVTs.push_back(MVT::Other); // chain
7518 SDVTList VTs = DAG.getVTList(ValueVTs);
7520 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7521 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7523 // Extract the value requested.
7524 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7525 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7526 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7528 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7529 PtrInfo.getWithOffset(Offset),
7530 false, false, false, 0);
7532 if (!Subtarget.useCRBits())
7535 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7538 /// Lowering for QPX v4i1 loads
7539 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7540 SelectionDAG &DAG) const {
7542 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7543 SDValue LoadChain = LN->getChain();
7544 SDValue BasePtr = LN->getBasePtr();
7546 if (Op.getValueType() == MVT::v4f64 ||
7547 Op.getValueType() == MVT::v4f32) {
7548 EVT MemVT = LN->getMemoryVT();
7549 unsigned Alignment = LN->getAlignment();
7551 // If this load is properly aligned, then it is legal.
7552 if (Alignment >= MemVT.getStoreSize())
7555 EVT ScalarVT = Op.getValueType().getScalarType(),
7556 ScalarMemVT = MemVT.getScalarType();
7557 unsigned Stride = ScalarMemVT.getStoreSize();
7559 SmallVector<SDValue, 8> Vals, LoadChains;
7560 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7562 if (ScalarVT != ScalarMemVT)
7564 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7566 LN->getPointerInfo().getWithOffset(Idx*Stride),
7567 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7568 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7572 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7573 LN->getPointerInfo().getWithOffset(Idx*Stride),
7574 LN->isVolatile(), LN->isNonTemporal(),
7575 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7578 if (Idx == 0 && LN->isIndexed()) {
7579 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7580 "Unknown addressing mode on vector load");
7581 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7582 LN->getAddressingMode());
7585 Vals.push_back(Load);
7586 LoadChains.push_back(Load.getValue(1));
7588 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7589 DAG.getConstant(Stride, dl,
7590 BasePtr.getValueType()));
7593 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7594 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7595 Op.getValueType(), Vals);
7597 if (LN->isIndexed()) {
7598 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7599 return DAG.getMergeValues(RetOps, dl);
7602 SDValue RetOps[] = { Value, TF };
7603 return DAG.getMergeValues(RetOps, dl);
7606 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7607 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7609 // To lower v4i1 from a byte array, we load the byte elements of the
7610 // vector and then reuse the BUILD_VECTOR logic.
7612 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7613 for (unsigned i = 0; i < 4; ++i) {
7614 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7615 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7617 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7618 dl, MVT::i32, LoadChain, Idx,
7619 LN->getPointerInfo().getWithOffset(i),
7620 MVT::i8 /* memory type */,
7621 LN->isVolatile(), LN->isNonTemporal(),
7623 1 /* alignment */, LN->getAAInfo()));
7624 VectElmtChains.push_back(VectElmts[i].getValue(1));
7627 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7628 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7630 SDValue RVals[] = { Value, LoadChain };
7631 return DAG.getMergeValues(RVals, dl);
7634 /// Lowering for QPX v4i1 stores
7635 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7636 SelectionDAG &DAG) const {
7638 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7639 SDValue StoreChain = SN->getChain();
7640 SDValue BasePtr = SN->getBasePtr();
7641 SDValue Value = SN->getValue();
7643 if (Value.getValueType() == MVT::v4f64 ||
7644 Value.getValueType() == MVT::v4f32) {
7645 EVT MemVT = SN->getMemoryVT();
7646 unsigned Alignment = SN->getAlignment();
7648 // If this store is properly aligned, then it is legal.
7649 if (Alignment >= MemVT.getStoreSize())
7652 EVT ScalarVT = Value.getValueType().getScalarType(),
7653 ScalarMemVT = MemVT.getScalarType();
7654 unsigned Stride = ScalarMemVT.getStoreSize();
7656 SmallVector<SDValue, 8> Stores;
7657 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7658 SDValue Ex = DAG.getNode(
7659 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7660 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7662 if (ScalarVT != ScalarMemVT)
7664 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7665 SN->getPointerInfo().getWithOffset(Idx*Stride),
7666 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7667 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7670 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7671 SN->getPointerInfo().getWithOffset(Idx*Stride),
7672 SN->isVolatile(), SN->isNonTemporal(),
7673 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7675 if (Idx == 0 && SN->isIndexed()) {
7676 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7677 "Unknown addressing mode on vector store");
7678 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7679 SN->getAddressingMode());
7682 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7683 DAG.getConstant(Stride, dl,
7684 BasePtr.getValueType()));
7685 Stores.push_back(Store);
7688 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7690 if (SN->isIndexed()) {
7691 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7692 return DAG.getMergeValues(RetOps, dl);
7698 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7699 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7701 // The values are now known to be -1 (false) or 1 (true). To convert this
7702 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7703 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7704 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7706 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7707 // understand how to form the extending load.
7708 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7709 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7710 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7712 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7714 // Now convert to an integer and store.
7715 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7716 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7719 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7720 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7721 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7722 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7723 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7725 SmallVector<SDValue, 2> Ops;
7726 Ops.push_back(StoreChain);
7727 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7728 Ops.push_back(Value);
7729 Ops.push_back(FIdx);
7731 SmallVector<EVT, 2> ValueVTs;
7732 ValueVTs.push_back(MVT::Other); // chain
7733 SDVTList VTs = DAG.getVTList(ValueVTs);
7735 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7736 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7738 // Move data into the byte array.
7739 SmallVector<SDValue, 4> Loads, LoadChains;
7740 for (unsigned i = 0; i < 4; ++i) {
7741 unsigned Offset = 4*i;
7742 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7743 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7745 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7746 PtrInfo.getWithOffset(Offset),
7747 false, false, false, 0));
7748 LoadChains.push_back(Loads[i].getValue(1));
7751 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7753 SmallVector<SDValue, 4> Stores;
7754 for (unsigned i = 0; i < 4; ++i) {
7755 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7756 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7758 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7759 SN->getPointerInfo().getWithOffset(i),
7760 MVT::i8 /* memory type */,
7761 SN->isNonTemporal(), SN->isVolatile(),
7762 1 /* alignment */, SN->getAAInfo()));
7765 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7770 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7772 if (Op.getValueType() == MVT::v4i32) {
7773 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7775 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7776 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7778 SDValue RHSSwap = // = vrlw RHS, 16
7779 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7781 // Shrinkify inputs to v8i16.
7782 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7783 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7784 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7786 // Low parts multiplied together, generating 32-bit results (we ignore the
7788 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7789 LHS, RHS, DAG, dl, MVT::v4i32);
7791 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7792 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7793 // Shift the high parts up 16 bits.
7794 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7796 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7797 } else if (Op.getValueType() == MVT::v8i16) {
7798 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7800 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7802 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7803 LHS, RHS, Zero, DAG, dl);
7804 } else if (Op.getValueType() == MVT::v16i8) {
7805 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7806 bool isLittleEndian = Subtarget.isLittleEndian();
7808 // Multiply the even 8-bit parts, producing 16-bit sums.
7809 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7810 LHS, RHS, DAG, dl, MVT::v8i16);
7811 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7813 // Multiply the odd 8-bit parts, producing 16-bit sums.
7814 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7815 LHS, RHS, DAG, dl, MVT::v8i16);
7816 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7818 // Merge the results together. Because vmuleub and vmuloub are
7819 // instructions with a big-endian bias, we must reverse the
7820 // element numbering and reverse the meaning of "odd" and "even"
7821 // when generating little endian code.
7823 for (unsigned i = 0; i != 8; ++i) {
7824 if (isLittleEndian) {
7826 Ops[i*2+1] = 2*i+16;
7829 Ops[i*2+1] = 2*i+1+16;
7833 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7835 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7837 llvm_unreachable("Unknown mul to lower!");
7841 /// LowerOperation - Provide custom lowering hooks for some operations.
7843 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7844 switch (Op.getOpcode()) {
7845 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7846 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7847 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7848 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7849 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7850 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7851 case ISD::SETCC: return LowerSETCC(Op, DAG);
7852 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7853 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7855 return LowerVASTART(Op, DAG, Subtarget);
7858 return LowerVAARG(Op, DAG, Subtarget);
7861 return LowerVACOPY(Op, DAG, Subtarget);
7863 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7864 case ISD::DYNAMIC_STACKALLOC:
7865 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7867 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7868 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7870 case ISD::LOAD: return LowerLOAD(Op, DAG);
7871 case ISD::STORE: return LowerSTORE(Op, DAG);
7872 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7873 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7874 case ISD::FP_TO_UINT:
7875 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7877 case ISD::UINT_TO_FP:
7878 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7879 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7881 // Lower 64-bit shifts.
7882 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7883 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7884 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7886 // Vector-related lowering.
7887 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7888 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7889 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7890 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7891 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7892 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7893 case ISD::MUL: return LowerMUL(Op, DAG);
7895 // For counter-based loop handling.
7896 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7898 // Frame & Return address.
7899 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7900 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7904 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7905 SmallVectorImpl<SDValue>&Results,
7906 SelectionDAG &DAG) const {
7908 switch (N->getOpcode()) {
7910 llvm_unreachable("Do not know how to custom type legalize this operation!");
7911 case ISD::READCYCLECOUNTER: {
7912 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7913 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7915 Results.push_back(RTB);
7916 Results.push_back(RTB.getValue(1));
7917 Results.push_back(RTB.getValue(2));
7920 case ISD::INTRINSIC_W_CHAIN: {
7921 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7922 Intrinsic::ppc_is_decremented_ctr_nonzero)
7925 assert(N->getValueType(0) == MVT::i1 &&
7926 "Unexpected result type for CTR decrement intrinsic");
7927 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
7928 N->getValueType(0));
7929 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7930 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7933 Results.push_back(NewInt);
7934 Results.push_back(NewInt.getValue(1));
7938 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7941 EVT VT = N->getValueType(0);
7943 if (VT == MVT::i64) {
7944 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7946 Results.push_back(NewNode);
7947 Results.push_back(NewNode.getValue(1));
7951 case ISD::FP_ROUND_INREG: {
7952 assert(N->getValueType(0) == MVT::ppcf128);
7953 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7954 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7955 MVT::f64, N->getOperand(0),
7956 DAG.getIntPtrConstant(0, dl));
7957 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7958 MVT::f64, N->getOperand(0),
7959 DAG.getIntPtrConstant(1, dl));
7961 // Add the two halves of the long double in round-to-zero mode.
7962 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
7964 // We know the low half is about to be thrown away, so just use something
7966 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
7970 case ISD::FP_TO_SINT:
7971 case ISD::FP_TO_UINT:
7972 // LowerFP_TO_INT() can only handle f32 and f64.
7973 if (N->getOperand(0).getValueType() == MVT::ppcf128)
7975 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
7981 //===----------------------------------------------------------------------===//
7982 // Other Lowering Code
7983 //===----------------------------------------------------------------------===//
7985 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
7986 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7987 Function *Func = Intrinsic::getDeclaration(M, Id);
7988 return Builder.CreateCall(Func, {});
7991 // The mappings for emitLeading/TrailingFence is taken from
7992 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
7993 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
7994 AtomicOrdering Ord, bool IsStore,
7995 bool IsLoad) const {
7996 if (Ord == SequentiallyConsistent)
7997 return callIntrinsic(Builder, Intrinsic::ppc_sync);
7998 if (isAtLeastRelease(Ord))
7999 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8003 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8004 AtomicOrdering Ord, bool IsStore,
8005 bool IsLoad) const {
8006 if (IsLoad && isAtLeastAcquire(Ord))
8007 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8008 // FIXME: this is too conservative, a dependent branch + isync is enough.
8009 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8010 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8011 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8016 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8017 unsigned AtomicSize,
8018 unsigned BinOpcode) const {
8019 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8020 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8022 auto LoadMnemonic = PPC::LDARX;
8023 auto StoreMnemonic = PPC::STDCX;
8024 switch (AtomicSize) {
8026 llvm_unreachable("Unexpected size of atomic entity");
8028 LoadMnemonic = PPC::LBARX;
8029 StoreMnemonic = PPC::STBCX;
8030 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8033 LoadMnemonic = PPC::LHARX;
8034 StoreMnemonic = PPC::STHCX;
8035 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8038 LoadMnemonic = PPC::LWARX;
8039 StoreMnemonic = PPC::STWCX;
8042 LoadMnemonic = PPC::LDARX;
8043 StoreMnemonic = PPC::STDCX;
8047 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8048 MachineFunction *F = BB->getParent();
8049 MachineFunction::iterator It = BB;
8052 unsigned dest = MI->getOperand(0).getReg();
8053 unsigned ptrA = MI->getOperand(1).getReg();
8054 unsigned ptrB = MI->getOperand(2).getReg();
8055 unsigned incr = MI->getOperand(3).getReg();
8056 DebugLoc dl = MI->getDebugLoc();
8058 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8059 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8060 F->insert(It, loopMBB);
8061 F->insert(It, exitMBB);
8062 exitMBB->splice(exitMBB->begin(), BB,
8063 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8064 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8066 MachineRegisterInfo &RegInfo = F->getRegInfo();
8067 unsigned TmpReg = (!BinOpcode) ? incr :
8068 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8069 : &PPC::GPRCRegClass);
8073 // fallthrough --> loopMBB
8074 BB->addSuccessor(loopMBB);
8077 // l[wd]arx dest, ptr
8078 // add r0, dest, incr
8079 // st[wd]cx. r0, ptr
8081 // fallthrough --> exitMBB
8083 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8084 .addReg(ptrA).addReg(ptrB);
8086 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8087 BuildMI(BB, dl, TII->get(StoreMnemonic))
8088 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8089 BuildMI(BB, dl, TII->get(PPC::BCC))
8090 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8091 BB->addSuccessor(loopMBB);
8092 BB->addSuccessor(exitMBB);
8101 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8102 MachineBasicBlock *BB,
8103 bool is8bit, // operation
8104 unsigned BinOpcode) const {
8105 // If we support part-word atomic mnemonics, just use them
8106 if (Subtarget.hasPartwordAtomics())
8107 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8109 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8110 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8111 // In 64 bit mode we have to use 64 bits for addresses, even though the
8112 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8113 // registers without caring whether they're 32 or 64, but here we're
8114 // doing actual arithmetic on the addresses.
8115 bool is64bit = Subtarget.isPPC64();
8116 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8118 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8119 MachineFunction *F = BB->getParent();
8120 MachineFunction::iterator It = BB;
8123 unsigned dest = MI->getOperand(0).getReg();
8124 unsigned ptrA = MI->getOperand(1).getReg();
8125 unsigned ptrB = MI->getOperand(2).getReg();
8126 unsigned incr = MI->getOperand(3).getReg();
8127 DebugLoc dl = MI->getDebugLoc();
8129 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8130 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8131 F->insert(It, loopMBB);
8132 F->insert(It, exitMBB);
8133 exitMBB->splice(exitMBB->begin(), BB,
8134 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8135 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8137 MachineRegisterInfo &RegInfo = F->getRegInfo();
8138 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8139 : &PPC::GPRCRegClass;
8140 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8141 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8142 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8143 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8144 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8145 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8146 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8147 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8148 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8149 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8150 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8152 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8156 // fallthrough --> loopMBB
8157 BB->addSuccessor(loopMBB);
8159 // The 4-byte load must be aligned, while a char or short may be
8160 // anywhere in the word. Hence all this nasty bookkeeping code.
8161 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8162 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8163 // xori shift, shift1, 24 [16]
8164 // rlwinm ptr, ptr1, 0, 0, 29
8165 // slw incr2, incr, shift
8166 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8167 // slw mask, mask2, shift
8169 // lwarx tmpDest, ptr
8170 // add tmp, tmpDest, incr2
8171 // andc tmp2, tmpDest, mask
8172 // and tmp3, tmp, mask
8173 // or tmp4, tmp3, tmp2
8176 // fallthrough --> exitMBB
8177 // srw dest, tmpDest, shift
8178 if (ptrA != ZeroReg) {
8179 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8180 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8181 .addReg(ptrA).addReg(ptrB);
8185 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8186 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8187 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8188 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8190 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8191 .addReg(Ptr1Reg).addImm(0).addImm(61);
8193 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8194 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8195 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8196 .addReg(incr).addReg(ShiftReg);
8198 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8200 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8201 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8203 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8204 .addReg(Mask2Reg).addReg(ShiftReg);
8207 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8208 .addReg(ZeroReg).addReg(PtrReg);
8210 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8211 .addReg(Incr2Reg).addReg(TmpDestReg);
8212 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8213 .addReg(TmpDestReg).addReg(MaskReg);
8214 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8215 .addReg(TmpReg).addReg(MaskReg);
8216 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8217 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8218 BuildMI(BB, dl, TII->get(PPC::STWCX))
8219 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8220 BuildMI(BB, dl, TII->get(PPC::BCC))
8221 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8222 BB->addSuccessor(loopMBB);
8223 BB->addSuccessor(exitMBB);
8228 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8233 llvm::MachineBasicBlock*
8234 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8235 MachineBasicBlock *MBB) const {
8236 DebugLoc DL = MI->getDebugLoc();
8237 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8239 MachineFunction *MF = MBB->getParent();
8240 MachineRegisterInfo &MRI = MF->getRegInfo();
8242 const BasicBlock *BB = MBB->getBasicBlock();
8243 MachineFunction::iterator I = MBB;
8247 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8248 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8250 unsigned DstReg = MI->getOperand(0).getReg();
8251 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8252 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8253 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8254 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8256 MVT PVT = getPointerTy(MF->getDataLayout());
8257 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8258 "Invalid Pointer Size!");
8259 // For v = setjmp(buf), we generate
8262 // SjLjSetup mainMBB
8268 // buf[LabelOffset] = LR
8272 // v = phi(main, restore)
8275 MachineBasicBlock *thisMBB = MBB;
8276 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8277 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8278 MF->insert(I, mainMBB);
8279 MF->insert(I, sinkMBB);
8281 MachineInstrBuilder MIB;
8283 // Transfer the remainder of BB and its successor edges to sinkMBB.
8284 sinkMBB->splice(sinkMBB->begin(), MBB,
8285 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8286 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8288 // Note that the structure of the jmp_buf used here is not compatible
8289 // with that used by libc, and is not designed to be. Specifically, it
8290 // stores only those 'reserved' registers that LLVM does not otherwise
8291 // understand how to spill. Also, by convention, by the time this
8292 // intrinsic is called, Clang has already stored the frame address in the
8293 // first slot of the buffer and stack address in the third. Following the
8294 // X86 target code, we'll store the jump address in the second slot. We also
8295 // need to save the TOC pointer (R2) to handle jumps between shared
8296 // libraries, and that will be stored in the fourth slot. The thread
8297 // identifier (R13) is not affected.
8300 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8301 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8302 const int64_t BPOffset = 4 * PVT.getStoreSize();
8304 // Prepare IP either in reg.
8305 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8306 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8307 unsigned BufReg = MI->getOperand(1).getReg();
8309 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8310 setUsesTOCBasePtr(*MBB->getParent());
8311 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8315 MIB.setMemRefs(MMOBegin, MMOEnd);
8318 // Naked functions never have a base pointer, and so we use r1. For all
8319 // other functions, this decision must be delayed until during PEI.
8321 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8322 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8324 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8326 MIB = BuildMI(*thisMBB, MI, DL,
8327 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8331 MIB.setMemRefs(MMOBegin, MMOEnd);
8334 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8335 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8336 MIB.addRegMask(TRI->getNoPreservedMask());
8338 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8340 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8342 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8344 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8345 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8350 BuildMI(mainMBB, DL,
8351 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8354 if (Subtarget.isPPC64()) {
8355 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8357 .addImm(LabelOffset)
8360 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8362 .addImm(LabelOffset)
8366 MIB.setMemRefs(MMOBegin, MMOEnd);
8368 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8369 mainMBB->addSuccessor(sinkMBB);
8372 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8373 TII->get(PPC::PHI), DstReg)
8374 .addReg(mainDstReg).addMBB(mainMBB)
8375 .addReg(restoreDstReg).addMBB(thisMBB);
8377 MI->eraseFromParent();
8382 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8383 MachineBasicBlock *MBB) const {
8384 DebugLoc DL = MI->getDebugLoc();
8385 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8387 MachineFunction *MF = MBB->getParent();
8388 MachineRegisterInfo &MRI = MF->getRegInfo();
8391 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8392 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8394 MVT PVT = getPointerTy(MF->getDataLayout());
8395 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8396 "Invalid Pointer Size!");
8398 const TargetRegisterClass *RC =
8399 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8400 unsigned Tmp = MRI.createVirtualRegister(RC);
8401 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8402 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8403 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8407 : (Subtarget.isSVR4ABI() &&
8408 MF->getTarget().getRelocationModel() == Reloc::PIC_
8412 MachineInstrBuilder MIB;
8414 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8415 const int64_t SPOffset = 2 * PVT.getStoreSize();
8416 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8417 const int64_t BPOffset = 4 * PVT.getStoreSize();
8419 unsigned BufReg = MI->getOperand(0).getReg();
8421 // Reload FP (the jumped-to function may not have had a
8422 // frame pointer, and if so, then its r31 will be restored
8424 if (PVT == MVT::i64) {
8425 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8429 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8433 MIB.setMemRefs(MMOBegin, MMOEnd);
8436 if (PVT == MVT::i64) {
8437 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8438 .addImm(LabelOffset)
8441 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8442 .addImm(LabelOffset)
8445 MIB.setMemRefs(MMOBegin, MMOEnd);
8448 if (PVT == MVT::i64) {
8449 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8453 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8457 MIB.setMemRefs(MMOBegin, MMOEnd);
8460 if (PVT == MVT::i64) {
8461 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8465 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8469 MIB.setMemRefs(MMOBegin, MMOEnd);
8472 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8473 setUsesTOCBasePtr(*MBB->getParent());
8474 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8478 MIB.setMemRefs(MMOBegin, MMOEnd);
8482 BuildMI(*MBB, MI, DL,
8483 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8484 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8486 MI->eraseFromParent();
8491 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8492 MachineBasicBlock *BB) const {
8493 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8494 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8495 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8496 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8497 // Call lowering should have added an r2 operand to indicate a dependence
8498 // on the TOC base pointer value. It can't however, because there is no
8499 // way to mark the dependence as implicit there, and so the stackmap code
8500 // will confuse it with a regular operand. Instead, add the dependence
8502 setUsesTOCBasePtr(*BB->getParent());
8503 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8506 return emitPatchPoint(MI, BB);
8509 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8510 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8511 return emitEHSjLjSetJmp(MI, BB);
8512 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8513 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8514 return emitEHSjLjLongJmp(MI, BB);
8517 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8519 // To "insert" these instructions we actually have to insert their
8520 // control-flow patterns.
8521 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8522 MachineFunction::iterator It = BB;
8525 MachineFunction *F = BB->getParent();
8527 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8528 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8529 MI->getOpcode() == PPC::SELECT_I4 ||
8530 MI->getOpcode() == PPC::SELECT_I8)) {
8531 SmallVector<MachineOperand, 2> Cond;
8532 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8533 MI->getOpcode() == PPC::SELECT_CC_I8)
8534 Cond.push_back(MI->getOperand(4));
8536 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8537 Cond.push_back(MI->getOperand(1));
8539 DebugLoc dl = MI->getDebugLoc();
8540 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8541 Cond, MI->getOperand(2).getReg(),
8542 MI->getOperand(3).getReg());
8543 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8544 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8545 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8546 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8547 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8548 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8549 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8550 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8551 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8552 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8553 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8554 MI->getOpcode() == PPC::SELECT_I4 ||
8555 MI->getOpcode() == PPC::SELECT_I8 ||
8556 MI->getOpcode() == PPC::SELECT_F4 ||
8557 MI->getOpcode() == PPC::SELECT_F8 ||
8558 MI->getOpcode() == PPC::SELECT_QFRC ||
8559 MI->getOpcode() == PPC::SELECT_QSRC ||
8560 MI->getOpcode() == PPC::SELECT_QBRC ||
8561 MI->getOpcode() == PPC::SELECT_VRRC ||
8562 MI->getOpcode() == PPC::SELECT_VSFRC ||
8563 MI->getOpcode() == PPC::SELECT_VSSRC ||
8564 MI->getOpcode() == PPC::SELECT_VSRC) {
8565 // The incoming instruction knows the destination vreg to set, the
8566 // condition code register to branch on, the true/false values to
8567 // select between, and a branch opcode to use.
8572 // cmpTY ccX, r1, r2
8574 // fallthrough --> copy0MBB
8575 MachineBasicBlock *thisMBB = BB;
8576 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8577 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8578 DebugLoc dl = MI->getDebugLoc();
8579 F->insert(It, copy0MBB);
8580 F->insert(It, sinkMBB);
8582 // Transfer the remainder of BB and its successor edges to sinkMBB.
8583 sinkMBB->splice(sinkMBB->begin(), BB,
8584 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8585 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8587 // Next, add the true and fallthrough blocks as its successors.
8588 BB->addSuccessor(copy0MBB);
8589 BB->addSuccessor(sinkMBB);
8591 if (MI->getOpcode() == PPC::SELECT_I4 ||
8592 MI->getOpcode() == PPC::SELECT_I8 ||
8593 MI->getOpcode() == PPC::SELECT_F4 ||
8594 MI->getOpcode() == PPC::SELECT_F8 ||
8595 MI->getOpcode() == PPC::SELECT_QFRC ||
8596 MI->getOpcode() == PPC::SELECT_QSRC ||
8597 MI->getOpcode() == PPC::SELECT_QBRC ||
8598 MI->getOpcode() == PPC::SELECT_VRRC ||
8599 MI->getOpcode() == PPC::SELECT_VSFRC ||
8600 MI->getOpcode() == PPC::SELECT_VSSRC ||
8601 MI->getOpcode() == PPC::SELECT_VSRC) {
8602 BuildMI(BB, dl, TII->get(PPC::BC))
8603 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8605 unsigned SelectPred = MI->getOperand(4).getImm();
8606 BuildMI(BB, dl, TII->get(PPC::BCC))
8607 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8611 // %FalseValue = ...
8612 // # fallthrough to sinkMBB
8615 // Update machine-CFG edges
8616 BB->addSuccessor(sinkMBB);
8619 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8622 BuildMI(*BB, BB->begin(), dl,
8623 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8624 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8625 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8626 } else if (MI->getOpcode() == PPC::ReadTB) {
8627 // To read the 64-bit time-base register on a 32-bit target, we read the
8628 // two halves. Should the counter have wrapped while it was being read, we
8629 // need to try again.
8632 // mfspr Rx,TBU # load from TBU
8633 // mfspr Ry,TB # load from TB
8634 // mfspr Rz,TBU # load from TBU
8635 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8636 // bne readLoop # branch if they're not equal
8639 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8640 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8641 DebugLoc dl = MI->getDebugLoc();
8642 F->insert(It, readMBB);
8643 F->insert(It, sinkMBB);
8645 // Transfer the remainder of BB and its successor edges to sinkMBB.
8646 sinkMBB->splice(sinkMBB->begin(), BB,
8647 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8648 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8650 BB->addSuccessor(readMBB);
8653 MachineRegisterInfo &RegInfo = F->getRegInfo();
8654 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8655 unsigned LoReg = MI->getOperand(0).getReg();
8656 unsigned HiReg = MI->getOperand(1).getReg();
8658 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8659 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8660 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8662 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8664 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8665 .addReg(HiReg).addReg(ReadAgainReg);
8666 BuildMI(BB, dl, TII->get(PPC::BCC))
8667 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8669 BB->addSuccessor(readMBB);
8670 BB->addSuccessor(sinkMBB);
8672 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8673 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8674 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8675 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8676 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8677 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8678 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8679 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8681 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8682 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8683 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8684 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8685 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8686 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8687 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8688 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8690 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8691 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8692 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8693 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8694 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8695 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8696 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8697 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8699 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8700 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8701 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8702 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8703 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8704 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8705 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8706 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8708 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8709 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8710 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8711 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8712 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8713 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8714 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8715 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8717 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8718 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8719 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8720 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8721 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8722 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8723 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8724 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8726 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8727 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8728 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8729 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8730 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8731 BB = EmitAtomicBinary(MI, BB, 4, 0);
8732 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8733 BB = EmitAtomicBinary(MI, BB, 8, 0);
8735 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8736 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8737 (Subtarget.hasPartwordAtomics() &&
8738 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8739 (Subtarget.hasPartwordAtomics() &&
8740 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8741 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8743 auto LoadMnemonic = PPC::LDARX;
8744 auto StoreMnemonic = PPC::STDCX;
8745 switch(MI->getOpcode()) {
8747 llvm_unreachable("Compare and swap of unknown size");
8748 case PPC::ATOMIC_CMP_SWAP_I8:
8749 LoadMnemonic = PPC::LBARX;
8750 StoreMnemonic = PPC::STBCX;
8751 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8753 case PPC::ATOMIC_CMP_SWAP_I16:
8754 LoadMnemonic = PPC::LHARX;
8755 StoreMnemonic = PPC::STHCX;
8756 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8758 case PPC::ATOMIC_CMP_SWAP_I32:
8759 LoadMnemonic = PPC::LWARX;
8760 StoreMnemonic = PPC::STWCX;
8762 case PPC::ATOMIC_CMP_SWAP_I64:
8763 LoadMnemonic = PPC::LDARX;
8764 StoreMnemonic = PPC::STDCX;
8767 unsigned dest = MI->getOperand(0).getReg();
8768 unsigned ptrA = MI->getOperand(1).getReg();
8769 unsigned ptrB = MI->getOperand(2).getReg();
8770 unsigned oldval = MI->getOperand(3).getReg();
8771 unsigned newval = MI->getOperand(4).getReg();
8772 DebugLoc dl = MI->getDebugLoc();
8774 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8775 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8776 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8777 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8778 F->insert(It, loop1MBB);
8779 F->insert(It, loop2MBB);
8780 F->insert(It, midMBB);
8781 F->insert(It, exitMBB);
8782 exitMBB->splice(exitMBB->begin(), BB,
8783 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8784 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8788 // fallthrough --> loopMBB
8789 BB->addSuccessor(loop1MBB);
8792 // l[bhwd]arx dest, ptr
8793 // cmp[wd] dest, oldval
8796 // st[bhwd]cx. newval, ptr
8800 // st[bhwd]cx. dest, ptr
8803 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8804 .addReg(ptrA).addReg(ptrB);
8805 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8806 .addReg(oldval).addReg(dest);
8807 BuildMI(BB, dl, TII->get(PPC::BCC))
8808 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8809 BB->addSuccessor(loop2MBB);
8810 BB->addSuccessor(midMBB);
8813 BuildMI(BB, dl, TII->get(StoreMnemonic))
8814 .addReg(newval).addReg(ptrA).addReg(ptrB);
8815 BuildMI(BB, dl, TII->get(PPC::BCC))
8816 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8817 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8818 BB->addSuccessor(loop1MBB);
8819 BB->addSuccessor(exitMBB);
8822 BuildMI(BB, dl, TII->get(StoreMnemonic))
8823 .addReg(dest).addReg(ptrA).addReg(ptrB);
8824 BB->addSuccessor(exitMBB);
8829 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8830 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8831 // We must use 64-bit registers for addresses when targeting 64-bit,
8832 // since we're actually doing arithmetic on them. Other registers
8834 bool is64bit = Subtarget.isPPC64();
8835 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8837 unsigned dest = MI->getOperand(0).getReg();
8838 unsigned ptrA = MI->getOperand(1).getReg();
8839 unsigned ptrB = MI->getOperand(2).getReg();
8840 unsigned oldval = MI->getOperand(3).getReg();
8841 unsigned newval = MI->getOperand(4).getReg();
8842 DebugLoc dl = MI->getDebugLoc();
8844 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8845 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8846 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8847 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8848 F->insert(It, loop1MBB);
8849 F->insert(It, loop2MBB);
8850 F->insert(It, midMBB);
8851 F->insert(It, exitMBB);
8852 exitMBB->splice(exitMBB->begin(), BB,
8853 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8854 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8856 MachineRegisterInfo &RegInfo = F->getRegInfo();
8857 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8858 : &PPC::GPRCRegClass;
8859 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8860 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8861 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8862 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8863 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8864 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8865 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8866 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8867 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8868 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8869 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8870 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8871 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8873 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8874 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8877 // fallthrough --> loopMBB
8878 BB->addSuccessor(loop1MBB);
8880 // The 4-byte load must be aligned, while a char or short may be
8881 // anywhere in the word. Hence all this nasty bookkeeping code.
8882 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8883 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8884 // xori shift, shift1, 24 [16]
8885 // rlwinm ptr, ptr1, 0, 0, 29
8886 // slw newval2, newval, shift
8887 // slw oldval2, oldval,shift
8888 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8889 // slw mask, mask2, shift
8890 // and newval3, newval2, mask
8891 // and oldval3, oldval2, mask
8893 // lwarx tmpDest, ptr
8894 // and tmp, tmpDest, mask
8895 // cmpw tmp, oldval3
8898 // andc tmp2, tmpDest, mask
8899 // or tmp4, tmp2, newval3
8904 // stwcx. tmpDest, ptr
8906 // srw dest, tmpDest, shift
8907 if (ptrA != ZeroReg) {
8908 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8909 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8910 .addReg(ptrA).addReg(ptrB);
8914 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8915 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8916 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8917 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8919 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8920 .addReg(Ptr1Reg).addImm(0).addImm(61);
8922 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8923 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8924 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8925 .addReg(newval).addReg(ShiftReg);
8926 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8927 .addReg(oldval).addReg(ShiftReg);
8929 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8931 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8932 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8933 .addReg(Mask3Reg).addImm(65535);
8935 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8936 .addReg(Mask2Reg).addReg(ShiftReg);
8937 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8938 .addReg(NewVal2Reg).addReg(MaskReg);
8939 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8940 .addReg(OldVal2Reg).addReg(MaskReg);
8943 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8944 .addReg(ZeroReg).addReg(PtrReg);
8945 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8946 .addReg(TmpDestReg).addReg(MaskReg);
8947 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8948 .addReg(TmpReg).addReg(OldVal3Reg);
8949 BuildMI(BB, dl, TII->get(PPC::BCC))
8950 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8951 BB->addSuccessor(loop2MBB);
8952 BB->addSuccessor(midMBB);
8955 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8956 .addReg(TmpDestReg).addReg(MaskReg);
8957 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8958 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8959 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8960 .addReg(ZeroReg).addReg(PtrReg);
8961 BuildMI(BB, dl, TII->get(PPC::BCC))
8962 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8963 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8964 BB->addSuccessor(loop1MBB);
8965 BB->addSuccessor(exitMBB);
8968 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
8969 .addReg(ZeroReg).addReg(PtrReg);
8970 BB->addSuccessor(exitMBB);
8975 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
8977 } else if (MI->getOpcode() == PPC::FADDrtz) {
8978 // This pseudo performs an FADD with rounding mode temporarily forced
8979 // to round-to-zero. We emit this via custom inserter since the FPSCR
8980 // is not modeled at the SelectionDAG level.
8981 unsigned Dest = MI->getOperand(0).getReg();
8982 unsigned Src1 = MI->getOperand(1).getReg();
8983 unsigned Src2 = MI->getOperand(2).getReg();
8984 DebugLoc dl = MI->getDebugLoc();
8986 MachineRegisterInfo &RegInfo = F->getRegInfo();
8987 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
8989 // Save FPSCR value.
8990 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
8992 // Set rounding mode to round-to-zero.
8993 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
8994 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
8996 // Perform addition.
8997 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
8999 // Restore FPSCR value.
9000 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9001 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9002 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9003 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9004 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9005 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9006 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9007 PPC::ANDIo8 : PPC::ANDIo;
9008 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9009 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9011 MachineRegisterInfo &RegInfo = F->getRegInfo();
9012 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9013 &PPC::GPRCRegClass :
9014 &PPC::G8RCRegClass);
9016 DebugLoc dl = MI->getDebugLoc();
9017 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9018 .addReg(MI->getOperand(1).getReg()).addImm(1);
9019 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9020 MI->getOperand(0).getReg())
9021 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9022 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9023 DebugLoc Dl = MI->getDebugLoc();
9024 MachineRegisterInfo &RegInfo = F->getRegInfo();
9025 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9026 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9029 llvm_unreachable("Unexpected instr type to insert");
9032 MI->eraseFromParent(); // The pseudo instruction is gone now.
9036 //===----------------------------------------------------------------------===//
9037 // Target Optimization Hooks
9038 //===----------------------------------------------------------------------===//
9040 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9041 DAGCombinerInfo &DCI,
9042 unsigned &RefinementSteps,
9043 bool &UseOneConstNR) const {
9044 EVT VT = Operand.getValueType();
9045 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9046 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9047 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9048 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9049 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9050 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9051 // Convergence is quadratic, so we essentially double the number of digits
9052 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9053 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9054 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9055 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9056 if (VT.getScalarType() == MVT::f64)
9058 UseOneConstNR = true;
9059 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9064 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9065 DAGCombinerInfo &DCI,
9066 unsigned &RefinementSteps) const {
9067 EVT VT = Operand.getValueType();
9068 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9069 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9070 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9071 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9072 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9073 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9074 // Convergence is quadratic, so we essentially double the number of digits
9075 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9076 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9077 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9078 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9079 if (VT.getScalarType() == MVT::f64)
9081 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9086 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9087 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9088 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9089 // enabled for division), this functionality is redundant with the default
9090 // combiner logic (once the division -> reciprocal/multiply transformation
9091 // has taken place). As a result, this matters more for older cores than for
9094 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9095 // reciprocal if there are two or more FDIVs (for embedded cores with only
9096 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9097 switch (Subtarget.getDarwinDirective()) {
9099 return NumUsers > 2;
9102 case PPC::DIR_E500mc:
9103 case PPC::DIR_E5500:
9104 return NumUsers > 1;
9108 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9109 unsigned Bytes, int Dist,
9110 SelectionDAG &DAG) {
9111 if (VT.getSizeInBits() / 8 != Bytes)
9114 SDValue BaseLoc = Base->getBasePtr();
9115 if (Loc.getOpcode() == ISD::FrameIndex) {
9116 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9118 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9119 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9120 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9121 int FS = MFI->getObjectSize(FI);
9122 int BFS = MFI->getObjectSize(BFI);
9123 if (FS != BFS || FS != (int)Bytes) return false;
9124 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9128 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
9129 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
9132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9133 const GlobalValue *GV1 = nullptr;
9134 const GlobalValue *GV2 = nullptr;
9135 int64_t Offset1 = 0;
9136 int64_t Offset2 = 0;
9137 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9138 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9139 if (isGA1 && isGA2 && GV1 == GV2)
9140 return Offset1 == (Offset2 + Dist*Bytes);
9144 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9145 // not enforce equality of the chain operands.
9146 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9147 unsigned Bytes, int Dist,
9148 SelectionDAG &DAG) {
9149 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9150 EVT VT = LS->getMemoryVT();
9151 SDValue Loc = LS->getBasePtr();
9152 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9155 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9157 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9158 default: return false;
9159 case Intrinsic::ppc_qpx_qvlfd:
9160 case Intrinsic::ppc_qpx_qvlfda:
9163 case Intrinsic::ppc_qpx_qvlfs:
9164 case Intrinsic::ppc_qpx_qvlfsa:
9167 case Intrinsic::ppc_qpx_qvlfcd:
9168 case Intrinsic::ppc_qpx_qvlfcda:
9171 case Intrinsic::ppc_qpx_qvlfcs:
9172 case Intrinsic::ppc_qpx_qvlfcsa:
9175 case Intrinsic::ppc_qpx_qvlfiwa:
9176 case Intrinsic::ppc_qpx_qvlfiwz:
9177 case Intrinsic::ppc_altivec_lvx:
9178 case Intrinsic::ppc_altivec_lvxl:
9179 case Intrinsic::ppc_vsx_lxvw4x:
9182 case Intrinsic::ppc_vsx_lxvd2x:
9185 case Intrinsic::ppc_altivec_lvebx:
9188 case Intrinsic::ppc_altivec_lvehx:
9191 case Intrinsic::ppc_altivec_lvewx:
9196 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9199 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9201 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9202 default: return false;
9203 case Intrinsic::ppc_qpx_qvstfd:
9204 case Intrinsic::ppc_qpx_qvstfda:
9207 case Intrinsic::ppc_qpx_qvstfs:
9208 case Intrinsic::ppc_qpx_qvstfsa:
9211 case Intrinsic::ppc_qpx_qvstfcd:
9212 case Intrinsic::ppc_qpx_qvstfcda:
9215 case Intrinsic::ppc_qpx_qvstfcs:
9216 case Intrinsic::ppc_qpx_qvstfcsa:
9219 case Intrinsic::ppc_qpx_qvstfiw:
9220 case Intrinsic::ppc_qpx_qvstfiwa:
9221 case Intrinsic::ppc_altivec_stvx:
9222 case Intrinsic::ppc_altivec_stvxl:
9223 case Intrinsic::ppc_vsx_stxvw4x:
9226 case Intrinsic::ppc_vsx_stxvd2x:
9229 case Intrinsic::ppc_altivec_stvebx:
9232 case Intrinsic::ppc_altivec_stvehx:
9235 case Intrinsic::ppc_altivec_stvewx:
9240 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9246 // Return true is there is a nearyby consecutive load to the one provided
9247 // (regardless of alignment). We search up and down the chain, looking though
9248 // token factors and other loads (but nothing else). As a result, a true result
9249 // indicates that it is safe to create a new consecutive load adjacent to the
9251 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9252 SDValue Chain = LD->getChain();
9253 EVT VT = LD->getMemoryVT();
9255 SmallSet<SDNode *, 16> LoadRoots;
9256 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9257 SmallSet<SDNode *, 16> Visited;
9259 // First, search up the chain, branching to follow all token-factor operands.
9260 // If we find a consecutive load, then we're done, otherwise, record all
9261 // nodes just above the top-level loads and token factors.
9262 while (!Queue.empty()) {
9263 SDNode *ChainNext = Queue.pop_back_val();
9264 if (!Visited.insert(ChainNext).second)
9267 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9268 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9271 if (!Visited.count(ChainLD->getChain().getNode()))
9272 Queue.push_back(ChainLD->getChain().getNode());
9273 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9274 for (const SDUse &O : ChainNext->ops())
9275 if (!Visited.count(O.getNode()))
9276 Queue.push_back(O.getNode());
9278 LoadRoots.insert(ChainNext);
9281 // Second, search down the chain, starting from the top-level nodes recorded
9282 // in the first phase. These top-level nodes are the nodes just above all
9283 // loads and token factors. Starting with their uses, recursively look though
9284 // all loads (just the chain uses) and token factors to find a consecutive
9289 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9290 IE = LoadRoots.end(); I != IE; ++I) {
9291 Queue.push_back(*I);
9293 while (!Queue.empty()) {
9294 SDNode *LoadRoot = Queue.pop_back_val();
9295 if (!Visited.insert(LoadRoot).second)
9298 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9299 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9302 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9303 UE = LoadRoot->use_end(); UI != UE; ++UI)
9304 if (((isa<MemSDNode>(*UI) &&
9305 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9306 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9307 Queue.push_back(*UI);
9314 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9315 DAGCombinerInfo &DCI) const {
9316 SelectionDAG &DAG = DCI.DAG;
9319 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9320 // If we're tracking CR bits, we need to be careful that we don't have:
9321 // trunc(binary-ops(zext(x), zext(y)))
9323 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9324 // such that we're unnecessarily moving things into GPRs when it would be
9325 // better to keep them in CR bits.
9327 // Note that trunc here can be an actual i1 trunc, or can be the effective
9328 // truncation that comes from a setcc or select_cc.
9329 if (N->getOpcode() == ISD::TRUNCATE &&
9330 N->getValueType(0) != MVT::i1)
9333 if (N->getOperand(0).getValueType() != MVT::i32 &&
9334 N->getOperand(0).getValueType() != MVT::i64)
9337 if (N->getOpcode() == ISD::SETCC ||
9338 N->getOpcode() == ISD::SELECT_CC) {
9339 // If we're looking at a comparison, then we need to make sure that the
9340 // high bits (all except for the first) don't matter the result.
9342 cast<CondCodeSDNode>(N->getOperand(
9343 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9344 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9346 if (ISD::isSignedIntSetCC(CC)) {
9347 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9348 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9350 } else if (ISD::isUnsignedIntSetCC(CC)) {
9351 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9352 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9353 !DAG.MaskedValueIsZero(N->getOperand(1),
9354 APInt::getHighBitsSet(OpBits, OpBits-1)))
9357 // This is neither a signed nor an unsigned comparison, just make sure
9358 // that the high bits are equal.
9359 APInt Op1Zero, Op1One;
9360 APInt Op2Zero, Op2One;
9361 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9362 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9364 // We don't really care about what is known about the first bit (if
9365 // anything), so clear it in all masks prior to comparing them.
9366 Op1Zero.clearBit(0); Op1One.clearBit(0);
9367 Op2Zero.clearBit(0); Op2One.clearBit(0);
9369 if (Op1Zero != Op2Zero || Op1One != Op2One)
9374 // We now know that the higher-order bits are irrelevant, we just need to
9375 // make sure that all of the intermediate operations are bit operations, and
9376 // all inputs are extensions.
9377 if (N->getOperand(0).getOpcode() != ISD::AND &&
9378 N->getOperand(0).getOpcode() != ISD::OR &&
9379 N->getOperand(0).getOpcode() != ISD::XOR &&
9380 N->getOperand(0).getOpcode() != ISD::SELECT &&
9381 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9382 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9383 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9384 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9385 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9388 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9389 N->getOperand(1).getOpcode() != ISD::AND &&
9390 N->getOperand(1).getOpcode() != ISD::OR &&
9391 N->getOperand(1).getOpcode() != ISD::XOR &&
9392 N->getOperand(1).getOpcode() != ISD::SELECT &&
9393 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9394 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9395 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9396 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9397 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9400 SmallVector<SDValue, 4> Inputs;
9401 SmallVector<SDValue, 8> BinOps, PromOps;
9402 SmallPtrSet<SDNode *, 16> Visited;
9404 for (unsigned i = 0; i < 2; ++i) {
9405 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9406 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9407 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9408 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9409 isa<ConstantSDNode>(N->getOperand(i)))
9410 Inputs.push_back(N->getOperand(i));
9412 BinOps.push_back(N->getOperand(i));
9414 if (N->getOpcode() == ISD::TRUNCATE)
9418 // Visit all inputs, collect all binary operations (and, or, xor and
9419 // select) that are all fed by extensions.
9420 while (!BinOps.empty()) {
9421 SDValue BinOp = BinOps.back();
9424 if (!Visited.insert(BinOp.getNode()).second)
9427 PromOps.push_back(BinOp);
9429 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9430 // The condition of the select is not promoted.
9431 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9433 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9436 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9437 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9438 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9439 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9440 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9441 Inputs.push_back(BinOp.getOperand(i));
9442 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9443 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9444 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9445 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9446 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9447 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9448 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9449 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9450 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9451 BinOps.push_back(BinOp.getOperand(i));
9453 // We have an input that is not an extension or another binary
9454 // operation; we'll abort this transformation.
9460 // Make sure that this is a self-contained cluster of operations (which
9461 // is not quite the same thing as saying that everything has only one
9463 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9464 if (isa<ConstantSDNode>(Inputs[i]))
9467 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9468 UE = Inputs[i].getNode()->use_end();
9471 if (User != N && !Visited.count(User))
9474 // Make sure that we're not going to promote the non-output-value
9475 // operand(s) or SELECT or SELECT_CC.
9476 // FIXME: Although we could sometimes handle this, and it does occur in
9477 // practice that one of the condition inputs to the select is also one of
9478 // the outputs, we currently can't deal with this.
9479 if (User->getOpcode() == ISD::SELECT) {
9480 if (User->getOperand(0) == Inputs[i])
9482 } else if (User->getOpcode() == ISD::SELECT_CC) {
9483 if (User->getOperand(0) == Inputs[i] ||
9484 User->getOperand(1) == Inputs[i])
9490 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9491 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9492 UE = PromOps[i].getNode()->use_end();
9495 if (User != N && !Visited.count(User))
9498 // Make sure that we're not going to promote the non-output-value
9499 // operand(s) or SELECT or SELECT_CC.
9500 // FIXME: Although we could sometimes handle this, and it does occur in
9501 // practice that one of the condition inputs to the select is also one of
9502 // the outputs, we currently can't deal with this.
9503 if (User->getOpcode() == ISD::SELECT) {
9504 if (User->getOperand(0) == PromOps[i])
9506 } else if (User->getOpcode() == ISD::SELECT_CC) {
9507 if (User->getOperand(0) == PromOps[i] ||
9508 User->getOperand(1) == PromOps[i])
9514 // Replace all inputs with the extension operand.
9515 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9516 // Constants may have users outside the cluster of to-be-promoted nodes,
9517 // and so we need to replace those as we do the promotions.
9518 if (isa<ConstantSDNode>(Inputs[i]))
9521 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9524 // Replace all operations (these are all the same, but have a different
9525 // (i1) return type). DAG.getNode will validate that the types of
9526 // a binary operator match, so go through the list in reverse so that
9527 // we've likely promoted both operands first. Any intermediate truncations or
9528 // extensions disappear.
9529 while (!PromOps.empty()) {
9530 SDValue PromOp = PromOps.back();
9533 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9534 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9535 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9536 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9537 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9538 PromOp.getOperand(0).getValueType() != MVT::i1) {
9539 // The operand is not yet ready (see comment below).
9540 PromOps.insert(PromOps.begin(), PromOp);
9544 SDValue RepValue = PromOp.getOperand(0);
9545 if (isa<ConstantSDNode>(RepValue))
9546 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9548 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9553 switch (PromOp.getOpcode()) {
9554 default: C = 0; break;
9555 case ISD::SELECT: C = 1; break;
9556 case ISD::SELECT_CC: C = 2; break;
9559 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9560 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9561 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9562 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9563 // The to-be-promoted operands of this node have not yet been
9564 // promoted (this should be rare because we're going through the
9565 // list backward, but if one of the operands has several users in
9566 // this cluster of to-be-promoted nodes, it is possible).
9567 PromOps.insert(PromOps.begin(), PromOp);
9571 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9572 PromOp.getNode()->op_end());
9574 // If there are any constant inputs, make sure they're replaced now.
9575 for (unsigned i = 0; i < 2; ++i)
9576 if (isa<ConstantSDNode>(Ops[C+i]))
9577 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9579 DAG.ReplaceAllUsesOfValueWith(PromOp,
9580 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9583 // Now we're left with the initial truncation itself.
9584 if (N->getOpcode() == ISD::TRUNCATE)
9585 return N->getOperand(0);
9587 // Otherwise, this is a comparison. The operands to be compared have just
9588 // changed type (to i1), but everything else is the same.
9589 return SDValue(N, 0);
9592 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9593 DAGCombinerInfo &DCI) const {
9594 SelectionDAG &DAG = DCI.DAG;
9597 // If we're tracking CR bits, we need to be careful that we don't have:
9598 // zext(binary-ops(trunc(x), trunc(y)))
9600 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9601 // such that we're unnecessarily moving things into CR bits that can more
9602 // efficiently stay in GPRs. Note that if we're not certain that the high
9603 // bits are set as required by the final extension, we still may need to do
9604 // some masking to get the proper behavior.
9606 // This same functionality is important on PPC64 when dealing with
9607 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9608 // the return values of functions. Because it is so similar, it is handled
9611 if (N->getValueType(0) != MVT::i32 &&
9612 N->getValueType(0) != MVT::i64)
9615 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9616 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9619 if (N->getOperand(0).getOpcode() != ISD::AND &&
9620 N->getOperand(0).getOpcode() != ISD::OR &&
9621 N->getOperand(0).getOpcode() != ISD::XOR &&
9622 N->getOperand(0).getOpcode() != ISD::SELECT &&
9623 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9626 SmallVector<SDValue, 4> Inputs;
9627 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9628 SmallPtrSet<SDNode *, 16> Visited;
9630 // Visit all inputs, collect all binary operations (and, or, xor and
9631 // select) that are all fed by truncations.
9632 while (!BinOps.empty()) {
9633 SDValue BinOp = BinOps.back();
9636 if (!Visited.insert(BinOp.getNode()).second)
9639 PromOps.push_back(BinOp);
9641 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9642 // The condition of the select is not promoted.
9643 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9645 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9648 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9649 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9650 Inputs.push_back(BinOp.getOperand(i));
9651 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9652 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9653 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9654 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9655 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9656 BinOps.push_back(BinOp.getOperand(i));
9658 // We have an input that is not a truncation or another binary
9659 // operation; we'll abort this transformation.
9665 // The operands of a select that must be truncated when the select is
9666 // promoted because the operand is actually part of the to-be-promoted set.
9667 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9669 // Make sure that this is a self-contained cluster of operations (which
9670 // is not quite the same thing as saying that everything has only one
9672 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9673 if (isa<ConstantSDNode>(Inputs[i]))
9676 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9677 UE = Inputs[i].getNode()->use_end();
9680 if (User != N && !Visited.count(User))
9683 // If we're going to promote the non-output-value operand(s) or SELECT or
9684 // SELECT_CC, record them for truncation.
9685 if (User->getOpcode() == ISD::SELECT) {
9686 if (User->getOperand(0) == Inputs[i])
9687 SelectTruncOp[0].insert(std::make_pair(User,
9688 User->getOperand(0).getValueType()));
9689 } else if (User->getOpcode() == ISD::SELECT_CC) {
9690 if (User->getOperand(0) == Inputs[i])
9691 SelectTruncOp[0].insert(std::make_pair(User,
9692 User->getOperand(0).getValueType()));
9693 if (User->getOperand(1) == Inputs[i])
9694 SelectTruncOp[1].insert(std::make_pair(User,
9695 User->getOperand(1).getValueType()));
9700 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9701 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9702 UE = PromOps[i].getNode()->use_end();
9705 if (User != N && !Visited.count(User))
9708 // If we're going to promote the non-output-value operand(s) or SELECT or
9709 // SELECT_CC, record them for truncation.
9710 if (User->getOpcode() == ISD::SELECT) {
9711 if (User->getOperand(0) == PromOps[i])
9712 SelectTruncOp[0].insert(std::make_pair(User,
9713 User->getOperand(0).getValueType()));
9714 } else if (User->getOpcode() == ISD::SELECT_CC) {
9715 if (User->getOperand(0) == PromOps[i])
9716 SelectTruncOp[0].insert(std::make_pair(User,
9717 User->getOperand(0).getValueType()));
9718 if (User->getOperand(1) == PromOps[i])
9719 SelectTruncOp[1].insert(std::make_pair(User,
9720 User->getOperand(1).getValueType()));
9725 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9726 bool ReallyNeedsExt = false;
9727 if (N->getOpcode() != ISD::ANY_EXTEND) {
9728 // If all of the inputs are not already sign/zero extended, then
9729 // we'll still need to do that at the end.
9730 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9731 if (isa<ConstantSDNode>(Inputs[i]))
9735 Inputs[i].getOperand(0).getValueSizeInBits();
9736 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9738 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9739 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9740 APInt::getHighBitsSet(OpBits,
9741 OpBits-PromBits))) ||
9742 (N->getOpcode() == ISD::SIGN_EXTEND &&
9743 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9744 (OpBits-(PromBits-1)))) {
9745 ReallyNeedsExt = true;
9751 // Replace all inputs, either with the truncation operand, or a
9752 // truncation or extension to the final output type.
9753 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9754 // Constant inputs need to be replaced with the to-be-promoted nodes that
9755 // use them because they might have users outside of the cluster of
9757 if (isa<ConstantSDNode>(Inputs[i]))
9760 SDValue InSrc = Inputs[i].getOperand(0);
9761 if (Inputs[i].getValueType() == N->getValueType(0))
9762 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9763 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9764 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9765 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9766 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9767 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9768 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9770 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9771 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9774 // Replace all operations (these are all the same, but have a different
9775 // (promoted) return type). DAG.getNode will validate that the types of
9776 // a binary operator match, so go through the list in reverse so that
9777 // we've likely promoted both operands first.
9778 while (!PromOps.empty()) {
9779 SDValue PromOp = PromOps.back();
9783 switch (PromOp.getOpcode()) {
9784 default: C = 0; break;
9785 case ISD::SELECT: C = 1; break;
9786 case ISD::SELECT_CC: C = 2; break;
9789 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9790 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9791 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9792 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9793 // The to-be-promoted operands of this node have not yet been
9794 // promoted (this should be rare because we're going through the
9795 // list backward, but if one of the operands has several users in
9796 // this cluster of to-be-promoted nodes, it is possible).
9797 PromOps.insert(PromOps.begin(), PromOp);
9801 // For SELECT and SELECT_CC nodes, we do a similar check for any
9802 // to-be-promoted comparison inputs.
9803 if (PromOp.getOpcode() == ISD::SELECT ||
9804 PromOp.getOpcode() == ISD::SELECT_CC) {
9805 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9806 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9807 (SelectTruncOp[1].count(PromOp.getNode()) &&
9808 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9809 PromOps.insert(PromOps.begin(), PromOp);
9814 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9815 PromOp.getNode()->op_end());
9817 // If this node has constant inputs, then they'll need to be promoted here.
9818 for (unsigned i = 0; i < 2; ++i) {
9819 if (!isa<ConstantSDNode>(Ops[C+i]))
9821 if (Ops[C+i].getValueType() == N->getValueType(0))
9824 if (N->getOpcode() == ISD::SIGN_EXTEND)
9825 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9826 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9827 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9829 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9832 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9833 // truncate them again to the original value type.
9834 if (PromOp.getOpcode() == ISD::SELECT ||
9835 PromOp.getOpcode() == ISD::SELECT_CC) {
9836 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9837 if (SI0 != SelectTruncOp[0].end())
9838 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9839 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9840 if (SI1 != SelectTruncOp[1].end())
9841 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9844 DAG.ReplaceAllUsesOfValueWith(PromOp,
9845 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9848 // Now we're left with the initial extension itself.
9849 if (!ReallyNeedsExt)
9850 return N->getOperand(0);
9852 // To zero extend, just mask off everything except for the first bit (in the
9854 if (N->getOpcode() == ISD::ZERO_EXTEND)
9855 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9856 DAG.getConstant(APInt::getLowBitsSet(
9857 N->getValueSizeInBits(0), PromBits),
9858 dl, N->getValueType(0)));
9860 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9861 "Invalid extension type");
9862 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9864 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9865 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9866 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9867 N->getOperand(0), ShiftCst), ShiftCst);
9870 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9871 DAGCombinerInfo &DCI) const {
9872 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9873 N->getOpcode() == ISD::UINT_TO_FP) &&
9874 "Need an int -> FP conversion node here");
9876 if (!Subtarget.has64BitSupport())
9879 SelectionDAG &DAG = DCI.DAG;
9883 // Don't handle ppc_fp128 here or i1 conversions.
9884 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9886 if (Op.getOperand(0).getValueType() == MVT::i1)
9889 // For i32 intermediate values, unfortunately, the conversion functions
9890 // leave the upper 32 bits of the value are undefined. Within the set of
9891 // scalar instructions, we have no method for zero- or sign-extending the
9892 // value. Thus, we cannot handle i32 intermediate values here.
9893 if (Op.getOperand(0).getValueType() == MVT::i32)
9896 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9897 "UINT_TO_FP is supported only with FPCVT");
9899 // If we have FCFIDS, then use it when converting to single-precision.
9900 // Otherwise, convert to double-precision and then round.
9901 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9902 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9904 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9906 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9910 // If we're converting from a float, to an int, and back to a float again,
9911 // then we don't need the store/load pair at all.
9912 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9913 Subtarget.hasFPCVT()) ||
9914 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9915 SDValue Src = Op.getOperand(0).getOperand(0);
9916 if (Src.getValueType() == MVT::f32) {
9917 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9918 DCI.AddToWorklist(Src.getNode());
9922 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9925 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9926 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9928 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9929 FP = DAG.getNode(ISD::FP_ROUND, dl,
9930 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
9931 DCI.AddToWorklist(FP.getNode());
9940 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9941 // builtins) into loads with swaps.
9942 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9943 DAGCombinerInfo &DCI) const {
9944 SelectionDAG &DAG = DCI.DAG;
9948 MachineMemOperand *MMO;
9950 switch (N->getOpcode()) {
9952 llvm_unreachable("Unexpected opcode for little endian VSX load");
9954 LoadSDNode *LD = cast<LoadSDNode>(N);
9955 Chain = LD->getChain();
9956 Base = LD->getBasePtr();
9957 MMO = LD->getMemOperand();
9958 // If the MMO suggests this isn't a load of a full vector, leave
9959 // things alone. For a built-in, we have to make the change for
9960 // correctness, so if there is a size problem that will be a bug.
9961 if (MMO->getSize() < 16)
9965 case ISD::INTRINSIC_W_CHAIN: {
9966 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9967 Chain = Intrin->getChain();
9968 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
9969 // us what we want. Get operand 2 instead.
9970 Base = Intrin->getOperand(2);
9971 MMO = Intrin->getMemOperand();
9976 MVT VecTy = N->getValueType(0).getSimpleVT();
9977 SDValue LoadOps[] = { Chain, Base };
9978 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9979 DAG.getVTList(VecTy, MVT::Other),
9980 LoadOps, VecTy, MMO);
9981 DCI.AddToWorklist(Load.getNode());
9982 Chain = Load.getValue(1);
9983 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9984 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9985 DCI.AddToWorklist(Swap.getNode());
9989 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
9990 // builtins) into stores with swaps.
9991 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
9992 DAGCombinerInfo &DCI) const {
9993 SelectionDAG &DAG = DCI.DAG;
9998 MachineMemOperand *MMO;
10000 switch (N->getOpcode()) {
10002 llvm_unreachable("Unexpected opcode for little endian VSX store");
10004 StoreSDNode *ST = cast<StoreSDNode>(N);
10005 Chain = ST->getChain();
10006 Base = ST->getBasePtr();
10007 MMO = ST->getMemOperand();
10009 // If the MMO suggests this isn't a store of a full vector, leave
10010 // things alone. For a built-in, we have to make the change for
10011 // correctness, so if there is a size problem that will be a bug.
10012 if (MMO->getSize() < 16)
10016 case ISD::INTRINSIC_VOID: {
10017 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10018 Chain = Intrin->getChain();
10019 // Intrin->getBasePtr() oddly does not get what we want.
10020 Base = Intrin->getOperand(3);
10021 MMO = Intrin->getMemOperand();
10027 SDValue Src = N->getOperand(SrcOpnd);
10028 MVT VecTy = Src.getValueType().getSimpleVT();
10029 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10030 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10031 DCI.AddToWorklist(Swap.getNode());
10032 Chain = Swap.getValue(1);
10033 SDValue StoreOps[] = { Chain, Swap, Base };
10034 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10035 DAG.getVTList(MVT::Other),
10036 StoreOps, VecTy, MMO);
10037 DCI.AddToWorklist(Store.getNode());
10041 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10042 DAGCombinerInfo &DCI) const {
10043 SelectionDAG &DAG = DCI.DAG;
10045 switch (N->getOpcode()) {
10048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10049 if (C->isNullValue()) // 0 << V -> 0.
10050 return N->getOperand(0);
10054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10055 if (C->isNullValue()) // 0 >>u V -> 0.
10056 return N->getOperand(0);
10060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10061 if (C->isNullValue() || // 0 >>s V -> 0.
10062 C->isAllOnesValue()) // -1 >>s V -> -1.
10063 return N->getOperand(0);
10066 case ISD::SIGN_EXTEND:
10067 case ISD::ZERO_EXTEND:
10068 case ISD::ANY_EXTEND:
10069 return DAGCombineExtBoolTrunc(N, DCI);
10070 case ISD::TRUNCATE:
10072 case ISD::SELECT_CC:
10073 return DAGCombineTruncBoolExt(N, DCI);
10074 case ISD::SINT_TO_FP:
10075 case ISD::UINT_TO_FP:
10076 return combineFPToIntToFP(N, DCI);
10078 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10079 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10080 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10081 N->getOperand(1).getValueType() == MVT::i32 &&
10082 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10083 SDValue Val = N->getOperand(1).getOperand(0);
10084 if (Val.getValueType() == MVT::f32) {
10085 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10086 DCI.AddToWorklist(Val.getNode());
10088 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10089 DCI.AddToWorklist(Val.getNode());
10092 N->getOperand(0), Val, N->getOperand(2),
10093 DAG.getValueType(N->getOperand(1).getValueType())
10096 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10097 DAG.getVTList(MVT::Other), Ops,
10098 cast<StoreSDNode>(N)->getMemoryVT(),
10099 cast<StoreSDNode>(N)->getMemOperand());
10100 DCI.AddToWorklist(Val.getNode());
10104 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10105 if (cast<StoreSDNode>(N)->isUnindexed() &&
10106 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10107 N->getOperand(1).getNode()->hasOneUse() &&
10108 (N->getOperand(1).getValueType() == MVT::i32 ||
10109 N->getOperand(1).getValueType() == MVT::i16 ||
10110 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10111 N->getOperand(1).getValueType() == MVT::i64))) {
10112 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10113 // Do an any-extend to 32-bits if this is a half-word input.
10114 if (BSwapOp.getValueType() == MVT::i16)
10115 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10118 N->getOperand(0), BSwapOp, N->getOperand(2),
10119 DAG.getValueType(N->getOperand(1).getValueType())
10122 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10123 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10124 cast<StoreSDNode>(N)->getMemOperand());
10127 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10128 EVT VT = N->getOperand(1).getValueType();
10129 if (VT.isSimple()) {
10130 MVT StoreVT = VT.getSimpleVT();
10131 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10132 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10133 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10134 return expandVSXStoreForLE(N, DCI);
10139 LoadSDNode *LD = cast<LoadSDNode>(N);
10140 EVT VT = LD->getValueType(0);
10142 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10143 if (VT.isSimple()) {
10144 MVT LoadVT = VT.getSimpleVT();
10145 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10146 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10147 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10148 return expandVSXLoadForLE(N, DCI);
10151 EVT MemVT = LD->getMemoryVT();
10152 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10153 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
10154 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10155 unsigned ScalarABIAlignment = getDataLayout()->getABITypeAlignment(STy);
10156 if (LD->isUnindexed() && VT.isVector() &&
10157 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10158 // P8 and later hardware should just use LOAD.
10159 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10160 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10161 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10162 LD->getAlignment() >= ScalarABIAlignment)) &&
10163 LD->getAlignment() < ABIAlignment) {
10164 // This is a type-legal unaligned Altivec or QPX load.
10165 SDValue Chain = LD->getChain();
10166 SDValue Ptr = LD->getBasePtr();
10167 bool isLittleEndian = Subtarget.isLittleEndian();
10169 // This implements the loading of unaligned vectors as described in
10170 // the venerable Apple Velocity Engine overview. Specifically:
10171 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10172 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10174 // The general idea is to expand a sequence of one or more unaligned
10175 // loads into an alignment-based permutation-control instruction (lvsl
10176 // or lvsr), a series of regular vector loads (which always truncate
10177 // their input address to an aligned address), and a series of
10178 // permutations. The results of these permutations are the requested
10179 // loaded values. The trick is that the last "extra" load is not taken
10180 // from the address you might suspect (sizeof(vector) bytes after the
10181 // last requested load), but rather sizeof(vector) - 1 bytes after the
10182 // last requested vector. The point of this is to avoid a page fault if
10183 // the base address happened to be aligned. This works because if the
10184 // base address is aligned, then adding less than a full vector length
10185 // will cause the last vector in the sequence to be (re)loaded.
10186 // Otherwise, the next vector will be fetched as you might suspect was
10189 // We might be able to reuse the permutation generation from
10190 // a different base address offset from this one by an aligned amount.
10191 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10192 // optimization later.
10193 Intrinsic::ID Intr, IntrLD, IntrPerm;
10194 MVT PermCntlTy, PermTy, LDTy;
10195 if (Subtarget.hasAltivec()) {
10196 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10197 Intrinsic::ppc_altivec_lvsl;
10198 IntrLD = Intrinsic::ppc_altivec_lvx;
10199 IntrPerm = Intrinsic::ppc_altivec_vperm;
10200 PermCntlTy = MVT::v16i8;
10201 PermTy = MVT::v4i32;
10204 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10205 Intrinsic::ppc_qpx_qvlpcls;
10206 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10207 Intrinsic::ppc_qpx_qvlfs;
10208 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10209 PermCntlTy = MVT::v4f64;
10210 PermTy = MVT::v4f64;
10211 LDTy = MemVT.getSimpleVT();
10214 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10216 // Create the new MMO for the new base load. It is like the original MMO,
10217 // but represents an area in memory almost twice the vector size centered
10218 // on the original address. If the address is unaligned, we might start
10219 // reading up to (sizeof(vector)-1) bytes below the address of the
10220 // original unaligned load.
10221 MachineFunction &MF = DAG.getMachineFunction();
10222 MachineMemOperand *BaseMMO =
10223 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
10224 2*MemVT.getStoreSize()-1);
10226 // Create the new base load.
10228 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10229 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10231 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10232 DAG.getVTList(PermTy, MVT::Other),
10233 BaseLoadOps, LDTy, BaseMMO);
10235 // Note that the value of IncOffset (which is provided to the next
10236 // load's pointer info offset value, and thus used to calculate the
10237 // alignment), and the value of IncValue (which is actually used to
10238 // increment the pointer value) are different! This is because we
10239 // require the next load to appear to be aligned, even though it
10240 // is actually offset from the base pointer by a lesser amount.
10241 int IncOffset = VT.getSizeInBits() / 8;
10242 int IncValue = IncOffset;
10244 // Walk (both up and down) the chain looking for another load at the real
10245 // (aligned) offset (the alignment of the other load does not matter in
10246 // this case). If found, then do not use the offset reduction trick, as
10247 // that will prevent the loads from being later combined (as they would
10248 // otherwise be duplicates).
10249 if (!findConsecutiveLoad(LD, DAG))
10252 SDValue Increment =
10253 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10254 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10256 MachineMemOperand *ExtraMMO =
10257 MF.getMachineMemOperand(LD->getMemOperand(),
10258 1, 2*MemVT.getStoreSize()-1);
10259 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10260 SDValue ExtraLoad =
10261 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10262 DAG.getVTList(PermTy, MVT::Other),
10263 ExtraLoadOps, LDTy, ExtraMMO);
10265 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10266 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10268 // Because vperm has a big-endian bias, we must reverse the order
10269 // of the input vectors and complement the permute control vector
10270 // when generating little endian code. We have already handled the
10271 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10272 // and ExtraLoad here.
10274 if (isLittleEndian)
10275 Perm = BuildIntrinsicOp(IntrPerm,
10276 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10278 Perm = BuildIntrinsicOp(IntrPerm,
10279 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10282 Perm = Subtarget.hasAltivec() ?
10283 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10284 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10285 DAG.getTargetConstant(1, dl, MVT::i64));
10286 // second argument is 1 because this rounding
10287 // is always exact.
10289 // The output of the permutation is our loaded result, the TokenFactor is
10291 DCI.CombineTo(N, Perm, TF);
10292 return SDValue(N, 0);
10296 case ISD::INTRINSIC_WO_CHAIN: {
10297 bool isLittleEndian = Subtarget.isLittleEndian();
10298 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10299 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10300 : Intrinsic::ppc_altivec_lvsl);
10301 if ((IID == Intr ||
10302 IID == Intrinsic::ppc_qpx_qvlpcld ||
10303 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10304 N->getOperand(1)->getOpcode() == ISD::ADD) {
10305 SDValue Add = N->getOperand(1);
10307 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10308 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10310 if (DAG.MaskedValueIsZero(
10311 Add->getOperand(1),
10312 APInt::getAllOnesValue(Bits /* alignment */)
10314 Add.getValueType().getScalarType().getSizeInBits()))) {
10315 SDNode *BasePtr = Add->getOperand(0).getNode();
10316 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10317 UE = BasePtr->use_end();
10319 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10320 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10321 // We've found another LVSL/LVSR, and this address is an aligned
10322 // multiple of that one. The results will be the same, so use the
10323 // one we've just found instead.
10325 return SDValue(*UI, 0);
10330 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10331 SDNode *BasePtr = Add->getOperand(0).getNode();
10332 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10333 UE = BasePtr->use_end(); UI != UE; ++UI) {
10334 if (UI->getOpcode() == ISD::ADD &&
10335 isa<ConstantSDNode>(UI->getOperand(1)) &&
10336 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10337 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10338 (1ULL << Bits) == 0) {
10339 SDNode *OtherAdd = *UI;
10340 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10341 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10342 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10343 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10344 return SDValue(*VI, 0);
10354 case ISD::INTRINSIC_W_CHAIN: {
10355 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10356 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10357 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10360 case Intrinsic::ppc_vsx_lxvw4x:
10361 case Intrinsic::ppc_vsx_lxvd2x:
10362 return expandVSXLoadForLE(N, DCI);
10367 case ISD::INTRINSIC_VOID: {
10368 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10369 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10370 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10373 case Intrinsic::ppc_vsx_stxvw4x:
10374 case Intrinsic::ppc_vsx_stxvd2x:
10375 return expandVSXStoreForLE(N, DCI);
10381 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10382 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10383 N->getOperand(0).hasOneUse() &&
10384 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10385 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10386 N->getValueType(0) == MVT::i64))) {
10387 SDValue Load = N->getOperand(0);
10388 LoadSDNode *LD = cast<LoadSDNode>(Load);
10389 // Create the byte-swapping load.
10391 LD->getChain(), // Chain
10392 LD->getBasePtr(), // Ptr
10393 DAG.getValueType(N->getValueType(0)) // VT
10396 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10397 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10398 MVT::i64 : MVT::i32, MVT::Other),
10399 Ops, LD->getMemoryVT(), LD->getMemOperand());
10401 // If this is an i16 load, insert the truncate.
10402 SDValue ResVal = BSLoad;
10403 if (N->getValueType(0) == MVT::i16)
10404 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10406 // First, combine the bswap away. This makes the value produced by the
10408 DCI.CombineTo(N, ResVal);
10410 // Next, combine the load away, we give it a bogus result value but a real
10411 // chain result. The result value is dead because the bswap is dead.
10412 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10414 // Return N so it doesn't get rechecked!
10415 return SDValue(N, 0);
10419 case PPCISD::VCMP: {
10420 // If a VCMPo node already exists with exactly the same operands as this
10421 // node, use its result instead of this node (VCMPo computes both a CR6 and
10422 // a normal output).
10424 if (!N->getOperand(0).hasOneUse() &&
10425 !N->getOperand(1).hasOneUse() &&
10426 !N->getOperand(2).hasOneUse()) {
10428 // Scan all of the users of the LHS, looking for VCMPo's that match.
10429 SDNode *VCMPoNode = nullptr;
10431 SDNode *LHSN = N->getOperand(0).getNode();
10432 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10434 if (UI->getOpcode() == PPCISD::VCMPo &&
10435 UI->getOperand(1) == N->getOperand(1) &&
10436 UI->getOperand(2) == N->getOperand(2) &&
10437 UI->getOperand(0) == N->getOperand(0)) {
10442 // If there is no VCMPo node, or if the flag value has a single use, don't
10444 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10447 // Look at the (necessarily single) use of the flag value. If it has a
10448 // chain, this transformation is more complex. Note that multiple things
10449 // could use the value result, which we should ignore.
10450 SDNode *FlagUser = nullptr;
10451 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10452 FlagUser == nullptr; ++UI) {
10453 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10454 SDNode *User = *UI;
10455 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10456 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10463 // If the user is a MFOCRF instruction, we know this is safe.
10464 // Otherwise we give up for right now.
10465 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10466 return SDValue(VCMPoNode, 0);
10470 case ISD::BRCOND: {
10471 SDValue Cond = N->getOperand(1);
10472 SDValue Target = N->getOperand(2);
10474 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10475 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10476 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10478 // We now need to make the intrinsic dead (it cannot be instruction
10480 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10481 assert(Cond.getNode()->hasOneUse() &&
10482 "Counter decrement has more than one use");
10484 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10485 N->getOperand(0), Target);
10490 // If this is a branch on an altivec predicate comparison, lower this so
10491 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10492 // lowering is done pre-legalize, because the legalizer lowers the predicate
10493 // compare down to code that is difficult to reassemble.
10494 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10495 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10497 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10498 // value. If so, pass-through the AND to get to the intrinsic.
10499 if (LHS.getOpcode() == ISD::AND &&
10500 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10501 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10502 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10503 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10504 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10506 LHS = LHS.getOperand(0);
10508 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10509 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10510 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10511 isa<ConstantSDNode>(RHS)) {
10512 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10513 "Counter decrement comparison is not EQ or NE");
10515 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10516 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10517 (CC == ISD::SETNE && !Val);
10519 // We now need to make the intrinsic dead (it cannot be instruction
10521 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10522 assert(LHS.getNode()->hasOneUse() &&
10523 "Counter decrement has more than one use");
10525 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10526 N->getOperand(0), N->getOperand(4));
10532 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10533 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10534 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10535 assert(isDot && "Can't compare against a vector result!");
10537 // If this is a comparison against something other than 0/1, then we know
10538 // that the condition is never/always true.
10539 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10540 if (Val != 0 && Val != 1) {
10541 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10542 return N->getOperand(0);
10543 // Always !=, turn it into an unconditional branch.
10544 return DAG.getNode(ISD::BR, dl, MVT::Other,
10545 N->getOperand(0), N->getOperand(4));
10548 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10550 // Create the PPCISD altivec 'dot' comparison node.
10552 LHS.getOperand(2), // LHS of compare
10553 LHS.getOperand(3), // RHS of compare
10554 DAG.getConstant(CompareOpc, dl, MVT::i32)
10556 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10557 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10559 // Unpack the result based on how the target uses it.
10560 PPC::Predicate CompOpc;
10561 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10562 default: // Can't happen, don't crash on invalid number though.
10563 case 0: // Branch on the value of the EQ bit of CR6.
10564 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10566 case 1: // Branch on the inverted value of the EQ bit of CR6.
10567 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10569 case 2: // Branch on the value of the LT bit of CR6.
10570 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10572 case 3: // Branch on the inverted value of the LT bit of CR6.
10573 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10577 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10578 DAG.getConstant(CompOpc, dl, MVT::i32),
10579 DAG.getRegister(PPC::CR6, MVT::i32),
10580 N->getOperand(4), CompNode.getValue(1));
10590 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10592 std::vector<SDNode *> *Created) const {
10593 // fold (sdiv X, pow2)
10594 EVT VT = N->getValueType(0);
10595 if (VT == MVT::i64 && !Subtarget.isPPC64())
10597 if ((VT != MVT::i32 && VT != MVT::i64) ||
10598 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10602 SDValue N0 = N->getOperand(0);
10604 bool IsNegPow2 = (-Divisor).isPowerOf2();
10605 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10606 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10608 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10610 Created->push_back(Op.getNode());
10613 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10615 Created->push_back(Op.getNode());
10621 //===----------------------------------------------------------------------===//
10622 // Inline Assembly Support
10623 //===----------------------------------------------------------------------===//
10625 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10628 const SelectionDAG &DAG,
10629 unsigned Depth) const {
10630 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10631 switch (Op.getOpcode()) {
10633 case PPCISD::LBRX: {
10634 // lhbrx is known to have the top bits cleared out.
10635 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10636 KnownZero = 0xFFFF0000;
10639 case ISD::INTRINSIC_WO_CHAIN: {
10640 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10642 case Intrinsic::ppc_altivec_vcmpbfp_p:
10643 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10644 case Intrinsic::ppc_altivec_vcmpequb_p:
10645 case Intrinsic::ppc_altivec_vcmpequh_p:
10646 case Intrinsic::ppc_altivec_vcmpequw_p:
10647 case Intrinsic::ppc_altivec_vcmpequd_p:
10648 case Intrinsic::ppc_altivec_vcmpgefp_p:
10649 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10650 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10651 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10652 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10653 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10654 case Intrinsic::ppc_altivec_vcmpgtub_p:
10655 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10656 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10657 case Intrinsic::ppc_altivec_vcmpgtud_p:
10658 KnownZero = ~1U; // All bits but the low one are known to be zero.
10665 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10666 switch (Subtarget.getDarwinDirective()) {
10669 case PPC::DIR_PWR4:
10670 case PPC::DIR_PWR5:
10671 case PPC::DIR_PWR5X:
10672 case PPC::DIR_PWR6:
10673 case PPC::DIR_PWR6X:
10674 case PPC::DIR_PWR7:
10675 case PPC::DIR_PWR8: {
10679 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10681 // For small loops (between 5 and 8 instructions), align to a 32-byte
10682 // boundary so that the entire loop fits in one instruction-cache line.
10683 uint64_t LoopSize = 0;
10684 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10685 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10686 LoopSize += TII->GetInstSizeInBytes(J);
10688 if (LoopSize > 16 && LoopSize <= 32)
10695 return TargetLowering::getPrefLoopAlignment(ML);
10698 /// getConstraintType - Given a constraint, return the type of
10699 /// constraint it is for this target.
10700 PPCTargetLowering::ConstraintType
10701 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10702 if (Constraint.size() == 1) {
10703 switch (Constraint[0]) {
10710 return C_RegisterClass;
10712 // FIXME: While Z does indicate a memory constraint, it specifically
10713 // indicates an r+r address (used in conjunction with the 'y' modifier
10714 // in the replacement string). Currently, we're forcing the base
10715 // register to be r0 in the asm printer (which is interpreted as zero)
10716 // and forming the complete address in the second register. This is
10720 } else if (Constraint == "wc") { // individual CR bits.
10721 return C_RegisterClass;
10722 } else if (Constraint == "wa" || Constraint == "wd" ||
10723 Constraint == "wf" || Constraint == "ws") {
10724 return C_RegisterClass; // VSX registers.
10726 return TargetLowering::getConstraintType(Constraint);
10729 /// Examine constraint type and operand type and determine a weight value.
10730 /// This object must already have been set up with the operand type
10731 /// and the current alternative constraint selected.
10732 TargetLowering::ConstraintWeight
10733 PPCTargetLowering::getSingleConstraintMatchWeight(
10734 AsmOperandInfo &info, const char *constraint) const {
10735 ConstraintWeight weight = CW_Invalid;
10736 Value *CallOperandVal = info.CallOperandVal;
10737 // If we don't have a value, we can't do a match,
10738 // but allow it at the lowest weight.
10739 if (!CallOperandVal)
10741 Type *type = CallOperandVal->getType();
10743 // Look at the constraint type.
10744 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10745 return CW_Register; // an individual CR bit.
10746 else if ((StringRef(constraint) == "wa" ||
10747 StringRef(constraint) == "wd" ||
10748 StringRef(constraint) == "wf") &&
10749 type->isVectorTy())
10750 return CW_Register;
10751 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10752 return CW_Register;
10754 switch (*constraint) {
10756 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10759 if (type->isIntegerTy())
10760 weight = CW_Register;
10763 if (type->isFloatTy())
10764 weight = CW_Register;
10767 if (type->isDoubleTy())
10768 weight = CW_Register;
10771 if (type->isVectorTy())
10772 weight = CW_Register;
10775 weight = CW_Register;
10778 weight = CW_Memory;
10784 std::pair<unsigned, const TargetRegisterClass *>
10785 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10786 StringRef Constraint,
10788 if (Constraint.size() == 1) {
10789 // GCC RS6000 Constraint Letters
10790 switch (Constraint[0]) {
10791 case 'b': // R1-R31
10792 if (VT == MVT::i64 && Subtarget.isPPC64())
10793 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10794 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10795 case 'r': // R0-R31
10796 if (VT == MVT::i64 && Subtarget.isPPC64())
10797 return std::make_pair(0U, &PPC::G8RCRegClass);
10798 return std::make_pair(0U, &PPC::GPRCRegClass);
10800 if (VT == MVT::f32 || VT == MVT::i32)
10801 return std::make_pair(0U, &PPC::F4RCRegClass);
10802 if (VT == MVT::f64 || VT == MVT::i64)
10803 return std::make_pair(0U, &PPC::F8RCRegClass);
10804 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10805 return std::make_pair(0U, &PPC::QFRCRegClass);
10806 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10807 return std::make_pair(0U, &PPC::QSRCRegClass);
10810 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10811 return std::make_pair(0U, &PPC::QFRCRegClass);
10812 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10813 return std::make_pair(0U, &PPC::QSRCRegClass);
10814 return std::make_pair(0U, &PPC::VRRCRegClass);
10816 return std::make_pair(0U, &PPC::CRRCRegClass);
10818 } else if (Constraint == "wc") { // an individual CR bit.
10819 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10820 } else if (Constraint == "wa" || Constraint == "wd" ||
10821 Constraint == "wf") {
10822 return std::make_pair(0U, &PPC::VSRCRegClass);
10823 } else if (Constraint == "ws") {
10824 if (VT == MVT::f32)
10825 return std::make_pair(0U, &PPC::VSSRCRegClass);
10827 return std::make_pair(0U, &PPC::VSFRCRegClass);
10830 std::pair<unsigned, const TargetRegisterClass *> R =
10831 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10833 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10834 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10835 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10837 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10838 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10839 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10840 PPC::GPRCRegClass.contains(R.first))
10841 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10842 PPC::sub_32, &PPC::G8RCRegClass),
10843 &PPC::G8RCRegClass);
10845 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10846 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10847 R.first = PPC::CR0;
10848 R.second = &PPC::CRRCRegClass;
10855 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10856 /// vector. If it is invalid, don't add anything to Ops.
10857 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10858 std::string &Constraint,
10859 std::vector<SDValue>&Ops,
10860 SelectionDAG &DAG) const {
10863 // Only support length 1 constraints.
10864 if (Constraint.length() > 1) return;
10866 char Letter = Constraint[0];
10877 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10878 if (!CST) return; // Must be an immediate to match.
10880 int64_t Value = CST->getSExtValue();
10881 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10882 // numbers are printed as such.
10884 default: llvm_unreachable("Unknown constraint letter!");
10885 case 'I': // "I" is a signed 16-bit constant.
10886 if (isInt<16>(Value))
10887 Result = DAG.getTargetConstant(Value, dl, TCVT);
10889 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10890 if (isShiftedUInt<16, 16>(Value))
10891 Result = DAG.getTargetConstant(Value, dl, TCVT);
10893 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10894 if (isShiftedInt<16, 16>(Value))
10895 Result = DAG.getTargetConstant(Value, dl, TCVT);
10897 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10898 if (isUInt<16>(Value))
10899 Result = DAG.getTargetConstant(Value, dl, TCVT);
10901 case 'M': // "M" is a constant that is greater than 31.
10903 Result = DAG.getTargetConstant(Value, dl, TCVT);
10905 case 'N': // "N" is a positive constant that is an exact power of two.
10906 if (Value > 0 && isPowerOf2_64(Value))
10907 Result = DAG.getTargetConstant(Value, dl, TCVT);
10909 case 'O': // "O" is the constant zero.
10911 Result = DAG.getTargetConstant(Value, dl, TCVT);
10913 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10914 if (isInt<16>(-Value))
10915 Result = DAG.getTargetConstant(Value, dl, TCVT);
10922 if (Result.getNode()) {
10923 Ops.push_back(Result);
10927 // Handle standard constraint letters.
10928 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10931 // isLegalAddressingMode - Return true if the addressing mode represented
10932 // by AM is legal for this target, for a load/store of the specified type.
10933 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10935 unsigned AS) const {
10936 // PPC does not allow r+i addressing modes for vectors!
10937 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10940 // PPC allows a sign-extended 16-bit immediate field.
10941 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10944 // No global is ever allowed as a base.
10948 // PPC only support r+r,
10949 switch (AM.Scale) {
10950 case 0: // "r+i" or just "i", depending on HasBaseReg.
10953 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
10955 // Otherwise we have r+r or r+i.
10958 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
10960 // Allow 2*r as r+r.
10963 // No other scales are supported.
10970 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
10971 SelectionDAG &DAG) const {
10972 MachineFunction &MF = DAG.getMachineFunction();
10973 MachineFrameInfo *MFI = MF.getFrameInfo();
10974 MFI->setReturnAddressIsTaken(true);
10976 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
10980 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10982 // Make sure the function does not optimize away the store of the RA to
10984 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
10985 FuncInfo->setLRStoreRequired();
10986 bool isPPC64 = Subtarget.isPPC64();
10987 auto PtrVT = getPointerTy(MF.getDataLayout());
10990 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10992 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
10993 isPPC64 ? MVT::i64 : MVT::i32);
10994 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10995 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
10996 MachinePointerInfo(), false, false, false, 0);
10999 // Just load the return address off the stack.
11000 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11001 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11002 MachinePointerInfo(), false, false, false, 0);
11005 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11006 SelectionDAG &DAG) const {
11008 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11010 MachineFunction &MF = DAG.getMachineFunction();
11011 MachineFrameInfo *MFI = MF.getFrameInfo();
11012 MFI->setFrameAddressIsTaken(true);
11014 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11015 bool isPPC64 = PtrVT == MVT::i64;
11017 // Naked functions never have a frame pointer, and so we use r1. For all
11018 // other functions, this decision must be delayed until during PEI.
11020 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11021 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11023 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11025 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11028 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11029 FrameAddr, MachinePointerInfo(), false, false,
11034 // FIXME? Maybe this could be a TableGen attribute on some registers and
11035 // this table could be generated automatically from RegInfo.
11036 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
11038 bool isPPC64 = Subtarget.isPPC64();
11039 bool isDarwinABI = Subtarget.isDarwinABI();
11041 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11042 (!isPPC64 && VT != MVT::i32))
11043 report_fatal_error("Invalid register global variable type");
11045 bool is64Bit = isPPC64 && VT == MVT::i64;
11046 unsigned Reg = StringSwitch<unsigned>(RegName)
11047 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11048 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11049 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11050 (is64Bit ? PPC::X13 : PPC::R13))
11055 report_fatal_error("Invalid register name global variable");
11059 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11060 // The PowerPC target isn't yet aware of offsets.
11064 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11066 unsigned Intrinsic) const {
11068 switch (Intrinsic) {
11069 case Intrinsic::ppc_qpx_qvlfd:
11070 case Intrinsic::ppc_qpx_qvlfs:
11071 case Intrinsic::ppc_qpx_qvlfcd:
11072 case Intrinsic::ppc_qpx_qvlfcs:
11073 case Intrinsic::ppc_qpx_qvlfiwa:
11074 case Intrinsic::ppc_qpx_qvlfiwz:
11075 case Intrinsic::ppc_altivec_lvx:
11076 case Intrinsic::ppc_altivec_lvxl:
11077 case Intrinsic::ppc_altivec_lvebx:
11078 case Intrinsic::ppc_altivec_lvehx:
11079 case Intrinsic::ppc_altivec_lvewx:
11080 case Intrinsic::ppc_vsx_lxvd2x:
11081 case Intrinsic::ppc_vsx_lxvw4x: {
11083 switch (Intrinsic) {
11084 case Intrinsic::ppc_altivec_lvebx:
11087 case Intrinsic::ppc_altivec_lvehx:
11090 case Intrinsic::ppc_altivec_lvewx:
11093 case Intrinsic::ppc_vsx_lxvd2x:
11096 case Intrinsic::ppc_qpx_qvlfd:
11099 case Intrinsic::ppc_qpx_qvlfs:
11102 case Intrinsic::ppc_qpx_qvlfcd:
11105 case Intrinsic::ppc_qpx_qvlfcs:
11113 Info.opc = ISD::INTRINSIC_W_CHAIN;
11115 Info.ptrVal = I.getArgOperand(0);
11116 Info.offset = -VT.getStoreSize()+1;
11117 Info.size = 2*VT.getStoreSize()-1;
11120 Info.readMem = true;
11121 Info.writeMem = false;
11124 case Intrinsic::ppc_qpx_qvlfda:
11125 case Intrinsic::ppc_qpx_qvlfsa:
11126 case Intrinsic::ppc_qpx_qvlfcda:
11127 case Intrinsic::ppc_qpx_qvlfcsa:
11128 case Intrinsic::ppc_qpx_qvlfiwaa:
11129 case Intrinsic::ppc_qpx_qvlfiwza: {
11131 switch (Intrinsic) {
11132 case Intrinsic::ppc_qpx_qvlfda:
11135 case Intrinsic::ppc_qpx_qvlfsa:
11138 case Intrinsic::ppc_qpx_qvlfcda:
11141 case Intrinsic::ppc_qpx_qvlfcsa:
11149 Info.opc = ISD::INTRINSIC_W_CHAIN;
11151 Info.ptrVal = I.getArgOperand(0);
11153 Info.size = VT.getStoreSize();
11156 Info.readMem = true;
11157 Info.writeMem = false;
11160 case Intrinsic::ppc_qpx_qvstfd:
11161 case Intrinsic::ppc_qpx_qvstfs:
11162 case Intrinsic::ppc_qpx_qvstfcd:
11163 case Intrinsic::ppc_qpx_qvstfcs:
11164 case Intrinsic::ppc_qpx_qvstfiw:
11165 case Intrinsic::ppc_altivec_stvx:
11166 case Intrinsic::ppc_altivec_stvxl:
11167 case Intrinsic::ppc_altivec_stvebx:
11168 case Intrinsic::ppc_altivec_stvehx:
11169 case Intrinsic::ppc_altivec_stvewx:
11170 case Intrinsic::ppc_vsx_stxvd2x:
11171 case Intrinsic::ppc_vsx_stxvw4x: {
11173 switch (Intrinsic) {
11174 case Intrinsic::ppc_altivec_stvebx:
11177 case Intrinsic::ppc_altivec_stvehx:
11180 case Intrinsic::ppc_altivec_stvewx:
11183 case Intrinsic::ppc_vsx_stxvd2x:
11186 case Intrinsic::ppc_qpx_qvstfd:
11189 case Intrinsic::ppc_qpx_qvstfs:
11192 case Intrinsic::ppc_qpx_qvstfcd:
11195 case Intrinsic::ppc_qpx_qvstfcs:
11203 Info.opc = ISD::INTRINSIC_VOID;
11205 Info.ptrVal = I.getArgOperand(1);
11206 Info.offset = -VT.getStoreSize()+1;
11207 Info.size = 2*VT.getStoreSize()-1;
11210 Info.readMem = false;
11211 Info.writeMem = true;
11214 case Intrinsic::ppc_qpx_qvstfda:
11215 case Intrinsic::ppc_qpx_qvstfsa:
11216 case Intrinsic::ppc_qpx_qvstfcda:
11217 case Intrinsic::ppc_qpx_qvstfcsa:
11218 case Intrinsic::ppc_qpx_qvstfiwa: {
11220 switch (Intrinsic) {
11221 case Intrinsic::ppc_qpx_qvstfda:
11224 case Intrinsic::ppc_qpx_qvstfsa:
11227 case Intrinsic::ppc_qpx_qvstfcda:
11230 case Intrinsic::ppc_qpx_qvstfcsa:
11238 Info.opc = ISD::INTRINSIC_VOID;
11240 Info.ptrVal = I.getArgOperand(1);
11242 Info.size = VT.getStoreSize();
11245 Info.readMem = false;
11246 Info.writeMem = true;
11256 /// getOptimalMemOpType - Returns the target specific optimal type for load
11257 /// and store operations as a result of memset, memcpy, and memmove
11258 /// lowering. If DstAlign is zero that means it's safe to destination
11259 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11260 /// means there isn't a need to check it against alignment requirement,
11261 /// probably because the source does not need to be loaded. If 'IsMemset' is
11262 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11263 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11264 /// source is constant so it does not need to be loaded.
11265 /// It returns EVT::Other if the type should be determined using generic
11266 /// target-independent logic.
11267 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11268 unsigned DstAlign, unsigned SrcAlign,
11269 bool IsMemset, bool ZeroMemset,
11271 MachineFunction &MF) const {
11272 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11273 const Function *F = MF.getFunction();
11274 // When expanding a memset, require at least two QPX instructions to cover
11275 // the cost of loading the value to be stored from the constant pool.
11276 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11277 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11278 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11282 // We should use Altivec/VSX loads and stores when available. For unaligned
11283 // addresses, unaligned VSX loads are only fast starting with the P8.
11284 if (Subtarget.hasAltivec() && Size >= 16 &&
11285 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11286 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11290 if (Subtarget.isPPC64()) {
11297 /// \brief Returns true if it is beneficial to convert a load of a constant
11298 /// to just the constant itself.
11299 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11301 assert(Ty->isIntegerTy());
11303 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11304 if (BitSize == 0 || BitSize > 64)
11309 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11310 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11312 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11313 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11314 return NumBits1 == 64 && NumBits2 == 32;
11317 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11318 if (!VT1.isInteger() || !VT2.isInteger())
11320 unsigned NumBits1 = VT1.getSizeInBits();
11321 unsigned NumBits2 = VT2.getSizeInBits();
11322 return NumBits1 == 64 && NumBits2 == 32;
11325 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11326 // Generally speaking, zexts are not free, but they are free when they can be
11327 // folded with other operations.
11328 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11329 EVT MemVT = LD->getMemoryVT();
11330 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11331 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11332 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11333 LD->getExtensionType() == ISD::ZEXTLOAD))
11337 // FIXME: Add other cases...
11338 // - 32-bit shifts with a zext to i64
11339 // - zext after ctlz, bswap, etc.
11340 // - zext after and by a constant mask
11342 return TargetLowering::isZExtFree(Val, VT2);
11345 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11346 assert(VT.isFloatingPoint());
11350 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11351 return isInt<16>(Imm) || isUInt<16>(Imm);
11354 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11355 return isInt<16>(Imm) || isUInt<16>(Imm);
11358 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11361 bool *Fast) const {
11362 if (DisablePPCUnaligned)
11365 // PowerPC supports unaligned memory access for simple non-vector types.
11366 // Although accessing unaligned addresses is not as efficient as accessing
11367 // aligned addresses, it is generally more efficient than manual expansion,
11368 // and generally only traps for software emulation when crossing page
11371 if (!VT.isSimple())
11374 if (VT.getSimpleVT().isVector()) {
11375 if (Subtarget.hasVSX()) {
11376 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11377 VT != MVT::v4f32 && VT != MVT::v4i32)
11384 if (VT == MVT::ppcf128)
11393 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11394 VT = VT.getScalarType();
11396 if (!VT.isSimple())
11399 switch (VT.getSimpleVT().SimpleTy) {
11411 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11412 // LR is a callee-save register, but we must treat it as clobbered by any call
11413 // site. Hence we include LR in the scratch registers, which are in turn added
11414 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11415 // to CTR, which is used by any indirect call.
11416 static const MCPhysReg ScratchRegs[] = {
11417 PPC::X12, PPC::LR8, PPC::CTR8, 0
11420 return ScratchRegs;
11424 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11425 EVT VT , unsigned DefinedValues) const {
11426 if (VT == MVT::v2i64)
11429 if (Subtarget.hasQPX()) {
11430 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11434 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11437 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11438 if (DisableILPPref || Subtarget.enableMachineScheduler())
11439 return TargetLowering::getSchedulingPreference(N);
11444 // Create a fast isel object.
11446 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11447 const TargetLibraryInfo *LibInfo) const {
11448 return PPC::createFastISel(FuncInfo, LibInfo);