1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::MULHU, VT, Expand);
457 setOperationAction(ISD::MULHS, VT, Expand);
458 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
459 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
460 setOperationAction(ISD::UDIVREM, VT, Expand);
461 setOperationAction(ISD::SDIVREM, VT, Expand);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
463 setOperationAction(ISD::FPOW, VT, Expand);
464 setOperationAction(ISD::BSWAP, VT, Expand);
465 setOperationAction(ISD::CTPOP, VT, Expand);
466 setOperationAction(ISD::CTLZ, VT, Expand);
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::CTTZ, VT, Expand);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
470 setOperationAction(ISD::VSELECT, VT, Expand);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
473 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
474 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
475 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
476 setTruncStoreAction(VT, InnerVT, Expand);
478 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
479 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
480 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
483 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
484 // with merges, splats, etc.
485 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
487 setOperationAction(ISD::AND , MVT::v4i32, Legal);
488 setOperationAction(ISD::OR , MVT::v4i32, Legal);
489 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
490 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
491 setOperationAction(ISD::SELECT, MVT::v4i32,
492 Subtarget.useCRBits() ? Legal : Expand);
493 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
494 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
495 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
496 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
497 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
498 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
501 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
503 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
505 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
506 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
508 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
509 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
511 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
512 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
513 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
516 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
520 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
521 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
525 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
528 // Altivec does not contain unordered floating-point compare instructions
529 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
534 if (Subtarget.hasVSX()) {
535 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
536 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
538 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
540 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
541 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
544 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
546 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
547 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
549 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
550 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
552 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
553 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
558 // Share the Altivec comparison restrictions.
559 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
560 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
561 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
562 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
564 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
565 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
567 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
569 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
571 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
572 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
574 // VSX v2i64 only supports non-arithmetic operations.
575 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
576 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
578 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
579 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
580 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
584 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
585 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
586 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
587 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
591 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
592 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
593 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
594 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
596 // Vector operation legalization checks the result type of
597 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
603 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
607 if (Subtarget.has64BitSupport()) {
608 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
609 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
612 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
613 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
617 setBooleanContents(ZeroOrOneBooleanContent);
618 // Altivec instructions set fields to all zeros or all ones.
619 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
622 // These libcalls are not available in 32-bit.
623 setLibcallName(RTLIB::SHL_I128, nullptr);
624 setLibcallName(RTLIB::SRL_I128, nullptr);
625 setLibcallName(RTLIB::SRA_I128, nullptr);
629 setStackPointerRegisterToSaveRestore(PPC::X1);
630 setExceptionPointerRegister(PPC::X3);
631 setExceptionSelectorRegister(PPC::X4);
633 setStackPointerRegisterToSaveRestore(PPC::R1);
634 setExceptionPointerRegister(PPC::R3);
635 setExceptionSelectorRegister(PPC::R4);
638 // We have target-specific dag combine patterns for the following nodes:
639 setTargetDAGCombine(ISD::SINT_TO_FP);
640 setTargetDAGCombine(ISD::LOAD);
641 setTargetDAGCombine(ISD::STORE);
642 setTargetDAGCombine(ISD::BR_CC);
643 if (Subtarget.useCRBits())
644 setTargetDAGCombine(ISD::BRCOND);
645 setTargetDAGCombine(ISD::BSWAP);
646 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
648 setTargetDAGCombine(ISD::SIGN_EXTEND);
649 setTargetDAGCombine(ISD::ZERO_EXTEND);
650 setTargetDAGCombine(ISD::ANY_EXTEND);
652 if (Subtarget.useCRBits()) {
653 setTargetDAGCombine(ISD::TRUNCATE);
654 setTargetDAGCombine(ISD::SETCC);
655 setTargetDAGCombine(ISD::SELECT_CC);
658 // Use reciprocal estimates.
659 if (TM.Options.UnsafeFPMath) {
660 setTargetDAGCombine(ISD::FDIV);
661 setTargetDAGCombine(ISD::FSQRT);
664 // Darwin long double math library functions have $LDBL128 appended.
665 if (Subtarget.isDarwin()) {
666 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
678 // With 32 condition bits, we don't need to sink (and duplicate) compares
679 // aggressively in CodeGenPrep.
680 if (Subtarget.useCRBits())
681 setHasMultipleConditionRegisters();
683 setMinFunctionAlignment(2);
684 if (Subtarget.isDarwin())
685 setPrefFunctionAlignment(4);
687 if (isPPC64 && Subtarget.isJITCodeModel())
688 // Temporary workaround for the inability of PPC64 JIT to handle jump
690 setSupportJumpTables(false);
692 setInsertFencesForAtomic(true);
694 if (Subtarget.enableMachineScheduler())
695 setSchedulingPreference(Sched::Source);
697 setSchedulingPreference(Sched::Hybrid);
699 computeRegisterProperties();
701 // The Freescale cores does better with aggressive inlining of memcpy and
702 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
703 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
704 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
705 MaxStoresPerMemset = 32;
706 MaxStoresPerMemsetOptSize = 16;
707 MaxStoresPerMemcpy = 32;
708 MaxStoresPerMemcpyOptSize = 8;
709 MaxStoresPerMemmove = 32;
710 MaxStoresPerMemmoveOptSize = 8;
712 setPrefFunctionAlignment(4);
716 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
717 /// the desired ByVal argument alignment.
718 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
719 unsigned MaxMaxAlign) {
720 if (MaxAlign == MaxMaxAlign)
722 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
723 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
725 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
727 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
728 unsigned EltAlign = 0;
729 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
730 if (EltAlign > MaxAlign)
732 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
733 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 if (MaxAlign == MaxMaxAlign)
744 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
745 /// function arguments in the caller parameter area.
746 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
747 // Darwin passes everything on 4 byte boundary.
748 if (Subtarget.isDarwin())
751 // 16byte and wider vectors are passed on 16byte boundary.
752 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
753 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
754 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
755 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
759 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 default: return nullptr;
762 case PPCISD::FSEL: return "PPCISD::FSEL";
763 case PPCISD::FCFID: return "PPCISD::FCFID";
764 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
765 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
766 case PPCISD::FRE: return "PPCISD::FRE";
767 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
768 case PPCISD::STFIWX: return "PPCISD::STFIWX";
769 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
770 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
771 case PPCISD::VPERM: return "PPCISD::VPERM";
772 case PPCISD::Hi: return "PPCISD::Hi";
773 case PPCISD::Lo: return "PPCISD::Lo";
774 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
775 case PPCISD::LOAD: return "PPCISD::LOAD";
776 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
777 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
778 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
779 case PPCISD::SRL: return "PPCISD::SRL";
780 case PPCISD::SRA: return "PPCISD::SRA";
781 case PPCISD::SHL: return "PPCISD::SHL";
782 case PPCISD::CALL: return "PPCISD::CALL";
783 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
784 case PPCISD::MTCTR: return "PPCISD::MTCTR";
785 case PPCISD::BCTRL: return "PPCISD::BCTRL";
786 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
787 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
788 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
789 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
790 case PPCISD::VCMP: return "PPCISD::VCMP";
791 case PPCISD::VCMPo: return "PPCISD::VCMPo";
792 case PPCISD::LBRX: return "PPCISD::LBRX";
793 case PPCISD::STBRX: return "PPCISD::STBRX";
794 case PPCISD::LARX: return "PPCISD::LARX";
795 case PPCISD::STCX: return "PPCISD::STCX";
796 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
797 case PPCISD::BDNZ: return "PPCISD::BDNZ";
798 case PPCISD::BDZ: return "PPCISD::BDZ";
799 case PPCISD::MFFS: return "PPCISD::MFFS";
800 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
801 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
802 case PPCISD::CR6SET: return "PPCISD::CR6SET";
803 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
804 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
805 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
806 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
807 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
808 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
809 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
810 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
811 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
812 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
813 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
814 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
815 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
816 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
817 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
818 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
819 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
820 case PPCISD::SC: return "PPCISD::SC";
824 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
826 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
827 return VT.changeVectorElementTypeToInteger();
830 //===----------------------------------------------------------------------===//
831 // Node matching predicates, for use by the tblgen matching code.
832 //===----------------------------------------------------------------------===//
834 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
835 static bool isFloatingPointZero(SDValue Op) {
836 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
837 return CFP->getValueAPF().isZero();
838 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
839 // Maybe this has already been legalized into the constant pool?
840 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
841 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
842 return CFP->getValueAPF().isZero();
847 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
848 /// true if Op is undef or if it matches the specified value.
849 static bool isConstantOrUndef(int Op, int Val) {
850 return Op < 0 || Op == Val;
853 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
854 /// VPKUHUM instruction.
855 /// The ShuffleKind distinguishes between big-endian operations with
856 /// two different inputs (0), either-endian operations with two identical
857 /// inputs (1), and little-endian operantion with two different inputs (2).
858 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
859 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
862 DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian();
863 if (ShuffleKind == 0) {
866 for (unsigned i = 0; i != 16; ++i)
867 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
869 } else if (ShuffleKind == 2) {
872 for (unsigned i = 0; i != 16; ++i)
873 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
875 } else if (ShuffleKind == 1) {
876 unsigned j = IsLE ? 0 : 1;
877 for (unsigned i = 0; i != 8; ++i)
878 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
879 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
885 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
886 /// VPKUWUM instruction.
887 /// The ShuffleKind distinguishes between big-endian operations with
888 /// two different inputs (0), either-endian operations with two identical
889 /// inputs (1), and little-endian operantion with two different inputs (2).
890 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
891 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
894 DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian();
895 if (ShuffleKind == 0) {
898 for (unsigned i = 0; i != 16; i += 2)
899 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
900 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
902 } else if (ShuffleKind == 2) {
905 for (unsigned i = 0; i != 16; i += 2)
906 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
907 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
909 } else if (ShuffleKind == 1) {
910 unsigned j = IsLE ? 0 : 2;
911 for (unsigned i = 0; i != 8; i += 2)
912 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
913 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
914 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
915 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
921 /// isVMerge - Common function, used to match vmrg* shuffles.
923 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
924 unsigned LHSStart, unsigned RHSStart) {
925 if (N->getValueType(0) != MVT::v16i8)
927 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
928 "Unsupported merge size!");
930 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
931 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
932 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
933 LHSStart+j+i*UnitSize) ||
934 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
935 RHSStart+j+i*UnitSize))
941 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
942 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
943 /// The ShuffleKind distinguishes between big-endian merges with two
944 /// different inputs (0), either-endian merges with two identical inputs (1),
945 /// and little-endian merges with two different inputs (2). For the latter,
946 /// the input operands are swapped (see PPCInstrAltivec.td).
947 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
948 unsigned ShuffleKind, SelectionDAG &DAG) {
949 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
950 if (ShuffleKind == 1) // unary
951 return isVMerge(N, UnitSize, 0, 0);
952 else if (ShuffleKind == 2) // swapped
953 return isVMerge(N, UnitSize, 0, 16);
957 if (ShuffleKind == 1) // unary
958 return isVMerge(N, UnitSize, 8, 8);
959 else if (ShuffleKind == 0) // normal
960 return isVMerge(N, UnitSize, 8, 24);
966 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
967 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
968 /// The ShuffleKind distinguishes between big-endian merges with two
969 /// different inputs (0), either-endian merges with two identical inputs (1),
970 /// and little-endian merges with two different inputs (2). For the latter,
971 /// the input operands are swapped (see PPCInstrAltivec.td).
972 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
973 unsigned ShuffleKind, SelectionDAG &DAG) {
974 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
975 if (ShuffleKind == 1) // unary
976 return isVMerge(N, UnitSize, 8, 8);
977 else if (ShuffleKind == 2) // swapped
978 return isVMerge(N, UnitSize, 8, 24);
982 if (ShuffleKind == 1) // unary
983 return isVMerge(N, UnitSize, 0, 0);
984 else if (ShuffleKind == 0) // normal
985 return isVMerge(N, UnitSize, 0, 16);
992 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
993 /// amount, otherwise return -1.
994 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
995 if (N->getValueType(0) != MVT::v16i8)
998 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1000 // Find the first non-undef value in the shuffle mask.
1002 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1005 if (i == 16) return -1; // all undef.
1007 // Otherwise, check to see if the rest of the elements are consecutively
1008 // numbered from this value.
1009 unsigned ShiftAmt = SVOp->getMaskElt(i);
1010 if (ShiftAmt < i) return -1;
1012 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
1017 // Check the rest of the elements to see if they are consecutive.
1018 for (++i; i != 16; ++i)
1019 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
1022 // Check the rest of the elements to see if they are consecutive.
1023 for (++i; i != 16; ++i)
1024 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
1028 } else { // Big Endian
1033 // Check the rest of the elements to see if they are consecutive.
1034 for (++i; i != 16; ++i)
1035 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1038 // Check the rest of the elements to see if they are consecutive.
1039 for (++i; i != 16; ++i)
1040 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1047 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1048 /// specifies a splat of a single element that is suitable for input to
1049 /// VSPLTB/VSPLTH/VSPLTW.
1050 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1051 assert(N->getValueType(0) == MVT::v16i8 &&
1052 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1054 // This is a splat operation if each element of the permute is the same, and
1055 // if the value doesn't reference the second vector.
1056 unsigned ElementBase = N->getMaskElt(0);
1058 // FIXME: Handle UNDEF elements too!
1059 if (ElementBase >= 16)
1062 // Check that the indices are consecutive, in the case of a multi-byte element
1063 // splatted with a v16i8 mask.
1064 for (unsigned i = 1; i != EltSize; ++i)
1065 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1068 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1069 if (N->getMaskElt(i) < 0) continue;
1070 for (unsigned j = 0; j != EltSize; ++j)
1071 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1077 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1079 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1080 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1082 APInt APVal, APUndef;
1086 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1087 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1088 return CFP->getValueAPF().isNegZero();
1093 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1094 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1095 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1096 SelectionDAG &DAG) {
1097 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1098 assert(isSplatShuffleMask(SVOp, EltSize));
1099 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian())
1100 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1102 return SVOp->getMaskElt(0) / EltSize;
1105 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1106 /// by using a vspltis[bhw] instruction of the specified element size, return
1107 /// the constant being splatted. The ByteSize field indicates the number of
1108 /// bytes of each element [124] -> [bhw].
1109 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1110 SDValue OpVal(nullptr, 0);
1112 // If ByteSize of the splat is bigger than the element size of the
1113 // build_vector, then we have a case where we are checking for a splat where
1114 // multiple elements of the buildvector are folded together into a single
1115 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1116 unsigned EltSize = 16/N->getNumOperands();
1117 if (EltSize < ByteSize) {
1118 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1119 SDValue UniquedVals[4];
1120 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1122 // See if all of the elements in the buildvector agree across.
1123 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1124 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1125 // If the element isn't a constant, bail fully out.
1126 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1129 if (!UniquedVals[i&(Multiple-1)].getNode())
1130 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1131 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1132 return SDValue(); // no match.
1135 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1136 // either constant or undef values that are identical for each chunk. See
1137 // if these chunks can form into a larger vspltis*.
1139 // Check to see if all of the leading entries are either 0 or -1. If
1140 // neither, then this won't fit into the immediate field.
1141 bool LeadingZero = true;
1142 bool LeadingOnes = true;
1143 for (unsigned i = 0; i != Multiple-1; ++i) {
1144 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1146 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1147 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1149 // Finally, check the least significant entry.
1151 if (!UniquedVals[Multiple-1].getNode())
1152 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1153 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1155 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1158 if (!UniquedVals[Multiple-1].getNode())
1159 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1160 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1161 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1162 return DAG.getTargetConstant(Val, MVT::i32);
1168 // Check to see if this buildvec has a single non-undef value in its elements.
1169 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1170 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1171 if (!OpVal.getNode())
1172 OpVal = N->getOperand(i);
1173 else if (OpVal != N->getOperand(i))
1177 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1179 unsigned ValSizeInBytes = EltSize;
1181 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1182 Value = CN->getZExtValue();
1183 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1184 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1185 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1188 // If the splat value is larger than the element value, then we can never do
1189 // this splat. The only case that we could fit the replicated bits into our
1190 // immediate field for would be zero, and we prefer to use vxor for it.
1191 if (ValSizeInBytes < ByteSize) return SDValue();
1193 // If the element value is larger than the splat value, cut it in half and
1194 // check to see if the two halves are equal. Continue doing this until we
1195 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1196 while (ValSizeInBytes > ByteSize) {
1197 ValSizeInBytes >>= 1;
1199 // If the top half equals the bottom half, we're still ok.
1200 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1201 (Value & ((1 << (8*ValSizeInBytes))-1)))
1205 // Properly sign extend the value.
1206 int MaskVal = SignExtend32(Value, ByteSize * 8);
1208 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1209 if (MaskVal == 0) return SDValue();
1211 // Finally, if this value fits in a 5 bit sext field, return it
1212 if (SignExtend32<5>(MaskVal) == MaskVal)
1213 return DAG.getTargetConstant(MaskVal, MVT::i32);
1217 //===----------------------------------------------------------------------===//
1218 // Addressing Mode Selection
1219 //===----------------------------------------------------------------------===//
1221 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1222 /// or 64-bit immediate, and if the value can be accurately represented as a
1223 /// sign extension from a 16-bit value. If so, this returns true and the
1225 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1226 if (!isa<ConstantSDNode>(N))
1229 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1230 if (N->getValueType(0) == MVT::i32)
1231 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1233 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1235 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1236 return isIntS16Immediate(Op.getNode(), Imm);
1240 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1241 /// can be represented as an indexed [r+r] operation. Returns false if it
1242 /// can be more efficiently represented with [r+imm].
1243 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1245 SelectionDAG &DAG) const {
1247 if (N.getOpcode() == ISD::ADD) {
1248 if (isIntS16Immediate(N.getOperand(1), imm))
1249 return false; // r+i
1250 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1251 return false; // r+i
1253 Base = N.getOperand(0);
1254 Index = N.getOperand(1);
1256 } else if (N.getOpcode() == ISD::OR) {
1257 if (isIntS16Immediate(N.getOperand(1), imm))
1258 return false; // r+i can fold it if we can.
1260 // If this is an or of disjoint bitfields, we can codegen this as an add
1261 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1263 APInt LHSKnownZero, LHSKnownOne;
1264 APInt RHSKnownZero, RHSKnownOne;
1265 DAG.computeKnownBits(N.getOperand(0),
1266 LHSKnownZero, LHSKnownOne);
1268 if (LHSKnownZero.getBoolValue()) {
1269 DAG.computeKnownBits(N.getOperand(1),
1270 RHSKnownZero, RHSKnownOne);
1271 // If all of the bits are known zero on the LHS or RHS, the add won't
1273 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1274 Base = N.getOperand(0);
1275 Index = N.getOperand(1);
1284 // If we happen to be doing an i64 load or store into a stack slot that has
1285 // less than a 4-byte alignment, then the frame-index elimination may need to
1286 // use an indexed load or store instruction (because the offset may not be a
1287 // multiple of 4). The extra register needed to hold the offset comes from the
1288 // register scavenger, and it is possible that the scavenger will need to use
1289 // an emergency spill slot. As a result, we need to make sure that a spill slot
1290 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1292 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1293 // FIXME: This does not handle the LWA case.
1297 // NOTE: We'll exclude negative FIs here, which come from argument
1298 // lowering, because there are no known test cases triggering this problem
1299 // using packed structures (or similar). We can remove this exclusion if
1300 // we find such a test case. The reason why this is so test-case driven is
1301 // because this entire 'fixup' is only to prevent crashes (from the
1302 // register scavenger) on not-really-valid inputs. For example, if we have:
1304 // %b = bitcast i1* %a to i64*
1305 // store i64* a, i64 b
1306 // then the store should really be marked as 'align 1', but is not. If it
1307 // were marked as 'align 1' then the indexed form would have been
1308 // instruction-selected initially, and the problem this 'fixup' is preventing
1309 // won't happen regardless.
1313 MachineFunction &MF = DAG.getMachineFunction();
1314 MachineFrameInfo *MFI = MF.getFrameInfo();
1316 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1320 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1321 FuncInfo->setHasNonRISpills();
1324 /// Returns true if the address N can be represented by a base register plus
1325 /// a signed 16-bit displacement [r+imm], and if it is not better
1326 /// represented as reg+reg. If Aligned is true, only accept displacements
1327 /// suitable for STD and friends, i.e. multiples of 4.
1328 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1331 bool Aligned) const {
1332 // FIXME dl should come from parent load or store, not from address
1334 // If this can be more profitably realized as r+r, fail.
1335 if (SelectAddressRegReg(N, Disp, Base, DAG))
1338 if (N.getOpcode() == ISD::ADD) {
1340 if (isIntS16Immediate(N.getOperand(1), imm) &&
1341 (!Aligned || (imm & 3) == 0)) {
1342 Disp = DAG.getTargetConstant(imm, N.getValueType());
1343 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1344 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1345 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1347 Base = N.getOperand(0);
1349 return true; // [r+i]
1350 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1351 // Match LOAD (ADD (X, Lo(G))).
1352 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1353 && "Cannot handle constant offsets yet!");
1354 Disp = N.getOperand(1).getOperand(0); // The global address.
1355 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1356 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1357 Disp.getOpcode() == ISD::TargetConstantPool ||
1358 Disp.getOpcode() == ISD::TargetJumpTable);
1359 Base = N.getOperand(0);
1360 return true; // [&g+r]
1362 } else if (N.getOpcode() == ISD::OR) {
1364 if (isIntS16Immediate(N.getOperand(1), imm) &&
1365 (!Aligned || (imm & 3) == 0)) {
1366 // If this is an or of disjoint bitfields, we can codegen this as an add
1367 // (for better address arithmetic) if the LHS and RHS of the OR are
1368 // provably disjoint.
1369 APInt LHSKnownZero, LHSKnownOne;
1370 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1372 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1373 // If all of the bits are known zero on the LHS or RHS, the add won't
1375 if (FrameIndexSDNode *FI =
1376 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1377 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1378 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1380 Base = N.getOperand(0);
1382 Disp = DAG.getTargetConstant(imm, N.getValueType());
1386 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1387 // Loading from a constant address.
1389 // If this address fits entirely in a 16-bit sext immediate field, codegen
1392 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1393 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1394 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1395 CN->getValueType(0));
1399 // Handle 32-bit sext immediates with LIS + addr mode.
1400 if ((CN->getValueType(0) == MVT::i32 ||
1401 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1402 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1403 int Addr = (int)CN->getZExtValue();
1405 // Otherwise, break this down into an LIS + disp.
1406 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1408 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1409 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1410 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1415 Disp = DAG.getTargetConstant(0, getPointerTy());
1416 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1417 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1418 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1421 return true; // [r+0]
1424 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1425 /// represented as an indexed [r+r] operation.
1426 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1428 SelectionDAG &DAG) const {
1429 // Check to see if we can easily represent this as an [r+r] address. This
1430 // will fail if it thinks that the address is more profitably represented as
1431 // reg+imm, e.g. where imm = 0.
1432 if (SelectAddressRegReg(N, Base, Index, DAG))
1435 // If the operand is an addition, always emit this as [r+r], since this is
1436 // better (for code size, and execution, as the memop does the add for free)
1437 // than emitting an explicit add.
1438 if (N.getOpcode() == ISD::ADD) {
1439 Base = N.getOperand(0);
1440 Index = N.getOperand(1);
1444 // Otherwise, do it the hard way, using R0 as the base register.
1445 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1451 /// getPreIndexedAddressParts - returns true by value, base pointer and
1452 /// offset pointer and addressing mode by reference if the node's address
1453 /// can be legally represented as pre-indexed load / store address.
1454 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1456 ISD::MemIndexedMode &AM,
1457 SelectionDAG &DAG) const {
1458 if (DisablePPCPreinc) return false;
1464 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1465 Ptr = LD->getBasePtr();
1466 VT = LD->getMemoryVT();
1467 Alignment = LD->getAlignment();
1468 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1469 Ptr = ST->getBasePtr();
1470 VT = ST->getMemoryVT();
1471 Alignment = ST->getAlignment();
1476 // PowerPC doesn't have preinc load/store instructions for vectors.
1480 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1482 // Common code will reject creating a pre-inc form if the base pointer
1483 // is a frame index, or if N is a store and the base pointer is either
1484 // the same as or a predecessor of the value being stored. Check for
1485 // those situations here, and try with swapped Base/Offset instead.
1488 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1491 SDValue Val = cast<StoreSDNode>(N)->getValue();
1492 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1497 std::swap(Base, Offset);
1503 // LDU/STU can only handle immediates that are a multiple of 4.
1504 if (VT != MVT::i64) {
1505 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1508 // LDU/STU need an address with at least 4-byte alignment.
1512 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1516 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1517 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1518 // sext i32 to i64 when addr mode is r+i.
1519 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1520 LD->getExtensionType() == ISD::SEXTLOAD &&
1521 isa<ConstantSDNode>(Offset))
1529 //===----------------------------------------------------------------------===//
1530 // LowerOperation implementation
1531 //===----------------------------------------------------------------------===//
1533 /// GetLabelAccessInfo - Return true if we should reference labels using a
1534 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1535 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1536 unsigned &LoOpFlags,
1537 const GlobalValue *GV = nullptr) {
1538 HiOpFlags = PPCII::MO_HA;
1539 LoOpFlags = PPCII::MO_LO;
1541 // Don't use the pic base if not in PIC relocation model.
1542 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1545 HiOpFlags |= PPCII::MO_PIC_FLAG;
1546 LoOpFlags |= PPCII::MO_PIC_FLAG;
1549 // If this is a reference to a global value that requires a non-lazy-ptr, make
1550 // sure that instruction lowering adds it.
1551 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1552 HiOpFlags |= PPCII::MO_NLP_FLAG;
1553 LoOpFlags |= PPCII::MO_NLP_FLAG;
1555 if (GV->hasHiddenVisibility()) {
1556 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1557 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1564 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1565 SelectionDAG &DAG) {
1566 EVT PtrVT = HiPart.getValueType();
1567 SDValue Zero = DAG.getConstant(0, PtrVT);
1570 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1571 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1573 // With PIC, the first instruction is actually "GR+hi(&G)".
1575 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1576 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1578 // Generate non-pic code that has direct accesses to the constant pool.
1579 // The address of the global is just (hi(&g)+lo(&g)).
1580 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1583 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1584 SelectionDAG &DAG) const {
1585 EVT PtrVT = Op.getValueType();
1586 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1587 const Constant *C = CP->getConstVal();
1589 // 64-bit SVR4 ABI code is always position-independent.
1590 // The actual address of the GlobalValue is stored in the TOC.
1591 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1592 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1593 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1594 DAG.getRegister(PPC::X2, MVT::i64));
1597 unsigned MOHiFlag, MOLoFlag;
1598 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1600 if (isPIC && Subtarget.isSVR4ABI()) {
1601 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1602 PPCII::MO_PIC_FLAG);
1604 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1605 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1609 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1611 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1612 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1615 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1616 EVT PtrVT = Op.getValueType();
1617 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1619 // 64-bit SVR4 ABI code is always position-independent.
1620 // The actual address of the GlobalValue is stored in the TOC.
1621 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1622 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1623 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1624 DAG.getRegister(PPC::X2, MVT::i64));
1627 unsigned MOHiFlag, MOLoFlag;
1628 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1630 if (isPIC && Subtarget.isSVR4ABI()) {
1631 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1632 PPCII::MO_PIC_FLAG);
1634 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1635 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1638 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1639 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1640 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1643 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1644 SelectionDAG &DAG) const {
1645 EVT PtrVT = Op.getValueType();
1647 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1649 unsigned MOHiFlag, MOLoFlag;
1650 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1651 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1652 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1653 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1656 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1657 SelectionDAG &DAG) const {
1659 // FIXME: TLS addresses currently use medium model code sequences,
1660 // which is the most useful form. Eventually support for small and
1661 // large models could be added if users need it, at the cost of
1662 // additional complexity.
1663 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1665 const GlobalValue *GV = GA->getGlobal();
1666 EVT PtrVT = getPointerTy();
1667 bool is64bit = Subtarget.isPPC64();
1669 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1671 if (Model == TLSModel::LocalExec) {
1672 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1673 PPCII::MO_TPREL_HA);
1674 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1675 PPCII::MO_TPREL_LO);
1676 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1677 is64bit ? MVT::i64 : MVT::i32);
1678 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1679 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1682 if (Model == TLSModel::InitialExec) {
1683 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1684 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1688 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1689 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1690 PtrVT, GOTReg, TGA);
1692 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1693 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1694 PtrVT, TGA, GOTPtr);
1695 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1698 if (Model == TLSModel::GeneralDynamic) {
1699 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1702 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1703 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1706 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1708 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1711 // We need a chain node, and don't have one handy. The underlying
1712 // call has no side effects, so using the function entry node
1714 SDValue Chain = DAG.getEntryNode();
1715 Chain = DAG.getCopyToReg(Chain, dl,
1716 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1717 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1718 is64bit ? MVT::i64 : MVT::i32);
1719 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1720 PtrVT, ParmReg, TGA);
1721 // The return value from GET_TLS_ADDR really is in X3 already, but
1722 // some hacks are needed here to tie everything together. The extra
1723 // copies dissolve during subsequent transforms.
1724 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1725 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1728 if (Model == TLSModel::LocalDynamic) {
1729 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1732 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1733 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1736 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1738 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1741 // We need a chain node, and don't have one handy. The underlying
1742 // call has no side effects, so using the function entry node
1744 SDValue Chain = DAG.getEntryNode();
1745 Chain = DAG.getCopyToReg(Chain, dl,
1746 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1747 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1748 is64bit ? MVT::i64 : MVT::i32);
1749 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1750 PtrVT, ParmReg, TGA);
1751 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1752 // some hacks are needed here to tie everything together. The extra
1753 // copies dissolve during subsequent transforms.
1754 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1755 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1756 Chain, ParmReg, TGA);
1757 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1760 llvm_unreachable("Unknown TLS model!");
1763 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1764 SelectionDAG &DAG) const {
1765 EVT PtrVT = Op.getValueType();
1766 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1768 const GlobalValue *GV = GSDN->getGlobal();
1770 // 64-bit SVR4 ABI code is always position-independent.
1771 // The actual address of the GlobalValue is stored in the TOC.
1772 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1773 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1774 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1775 DAG.getRegister(PPC::X2, MVT::i64));
1778 unsigned MOHiFlag, MOLoFlag;
1779 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1781 if (isPIC && Subtarget.isSVR4ABI()) {
1782 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1784 PPCII::MO_PIC_FLAG);
1785 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1786 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1790 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1792 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1794 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1796 // If the global reference is actually to a non-lazy-pointer, we have to do an
1797 // extra load to get the address of the global.
1798 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1799 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1800 false, false, false, 0);
1804 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1805 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1808 if (Op.getValueType() == MVT::v2i64) {
1809 // When the operands themselves are v2i64 values, we need to do something
1810 // special because VSX has no underlying comparison operations for these.
1811 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1812 // Equality can be handled by casting to the legal type for Altivec
1813 // comparisons, everything else needs to be expanded.
1814 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1815 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1816 DAG.getSetCC(dl, MVT::v4i32,
1817 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1818 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1825 // We handle most of these in the usual way.
1829 // If we're comparing for equality to zero, expose the fact that this is
1830 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1831 // fold the new nodes.
1832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1833 if (C->isNullValue() && CC == ISD::SETEQ) {
1834 EVT VT = Op.getOperand(0).getValueType();
1835 SDValue Zext = Op.getOperand(0);
1836 if (VT.bitsLT(MVT::i32)) {
1838 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1840 unsigned Log2b = Log2_32(VT.getSizeInBits());
1841 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1842 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1843 DAG.getConstant(Log2b, MVT::i32));
1844 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1846 // Leave comparisons against 0 and -1 alone for now, since they're usually
1847 // optimized. FIXME: revisit this when we can custom lower all setcc
1849 if (C->isAllOnesValue() || C->isNullValue())
1853 // If we have an integer seteq/setne, turn it into a compare against zero
1854 // by xor'ing the rhs with the lhs, which is faster than setting a
1855 // condition register, reading it back out, and masking the correct bit. The
1856 // normal approach here uses sub to do this instead of xor. Using xor exposes
1857 // the result to other bit-twiddling opportunities.
1858 EVT LHSVT = Op.getOperand(0).getValueType();
1859 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1860 EVT VT = Op.getValueType();
1861 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1863 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1868 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1869 const PPCSubtarget &Subtarget) const {
1870 SDNode *Node = Op.getNode();
1871 EVT VT = Node->getValueType(0);
1872 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1873 SDValue InChain = Node->getOperand(0);
1874 SDValue VAListPtr = Node->getOperand(1);
1875 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1878 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1881 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1882 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1883 false, false, false, 0);
1884 InChain = GprIndex.getValue(1);
1886 if (VT == MVT::i64) {
1887 // Check if GprIndex is even
1888 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1889 DAG.getConstant(1, MVT::i32));
1890 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1891 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1892 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1893 DAG.getConstant(1, MVT::i32));
1894 // Align GprIndex to be even if it isn't
1895 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1899 // fpr index is 1 byte after gpr
1900 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1901 DAG.getConstant(1, MVT::i32));
1904 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1905 FprPtr, MachinePointerInfo(SV), MVT::i8,
1906 false, false, false, 0);
1907 InChain = FprIndex.getValue(1);
1909 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1910 DAG.getConstant(8, MVT::i32));
1912 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1913 DAG.getConstant(4, MVT::i32));
1916 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1917 MachinePointerInfo(), false, false,
1919 InChain = OverflowArea.getValue(1);
1921 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1922 MachinePointerInfo(), false, false,
1924 InChain = RegSaveArea.getValue(1);
1926 // select overflow_area if index > 8
1927 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1928 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1930 // adjustment constant gpr_index * 4/8
1931 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1932 VT.isInteger() ? GprIndex : FprIndex,
1933 DAG.getConstant(VT.isInteger() ? 4 : 8,
1936 // OurReg = RegSaveArea + RegConstant
1937 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1940 // Floating types are 32 bytes into RegSaveArea
1941 if (VT.isFloatingPoint())
1942 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1943 DAG.getConstant(32, MVT::i32));
1945 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1946 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1947 VT.isInteger() ? GprIndex : FprIndex,
1948 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1951 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1952 VT.isInteger() ? VAListPtr : FprPtr,
1953 MachinePointerInfo(SV),
1954 MVT::i8, false, false, 0);
1956 // determine if we should load from reg_save_area or overflow_area
1957 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1959 // increase overflow_area by 4/8 if gpr/fpr > 8
1960 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1961 DAG.getConstant(VT.isInteger() ? 4 : 8,
1964 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1967 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1969 MachinePointerInfo(),
1970 MVT::i32, false, false, 0);
1972 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1973 false, false, false, 0);
1976 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1977 const PPCSubtarget &Subtarget) const {
1978 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1980 // We have to copy the entire va_list struct:
1981 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1982 return DAG.getMemcpy(Op.getOperand(0), Op,
1983 Op.getOperand(1), Op.getOperand(2),
1984 DAG.getConstant(12, MVT::i32), 8, false, true,
1985 MachinePointerInfo(), MachinePointerInfo());
1988 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1989 SelectionDAG &DAG) const {
1990 return Op.getOperand(0);
1993 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1994 SelectionDAG &DAG) const {
1995 SDValue Chain = Op.getOperand(0);
1996 SDValue Trmp = Op.getOperand(1); // trampoline
1997 SDValue FPtr = Op.getOperand(2); // nested function
1998 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2001 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2002 bool isPPC64 = (PtrVT == MVT::i64);
2004 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2007 TargetLowering::ArgListTy Args;
2008 TargetLowering::ArgListEntry Entry;
2010 Entry.Ty = IntPtrTy;
2011 Entry.Node = Trmp; Args.push_back(Entry);
2013 // TrampSize == (isPPC64 ? 48 : 40);
2014 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2015 isPPC64 ? MVT::i64 : MVT::i32);
2016 Args.push_back(Entry);
2018 Entry.Node = FPtr; Args.push_back(Entry);
2019 Entry.Node = Nest; Args.push_back(Entry);
2021 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2022 TargetLowering::CallLoweringInfo CLI(DAG);
2023 CLI.setDebugLoc(dl).setChain(Chain)
2024 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2025 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2026 std::move(Args), 0);
2028 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2029 return CallResult.second;
2032 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2033 const PPCSubtarget &Subtarget) const {
2034 MachineFunction &MF = DAG.getMachineFunction();
2035 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2039 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2040 // vastart just stores the address of the VarArgsFrameIndex slot into the
2041 // memory location argument.
2042 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2043 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2044 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2045 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2046 MachinePointerInfo(SV),
2050 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2051 // We suppose the given va_list is already allocated.
2054 // char gpr; /* index into the array of 8 GPRs
2055 // * stored in the register save area
2056 // * gpr=0 corresponds to r3,
2057 // * gpr=1 to r4, etc.
2059 // char fpr; /* index into the array of 8 FPRs
2060 // * stored in the register save area
2061 // * fpr=0 corresponds to f1,
2062 // * fpr=1 to f2, etc.
2064 // char *overflow_arg_area;
2065 // /* location on stack that holds
2066 // * the next overflow argument
2068 // char *reg_save_area;
2069 // /* where r3:r10 and f1:f8 (if saved)
2075 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2076 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2079 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2081 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2083 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2086 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2087 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2089 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2090 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2092 uint64_t FPROffset = 1;
2093 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2095 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2097 // Store first byte : number of int regs
2098 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2100 MachinePointerInfo(SV),
2101 MVT::i8, false, false, 0);
2102 uint64_t nextOffset = FPROffset;
2103 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2106 // Store second byte : number of float regs
2107 SDValue secondStore =
2108 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2109 MachinePointerInfo(SV, nextOffset), MVT::i8,
2111 nextOffset += StackOffset;
2112 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2114 // Store second word : arguments given on stack
2115 SDValue thirdStore =
2116 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2117 MachinePointerInfo(SV, nextOffset),
2119 nextOffset += FrameOffset;
2120 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2122 // Store third word : arguments given in registers
2123 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2124 MachinePointerInfo(SV, nextOffset),
2129 #include "PPCGenCallingConv.inc"
2131 // Function whose sole purpose is to kill compiler warnings
2132 // stemming from unused functions included from PPCGenCallingConv.inc.
2133 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2134 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2137 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2138 CCValAssign::LocInfo &LocInfo,
2139 ISD::ArgFlagsTy &ArgFlags,
2144 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2146 CCValAssign::LocInfo &LocInfo,
2147 ISD::ArgFlagsTy &ArgFlags,
2149 static const MCPhysReg ArgRegs[] = {
2150 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2151 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2153 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2155 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2157 // Skip one register if the first unallocated register has an even register
2158 // number and there are still argument registers available which have not been
2159 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2160 // need to skip a register if RegNum is odd.
2161 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2162 State.AllocateReg(ArgRegs[RegNum]);
2165 // Always return false here, as this function only makes sure that the first
2166 // unallocated register has an odd register number and does not actually
2167 // allocate a register for the current argument.
2171 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2173 CCValAssign::LocInfo &LocInfo,
2174 ISD::ArgFlagsTy &ArgFlags,
2176 static const MCPhysReg ArgRegs[] = {
2177 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2181 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2183 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2185 // If there is only one Floating-point register left we need to put both f64
2186 // values of a split ppc_fp128 value on the stack.
2187 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2188 State.AllocateReg(ArgRegs[RegNum]);
2191 // Always return false here, as this function only makes sure that the two f64
2192 // values a ppc_fp128 value is split into are both passed in registers or both
2193 // passed on the stack and does not actually allocate a register for the
2194 // current argument.
2198 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2200 static const MCPhysReg *GetFPR() {
2201 static const MCPhysReg FPR[] = {
2202 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2203 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2209 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2211 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2212 unsigned PtrByteSize) {
2213 unsigned ArgSize = ArgVT.getStoreSize();
2214 if (Flags.isByVal())
2215 ArgSize = Flags.getByValSize();
2217 // Round up to multiples of the pointer size, except for array members,
2218 // which are always packed.
2219 if (!Flags.isInConsecutiveRegs())
2220 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2225 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2227 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2228 ISD::ArgFlagsTy Flags,
2229 unsigned PtrByteSize) {
2230 unsigned Align = PtrByteSize;
2232 // Altivec parameters are padded to a 16 byte boundary.
2233 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2234 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2235 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2238 // ByVal parameters are aligned as requested.
2239 if (Flags.isByVal()) {
2240 unsigned BVAlign = Flags.getByValAlign();
2241 if (BVAlign > PtrByteSize) {
2242 if (BVAlign % PtrByteSize != 0)
2244 "ByVal alignment is not a multiple of the pointer size");
2250 // Array members are always packed to their original alignment.
2251 if (Flags.isInConsecutiveRegs()) {
2252 // If the array member was split into multiple registers, the first
2253 // needs to be aligned to the size of the full type. (Except for
2254 // ppcf128, which is only aligned as its f64 components.)
2255 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2256 Align = OrigVT.getStoreSize();
2258 Align = ArgVT.getStoreSize();
2264 /// CalculateStackSlotUsed - Return whether this argument will use its
2265 /// stack slot (instead of being passed in registers). ArgOffset,
2266 /// AvailableFPRs, and AvailableVRs must hold the current argument
2267 /// position, and will be updated to account for this argument.
2268 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2269 ISD::ArgFlagsTy Flags,
2270 unsigned PtrByteSize,
2271 unsigned LinkageSize,
2272 unsigned ParamAreaSize,
2273 unsigned &ArgOffset,
2274 unsigned &AvailableFPRs,
2275 unsigned &AvailableVRs) {
2276 bool UseMemory = false;
2278 // Respect alignment of argument on the stack.
2280 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2281 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2282 // If there's no space left in the argument save area, we must
2283 // use memory (this check also catches zero-sized arguments).
2284 if (ArgOffset >= LinkageSize + ParamAreaSize)
2287 // Allocate argument on the stack.
2288 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2289 if (Flags.isInConsecutiveRegsLast())
2290 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2291 // If we overran the argument save area, we must use memory
2292 // (this check catches arguments passed partially in memory)
2293 if (ArgOffset > LinkageSize + ParamAreaSize)
2296 // However, if the argument is actually passed in an FPR or a VR,
2297 // we don't use memory after all.
2298 if (!Flags.isByVal()) {
2299 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2300 if (AvailableFPRs > 0) {
2304 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2305 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2306 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2307 if (AvailableVRs > 0) {
2316 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2317 /// ensure minimum alignment required for target.
2318 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2319 unsigned NumBytes) {
2320 unsigned TargetAlign =
2321 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2322 unsigned AlignMask = TargetAlign - 1;
2323 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2328 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2329 CallingConv::ID CallConv, bool isVarArg,
2330 const SmallVectorImpl<ISD::InputArg>
2332 SDLoc dl, SelectionDAG &DAG,
2333 SmallVectorImpl<SDValue> &InVals)
2335 if (Subtarget.isSVR4ABI()) {
2336 if (Subtarget.isPPC64())
2337 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2340 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2343 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2349 PPCTargetLowering::LowerFormalArguments_32SVR4(
2351 CallingConv::ID CallConv, bool isVarArg,
2352 const SmallVectorImpl<ISD::InputArg>
2354 SDLoc dl, SelectionDAG &DAG,
2355 SmallVectorImpl<SDValue> &InVals) const {
2357 // 32-bit SVR4 ABI Stack Frame Layout:
2358 // +-----------------------------------+
2359 // +--> | Back chain |
2360 // | +-----------------------------------+
2361 // | | Floating-point register save area |
2362 // | +-----------------------------------+
2363 // | | General register save area |
2364 // | +-----------------------------------+
2365 // | | CR save word |
2366 // | +-----------------------------------+
2367 // | | VRSAVE save word |
2368 // | +-----------------------------------+
2369 // | | Alignment padding |
2370 // | +-----------------------------------+
2371 // | | Vector register save area |
2372 // | +-----------------------------------+
2373 // | | Local variable space |
2374 // | +-----------------------------------+
2375 // | | Parameter list area |
2376 // | +-----------------------------------+
2377 // | | LR save word |
2378 // | +-----------------------------------+
2379 // SP--> +--- | Back chain |
2380 // +-----------------------------------+
2383 // System V Application Binary Interface PowerPC Processor Supplement
2384 // AltiVec Technology Programming Interface Manual
2386 MachineFunction &MF = DAG.getMachineFunction();
2387 MachineFrameInfo *MFI = MF.getFrameInfo();
2388 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2390 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2391 // Potential tail calls could cause overwriting of argument stack slots.
2392 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2393 (CallConv == CallingConv::Fast));
2394 unsigned PtrByteSize = 4;
2396 // Assign locations to all of the incoming arguments.
2397 SmallVector<CCValAssign, 16> ArgLocs;
2398 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2399 getTargetMachine(), ArgLocs, *DAG.getContext());
2401 // Reserve space for the linkage area on the stack.
2402 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2403 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2405 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2407 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2408 CCValAssign &VA = ArgLocs[i];
2410 // Arguments stored in registers.
2411 if (VA.isRegLoc()) {
2412 const TargetRegisterClass *RC;
2413 EVT ValVT = VA.getValVT();
2415 switch (ValVT.getSimpleVT().SimpleTy) {
2417 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2420 RC = &PPC::GPRCRegClass;
2423 RC = &PPC::F4RCRegClass;
2426 if (Subtarget.hasVSX())
2427 RC = &PPC::VSFRCRegClass;
2429 RC = &PPC::F8RCRegClass;
2435 RC = &PPC::VRRCRegClass;
2439 RC = &PPC::VSHRCRegClass;
2443 // Transform the arguments stored in physical registers into virtual ones.
2444 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2445 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2446 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2448 if (ValVT == MVT::i1)
2449 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2451 InVals.push_back(ArgValue);
2453 // Argument stored in memory.
2454 assert(VA.isMemLoc());
2456 unsigned ArgSize = VA.getLocVT().getStoreSize();
2457 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2460 // Create load nodes to retrieve arguments from the stack.
2461 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2462 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2463 MachinePointerInfo(),
2464 false, false, false, 0));
2468 // Assign locations to all of the incoming aggregate by value arguments.
2469 // Aggregates passed by value are stored in the local variable space of the
2470 // caller's stack frame, right above the parameter list area.
2471 SmallVector<CCValAssign, 16> ByValArgLocs;
2472 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2473 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2475 // Reserve stack space for the allocations in CCInfo.
2476 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2478 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2480 // Area that is at least reserved in the caller of this function.
2481 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2482 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2484 // Set the size that is at least reserved in caller of this function. Tail
2485 // call optimized function's reserved stack space needs to be aligned so that
2486 // taking the difference between two stack areas will result in an aligned
2488 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2489 FuncInfo->setMinReservedArea(MinReservedArea);
2491 SmallVector<SDValue, 8> MemOps;
2493 // If the function takes variable number of arguments, make a frame index for
2494 // the start of the first vararg value... for expansion of llvm.va_start.
2496 static const MCPhysReg GPArgRegs[] = {
2497 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2498 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2500 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2502 static const MCPhysReg FPArgRegs[] = {
2503 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2506 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2508 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2510 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2513 // Make room for NumGPArgRegs and NumFPArgRegs.
2514 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2515 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2517 FuncInfo->setVarArgsStackOffset(
2518 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2519 CCInfo.getNextStackOffset(), true));
2521 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2522 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2524 // The fixed integer arguments of a variadic function are stored to the
2525 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2526 // the result of va_next.
2527 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2528 // Get an existing live-in vreg, or add a new one.
2529 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2531 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2533 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2534 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2535 MachinePointerInfo(), false, false, 0);
2536 MemOps.push_back(Store);
2537 // Increment the address by four for the next argument to store
2538 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2539 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2542 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2544 // The double arguments are stored to the VarArgsFrameIndex
2546 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2547 // Get an existing live-in vreg, or add a new one.
2548 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2550 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2552 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2553 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2554 MachinePointerInfo(), false, false, 0);
2555 MemOps.push_back(Store);
2556 // Increment the address by eight for the next argument to store
2557 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2559 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2563 if (!MemOps.empty())
2564 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2569 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2570 // value to MVT::i64 and then truncate to the correct register size.
2572 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2573 SelectionDAG &DAG, SDValue ArgVal,
2576 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2577 DAG.getValueType(ObjectVT));
2578 else if (Flags.isZExt())
2579 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2580 DAG.getValueType(ObjectVT));
2582 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2586 PPCTargetLowering::LowerFormalArguments_64SVR4(
2588 CallingConv::ID CallConv, bool isVarArg,
2589 const SmallVectorImpl<ISD::InputArg>
2591 SDLoc dl, SelectionDAG &DAG,
2592 SmallVectorImpl<SDValue> &InVals) const {
2593 // TODO: add description of PPC stack frame format, or at least some docs.
2595 bool isELFv2ABI = Subtarget.isELFv2ABI();
2596 bool isLittleEndian = Subtarget.isLittleEndian();
2597 MachineFunction &MF = DAG.getMachineFunction();
2598 MachineFrameInfo *MFI = MF.getFrameInfo();
2599 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2601 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2602 // Potential tail calls could cause overwriting of argument stack slots.
2603 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2604 (CallConv == CallingConv::Fast));
2605 unsigned PtrByteSize = 8;
2607 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2610 static const MCPhysReg GPR[] = {
2611 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2612 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2615 static const MCPhysReg *FPR = GetFPR();
2617 static const MCPhysReg VR[] = {
2618 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2619 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2621 static const MCPhysReg VSRH[] = {
2622 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2623 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2626 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2627 const unsigned Num_FPR_Regs = 13;
2628 const unsigned Num_VR_Regs = array_lengthof(VR);
2630 // Do a first pass over the arguments to determine whether the ABI
2631 // guarantees that our caller has allocated the parameter save area
2632 // on its stack frame. In the ELFv1 ABI, this is always the case;
2633 // in the ELFv2 ABI, it is true if this is a vararg function or if
2634 // any parameter is located in a stack slot.
2636 bool HasParameterArea = !isELFv2ABI || isVarArg;
2637 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2638 unsigned NumBytes = LinkageSize;
2639 unsigned AvailableFPRs = Num_FPR_Regs;
2640 unsigned AvailableVRs = Num_VR_Regs;
2641 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2642 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2643 PtrByteSize, LinkageSize, ParamAreaSize,
2644 NumBytes, AvailableFPRs, AvailableVRs))
2645 HasParameterArea = true;
2647 // Add DAG nodes to load the arguments or copy them out of registers. On
2648 // entry to a function on PPC, the arguments start after the linkage area,
2649 // although the first ones are often in registers.
2651 unsigned ArgOffset = LinkageSize;
2652 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2653 SmallVector<SDValue, 8> MemOps;
2654 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2655 unsigned CurArgIdx = 0;
2656 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2658 bool needsLoad = false;
2659 EVT ObjectVT = Ins[ArgNo].VT;
2660 EVT OrigVT = Ins[ArgNo].ArgVT;
2661 unsigned ObjSize = ObjectVT.getStoreSize();
2662 unsigned ArgSize = ObjSize;
2663 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2664 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2665 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2667 /* Respect alignment of argument on the stack. */
2669 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2670 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2671 unsigned CurArgOffset = ArgOffset;
2673 /* Compute GPR index associated with argument offset. */
2674 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2675 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2677 // FIXME the codegen can be much improved in some cases.
2678 // We do not have to keep everything in memory.
2679 if (Flags.isByVal()) {
2680 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2681 ObjSize = Flags.getByValSize();
2682 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2683 // Empty aggregate parameters do not take up registers. Examples:
2687 // etc. However, we have to provide a place-holder in InVals, so
2688 // pretend we have an 8-byte item at the current address for that
2691 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2692 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2693 InVals.push_back(FIN);
2697 // Create a stack object covering all stack doublewords occupied
2698 // by the argument. If the argument is (fully or partially) on
2699 // the stack, or if the argument is fully in registers but the
2700 // caller has allocated the parameter save anyway, we can refer
2701 // directly to the caller's stack frame. Otherwise, create a
2702 // local copy in our own frame.
2704 if (HasParameterArea ||
2705 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2706 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2708 FI = MFI->CreateStackObject(ArgSize, Align, false);
2709 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2711 // Handle aggregates smaller than 8 bytes.
2712 if (ObjSize < PtrByteSize) {
2713 // The value of the object is its address, which differs from the
2714 // address of the enclosing doubleword on big-endian systems.
2716 if (!isLittleEndian) {
2717 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2718 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2720 InVals.push_back(Arg);
2722 if (GPR_idx != Num_GPR_Regs) {
2723 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2724 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2727 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2728 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2729 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2730 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2731 MachinePointerInfo(FuncArg),
2732 ObjType, false, false, 0);
2734 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2735 // store the whole register as-is to the parameter save area
2737 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2738 MachinePointerInfo(FuncArg),
2742 MemOps.push_back(Store);
2744 // Whether we copied from a register or not, advance the offset
2745 // into the parameter save area by a full doubleword.
2746 ArgOffset += PtrByteSize;
2750 // The value of the object is its address, which is the address of
2751 // its first stack doubleword.
2752 InVals.push_back(FIN);
2754 // Store whatever pieces of the object are in registers to memory.
2755 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2756 if (GPR_idx == Num_GPR_Regs)
2759 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2760 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2763 SDValue Off = DAG.getConstant(j, PtrVT);
2764 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2766 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2767 MachinePointerInfo(FuncArg, j),
2769 MemOps.push_back(Store);
2772 ArgOffset += ArgSize;
2776 switch (ObjectVT.getSimpleVT().SimpleTy) {
2777 default: llvm_unreachable("Unhandled argument type!");
2781 // These can be scalar arguments or elements of an integer array type
2782 // passed directly. Clang may use those instead of "byval" aggregate
2783 // types to avoid forcing arguments to memory unnecessarily.
2784 if (GPR_idx != Num_GPR_Regs) {
2785 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2786 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2788 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2789 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2790 // value to MVT::i64 and then truncate to the correct register size.
2791 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2794 ArgSize = PtrByteSize;
2801 // These can be scalar arguments or elements of a float array type
2802 // passed directly. The latter are used to implement ELFv2 homogenous
2803 // float aggregates.
2804 if (FPR_idx != Num_FPR_Regs) {
2807 if (ObjectVT == MVT::f32)
2808 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2810 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2811 &PPC::VSFRCRegClass :
2812 &PPC::F8RCRegClass);
2814 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2816 } else if (GPR_idx != Num_GPR_Regs) {
2817 // This can only ever happen in the presence of f32 array types,
2818 // since otherwise we never run out of FPRs before running out
2820 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2821 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2823 if (ObjectVT == MVT::f32) {
2824 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2825 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2826 DAG.getConstant(32, MVT::i32));
2827 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2830 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2835 // When passing an array of floats, the array occupies consecutive
2836 // space in the argument area; only round up to the next doubleword
2837 // at the end of the array. Otherwise, each float takes 8 bytes.
2838 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2839 ArgOffset += ArgSize;
2840 if (Flags.isInConsecutiveRegsLast())
2841 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2849 // These can be scalar arguments or elements of a vector array type
2850 // passed directly. The latter are used to implement ELFv2 homogenous
2851 // vector aggregates.
2852 if (VR_idx != Num_VR_Regs) {
2853 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2854 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2855 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2856 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2865 // We need to load the argument to a virtual register if we determined
2866 // above that we ran out of physical registers of the appropriate type.
2868 if (ObjSize < ArgSize && !isLittleEndian)
2869 CurArgOffset += ArgSize - ObjSize;
2870 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2871 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2872 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2873 false, false, false, 0);
2876 InVals.push_back(ArgVal);
2879 // Area that is at least reserved in the caller of this function.
2880 unsigned MinReservedArea;
2881 if (HasParameterArea)
2882 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2884 MinReservedArea = LinkageSize;
2886 // Set the size that is at least reserved in caller of this function. Tail
2887 // call optimized functions' reserved stack space needs to be aligned so that
2888 // taking the difference between two stack areas will result in an aligned
2890 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2891 FuncInfo->setMinReservedArea(MinReservedArea);
2893 // If the function takes variable number of arguments, make a frame index for
2894 // the start of the first vararg value... for expansion of llvm.va_start.
2896 int Depth = ArgOffset;
2898 FuncInfo->setVarArgsFrameIndex(
2899 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2900 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2902 // If this function is vararg, store any remaining integer argument regs
2903 // to their spots on the stack so that they may be loaded by deferencing the
2904 // result of va_next.
2905 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2906 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2907 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2908 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2909 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2910 MachinePointerInfo(), false, false, 0);
2911 MemOps.push_back(Store);
2912 // Increment the address by four for the next argument to store
2913 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2914 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2918 if (!MemOps.empty())
2919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2925 PPCTargetLowering::LowerFormalArguments_Darwin(
2927 CallingConv::ID CallConv, bool isVarArg,
2928 const SmallVectorImpl<ISD::InputArg>
2930 SDLoc dl, SelectionDAG &DAG,
2931 SmallVectorImpl<SDValue> &InVals) const {
2932 // TODO: add description of PPC stack frame format, or at least some docs.
2934 MachineFunction &MF = DAG.getMachineFunction();
2935 MachineFrameInfo *MFI = MF.getFrameInfo();
2936 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2938 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2939 bool isPPC64 = PtrVT == MVT::i64;
2940 // Potential tail calls could cause overwriting of argument stack slots.
2941 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2942 (CallConv == CallingConv::Fast));
2943 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2945 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2947 unsigned ArgOffset = LinkageSize;
2948 // Area that is at least reserved in caller of this function.
2949 unsigned MinReservedArea = ArgOffset;
2951 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2952 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2953 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2955 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2956 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2957 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2960 static const MCPhysReg *FPR = GetFPR();
2962 static const MCPhysReg VR[] = {
2963 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2964 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2967 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2968 const unsigned Num_FPR_Regs = 13;
2969 const unsigned Num_VR_Regs = array_lengthof( VR);
2971 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2973 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2975 // In 32-bit non-varargs functions, the stack space for vectors is after the
2976 // stack space for non-vectors. We do not use this space unless we have
2977 // too many vectors to fit in registers, something that only occurs in
2978 // constructed examples:), but we have to walk the arglist to figure
2979 // that out...for the pathological case, compute VecArgOffset as the
2980 // start of the vector parameter area. Computing VecArgOffset is the
2981 // entire point of the following loop.
2982 unsigned VecArgOffset = ArgOffset;
2983 if (!isVarArg && !isPPC64) {
2984 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2986 EVT ObjectVT = Ins[ArgNo].VT;
2987 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2989 if (Flags.isByVal()) {
2990 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2991 unsigned ObjSize = Flags.getByValSize();
2993 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2994 VecArgOffset += ArgSize;
2998 switch(ObjectVT.getSimpleVT().SimpleTy) {
2999 default: llvm_unreachable("Unhandled argument type!");
3005 case MVT::i64: // PPC64
3007 // FIXME: We are guaranteed to be !isPPC64 at this point.
3008 // Does MVT::i64 apply?
3015 // Nothing to do, we're only looking at Nonvector args here.
3020 // We've found where the vector parameter area in memory is. Skip the
3021 // first 12 parameters; these don't use that memory.
3022 VecArgOffset = ((VecArgOffset+15)/16)*16;
3023 VecArgOffset += 12*16;
3025 // Add DAG nodes to load the arguments or copy them out of registers. On
3026 // entry to a function on PPC, the arguments start after the linkage area,
3027 // although the first ones are often in registers.
3029 SmallVector<SDValue, 8> MemOps;
3030 unsigned nAltivecParamsAtEnd = 0;
3031 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3032 unsigned CurArgIdx = 0;
3033 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3035 bool needsLoad = false;
3036 EVT ObjectVT = Ins[ArgNo].VT;
3037 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3038 unsigned ArgSize = ObjSize;
3039 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3040 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3041 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3043 unsigned CurArgOffset = ArgOffset;
3045 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3046 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3047 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3048 if (isVarArg || isPPC64) {
3049 MinReservedArea = ((MinReservedArea+15)/16)*16;
3050 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3053 } else nAltivecParamsAtEnd++;
3055 // Calculate min reserved area.
3056 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3060 // FIXME the codegen can be much improved in some cases.
3061 // We do not have to keep everything in memory.
3062 if (Flags.isByVal()) {
3063 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3064 ObjSize = Flags.getByValSize();
3065 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3066 // Objects of size 1 and 2 are right justified, everything else is
3067 // left justified. This means the memory address is adjusted forwards.
3068 if (ObjSize==1 || ObjSize==2) {
3069 CurArgOffset = CurArgOffset + (4 - ObjSize);
3071 // The value of the object is its address.
3072 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3073 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3074 InVals.push_back(FIN);
3075 if (ObjSize==1 || ObjSize==2) {
3076 if (GPR_idx != Num_GPR_Regs) {
3079 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3081 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3082 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3083 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3084 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3085 MachinePointerInfo(FuncArg),
3086 ObjType, false, false, 0);
3087 MemOps.push_back(Store);
3091 ArgOffset += PtrByteSize;
3095 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3096 // Store whatever pieces of the object are in registers
3097 // to memory. ArgOffset will be the address of the beginning
3099 if (GPR_idx != Num_GPR_Regs) {
3102 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3104 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3105 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3106 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3107 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3108 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3109 MachinePointerInfo(FuncArg, j),
3111 MemOps.push_back(Store);
3113 ArgOffset += PtrByteSize;
3115 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3122 switch (ObjectVT.getSimpleVT().SimpleTy) {
3123 default: llvm_unreachable("Unhandled argument type!");
3127 if (GPR_idx != Num_GPR_Regs) {
3128 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3129 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3131 if (ObjectVT == MVT::i1)
3132 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3137 ArgSize = PtrByteSize;
3139 // All int arguments reserve stack space in the Darwin ABI.
3140 ArgOffset += PtrByteSize;
3144 case MVT::i64: // PPC64
3145 if (GPR_idx != Num_GPR_Regs) {
3146 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3147 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3149 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3150 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3151 // value to MVT::i64 and then truncate to the correct register size.
3152 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3157 ArgSize = PtrByteSize;
3159 // All int arguments reserve stack space in the Darwin ABI.
3165 // Every 4 bytes of argument space consumes one of the GPRs available for
3166 // argument passing.
3167 if (GPR_idx != Num_GPR_Regs) {
3169 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3172 if (FPR_idx != Num_FPR_Regs) {
3175 if (ObjectVT == MVT::f32)
3176 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3178 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3180 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3186 // All FP arguments reserve stack space in the Darwin ABI.
3187 ArgOffset += isPPC64 ? 8 : ObjSize;
3193 // Note that vector arguments in registers don't reserve stack space,
3194 // except in varargs functions.
3195 if (VR_idx != Num_VR_Regs) {
3196 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3197 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3199 while ((ArgOffset % 16) != 0) {
3200 ArgOffset += PtrByteSize;
3201 if (GPR_idx != Num_GPR_Regs)
3205 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3209 if (!isVarArg && !isPPC64) {
3210 // Vectors go after all the nonvectors.
3211 CurArgOffset = VecArgOffset;
3214 // Vectors are aligned.
3215 ArgOffset = ((ArgOffset+15)/16)*16;
3216 CurArgOffset = ArgOffset;
3224 // We need to load the argument to a virtual register if we determined above
3225 // that we ran out of physical registers of the appropriate type.
3227 int FI = MFI->CreateFixedObject(ObjSize,
3228 CurArgOffset + (ArgSize - ObjSize),
3230 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3231 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3232 false, false, false, 0);
3235 InVals.push_back(ArgVal);
3238 // Allow for Altivec parameters at the end, if needed.
3239 if (nAltivecParamsAtEnd) {
3240 MinReservedArea = ((MinReservedArea+15)/16)*16;
3241 MinReservedArea += 16*nAltivecParamsAtEnd;
3244 // Area that is at least reserved in the caller of this function.
3245 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3247 // Set the size that is at least reserved in caller of this function. Tail
3248 // call optimized functions' reserved stack space needs to be aligned so that
3249 // taking the difference between two stack areas will result in an aligned
3251 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3252 FuncInfo->setMinReservedArea(MinReservedArea);
3254 // If the function takes variable number of arguments, make a frame index for
3255 // the start of the first vararg value... for expansion of llvm.va_start.
3257 int Depth = ArgOffset;
3259 FuncInfo->setVarArgsFrameIndex(
3260 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3262 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3264 // If this function is vararg, store any remaining integer argument regs
3265 // to their spots on the stack so that they may be loaded by deferencing the
3266 // result of va_next.
3267 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3271 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3273 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3275 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3276 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3277 MachinePointerInfo(), false, false, 0);
3278 MemOps.push_back(Store);
3279 // Increment the address by four for the next argument to store
3280 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3281 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3285 if (!MemOps.empty())
3286 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3291 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3292 /// adjusted to accommodate the arguments for the tailcall.
3293 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3294 unsigned ParamSize) {
3296 if (!isTailCall) return 0;
3298 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3299 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3300 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3301 // Remember only if the new adjustement is bigger.
3302 if (SPDiff < FI->getTailCallSPDelta())
3303 FI->setTailCallSPDelta(SPDiff);
3308 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3309 /// for tail call optimization. Targets which want to do tail call
3310 /// optimization should implement this function.
3312 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3313 CallingConv::ID CalleeCC,
3315 const SmallVectorImpl<ISD::InputArg> &Ins,
3316 SelectionDAG& DAG) const {
3317 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3320 // Variable argument functions are not supported.
3324 MachineFunction &MF = DAG.getMachineFunction();
3325 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3326 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3327 // Functions containing by val parameters are not supported.
3328 for (unsigned i = 0; i != Ins.size(); i++) {
3329 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3330 if (Flags.isByVal()) return false;
3333 // Non-PIC/GOT tail calls are supported.
3334 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3337 // At the moment we can only do local tail calls (in same module, hidden
3338 // or protected) if we are generating PIC.
3339 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3340 return G->getGlobal()->hasHiddenVisibility()
3341 || G->getGlobal()->hasProtectedVisibility();
3347 /// isCallCompatibleAddress - Return the immediate to use if the specified
3348 /// 32-bit value is representable in the immediate field of a BxA instruction.
3349 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3350 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3351 if (!C) return nullptr;
3353 int Addr = C->getZExtValue();
3354 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3355 SignExtend32<26>(Addr) != Addr)
3356 return nullptr; // Top 6 bits have to be sext of immediate.
3358 return DAG.getConstant((int)C->getZExtValue() >> 2,
3359 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3364 struct TailCallArgumentInfo {
3369 TailCallArgumentInfo() : FrameIdx(0) {}
3374 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3376 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3378 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3379 SmallVectorImpl<SDValue> &MemOpChains,
3381 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3382 SDValue Arg = TailCallArgs[i].Arg;
3383 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3384 int FI = TailCallArgs[i].FrameIdx;
3385 // Store relative to framepointer.
3386 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3387 MachinePointerInfo::getFixedStack(FI),
3392 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3393 /// the appropriate stack slot for the tail call optimized function call.
3394 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3395 MachineFunction &MF,
3404 // Calculate the new stack slot for the return address.
3405 int SlotSize = isPPC64 ? 8 : 4;
3406 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3408 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3409 NewRetAddrLoc, true);
3410 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3411 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3412 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3413 MachinePointerInfo::getFixedStack(NewRetAddr),
3416 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3417 // slot as the FP is never overwritten.
3420 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3421 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3423 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3424 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3425 MachinePointerInfo::getFixedStack(NewFPIdx),
3432 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3433 /// the position of the argument.
3435 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3436 SDValue Arg, int SPDiff, unsigned ArgOffset,
3437 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3438 int Offset = ArgOffset + SPDiff;
3439 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3440 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3441 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3442 SDValue FIN = DAG.getFrameIndex(FI, VT);
3443 TailCallArgumentInfo Info;
3445 Info.FrameIdxOp = FIN;
3447 TailCallArguments.push_back(Info);
3450 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3451 /// stack slot. Returns the chain as result and the loaded frame pointers in
3452 /// LROpOut/FPOpout. Used when tail calling.
3453 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3461 // Load the LR and FP stack slot for later adjusting.
3462 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3463 LROpOut = getReturnAddrFrameIndex(DAG);
3464 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3465 false, false, false, 0);
3466 Chain = SDValue(LROpOut.getNode(), 1);
3468 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3469 // slot as the FP is never overwritten.
3471 FPOpOut = getFramePointerFrameIndex(DAG);
3472 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3473 false, false, false, 0);
3474 Chain = SDValue(FPOpOut.getNode(), 1);
3480 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3481 /// by "Src" to address "Dst" of size "Size". Alignment information is
3482 /// specified by the specific parameter attribute. The copy will be passed as
3483 /// a byval function parameter.
3484 /// Sometimes what we are copying is the end of a larger object, the part that
3485 /// does not fit in registers.
3487 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3488 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3490 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3491 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3492 false, false, MachinePointerInfo(),
3493 MachinePointerInfo());
3496 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3499 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3500 SDValue Arg, SDValue PtrOff, int SPDiff,
3501 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3502 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3503 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3505 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3510 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3512 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3513 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3514 DAG.getConstant(ArgOffset, PtrVT));
3516 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3517 MachinePointerInfo(), false, false, 0));
3518 // Calculate and remember argument location.
3519 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3524 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3525 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3526 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3527 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3528 MachineFunction &MF = DAG.getMachineFunction();
3530 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3531 // might overwrite each other in case of tail call optimization.
3532 SmallVector<SDValue, 8> MemOpChains2;
3533 // Do not flag preceding copytoreg stuff together with the following stuff.
3535 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3537 if (!MemOpChains2.empty())
3538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3540 // Store the return address to the appropriate stack slot.
3541 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3542 isPPC64, isDarwinABI, dl);
3544 // Emit callseq_end just before tailcall node.
3545 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3546 DAG.getIntPtrConstant(0, true), InFlag, dl);
3547 InFlag = Chain.getValue(1);
3551 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3552 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3553 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3554 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3555 const PPCSubtarget &Subtarget) {
3557 bool isPPC64 = Subtarget.isPPC64();
3558 bool isSVR4ABI = Subtarget.isSVR4ABI();
3559 bool isELFv2ABI = Subtarget.isELFv2ABI();
3561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3562 NodeTys.push_back(MVT::Other); // Returns a chain
3563 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3565 unsigned CallOpc = PPCISD::CALL;
3567 bool needIndirectCall = true;
3568 if (!isSVR4ABI || !isPPC64)
3569 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3570 // If this is an absolute destination address, use the munged value.
3571 Callee = SDValue(Dest, 0);
3572 needIndirectCall = false;
3575 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3576 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3577 // Use indirect calls for ALL functions calls in JIT mode, since the
3578 // far-call stubs may be outside relocation limits for a BL instruction.
3579 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3580 unsigned OpFlags = 0;
3581 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3582 (Subtarget.getTargetTriple().isMacOSX() &&
3583 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3584 (G->getGlobal()->isDeclaration() ||
3585 G->getGlobal()->isWeakForLinker())) ||
3586 (Subtarget.isTargetELF() && !isPPC64 &&
3587 !G->getGlobal()->hasLocalLinkage() &&
3588 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3589 // PC-relative references to external symbols should go through $stub,
3590 // unless we're building with the leopard linker or later, which
3591 // automatically synthesizes these stubs.
3592 OpFlags = PPCII::MO_PLT_OR_STUB;
3595 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3596 // every direct call is) turn it into a TargetGlobalAddress /
3597 // TargetExternalSymbol node so that legalize doesn't hack it.
3598 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3599 Callee.getValueType(),
3601 needIndirectCall = false;
3605 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3606 unsigned char OpFlags = 0;
3608 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3609 (Subtarget.getTargetTriple().isMacOSX() &&
3610 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3611 (Subtarget.isTargetELF() && !isPPC64 &&
3612 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3613 // PC-relative references to external symbols should go through $stub,
3614 // unless we're building with the leopard linker or later, which
3615 // automatically synthesizes these stubs.
3616 OpFlags = PPCII::MO_PLT_OR_STUB;
3619 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3621 needIndirectCall = false;
3624 if (needIndirectCall) {
3625 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3626 // to do the call, we can't use PPCISD::CALL.
3627 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3629 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3630 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3631 // entry point, but to the function descriptor (the function entry point
3632 // address is part of the function descriptor though).
3633 // The function descriptor is a three doubleword structure with the
3634 // following fields: function entry point, TOC base address and
3635 // environment pointer.
3636 // Thus for a call through a function pointer, the following actions need
3638 // 1. Save the TOC of the caller in the TOC save area of its stack
3639 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3640 // 2. Load the address of the function entry point from the function
3642 // 3. Load the TOC of the callee from the function descriptor into r2.
3643 // 4. Load the environment pointer from the function descriptor into
3645 // 5. Branch to the function entry point address.
3646 // 6. On return of the callee, the TOC of the caller needs to be
3647 // restored (this is done in FinishCall()).
3649 // All those operations are flagged together to ensure that no other
3650 // operations can be scheduled in between. E.g. without flagging the
3651 // operations together, a TOC access in the caller could be scheduled
3652 // between the load of the callee TOC and the branch to the callee, which
3653 // results in the TOC access going through the TOC of the callee instead
3654 // of going through the TOC of the caller, which leads to incorrect code.
3656 // Load the address of the function entry point from the function
3658 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3659 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3660 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3661 Chain = LoadFuncPtr.getValue(1);
3662 InFlag = LoadFuncPtr.getValue(2);
3664 // Load environment pointer into r11.
3665 // Offset of the environment pointer within the function descriptor.
3666 SDValue PtrOff = DAG.getIntPtrConstant(16);
3668 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3669 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3671 Chain = LoadEnvPtr.getValue(1);
3672 InFlag = LoadEnvPtr.getValue(2);
3674 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3676 Chain = EnvVal.getValue(0);
3677 InFlag = EnvVal.getValue(1);
3679 // Load TOC of the callee into r2. We are using a target-specific load
3680 // with r2 hard coded, because the result of a target-independent load
3681 // would never go directly into r2, since r2 is a reserved register (which
3682 // prevents the register allocator from allocating it), resulting in an
3683 // additional register being allocated and an unnecessary move instruction
3685 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3686 SDValue TOCOff = DAG.getIntPtrConstant(8);
3687 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3688 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3690 Chain = LoadTOCPtr.getValue(0);
3691 InFlag = LoadTOCPtr.getValue(1);
3693 MTCTROps[0] = Chain;
3694 MTCTROps[1] = LoadFuncPtr;
3695 MTCTROps[2] = InFlag;
3698 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3699 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3700 InFlag = Chain.getValue(1);
3703 NodeTys.push_back(MVT::Other);
3704 NodeTys.push_back(MVT::Glue);
3705 Ops.push_back(Chain);
3706 CallOpc = PPCISD::BCTRL;
3707 Callee.setNode(nullptr);
3708 // Add use of X11 (holding environment pointer)
3709 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3710 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3711 // Add CTR register as callee so a bctr can be emitted later.
3713 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3716 // If this is a direct call, pass the chain and the callee.
3717 if (Callee.getNode()) {
3718 Ops.push_back(Chain);
3719 Ops.push_back(Callee);
3721 // If this is a tail call add stack pointer delta.
3723 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3725 // Add argument registers to the end of the list so that they are known live
3727 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3728 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3729 RegsToPass[i].second.getValueType()));
3731 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3732 if (Callee.getNode() && isELFv2ABI)
3733 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3739 bool isLocalCall(const SDValue &Callee)
3741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3742 return !G->getGlobal()->isDeclaration() &&
3743 !G->getGlobal()->isWeakForLinker();
3748 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3749 CallingConv::ID CallConv, bool isVarArg,
3750 const SmallVectorImpl<ISD::InputArg> &Ins,
3751 SDLoc dl, SelectionDAG &DAG,
3752 SmallVectorImpl<SDValue> &InVals) const {
3754 SmallVector<CCValAssign, 16> RVLocs;
3755 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3756 getTargetMachine(), RVLocs, *DAG.getContext());
3757 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3759 // Copy all of the result registers out of their specified physreg.
3760 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3761 CCValAssign &VA = RVLocs[i];
3762 assert(VA.isRegLoc() && "Can only return in registers!");
3764 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3765 VA.getLocReg(), VA.getLocVT(), InFlag);
3766 Chain = Val.getValue(1);
3767 InFlag = Val.getValue(2);
3769 switch (VA.getLocInfo()) {
3770 default: llvm_unreachable("Unknown loc info!");
3771 case CCValAssign::Full: break;
3772 case CCValAssign::AExt:
3773 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3775 case CCValAssign::ZExt:
3776 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3777 DAG.getValueType(VA.getValVT()));
3778 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3780 case CCValAssign::SExt:
3781 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3782 DAG.getValueType(VA.getValVT()));
3783 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3787 InVals.push_back(Val);
3794 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3795 bool isTailCall, bool isVarArg,
3797 SmallVector<std::pair<unsigned, SDValue>, 8>
3799 SDValue InFlag, SDValue Chain,
3801 int SPDiff, unsigned NumBytes,
3802 const SmallVectorImpl<ISD::InputArg> &Ins,
3803 SmallVectorImpl<SDValue> &InVals) const {
3805 bool isELFv2ABI = Subtarget.isELFv2ABI();
3806 std::vector<EVT> NodeTys;
3807 SmallVector<SDValue, 8> Ops;
3808 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3809 isTailCall, RegsToPass, Ops, NodeTys,
3812 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3813 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3814 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3816 // When performing tail call optimization the callee pops its arguments off
3817 // the stack. Account for this here so these bytes can be pushed back on in
3818 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3819 int BytesCalleePops =
3820 (CallConv == CallingConv::Fast &&
3821 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3823 // Add a register mask operand representing the call-preserved registers.
3824 const TargetRegisterInfo *TRI =
3825 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3826 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3827 assert(Mask && "Missing call preserved mask for calling convention");
3828 Ops.push_back(DAG.getRegisterMask(Mask));
3830 if (InFlag.getNode())
3831 Ops.push_back(InFlag);
3835 assert(((Callee.getOpcode() == ISD::Register &&
3836 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3837 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3838 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3839 isa<ConstantSDNode>(Callee)) &&
3840 "Expecting an global address, external symbol, absolute value or register");
3842 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3845 // Add a NOP immediately after the branch instruction when using the 64-bit
3846 // SVR4 ABI. At link time, if caller and callee are in a different module and
3847 // thus have a different TOC, the call will be replaced with a call to a stub
3848 // function which saves the current TOC, loads the TOC of the callee and
3849 // branches to the callee. The NOP will be replaced with a load instruction
3850 // which restores the TOC of the caller from the TOC save slot of the current
3851 // stack frame. If caller and callee belong to the same module (and have the
3852 // same TOC), the NOP will remain unchanged.
3854 bool needsTOCRestore = false;
3855 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3856 if (CallOpc == PPCISD::BCTRL) {
3857 // This is a call through a function pointer.
3858 // Restore the caller TOC from the save area into R2.
3859 // See PrepareCall() for more information about calls through function
3860 // pointers in the 64-bit SVR4 ABI.
3861 // We are using a target-specific load with r2 hard coded, because the
3862 // result of a target-independent load would never go directly into r2,
3863 // since r2 is a reserved register (which prevents the register allocator
3864 // from allocating it), resulting in an additional register being
3865 // allocated and an unnecessary move instruction being generated.
3866 needsTOCRestore = true;
3867 } else if ((CallOpc == PPCISD::CALL) &&
3868 (!isLocalCall(Callee) ||
3869 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3870 // Otherwise insert NOP for non-local calls.
3871 CallOpc = PPCISD::CALL_NOP;
3875 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3876 InFlag = Chain.getValue(1);
3878 if (needsTOCRestore) {
3879 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3880 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3881 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3882 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3883 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3884 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3885 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3886 InFlag = Chain.getValue(1);
3889 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3890 DAG.getIntPtrConstant(BytesCalleePops, true),
3893 InFlag = Chain.getValue(1);
3895 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3896 Ins, dl, DAG, InVals);
3900 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3901 SmallVectorImpl<SDValue> &InVals) const {
3902 SelectionDAG &DAG = CLI.DAG;
3904 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3905 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3906 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3907 SDValue Chain = CLI.Chain;
3908 SDValue Callee = CLI.Callee;
3909 bool &isTailCall = CLI.IsTailCall;
3910 CallingConv::ID CallConv = CLI.CallConv;
3911 bool isVarArg = CLI.IsVarArg;
3914 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3917 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3918 report_fatal_error("failed to perform tail call elimination on a call "
3919 "site marked musttail");
3921 if (Subtarget.isSVR4ABI()) {
3922 if (Subtarget.isPPC64())
3923 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3924 isTailCall, Outs, OutVals, Ins,
3927 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3928 isTailCall, Outs, OutVals, Ins,
3932 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3933 isTailCall, Outs, OutVals, Ins,
3938 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3939 CallingConv::ID CallConv, bool isVarArg,
3941 const SmallVectorImpl<ISD::OutputArg> &Outs,
3942 const SmallVectorImpl<SDValue> &OutVals,
3943 const SmallVectorImpl<ISD::InputArg> &Ins,
3944 SDLoc dl, SelectionDAG &DAG,
3945 SmallVectorImpl<SDValue> &InVals) const {
3946 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3947 // of the 32-bit SVR4 ABI stack frame layout.
3949 assert((CallConv == CallingConv::C ||
3950 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3952 unsigned PtrByteSize = 4;
3954 MachineFunction &MF = DAG.getMachineFunction();
3956 // Mark this function as potentially containing a function that contains a
3957 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3958 // and restoring the callers stack pointer in this functions epilog. This is
3959 // done because by tail calling the called function might overwrite the value
3960 // in this function's (MF) stack pointer stack slot 0(SP).
3961 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3962 CallConv == CallingConv::Fast)
3963 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3965 // Count how many bytes are to be pushed on the stack, including the linkage
3966 // area, parameter list area and the part of the local variable space which
3967 // contains copies of aggregates which are passed by value.
3969 // Assign locations to all of the outgoing arguments.
3970 SmallVector<CCValAssign, 16> ArgLocs;
3971 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3972 getTargetMachine(), ArgLocs, *DAG.getContext());
3974 // Reserve space for the linkage area on the stack.
3975 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3979 // Handle fixed and variable vector arguments differently.
3980 // Fixed vector arguments go into registers as long as registers are
3981 // available. Variable vector arguments always go into memory.
3982 unsigned NumArgs = Outs.size();
3984 for (unsigned i = 0; i != NumArgs; ++i) {
3985 MVT ArgVT = Outs[i].VT;
3986 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3989 if (Outs[i].IsFixed) {
3990 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3993 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3999 errs() << "Call operand #" << i << " has unhandled type "
4000 << EVT(ArgVT).getEVTString() << "\n";
4002 llvm_unreachable(nullptr);
4006 // All arguments are treated the same.
4007 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4010 // Assign locations to all of the outgoing aggregate by value arguments.
4011 SmallVector<CCValAssign, 16> ByValArgLocs;
4012 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4013 getTargetMachine(), ByValArgLocs, *DAG.getContext());
4015 // Reserve stack space for the allocations in CCInfo.
4016 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4018 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4020 // Size of the linkage area, parameter list area and the part of the local
4021 // space variable where copies of aggregates which are passed by value are
4023 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4025 // Calculate by how many bytes the stack has to be adjusted in case of tail
4026 // call optimization.
4027 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4029 // Adjust the stack pointer for the new arguments...
4030 // These operations are automatically eliminated by the prolog/epilog pass
4031 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4033 SDValue CallSeqStart = Chain;
4035 // Load the return address and frame pointer so it can be moved somewhere else
4038 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4041 // Set up a copy of the stack pointer for use loading and storing any
4042 // arguments that may not fit in the registers available for argument
4044 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4046 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4047 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4048 SmallVector<SDValue, 8> MemOpChains;
4050 bool seenFloatArg = false;
4051 // Walk the register/memloc assignments, inserting copies/loads.
4052 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4055 CCValAssign &VA = ArgLocs[i];
4056 SDValue Arg = OutVals[i];
4057 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4059 if (Flags.isByVal()) {
4060 // Argument is an aggregate which is passed by value, thus we need to
4061 // create a copy of it in the local variable space of the current stack
4062 // frame (which is the stack frame of the caller) and pass the address of
4063 // this copy to the callee.
4064 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4065 CCValAssign &ByValVA = ByValArgLocs[j++];
4066 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4068 // Memory reserved in the local variable space of the callers stack frame.
4069 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4071 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4072 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4074 // Create a copy of the argument in the local area of the current
4076 SDValue MemcpyCall =
4077 CreateCopyOfByValArgument(Arg, PtrOff,
4078 CallSeqStart.getNode()->getOperand(0),
4081 // This must go outside the CALLSEQ_START..END.
4082 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4083 CallSeqStart.getNode()->getOperand(1),
4085 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4086 NewCallSeqStart.getNode());
4087 Chain = CallSeqStart = NewCallSeqStart;
4089 // Pass the address of the aggregate copy on the stack either in a
4090 // physical register or in the parameter list area of the current stack
4091 // frame to the callee.
4095 if (VA.isRegLoc()) {
4096 if (Arg.getValueType() == MVT::i1)
4097 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4099 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4100 // Put argument in a physical register.
4101 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4103 // Put argument in the parameter list area of the current stack frame.
4104 assert(VA.isMemLoc());
4105 unsigned LocMemOffset = VA.getLocMemOffset();
4108 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4109 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4111 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4112 MachinePointerInfo(),
4115 // Calculate and remember argument location.
4116 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4122 if (!MemOpChains.empty())
4123 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4125 // Build a sequence of copy-to-reg nodes chained together with token chain
4126 // and flag operands which copy the outgoing args into the appropriate regs.
4128 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4129 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4130 RegsToPass[i].second, InFlag);
4131 InFlag = Chain.getValue(1);
4134 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4137 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4138 SDValue Ops[] = { Chain, InFlag };
4140 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4141 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4143 InFlag = Chain.getValue(1);
4147 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4148 false, TailCallArguments);
4150 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4151 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4155 // Copy an argument into memory, being careful to do this outside the
4156 // call sequence for the call to which the argument belongs.
4158 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4159 SDValue CallSeqStart,
4160 ISD::ArgFlagsTy Flags,
4163 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4164 CallSeqStart.getNode()->getOperand(0),
4166 // The MEMCPY must go outside the CALLSEQ_START..END.
4167 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4168 CallSeqStart.getNode()->getOperand(1),
4170 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4171 NewCallSeqStart.getNode());
4172 return NewCallSeqStart;
4176 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4177 CallingConv::ID CallConv, bool isVarArg,
4179 const SmallVectorImpl<ISD::OutputArg> &Outs,
4180 const SmallVectorImpl<SDValue> &OutVals,
4181 const SmallVectorImpl<ISD::InputArg> &Ins,
4182 SDLoc dl, SelectionDAG &DAG,
4183 SmallVectorImpl<SDValue> &InVals) const {
4185 bool isELFv2ABI = Subtarget.isELFv2ABI();
4186 bool isLittleEndian = Subtarget.isLittleEndian();
4187 unsigned NumOps = Outs.size();
4189 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4190 unsigned PtrByteSize = 8;
4192 MachineFunction &MF = DAG.getMachineFunction();
4194 // Mark this function as potentially containing a function that contains a
4195 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4196 // and restoring the callers stack pointer in this functions epilog. This is
4197 // done because by tail calling the called function might overwrite the value
4198 // in this function's (MF) stack pointer stack slot 0(SP).
4199 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4200 CallConv == CallingConv::Fast)
4201 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4203 // Count how many bytes are to be pushed on the stack, including the linkage
4204 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4205 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4206 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4207 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4209 unsigned NumBytes = LinkageSize;
4211 // Add up all the space actually used.
4212 for (unsigned i = 0; i != NumOps; ++i) {
4213 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4214 EVT ArgVT = Outs[i].VT;
4215 EVT OrigVT = Outs[i].ArgVT;
4217 /* Respect alignment of argument on the stack. */
4219 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4220 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4222 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4223 if (Flags.isInConsecutiveRegsLast())
4224 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4227 unsigned NumBytesActuallyUsed = NumBytes;
4229 // The prolog code of the callee may store up to 8 GPR argument registers to
4230 // the stack, allowing va_start to index over them in memory if its varargs.
4231 // Because we cannot tell if this is needed on the caller side, we have to
4232 // conservatively assume that it is needed. As such, make sure we have at
4233 // least enough stack space for the caller to store the 8 GPRs.
4234 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4235 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4237 // Tail call needs the stack to be aligned.
4238 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4239 CallConv == CallingConv::Fast)
4240 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4242 // Calculate by how many bytes the stack has to be adjusted in case of tail
4243 // call optimization.
4244 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4246 // To protect arguments on the stack from being clobbered in a tail call,
4247 // force all the loads to happen before doing any other lowering.
4249 Chain = DAG.getStackArgumentTokenFactor(Chain);
4251 // Adjust the stack pointer for the new arguments...
4252 // These operations are automatically eliminated by the prolog/epilog pass
4253 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4255 SDValue CallSeqStart = Chain;
4257 // Load the return address and frame pointer so it can be move somewhere else
4260 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4263 // Set up a copy of the stack pointer for use loading and storing any
4264 // arguments that may not fit in the registers available for argument
4266 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4268 // Figure out which arguments are going to go in registers, and which in
4269 // memory. Also, if this is a vararg function, floating point operations
4270 // must be stored to our stack, and loaded into integer regs as well, if
4271 // any integer regs are available for argument passing.
4272 unsigned ArgOffset = LinkageSize;
4273 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4275 static const MCPhysReg GPR[] = {
4276 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4277 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4279 static const MCPhysReg *FPR = GetFPR();
4281 static const MCPhysReg VR[] = {
4282 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4283 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4285 static const MCPhysReg VSRH[] = {
4286 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4287 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4290 const unsigned NumGPRs = array_lengthof(GPR);
4291 const unsigned NumFPRs = 13;
4292 const unsigned NumVRs = array_lengthof(VR);
4294 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4295 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4297 SmallVector<SDValue, 8> MemOpChains;
4298 for (unsigned i = 0; i != NumOps; ++i) {
4299 SDValue Arg = OutVals[i];
4300 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4301 EVT ArgVT = Outs[i].VT;
4302 EVT OrigVT = Outs[i].ArgVT;
4304 /* Respect alignment of argument on the stack. */
4306 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4307 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4309 /* Compute GPR index associated with argument offset. */
4310 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4311 GPR_idx = std::min(GPR_idx, NumGPRs);
4313 // PtrOff will be used to store the current argument to the stack if a
4314 // register cannot be found for it.
4317 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4319 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4321 // Promote integers to 64-bit values.
4322 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4323 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4324 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4325 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4328 // FIXME memcpy is used way more than necessary. Correctness first.
4329 // Note: "by value" is code for passing a structure by value, not
4331 if (Flags.isByVal()) {
4332 // Note: Size includes alignment padding, so
4333 // struct x { short a; char b; }
4334 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4335 // These are the proper values we need for right-justifying the
4336 // aggregate in a parameter register.
4337 unsigned Size = Flags.getByValSize();
4339 // An empty aggregate parameter takes up no storage and no
4344 // All aggregates smaller than 8 bytes must be passed right-justified.
4345 if (Size==1 || Size==2 || Size==4) {
4346 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4347 if (GPR_idx != NumGPRs) {
4348 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4349 MachinePointerInfo(), VT,
4350 false, false, false, 0);
4351 MemOpChains.push_back(Load.getValue(1));
4352 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4354 ArgOffset += PtrByteSize;
4359 if (GPR_idx == NumGPRs && Size < 8) {
4360 SDValue AddPtr = PtrOff;
4361 if (!isLittleEndian) {
4362 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4363 PtrOff.getValueType());
4364 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4366 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4369 ArgOffset += PtrByteSize;
4372 // Copy entire object into memory. There are cases where gcc-generated
4373 // code assumes it is there, even if it could be put entirely into
4374 // registers. (This is not what the doc says.)
4376 // FIXME: The above statement is likely due to a misunderstanding of the
4377 // documents. All arguments must be copied into the parameter area BY
4378 // THE CALLEE in the event that the callee takes the address of any
4379 // formal argument. That has not yet been implemented. However, it is
4380 // reasonable to use the stack area as a staging area for the register
4383 // Skip this for small aggregates, as we will use the same slot for a
4384 // right-justified copy, below.
4386 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4390 // When a register is available, pass a small aggregate right-justified.
4391 if (Size < 8 && GPR_idx != NumGPRs) {
4392 // The easiest way to get this right-justified in a register
4393 // is to copy the structure into the rightmost portion of a
4394 // local variable slot, then load the whole slot into the
4396 // FIXME: The memcpy seems to produce pretty awful code for
4397 // small aggregates, particularly for packed ones.
4398 // FIXME: It would be preferable to use the slot in the
4399 // parameter save area instead of a new local variable.
4400 SDValue AddPtr = PtrOff;
4401 if (!isLittleEndian) {
4402 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4403 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4405 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4409 // Load the slot into the register.
4410 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4411 MachinePointerInfo(),
4412 false, false, false, 0);
4413 MemOpChains.push_back(Load.getValue(1));
4414 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4416 // Done with this argument.
4417 ArgOffset += PtrByteSize;
4421 // For aggregates larger than PtrByteSize, copy the pieces of the
4422 // object that fit into registers from the parameter save area.
4423 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4424 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4425 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4426 if (GPR_idx != NumGPRs) {
4427 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4428 MachinePointerInfo(),
4429 false, false, false, 0);
4430 MemOpChains.push_back(Load.getValue(1));
4431 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4432 ArgOffset += PtrByteSize;
4434 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4441 switch (Arg.getSimpleValueType().SimpleTy) {
4442 default: llvm_unreachable("Unexpected ValueType for argument!");
4446 // These can be scalar arguments or elements of an integer array type
4447 // passed directly. Clang may use those instead of "byval" aggregate
4448 // types to avoid forcing arguments to memory unnecessarily.
4449 if (GPR_idx != NumGPRs) {
4450 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4452 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4453 true, isTailCall, false, MemOpChains,
4454 TailCallArguments, dl);
4456 ArgOffset += PtrByteSize;
4460 // These can be scalar arguments or elements of a float array type
4461 // passed directly. The latter are used to implement ELFv2 homogenous
4462 // float aggregates.
4464 // Named arguments go into FPRs first, and once they overflow, the
4465 // remaining arguments go into GPRs and then the parameter save area.
4466 // Unnamed arguments for vararg functions always go to GPRs and
4467 // then the parameter save area. For now, put all arguments to vararg
4468 // routines always in both locations (FPR *and* GPR or stack slot).
4469 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4471 // First load the argument into the next available FPR.
4472 if (FPR_idx != NumFPRs)
4473 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4475 // Next, load the argument into GPR or stack slot if needed.
4476 if (!NeedGPROrStack)
4478 else if (GPR_idx != NumGPRs) {
4479 // In the non-vararg case, this can only ever happen in the
4480 // presence of f32 array types, since otherwise we never run
4481 // out of FPRs before running out of GPRs.
4484 // Double values are always passed in a single GPR.
4485 if (Arg.getValueType() != MVT::f32) {
4486 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4488 // Non-array float values are extended and passed in a GPR.
4489 } else if (!Flags.isInConsecutiveRegs()) {
4490 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4491 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4493 // If we have an array of floats, we collect every odd element
4494 // together with its predecessor into one GPR.
4495 } else if (ArgOffset % PtrByteSize != 0) {
4497 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4498 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4499 if (!isLittleEndian)
4501 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4503 // The final element, if even, goes into the first half of a GPR.
4504 } else if (Flags.isInConsecutiveRegsLast()) {
4505 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4506 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4507 if (!isLittleEndian)
4508 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4509 DAG.getConstant(32, MVT::i32));
4511 // Non-final even elements are skipped; they will be handled
4512 // together the with subsequent argument on the next go-around.
4516 if (ArgVal.getNode())
4517 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4519 // Single-precision floating-point values are mapped to the
4520 // second (rightmost) word of the stack doubleword.
4521 if (Arg.getValueType() == MVT::f32 &&
4522 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4523 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4524 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4527 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4528 true, isTailCall, false, MemOpChains,
4529 TailCallArguments, dl);
4531 // When passing an array of floats, the array occupies consecutive
4532 // space in the argument area; only round up to the next doubleword
4533 // at the end of the array. Otherwise, each float takes 8 bytes.
4534 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4535 Flags.isInConsecutiveRegs()) ? 4 : 8;
4536 if (Flags.isInConsecutiveRegsLast())
4537 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4546 // These can be scalar arguments or elements of a vector array type
4547 // passed directly. The latter are used to implement ELFv2 homogenous
4548 // vector aggregates.
4550 // For a varargs call, named arguments go into VRs or on the stack as
4551 // usual; unnamed arguments always go to the stack or the corresponding
4552 // GPRs when within range. For now, we always put the value in both
4553 // locations (or even all three).
4555 // We could elide this store in the case where the object fits
4556 // entirely in R registers. Maybe later.
4557 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4558 MachinePointerInfo(), false, false, 0);
4559 MemOpChains.push_back(Store);
4560 if (VR_idx != NumVRs) {
4561 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4562 MachinePointerInfo(),
4563 false, false, false, 0);
4564 MemOpChains.push_back(Load.getValue(1));
4566 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4567 Arg.getSimpleValueType() == MVT::v2i64) ?
4568 VSRH[VR_idx] : VR[VR_idx];
4571 RegsToPass.push_back(std::make_pair(VReg, Load));
4574 for (unsigned i=0; i<16; i+=PtrByteSize) {
4575 if (GPR_idx == NumGPRs)
4577 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4578 DAG.getConstant(i, PtrVT));
4579 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4580 false, false, false, 0);
4581 MemOpChains.push_back(Load.getValue(1));
4582 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4587 // Non-varargs Altivec params go into VRs or on the stack.
4588 if (VR_idx != NumVRs) {
4589 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4590 Arg.getSimpleValueType() == MVT::v2i64) ?
4591 VSRH[VR_idx] : VR[VR_idx];
4594 RegsToPass.push_back(std::make_pair(VReg, Arg));
4596 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4597 true, isTailCall, true, MemOpChains,
4598 TailCallArguments, dl);
4605 assert(NumBytesActuallyUsed == ArgOffset);
4606 (void)NumBytesActuallyUsed;
4608 if (!MemOpChains.empty())
4609 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4611 // Check if this is an indirect call (MTCTR/BCTRL).
4612 // See PrepareCall() for more information about calls through function
4613 // pointers in the 64-bit SVR4 ABI.
4615 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4616 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4617 // Load r2 into a virtual register and store it to the TOC save area.
4618 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4619 // TOC save area offset.
4620 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4621 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4622 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4623 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4625 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4626 // This does not mean the MTCTR instruction must use R12; it's easier
4627 // to model this as an extra parameter, so do that.
4629 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4632 // Build a sequence of copy-to-reg nodes chained together with token chain
4633 // and flag operands which copy the outgoing args into the appropriate regs.
4635 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4636 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4637 RegsToPass[i].second, InFlag);
4638 InFlag = Chain.getValue(1);
4642 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4643 FPOp, true, TailCallArguments);
4645 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4646 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4651 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4652 CallingConv::ID CallConv, bool isVarArg,
4654 const SmallVectorImpl<ISD::OutputArg> &Outs,
4655 const SmallVectorImpl<SDValue> &OutVals,
4656 const SmallVectorImpl<ISD::InputArg> &Ins,
4657 SDLoc dl, SelectionDAG &DAG,
4658 SmallVectorImpl<SDValue> &InVals) const {
4660 unsigned NumOps = Outs.size();
4662 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4663 bool isPPC64 = PtrVT == MVT::i64;
4664 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4666 MachineFunction &MF = DAG.getMachineFunction();
4668 // Mark this function as potentially containing a function that contains a
4669 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4670 // and restoring the callers stack pointer in this functions epilog. This is
4671 // done because by tail calling the called function might overwrite the value
4672 // in this function's (MF) stack pointer stack slot 0(SP).
4673 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4674 CallConv == CallingConv::Fast)
4675 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4677 // Count how many bytes are to be pushed on the stack, including the linkage
4678 // area, and parameter passing area. We start with 24/48 bytes, which is
4679 // prereserved space for [SP][CR][LR][3 x unused].
4680 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4682 unsigned NumBytes = LinkageSize;
4684 // Add up all the space actually used.
4685 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4686 // they all go in registers, but we must reserve stack space for them for
4687 // possible use by the caller. In varargs or 64-bit calls, parameters are
4688 // assigned stack space in order, with padding so Altivec parameters are
4690 unsigned nAltivecParamsAtEnd = 0;
4691 for (unsigned i = 0; i != NumOps; ++i) {
4692 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4693 EVT ArgVT = Outs[i].VT;
4694 // Varargs Altivec parameters are padded to a 16 byte boundary.
4695 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4696 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4697 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4698 if (!isVarArg && !isPPC64) {
4699 // Non-varargs Altivec parameters go after all the non-Altivec
4700 // parameters; handle those later so we know how much padding we need.
4701 nAltivecParamsAtEnd++;
4704 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4705 NumBytes = ((NumBytes+15)/16)*16;
4707 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4710 // Allow for Altivec parameters at the end, if needed.
4711 if (nAltivecParamsAtEnd) {
4712 NumBytes = ((NumBytes+15)/16)*16;
4713 NumBytes += 16*nAltivecParamsAtEnd;
4716 // The prolog code of the callee may store up to 8 GPR argument registers to
4717 // the stack, allowing va_start to index over them in memory if its varargs.
4718 // Because we cannot tell if this is needed on the caller side, we have to
4719 // conservatively assume that it is needed. As such, make sure we have at
4720 // least enough stack space for the caller to store the 8 GPRs.
4721 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4723 // Tail call needs the stack to be aligned.
4724 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4725 CallConv == CallingConv::Fast)
4726 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4728 // Calculate by how many bytes the stack has to be adjusted in case of tail
4729 // call optimization.
4730 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4732 // To protect arguments on the stack from being clobbered in a tail call,
4733 // force all the loads to happen before doing any other lowering.
4735 Chain = DAG.getStackArgumentTokenFactor(Chain);
4737 // Adjust the stack pointer for the new arguments...
4738 // These operations are automatically eliminated by the prolog/epilog pass
4739 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4741 SDValue CallSeqStart = Chain;
4743 // Load the return address and frame pointer so it can be move somewhere else
4746 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4749 // Set up a copy of the stack pointer for use loading and storing any
4750 // arguments that may not fit in the registers available for argument
4754 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4756 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4758 // Figure out which arguments are going to go in registers, and which in
4759 // memory. Also, if this is a vararg function, floating point operations
4760 // must be stored to our stack, and loaded into integer regs as well, if
4761 // any integer regs are available for argument passing.
4762 unsigned ArgOffset = LinkageSize;
4763 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4765 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4766 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4767 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4769 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4770 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4771 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4773 static const MCPhysReg *FPR = GetFPR();
4775 static const MCPhysReg VR[] = {
4776 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4777 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4779 const unsigned NumGPRs = array_lengthof(GPR_32);
4780 const unsigned NumFPRs = 13;
4781 const unsigned NumVRs = array_lengthof(VR);
4783 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4785 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4786 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4788 SmallVector<SDValue, 8> MemOpChains;
4789 for (unsigned i = 0; i != NumOps; ++i) {
4790 SDValue Arg = OutVals[i];
4791 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4793 // PtrOff will be used to store the current argument to the stack if a
4794 // register cannot be found for it.
4797 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4799 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4801 // On PPC64, promote integers to 64-bit values.
4802 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4803 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4804 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4805 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4808 // FIXME memcpy is used way more than necessary. Correctness first.
4809 // Note: "by value" is code for passing a structure by value, not
4811 if (Flags.isByVal()) {
4812 unsigned Size = Flags.getByValSize();
4813 // Very small objects are passed right-justified. Everything else is
4814 // passed left-justified.
4815 if (Size==1 || Size==2) {
4816 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4817 if (GPR_idx != NumGPRs) {
4818 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4819 MachinePointerInfo(), VT,
4820 false, false, false, 0);
4821 MemOpChains.push_back(Load.getValue(1));
4822 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4824 ArgOffset += PtrByteSize;
4826 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4827 PtrOff.getValueType());
4828 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4829 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4832 ArgOffset += PtrByteSize;
4836 // Copy entire object into memory. There are cases where gcc-generated
4837 // code assumes it is there, even if it could be put entirely into
4838 // registers. (This is not what the doc says.)
4839 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4843 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4844 // copy the pieces of the object that fit into registers from the
4845 // parameter save area.
4846 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4847 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4848 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4849 if (GPR_idx != NumGPRs) {
4850 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4851 MachinePointerInfo(),
4852 false, false, false, 0);
4853 MemOpChains.push_back(Load.getValue(1));
4854 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4855 ArgOffset += PtrByteSize;
4857 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4864 switch (Arg.getSimpleValueType().SimpleTy) {
4865 default: llvm_unreachable("Unexpected ValueType for argument!");
4869 if (GPR_idx != NumGPRs) {
4870 if (Arg.getValueType() == MVT::i1)
4871 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4873 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4875 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4876 isPPC64, isTailCall, false, MemOpChains,
4877 TailCallArguments, dl);
4879 ArgOffset += PtrByteSize;
4883 if (FPR_idx != NumFPRs) {
4884 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4887 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4888 MachinePointerInfo(), false, false, 0);
4889 MemOpChains.push_back(Store);
4891 // Float varargs are always shadowed in available integer registers
4892 if (GPR_idx != NumGPRs) {
4893 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4894 MachinePointerInfo(), false, false,
4896 MemOpChains.push_back(Load.getValue(1));
4897 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4899 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4900 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4901 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4902 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4903 MachinePointerInfo(),
4904 false, false, false, 0);
4905 MemOpChains.push_back(Load.getValue(1));
4906 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4909 // If we have any FPRs remaining, we may also have GPRs remaining.
4910 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4912 if (GPR_idx != NumGPRs)
4914 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4915 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4919 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4920 isPPC64, isTailCall, false, MemOpChains,
4921 TailCallArguments, dl);
4925 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4932 // These go aligned on the stack, or in the corresponding R registers
4933 // when within range. The Darwin PPC ABI doc claims they also go in
4934 // V registers; in fact gcc does this only for arguments that are
4935 // prototyped, not for those that match the ... We do it for all
4936 // arguments, seems to work.
4937 while (ArgOffset % 16 !=0) {
4938 ArgOffset += PtrByteSize;
4939 if (GPR_idx != NumGPRs)
4942 // We could elide this store in the case where the object fits
4943 // entirely in R registers. Maybe later.
4944 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4945 DAG.getConstant(ArgOffset, PtrVT));
4946 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4947 MachinePointerInfo(), false, false, 0);
4948 MemOpChains.push_back(Store);
4949 if (VR_idx != NumVRs) {
4950 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4951 MachinePointerInfo(),
4952 false, false, false, 0);
4953 MemOpChains.push_back(Load.getValue(1));
4954 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4957 for (unsigned i=0; i<16; i+=PtrByteSize) {
4958 if (GPR_idx == NumGPRs)
4960 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4961 DAG.getConstant(i, PtrVT));
4962 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4963 false, false, false, 0);
4964 MemOpChains.push_back(Load.getValue(1));
4965 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4970 // Non-varargs Altivec params generally go in registers, but have
4971 // stack space allocated at the end.
4972 if (VR_idx != NumVRs) {
4973 // Doesn't have GPR space allocated.
4974 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4975 } else if (nAltivecParamsAtEnd==0) {
4976 // We are emitting Altivec params in order.
4977 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4978 isPPC64, isTailCall, true, MemOpChains,
4979 TailCallArguments, dl);
4985 // If all Altivec parameters fit in registers, as they usually do,
4986 // they get stack space following the non-Altivec parameters. We
4987 // don't track this here because nobody below needs it.
4988 // If there are more Altivec parameters than fit in registers emit
4990 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4992 // Offset is aligned; skip 1st 12 params which go in V registers.
4993 ArgOffset = ((ArgOffset+15)/16)*16;
4995 for (unsigned i = 0; i != NumOps; ++i) {
4996 SDValue Arg = OutVals[i];
4997 EVT ArgType = Outs[i].VT;
4998 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4999 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5002 // We are emitting Altivec params in order.
5003 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5004 isPPC64, isTailCall, true, MemOpChains,
5005 TailCallArguments, dl);
5012 if (!MemOpChains.empty())
5013 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5015 // On Darwin, R12 must contain the address of an indirect callee. This does
5016 // not mean the MTCTR instruction must use R12; it's easier to model this as
5017 // an extra parameter, so do that.
5019 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5020 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5021 !isBLACompatibleAddress(Callee, DAG))
5022 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5023 PPC::R12), Callee));
5025 // Build a sequence of copy-to-reg nodes chained together with token chain
5026 // and flag operands which copy the outgoing args into the appropriate regs.
5028 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5029 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5030 RegsToPass[i].second, InFlag);
5031 InFlag = Chain.getValue(1);
5035 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5036 FPOp, true, TailCallArguments);
5038 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5039 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5044 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5045 MachineFunction &MF, bool isVarArg,
5046 const SmallVectorImpl<ISD::OutputArg> &Outs,
5047 LLVMContext &Context) const {
5048 SmallVector<CCValAssign, 16> RVLocs;
5049 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5051 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5055 PPCTargetLowering::LowerReturn(SDValue Chain,
5056 CallingConv::ID CallConv, bool isVarArg,
5057 const SmallVectorImpl<ISD::OutputArg> &Outs,
5058 const SmallVectorImpl<SDValue> &OutVals,
5059 SDLoc dl, SelectionDAG &DAG) const {
5061 SmallVector<CCValAssign, 16> RVLocs;
5062 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5063 getTargetMachine(), RVLocs, *DAG.getContext());
5064 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5067 SmallVector<SDValue, 4> RetOps(1, Chain);
5069 // Copy the result values into the output registers.
5070 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5071 CCValAssign &VA = RVLocs[i];
5072 assert(VA.isRegLoc() && "Can only return in registers!");
5074 SDValue Arg = OutVals[i];
5076 switch (VA.getLocInfo()) {
5077 default: llvm_unreachable("Unknown loc info!");
5078 case CCValAssign::Full: break;
5079 case CCValAssign::AExt:
5080 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5082 case CCValAssign::ZExt:
5083 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5085 case CCValAssign::SExt:
5086 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5090 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5091 Flag = Chain.getValue(1);
5092 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5095 RetOps[0] = Chain; // Update chain.
5097 // Add the flag if we have it.
5099 RetOps.push_back(Flag);
5101 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5104 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5105 const PPCSubtarget &Subtarget) const {
5106 // When we pop the dynamic allocation we need to restore the SP link.
5109 // Get the corect type for pointers.
5110 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5112 // Construct the stack pointer operand.
5113 bool isPPC64 = Subtarget.isPPC64();
5114 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5115 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5117 // Get the operands for the STACKRESTORE.
5118 SDValue Chain = Op.getOperand(0);
5119 SDValue SaveSP = Op.getOperand(1);
5121 // Load the old link SP.
5122 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5123 MachinePointerInfo(),
5124 false, false, false, 0);
5126 // Restore the stack pointer.
5127 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5129 // Store the old link SP.
5130 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5137 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5138 MachineFunction &MF = DAG.getMachineFunction();
5139 bool isPPC64 = Subtarget.isPPC64();
5140 bool isDarwinABI = Subtarget.isDarwinABI();
5141 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5143 // Get current frame pointer save index. The users of this index will be
5144 // primarily DYNALLOC instructions.
5145 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5146 int RASI = FI->getReturnAddrSaveIndex();
5148 // If the frame pointer save index hasn't been defined yet.
5150 // Find out what the fix offset of the frame pointer save area.
5151 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5152 // Allocate the frame index for frame pointer save area.
5153 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5155 FI->setReturnAddrSaveIndex(RASI);
5157 return DAG.getFrameIndex(RASI, PtrVT);
5161 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5162 MachineFunction &MF = DAG.getMachineFunction();
5163 bool isPPC64 = Subtarget.isPPC64();
5164 bool isDarwinABI = Subtarget.isDarwinABI();
5165 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5167 // Get current frame pointer save index. The users of this index will be
5168 // primarily DYNALLOC instructions.
5169 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5170 int FPSI = FI->getFramePointerSaveIndex();
5172 // If the frame pointer save index hasn't been defined yet.
5174 // Find out what the fix offset of the frame pointer save area.
5175 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5178 // Allocate the frame index for frame pointer save area.
5179 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5181 FI->setFramePointerSaveIndex(FPSI);
5183 return DAG.getFrameIndex(FPSI, PtrVT);
5186 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5188 const PPCSubtarget &Subtarget) const {
5190 SDValue Chain = Op.getOperand(0);
5191 SDValue Size = Op.getOperand(1);
5194 // Get the corect type for pointers.
5195 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5197 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5198 DAG.getConstant(0, PtrVT), Size);
5199 // Construct a node for the frame pointer save index.
5200 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5201 // Build a DYNALLOC node.
5202 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5203 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5204 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5207 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5208 SelectionDAG &DAG) const {
5210 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5211 DAG.getVTList(MVT::i32, MVT::Other),
5212 Op.getOperand(0), Op.getOperand(1));
5215 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5216 SelectionDAG &DAG) const {
5218 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5219 Op.getOperand(0), Op.getOperand(1));
5222 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5223 assert(Op.getValueType() == MVT::i1 &&
5224 "Custom lowering only for i1 loads");
5226 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5229 LoadSDNode *LD = cast<LoadSDNode>(Op);
5231 SDValue Chain = LD->getChain();
5232 SDValue BasePtr = LD->getBasePtr();
5233 MachineMemOperand *MMO = LD->getMemOperand();
5235 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5236 BasePtr, MVT::i8, MMO);
5237 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5239 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5240 return DAG.getMergeValues(Ops, dl);
5243 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5244 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5245 "Custom lowering only for i1 stores");
5247 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5250 StoreSDNode *ST = cast<StoreSDNode>(Op);
5252 SDValue Chain = ST->getChain();
5253 SDValue BasePtr = ST->getBasePtr();
5254 SDValue Value = ST->getValue();
5255 MachineMemOperand *MMO = ST->getMemOperand();
5257 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5258 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5261 // FIXME: Remove this once the ANDI glue bug is fixed:
5262 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5263 assert(Op.getValueType() == MVT::i1 &&
5264 "Custom lowering only for i1 results");
5267 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5271 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5273 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5274 // Not FP? Not a fsel.
5275 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5276 !Op.getOperand(2).getValueType().isFloatingPoint())
5279 // We might be able to do better than this under some circumstances, but in
5280 // general, fsel-based lowering of select is a finite-math-only optimization.
5281 // For more information, see section F.3 of the 2.06 ISA specification.
5282 if (!DAG.getTarget().Options.NoInfsFPMath ||
5283 !DAG.getTarget().Options.NoNaNsFPMath)
5286 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5288 EVT ResVT = Op.getValueType();
5289 EVT CmpVT = Op.getOperand(0).getValueType();
5290 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5291 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5294 // If the RHS of the comparison is a 0.0, we don't need to do the
5295 // subtraction at all.
5297 if (isFloatingPointZero(RHS))
5299 default: break; // SETUO etc aren't handled by fsel.
5303 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5304 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5305 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5306 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5307 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5308 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5309 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5312 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5315 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5316 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5317 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5320 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5323 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5324 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5325 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5326 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5331 default: break; // SETUO etc aren't handled by fsel.
5335 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5336 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5337 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5338 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5339 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5340 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5341 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5342 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5345 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5346 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5347 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5348 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5351 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5352 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5353 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5354 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5357 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5358 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5359 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5360 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5363 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5364 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5365 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5366 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5371 // FIXME: Split this code up when LegalizeDAGTypes lands.
5372 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5374 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5375 SDValue Src = Op.getOperand(0);
5376 if (Src.getValueType() == MVT::f32)
5377 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5380 switch (Op.getSimpleValueType().SimpleTy) {
5381 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5383 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5384 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5389 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5390 "i64 FP_TO_UINT is supported only with FPCVT");
5391 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5397 // Convert the FP value to an int value through memory.
5398 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5399 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5400 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5401 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5402 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5404 // Emit a store to the stack slot.
5407 MachineFunction &MF = DAG.getMachineFunction();
5408 MachineMemOperand *MMO =
5409 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5410 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5411 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5412 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5414 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5415 MPI, false, false, 0);
5417 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5419 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5420 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5421 DAG.getConstant(4, FIPtr.getValueType()));
5422 MPI = MachinePointerInfo();
5425 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5426 false, false, false, 0);
5429 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5430 SelectionDAG &DAG) const {
5432 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5433 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5436 if (Op.getOperand(0).getValueType() == MVT::i1)
5437 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5438 DAG.getConstantFP(1.0, Op.getValueType()),
5439 DAG.getConstantFP(0.0, Op.getValueType()));
5441 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5442 "UINT_TO_FP is supported only with FPCVT");
5444 // If we have FCFIDS, then use it when converting to single-precision.
5445 // Otherwise, convert to double-precision and then round.
5446 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5447 (Op.getOpcode() == ISD::UINT_TO_FP ?
5448 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5449 (Op.getOpcode() == ISD::UINT_TO_FP ?
5450 PPCISD::FCFIDU : PPCISD::FCFID);
5451 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5452 MVT::f32 : MVT::f64;
5454 if (Op.getOperand(0).getValueType() == MVT::i64) {
5455 SDValue SINT = Op.getOperand(0);
5456 // When converting to single-precision, we actually need to convert
5457 // to double-precision first and then round to single-precision.
5458 // To avoid double-rounding effects during that operation, we have
5459 // to prepare the input operand. Bits that might be truncated when
5460 // converting to double-precision are replaced by a bit that won't
5461 // be lost at this stage, but is below the single-precision rounding
5464 // However, if -enable-unsafe-fp-math is in effect, accept double
5465 // rounding to avoid the extra overhead.
5466 if (Op.getValueType() == MVT::f32 &&
5467 !Subtarget.hasFPCVT() &&
5468 !DAG.getTarget().Options.UnsafeFPMath) {
5470 // Twiddle input to make sure the low 11 bits are zero. (If this
5471 // is the case, we are guaranteed the value will fit into the 53 bit
5472 // mantissa of an IEEE double-precision value without rounding.)
5473 // If any of those low 11 bits were not zero originally, make sure
5474 // bit 12 (value 2048) is set instead, so that the final rounding
5475 // to single-precision gets the correct result.
5476 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5477 SINT, DAG.getConstant(2047, MVT::i64));
5478 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5479 Round, DAG.getConstant(2047, MVT::i64));
5480 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5481 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5482 Round, DAG.getConstant(-2048, MVT::i64));
5484 // However, we cannot use that value unconditionally: if the magnitude
5485 // of the input value is small, the bit-twiddling we did above might
5486 // end up visibly changing the output. Fortunately, in that case, we
5487 // don't need to twiddle bits since the original input will convert
5488 // exactly to double-precision floating-point already. Therefore,
5489 // construct a conditional to use the original value if the top 11
5490 // bits are all sign-bit copies, and use the rounded value computed
5492 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5493 SINT, DAG.getConstant(53, MVT::i32));
5494 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5495 Cond, DAG.getConstant(1, MVT::i64));
5496 Cond = DAG.getSetCC(dl, MVT::i32,
5497 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5499 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5502 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5503 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5505 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5506 FP = DAG.getNode(ISD::FP_ROUND, dl,
5507 MVT::f32, FP, DAG.getIntPtrConstant(0));
5511 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5512 "Unhandled INT_TO_FP type in custom expander!");
5513 // Since we only generate this in 64-bit mode, we can take advantage of
5514 // 64-bit registers. In particular, sign extend the input value into the
5515 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5516 // then lfd it and fcfid it.
5517 MachineFunction &MF = DAG.getMachineFunction();
5518 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5519 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5522 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5523 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5524 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5526 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5527 MachinePointerInfo::getFixedStack(FrameIdx),
5530 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5531 "Expected an i32 store");
5532 MachineMemOperand *MMO =
5533 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5534 MachineMemOperand::MOLoad, 4, 4);
5535 SDValue Ops[] = { Store, FIdx };
5536 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5537 PPCISD::LFIWZX : PPCISD::LFIWAX,
5538 dl, DAG.getVTList(MVT::f64, MVT::Other),
5539 Ops, MVT::i32, MMO);
5541 assert(Subtarget.isPPC64() &&
5542 "i32->FP without LFIWAX supported only on PPC64");
5544 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5545 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5547 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5550 // STD the extended value into the stack slot.
5551 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5552 MachinePointerInfo::getFixedStack(FrameIdx),
5555 // Load the value as a double.
5556 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5557 MachinePointerInfo::getFixedStack(FrameIdx),
5558 false, false, false, 0);
5561 // FCFID it and return it.
5562 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5563 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5564 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5568 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5569 SelectionDAG &DAG) const {
5572 The rounding mode is in bits 30:31 of FPSR, and has the following
5579 FLT_ROUNDS, on the other hand, expects the following:
5586 To perform the conversion, we do:
5587 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5590 MachineFunction &MF = DAG.getMachineFunction();
5591 EVT VT = Op.getValueType();
5592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5594 // Save FP Control Word to register
5596 MVT::f64, // return register
5597 MVT::Glue // unused in this context
5599 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5601 // Save FP register to stack slot
5602 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5603 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5604 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5605 StackSlot, MachinePointerInfo(), false, false,0);
5607 // Load FP Control Word from low 32 bits of stack slot.
5608 SDValue Four = DAG.getConstant(4, PtrVT);
5609 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5610 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5611 false, false, false, 0);
5613 // Transform as necessary
5615 DAG.getNode(ISD::AND, dl, MVT::i32,
5616 CWD, DAG.getConstant(3, MVT::i32));
5618 DAG.getNode(ISD::SRL, dl, MVT::i32,
5619 DAG.getNode(ISD::AND, dl, MVT::i32,
5620 DAG.getNode(ISD::XOR, dl, MVT::i32,
5621 CWD, DAG.getConstant(3, MVT::i32)),
5622 DAG.getConstant(3, MVT::i32)),
5623 DAG.getConstant(1, MVT::i32));
5626 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5628 return DAG.getNode((VT.getSizeInBits() < 16 ?
5629 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5632 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5633 EVT VT = Op.getValueType();
5634 unsigned BitWidth = VT.getSizeInBits();
5636 assert(Op.getNumOperands() == 3 &&
5637 VT == Op.getOperand(1).getValueType() &&
5640 // Expand into a bunch of logical ops. Note that these ops
5641 // depend on the PPC behavior for oversized shift amounts.
5642 SDValue Lo = Op.getOperand(0);
5643 SDValue Hi = Op.getOperand(1);
5644 SDValue Amt = Op.getOperand(2);
5645 EVT AmtVT = Amt.getValueType();
5647 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5648 DAG.getConstant(BitWidth, AmtVT), Amt);
5649 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5650 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5651 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5652 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5653 DAG.getConstant(-BitWidth, AmtVT));
5654 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5655 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5656 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5657 SDValue OutOps[] = { OutLo, OutHi };
5658 return DAG.getMergeValues(OutOps, dl);
5661 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5662 EVT VT = Op.getValueType();
5664 unsigned BitWidth = VT.getSizeInBits();
5665 assert(Op.getNumOperands() == 3 &&
5666 VT == Op.getOperand(1).getValueType() &&
5669 // Expand into a bunch of logical ops. Note that these ops
5670 // depend on the PPC behavior for oversized shift amounts.
5671 SDValue Lo = Op.getOperand(0);
5672 SDValue Hi = Op.getOperand(1);
5673 SDValue Amt = Op.getOperand(2);
5674 EVT AmtVT = Amt.getValueType();
5676 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5677 DAG.getConstant(BitWidth, AmtVT), Amt);
5678 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5679 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5680 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5681 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5682 DAG.getConstant(-BitWidth, AmtVT));
5683 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5684 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5685 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5686 SDValue OutOps[] = { OutLo, OutHi };
5687 return DAG.getMergeValues(OutOps, dl);
5690 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5692 EVT VT = Op.getValueType();
5693 unsigned BitWidth = VT.getSizeInBits();
5694 assert(Op.getNumOperands() == 3 &&
5695 VT == Op.getOperand(1).getValueType() &&
5698 // Expand into a bunch of logical ops, followed by a select_cc.
5699 SDValue Lo = Op.getOperand(0);
5700 SDValue Hi = Op.getOperand(1);
5701 SDValue Amt = Op.getOperand(2);
5702 EVT AmtVT = Amt.getValueType();
5704 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5705 DAG.getConstant(BitWidth, AmtVT), Amt);
5706 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5707 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5708 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5709 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5710 DAG.getConstant(-BitWidth, AmtVT));
5711 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5712 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5713 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5714 Tmp4, Tmp6, ISD::SETLE);
5715 SDValue OutOps[] = { OutLo, OutHi };
5716 return DAG.getMergeValues(OutOps, dl);
5719 //===----------------------------------------------------------------------===//
5720 // Vector related lowering.
5723 /// BuildSplatI - Build a canonical splati of Val with an element size of
5724 /// SplatSize. Cast the result to VT.
5725 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5726 SelectionDAG &DAG, SDLoc dl) {
5727 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5729 static const EVT VTys[] = { // canonical VT to use for each size.
5730 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5733 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5735 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5739 EVT CanonicalVT = VTys[SplatSize-1];
5741 // Build a canonical splat for this value.
5742 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5743 SmallVector<SDValue, 8> Ops;
5744 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5745 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5746 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5749 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5750 /// specified intrinsic ID.
5751 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5752 SelectionDAG &DAG, SDLoc dl,
5753 EVT DestVT = MVT::Other) {
5754 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5755 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5756 DAG.getConstant(IID, MVT::i32), Op);
5759 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5760 /// specified intrinsic ID.
5761 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5762 SelectionDAG &DAG, SDLoc dl,
5763 EVT DestVT = MVT::Other) {
5764 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5765 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5766 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5769 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5770 /// specified intrinsic ID.
5771 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5772 SDValue Op2, SelectionDAG &DAG,
5773 SDLoc dl, EVT DestVT = MVT::Other) {
5774 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5775 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5776 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5780 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5781 /// amount. The result has the specified value type.
5782 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5783 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5784 // Force LHS/RHS to be the right type.
5785 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5786 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5789 for (unsigned i = 0; i != 16; ++i)
5791 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5792 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5795 // If this is a case we can't handle, return null and let the default
5796 // expansion code take care of it. If we CAN select this case, and if it
5797 // selects to a single instruction, return Op. Otherwise, if we can codegen
5798 // this case more efficiently than a constant pool load, lower it to the
5799 // sequence of ops that should be used.
5800 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5801 SelectionDAG &DAG) const {
5803 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5804 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5806 // Check if this is a splat of a constant value.
5807 APInt APSplatBits, APSplatUndef;
5808 unsigned SplatBitSize;
5810 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5811 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5814 unsigned SplatBits = APSplatBits.getZExtValue();
5815 unsigned SplatUndef = APSplatUndef.getZExtValue();
5816 unsigned SplatSize = SplatBitSize / 8;
5818 // First, handle single instruction cases.
5821 if (SplatBits == 0) {
5822 // Canonicalize all zero vectors to be v4i32.
5823 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5824 SDValue Z = DAG.getConstant(0, MVT::i32);
5825 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5826 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5831 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5832 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5834 if (SextVal >= -16 && SextVal <= 15)
5835 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5838 // Two instruction sequences.
5840 // If this value is in the range [-32,30] and is even, use:
5841 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5842 // If this value is in the range [17,31] and is odd, use:
5843 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5844 // If this value is in the range [-31,-17] and is odd, use:
5845 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5846 // Note the last two are three-instruction sequences.
5847 if (SextVal >= -32 && SextVal <= 31) {
5848 // To avoid having these optimizations undone by constant folding,
5849 // we convert to a pseudo that will be expanded later into one of
5851 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5852 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5853 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5854 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5855 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5856 if (VT == Op.getValueType())
5859 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5862 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5863 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5865 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5866 // Make -1 and vspltisw -1:
5867 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5869 // Make the VSLW intrinsic, computing 0x8000_0000.
5870 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5873 // xor by OnesV to invert it.
5874 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5875 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5878 // The remaining cases assume either big endian element order or
5879 // a splat-size that equates to the element size of the vector
5880 // to be built. An example that doesn't work for little endian is
5881 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5882 // and a vector element size of 16 bits. The code below will
5883 // produce the vector in big endian element order, which for little
5884 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5886 // For now, just avoid these optimizations in that case.
5887 // FIXME: Develop correct optimizations for LE with mismatched
5888 // splat and element sizes.
5890 if (Subtarget.isLittleEndian() &&
5891 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5894 // Check to see if this is a wide variety of vsplti*, binop self cases.
5895 static const signed char SplatCsts[] = {
5896 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5897 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5900 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5901 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5902 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5903 int i = SplatCsts[idx];
5905 // Figure out what shift amount will be used by altivec if shifted by i in
5907 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5909 // vsplti + shl self.
5910 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5911 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5912 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5913 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5914 Intrinsic::ppc_altivec_vslw
5916 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5917 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5920 // vsplti + srl self.
5921 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5922 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5923 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5924 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5925 Intrinsic::ppc_altivec_vsrw
5927 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5928 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5931 // vsplti + sra self.
5932 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5933 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5934 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5935 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5936 Intrinsic::ppc_altivec_vsraw
5938 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5939 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5942 // vsplti + rol self.
5943 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5944 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5945 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5946 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5947 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5948 Intrinsic::ppc_altivec_vrlw
5950 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5951 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5954 // t = vsplti c, result = vsldoi t, t, 1
5955 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5956 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5957 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5959 // t = vsplti c, result = vsldoi t, t, 2
5960 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5961 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5962 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5964 // t = vsplti c, result = vsldoi t, t, 3
5965 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5966 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5967 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5974 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5975 /// the specified operations to build the shuffle.
5976 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5977 SDValue RHS, SelectionDAG &DAG,
5979 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5980 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5981 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5984 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5996 if (OpNum == OP_COPY) {
5997 if (LHSID == (1*9+2)*9+3) return LHS;
5998 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6002 SDValue OpLHS, OpRHS;
6003 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6004 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6008 default: llvm_unreachable("Unknown i32 permute!");
6010 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6011 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6012 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6013 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6016 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6017 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6018 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6019 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6022 for (unsigned i = 0; i != 16; ++i)
6023 ShufIdxs[i] = (i&3)+0;
6026 for (unsigned i = 0; i != 16; ++i)
6027 ShufIdxs[i] = (i&3)+4;
6030 for (unsigned i = 0; i != 16; ++i)
6031 ShufIdxs[i] = (i&3)+8;
6034 for (unsigned i = 0; i != 16; ++i)
6035 ShufIdxs[i] = (i&3)+12;
6038 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6040 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6042 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6044 EVT VT = OpLHS.getValueType();
6045 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6046 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6047 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6048 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6051 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6052 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6053 /// return the code it can be lowered into. Worst case, it can always be
6054 /// lowered into a vperm.
6055 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6056 SelectionDAG &DAG) const {
6058 SDValue V1 = Op.getOperand(0);
6059 SDValue V2 = Op.getOperand(1);
6060 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6061 EVT VT = Op.getValueType();
6062 bool isLittleEndian = Subtarget.isLittleEndian();
6064 // Cases that are handled by instructions that take permute immediates
6065 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6066 // selected by the instruction selector.
6067 if (V2.getOpcode() == ISD::UNDEF) {
6068 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6069 PPC::isSplatShuffleMask(SVOp, 2) ||
6070 PPC::isSplatShuffleMask(SVOp, 4) ||
6071 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6072 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6073 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6074 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6075 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6076 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6077 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6078 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6079 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6084 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6085 // and produce a fixed permutation. If any of these match, do not lower to
6087 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6088 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6089 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6090 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6091 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6092 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6093 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6094 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6095 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6096 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6099 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6100 // perfect shuffle table to emit an optimal matching sequence.
6101 ArrayRef<int> PermMask = SVOp->getMask();
6103 unsigned PFIndexes[4];
6104 bool isFourElementShuffle = true;
6105 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6106 unsigned EltNo = 8; // Start out undef.
6107 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6108 if (PermMask[i*4+j] < 0)
6109 continue; // Undef, ignore it.
6111 unsigned ByteSource = PermMask[i*4+j];
6112 if ((ByteSource & 3) != j) {
6113 isFourElementShuffle = false;
6118 EltNo = ByteSource/4;
6119 } else if (EltNo != ByteSource/4) {
6120 isFourElementShuffle = false;
6124 PFIndexes[i] = EltNo;
6127 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6128 // perfect shuffle vector to determine if it is cost effective to do this as
6129 // discrete instructions, or whether we should use a vperm.
6130 // For now, we skip this for little endian until such time as we have a
6131 // little-endian perfect shuffle table.
6132 if (isFourElementShuffle && !isLittleEndian) {
6133 // Compute the index in the perfect shuffle table.
6134 unsigned PFTableIndex =
6135 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6137 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6138 unsigned Cost = (PFEntry >> 30);
6140 // Determining when to avoid vperm is tricky. Many things affect the cost
6141 // of vperm, particularly how many times the perm mask needs to be computed.
6142 // For example, if the perm mask can be hoisted out of a loop or is already
6143 // used (perhaps because there are multiple permutes with the same shuffle
6144 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6145 // the loop requires an extra register.
6147 // As a compromise, we only emit discrete instructions if the shuffle can be
6148 // generated in 3 or fewer operations. When we have loop information
6149 // available, if this block is within a loop, we should avoid using vperm
6150 // for 3-operation perms and use a constant pool load instead.
6152 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6155 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6156 // vector that will get spilled to the constant pool.
6157 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6159 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6160 // that it is in input element units, not in bytes. Convert now.
6162 // For little endian, the order of the input vectors is reversed, and
6163 // the permutation mask is complemented with respect to 31. This is
6164 // necessary to produce proper semantics with the big-endian-biased vperm
6166 EVT EltVT = V1.getValueType().getVectorElementType();
6167 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6169 SmallVector<SDValue, 16> ResultMask;
6170 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6171 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6173 for (unsigned j = 0; j != BytesPerElement; ++j)
6175 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6178 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6182 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6185 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6188 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6192 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6193 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6194 /// information about the intrinsic.
6195 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6197 unsigned IntrinsicID =
6198 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6201 switch (IntrinsicID) {
6202 default: return false;
6203 // Comparison predicates.
6204 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6205 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6206 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6207 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6208 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6209 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6210 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6211 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6212 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6213 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6214 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6215 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6216 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6218 // Normal Comparisons.
6219 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6220 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6221 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6222 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6223 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6224 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6225 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6226 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6227 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6228 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6229 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6230 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6231 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6236 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6237 /// lower, do it, otherwise return null.
6238 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6239 SelectionDAG &DAG) const {
6240 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6241 // opcode number of the comparison.
6245 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6246 return SDValue(); // Don't custom lower most intrinsics.
6248 // If this is a non-dot comparison, make the VCMP node and we are done.
6250 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6251 Op.getOperand(1), Op.getOperand(2),
6252 DAG.getConstant(CompareOpc, MVT::i32));
6253 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6256 // Create the PPCISD altivec 'dot' comparison node.
6258 Op.getOperand(2), // LHS
6259 Op.getOperand(3), // RHS
6260 DAG.getConstant(CompareOpc, MVT::i32)
6262 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6263 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6265 // Now that we have the comparison, emit a copy from the CR to a GPR.
6266 // This is flagged to the above dot comparison.
6267 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6268 DAG.getRegister(PPC::CR6, MVT::i32),
6269 CompNode.getValue(1));
6271 // Unpack the result based on how the target uses it.
6272 unsigned BitNo; // Bit # of CR6.
6273 bool InvertBit; // Invert result?
6274 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6275 default: // Can't happen, don't crash on invalid number though.
6276 case 0: // Return the value of the EQ bit of CR6.
6277 BitNo = 0; InvertBit = false;
6279 case 1: // Return the inverted value of the EQ bit of CR6.
6280 BitNo = 0; InvertBit = true;
6282 case 2: // Return the value of the LT bit of CR6.
6283 BitNo = 2; InvertBit = false;
6285 case 3: // Return the inverted value of the LT bit of CR6.
6286 BitNo = 2; InvertBit = true;
6290 // Shift the bit into the low position.
6291 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6292 DAG.getConstant(8-(3-BitNo), MVT::i32));
6294 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6295 DAG.getConstant(1, MVT::i32));
6297 // If we are supposed to, toggle the bit.
6299 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6300 DAG.getConstant(1, MVT::i32));
6304 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6305 SelectionDAG &DAG) const {
6307 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6308 // instructions), but for smaller types, we need to first extend up to v2i32
6309 // before doing going farther.
6310 if (Op.getValueType() == MVT::v2i64) {
6311 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6312 if (ExtVT != MVT::v2i32) {
6313 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6314 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6315 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6316 ExtVT.getVectorElementType(), 4)));
6317 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6318 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6319 DAG.getValueType(MVT::v2i32));
6328 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6329 SelectionDAG &DAG) const {
6331 // Create a stack slot that is 16-byte aligned.
6332 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6333 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6334 EVT PtrVT = getPointerTy();
6335 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6337 // Store the input value into Value#0 of the stack slot.
6338 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6339 Op.getOperand(0), FIdx, MachinePointerInfo(),
6342 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6343 false, false, false, 0);
6346 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6348 if (Op.getValueType() == MVT::v4i32) {
6349 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6351 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6352 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6354 SDValue RHSSwap = // = vrlw RHS, 16
6355 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6357 // Shrinkify inputs to v8i16.
6358 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6359 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6360 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6362 // Low parts multiplied together, generating 32-bit results (we ignore the
6364 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6365 LHS, RHS, DAG, dl, MVT::v4i32);
6367 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6368 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6369 // Shift the high parts up 16 bits.
6370 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6372 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6373 } else if (Op.getValueType() == MVT::v8i16) {
6374 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6376 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6378 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6379 LHS, RHS, Zero, DAG, dl);
6380 } else if (Op.getValueType() == MVT::v16i8) {
6381 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6382 bool isLittleEndian = Subtarget.isLittleEndian();
6384 // Multiply the even 8-bit parts, producing 16-bit sums.
6385 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6386 LHS, RHS, DAG, dl, MVT::v8i16);
6387 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6389 // Multiply the odd 8-bit parts, producing 16-bit sums.
6390 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6391 LHS, RHS, DAG, dl, MVT::v8i16);
6392 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6394 // Merge the results together. Because vmuleub and vmuloub are
6395 // instructions with a big-endian bias, we must reverse the
6396 // element numbering and reverse the meaning of "odd" and "even"
6397 // when generating little endian code.
6399 for (unsigned i = 0; i != 8; ++i) {
6400 if (isLittleEndian) {
6402 Ops[i*2+1] = 2*i+16;
6405 Ops[i*2+1] = 2*i+1+16;
6409 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6411 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6413 llvm_unreachable("Unknown mul to lower!");
6417 /// LowerOperation - Provide custom lowering hooks for some operations.
6419 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6420 switch (Op.getOpcode()) {
6421 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6422 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6423 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6424 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6425 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6426 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6427 case ISD::SETCC: return LowerSETCC(Op, DAG);
6428 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6429 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6431 return LowerVASTART(Op, DAG, Subtarget);
6434 return LowerVAARG(Op, DAG, Subtarget);
6437 return LowerVACOPY(Op, DAG, Subtarget);
6439 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6440 case ISD::DYNAMIC_STACKALLOC:
6441 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6443 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6444 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6446 case ISD::LOAD: return LowerLOAD(Op, DAG);
6447 case ISD::STORE: return LowerSTORE(Op, DAG);
6448 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6449 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6450 case ISD::FP_TO_UINT:
6451 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6453 case ISD::UINT_TO_FP:
6454 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6455 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6457 // Lower 64-bit shifts.
6458 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6459 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6460 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6462 // Vector-related lowering.
6463 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6464 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6465 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6466 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6467 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6468 case ISD::MUL: return LowerMUL(Op, DAG);
6470 // For counter-based loop handling.
6471 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6473 // Frame & Return address.
6474 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6475 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6479 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6480 SmallVectorImpl<SDValue>&Results,
6481 SelectionDAG &DAG) const {
6482 const TargetMachine &TM = getTargetMachine();
6484 switch (N->getOpcode()) {
6486 llvm_unreachable("Do not know how to custom type legalize this operation!");
6487 case ISD::INTRINSIC_W_CHAIN: {
6488 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6489 Intrinsic::ppc_is_decremented_ctr_nonzero)
6492 assert(N->getValueType(0) == MVT::i1 &&
6493 "Unexpected result type for CTR decrement intrinsic");
6494 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6495 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6496 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6499 Results.push_back(NewInt);
6500 Results.push_back(NewInt.getValue(1));
6504 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6505 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6508 EVT VT = N->getValueType(0);
6510 if (VT == MVT::i64) {
6511 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6513 Results.push_back(NewNode);
6514 Results.push_back(NewNode.getValue(1));
6518 case ISD::FP_ROUND_INREG: {
6519 assert(N->getValueType(0) == MVT::ppcf128);
6520 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6521 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6522 MVT::f64, N->getOperand(0),
6523 DAG.getIntPtrConstant(0));
6524 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6525 MVT::f64, N->getOperand(0),
6526 DAG.getIntPtrConstant(1));
6528 // Add the two halves of the long double in round-to-zero mode.
6529 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6531 // We know the low half is about to be thrown away, so just use something
6533 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6537 case ISD::FP_TO_SINT:
6538 // LowerFP_TO_INT() can only handle f32 and f64.
6539 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6541 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6547 //===----------------------------------------------------------------------===//
6548 // Other Lowering Code
6549 //===----------------------------------------------------------------------===//
6552 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6553 bool is64bit, unsigned BinOpcode) const {
6554 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6555 const TargetInstrInfo *TII =
6556 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6558 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6559 MachineFunction *F = BB->getParent();
6560 MachineFunction::iterator It = BB;
6563 unsigned dest = MI->getOperand(0).getReg();
6564 unsigned ptrA = MI->getOperand(1).getReg();
6565 unsigned ptrB = MI->getOperand(2).getReg();
6566 unsigned incr = MI->getOperand(3).getReg();
6567 DebugLoc dl = MI->getDebugLoc();
6569 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6570 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6571 F->insert(It, loopMBB);
6572 F->insert(It, exitMBB);
6573 exitMBB->splice(exitMBB->begin(), BB,
6574 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6575 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6577 MachineRegisterInfo &RegInfo = F->getRegInfo();
6578 unsigned TmpReg = (!BinOpcode) ? incr :
6579 RegInfo.createVirtualRegister(
6580 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6581 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6585 // fallthrough --> loopMBB
6586 BB->addSuccessor(loopMBB);
6589 // l[wd]arx dest, ptr
6590 // add r0, dest, incr
6591 // st[wd]cx. r0, ptr
6593 // fallthrough --> exitMBB
6595 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6596 .addReg(ptrA).addReg(ptrB);
6598 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6599 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6600 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6601 BuildMI(BB, dl, TII->get(PPC::BCC))
6602 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6603 BB->addSuccessor(loopMBB);
6604 BB->addSuccessor(exitMBB);
6613 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6614 MachineBasicBlock *BB,
6615 bool is8bit, // operation
6616 unsigned BinOpcode) const {
6617 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6618 const TargetInstrInfo *TII =
6619 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6620 // In 64 bit mode we have to use 64 bits for addresses, even though the
6621 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6622 // registers without caring whether they're 32 or 64, but here we're
6623 // doing actual arithmetic on the addresses.
6624 bool is64bit = Subtarget.isPPC64();
6625 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6627 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6628 MachineFunction *F = BB->getParent();
6629 MachineFunction::iterator It = BB;
6632 unsigned dest = MI->getOperand(0).getReg();
6633 unsigned ptrA = MI->getOperand(1).getReg();
6634 unsigned ptrB = MI->getOperand(2).getReg();
6635 unsigned incr = MI->getOperand(3).getReg();
6636 DebugLoc dl = MI->getDebugLoc();
6638 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6639 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6640 F->insert(It, loopMBB);
6641 F->insert(It, exitMBB);
6642 exitMBB->splice(exitMBB->begin(), BB,
6643 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6644 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6646 MachineRegisterInfo &RegInfo = F->getRegInfo();
6647 const TargetRegisterClass *RC =
6648 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6649 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6650 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6651 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6652 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6653 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6654 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6655 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6656 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6657 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6658 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6659 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6660 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6662 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6666 // fallthrough --> loopMBB
6667 BB->addSuccessor(loopMBB);
6669 // The 4-byte load must be aligned, while a char or short may be
6670 // anywhere in the word. Hence all this nasty bookkeeping code.
6671 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6672 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6673 // xori shift, shift1, 24 [16]
6674 // rlwinm ptr, ptr1, 0, 0, 29
6675 // slw incr2, incr, shift
6676 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6677 // slw mask, mask2, shift
6679 // lwarx tmpDest, ptr
6680 // add tmp, tmpDest, incr2
6681 // andc tmp2, tmpDest, mask
6682 // and tmp3, tmp, mask
6683 // or tmp4, tmp3, tmp2
6686 // fallthrough --> exitMBB
6687 // srw dest, tmpDest, shift
6688 if (ptrA != ZeroReg) {
6689 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6690 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6691 .addReg(ptrA).addReg(ptrB);
6695 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6696 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6697 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6698 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6700 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6701 .addReg(Ptr1Reg).addImm(0).addImm(61);
6703 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6704 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6705 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6706 .addReg(incr).addReg(ShiftReg);
6708 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6710 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6711 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6713 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6714 .addReg(Mask2Reg).addReg(ShiftReg);
6717 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6718 .addReg(ZeroReg).addReg(PtrReg);
6720 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6721 .addReg(Incr2Reg).addReg(TmpDestReg);
6722 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6723 .addReg(TmpDestReg).addReg(MaskReg);
6724 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6725 .addReg(TmpReg).addReg(MaskReg);
6726 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6727 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6728 BuildMI(BB, dl, TII->get(PPC::STWCX))
6729 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6730 BuildMI(BB, dl, TII->get(PPC::BCC))
6731 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6732 BB->addSuccessor(loopMBB);
6733 BB->addSuccessor(exitMBB);
6738 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6743 llvm::MachineBasicBlock*
6744 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6745 MachineBasicBlock *MBB) const {
6746 DebugLoc DL = MI->getDebugLoc();
6747 const TargetInstrInfo *TII =
6748 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6750 MachineFunction *MF = MBB->getParent();
6751 MachineRegisterInfo &MRI = MF->getRegInfo();
6753 const BasicBlock *BB = MBB->getBasicBlock();
6754 MachineFunction::iterator I = MBB;
6758 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6759 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6761 unsigned DstReg = MI->getOperand(0).getReg();
6762 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6763 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6764 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6765 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6767 MVT PVT = getPointerTy();
6768 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6769 "Invalid Pointer Size!");
6770 // For v = setjmp(buf), we generate
6773 // SjLjSetup mainMBB
6779 // buf[LabelOffset] = LR
6783 // v = phi(main, restore)
6786 MachineBasicBlock *thisMBB = MBB;
6787 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6788 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6789 MF->insert(I, mainMBB);
6790 MF->insert(I, sinkMBB);
6792 MachineInstrBuilder MIB;
6794 // Transfer the remainder of BB and its successor edges to sinkMBB.
6795 sinkMBB->splice(sinkMBB->begin(), MBB,
6796 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6797 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6799 // Note that the structure of the jmp_buf used here is not compatible
6800 // with that used by libc, and is not designed to be. Specifically, it
6801 // stores only those 'reserved' registers that LLVM does not otherwise
6802 // understand how to spill. Also, by convention, by the time this
6803 // intrinsic is called, Clang has already stored the frame address in the
6804 // first slot of the buffer and stack address in the third. Following the
6805 // X86 target code, we'll store the jump address in the second slot. We also
6806 // need to save the TOC pointer (R2) to handle jumps between shared
6807 // libraries, and that will be stored in the fourth slot. The thread
6808 // identifier (R13) is not affected.
6811 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6812 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6813 const int64_t BPOffset = 4 * PVT.getStoreSize();
6815 // Prepare IP either in reg.
6816 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6817 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6818 unsigned BufReg = MI->getOperand(1).getReg();
6820 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6821 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6825 MIB.setMemRefs(MMOBegin, MMOEnd);
6828 // Naked functions never have a base pointer, and so we use r1. For all
6829 // other functions, this decision must be delayed until during PEI.
6831 if (MF->getFunction()->getAttributes().hasAttribute(
6832 AttributeSet::FunctionIndex, Attribute::Naked))
6833 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6835 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6837 MIB = BuildMI(*thisMBB, MI, DL,
6838 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6842 MIB.setMemRefs(MMOBegin, MMOEnd);
6845 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6846 const PPCRegisterInfo *TRI =
6847 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6848 MIB.addRegMask(TRI->getNoPreservedMask());
6850 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6852 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6854 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6856 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6857 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6861 MIB = BuildMI(mainMBB, DL,
6862 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6865 if (Subtarget.isPPC64()) {
6866 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6868 .addImm(LabelOffset)
6871 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6873 .addImm(LabelOffset)
6877 MIB.setMemRefs(MMOBegin, MMOEnd);
6879 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6880 mainMBB->addSuccessor(sinkMBB);
6883 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6884 TII->get(PPC::PHI), DstReg)
6885 .addReg(mainDstReg).addMBB(mainMBB)
6886 .addReg(restoreDstReg).addMBB(thisMBB);
6888 MI->eraseFromParent();
6893 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6894 MachineBasicBlock *MBB) const {
6895 DebugLoc DL = MI->getDebugLoc();
6896 const TargetInstrInfo *TII =
6897 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6899 MachineFunction *MF = MBB->getParent();
6900 MachineRegisterInfo &MRI = MF->getRegInfo();
6903 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6904 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6906 MVT PVT = getPointerTy();
6907 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6908 "Invalid Pointer Size!");
6910 const TargetRegisterClass *RC =
6911 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6912 unsigned Tmp = MRI.createVirtualRegister(RC);
6913 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6914 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6915 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6916 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6917 (Subtarget.isSVR4ABI() &&
6918 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6919 PPC::R29 : PPC::R30);
6921 MachineInstrBuilder MIB;
6923 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6924 const int64_t SPOffset = 2 * PVT.getStoreSize();
6925 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6926 const int64_t BPOffset = 4 * PVT.getStoreSize();
6928 unsigned BufReg = MI->getOperand(0).getReg();
6930 // Reload FP (the jumped-to function may not have had a
6931 // frame pointer, and if so, then its r31 will be restored
6933 if (PVT == MVT::i64) {
6934 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6938 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6942 MIB.setMemRefs(MMOBegin, MMOEnd);
6945 if (PVT == MVT::i64) {
6946 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6947 .addImm(LabelOffset)
6950 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6951 .addImm(LabelOffset)
6954 MIB.setMemRefs(MMOBegin, MMOEnd);
6957 if (PVT == MVT::i64) {
6958 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6962 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6966 MIB.setMemRefs(MMOBegin, MMOEnd);
6969 if (PVT == MVT::i64) {
6970 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6974 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6978 MIB.setMemRefs(MMOBegin, MMOEnd);
6981 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6982 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6986 MIB.setMemRefs(MMOBegin, MMOEnd);
6990 BuildMI(*MBB, MI, DL,
6991 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6992 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6994 MI->eraseFromParent();
6999 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7000 MachineBasicBlock *BB) const {
7001 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7002 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7003 return emitEHSjLjSetJmp(MI, BB);
7004 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7005 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7006 return emitEHSjLjLongJmp(MI, BB);
7009 const TargetInstrInfo *TII =
7010 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7012 // To "insert" these instructions we actually have to insert their
7013 // control-flow patterns.
7014 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7015 MachineFunction::iterator It = BB;
7018 MachineFunction *F = BB->getParent();
7020 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7021 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7022 MI->getOpcode() == PPC::SELECT_I4 ||
7023 MI->getOpcode() == PPC::SELECT_I8)) {
7024 SmallVector<MachineOperand, 2> Cond;
7025 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7026 MI->getOpcode() == PPC::SELECT_CC_I8)
7027 Cond.push_back(MI->getOperand(4));
7029 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7030 Cond.push_back(MI->getOperand(1));
7032 DebugLoc dl = MI->getDebugLoc();
7033 const TargetInstrInfo *TII =
7034 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7035 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7036 Cond, MI->getOperand(2).getReg(),
7037 MI->getOperand(3).getReg());
7038 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7039 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7040 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7041 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7042 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7043 MI->getOpcode() == PPC::SELECT_I4 ||
7044 MI->getOpcode() == PPC::SELECT_I8 ||
7045 MI->getOpcode() == PPC::SELECT_F4 ||
7046 MI->getOpcode() == PPC::SELECT_F8 ||
7047 MI->getOpcode() == PPC::SELECT_VRRC) {
7048 // The incoming instruction knows the destination vreg to set, the
7049 // condition code register to branch on, the true/false values to
7050 // select between, and a branch opcode to use.
7055 // cmpTY ccX, r1, r2
7057 // fallthrough --> copy0MBB
7058 MachineBasicBlock *thisMBB = BB;
7059 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7060 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7061 DebugLoc dl = MI->getDebugLoc();
7062 F->insert(It, copy0MBB);
7063 F->insert(It, sinkMBB);
7065 // Transfer the remainder of BB and its successor edges to sinkMBB.
7066 sinkMBB->splice(sinkMBB->begin(), BB,
7067 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7068 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7070 // Next, add the true and fallthrough blocks as its successors.
7071 BB->addSuccessor(copy0MBB);
7072 BB->addSuccessor(sinkMBB);
7074 if (MI->getOpcode() == PPC::SELECT_I4 ||
7075 MI->getOpcode() == PPC::SELECT_I8 ||
7076 MI->getOpcode() == PPC::SELECT_F4 ||
7077 MI->getOpcode() == PPC::SELECT_F8 ||
7078 MI->getOpcode() == PPC::SELECT_VRRC) {
7079 BuildMI(BB, dl, TII->get(PPC::BC))
7080 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7082 unsigned SelectPred = MI->getOperand(4).getImm();
7083 BuildMI(BB, dl, TII->get(PPC::BCC))
7084 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7088 // %FalseValue = ...
7089 // # fallthrough to sinkMBB
7092 // Update machine-CFG edges
7093 BB->addSuccessor(sinkMBB);
7096 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7099 BuildMI(*BB, BB->begin(), dl,
7100 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7101 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7102 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7105 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7107 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7108 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7109 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7110 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7111 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7114 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7116 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7117 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7118 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7119 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7120 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7123 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7125 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7126 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7127 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7128 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7129 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7132 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7134 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7135 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7136 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7137 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7138 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7140 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7141 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7142 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7143 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7144 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7145 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7146 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7147 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7149 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7150 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7151 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7152 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7153 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7154 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7155 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7156 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7158 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7159 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7160 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7161 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7162 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7163 BB = EmitAtomicBinary(MI, BB, false, 0);
7164 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7165 BB = EmitAtomicBinary(MI, BB, true, 0);
7167 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7168 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7169 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7171 unsigned dest = MI->getOperand(0).getReg();
7172 unsigned ptrA = MI->getOperand(1).getReg();
7173 unsigned ptrB = MI->getOperand(2).getReg();
7174 unsigned oldval = MI->getOperand(3).getReg();
7175 unsigned newval = MI->getOperand(4).getReg();
7176 DebugLoc dl = MI->getDebugLoc();
7178 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7179 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7180 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7181 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7182 F->insert(It, loop1MBB);
7183 F->insert(It, loop2MBB);
7184 F->insert(It, midMBB);
7185 F->insert(It, exitMBB);
7186 exitMBB->splice(exitMBB->begin(), BB,
7187 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7188 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7192 // fallthrough --> loopMBB
7193 BB->addSuccessor(loop1MBB);
7196 // l[wd]arx dest, ptr
7197 // cmp[wd] dest, oldval
7200 // st[wd]cx. newval, ptr
7204 // st[wd]cx. dest, ptr
7207 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7208 .addReg(ptrA).addReg(ptrB);
7209 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7210 .addReg(oldval).addReg(dest);
7211 BuildMI(BB, dl, TII->get(PPC::BCC))
7212 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7213 BB->addSuccessor(loop2MBB);
7214 BB->addSuccessor(midMBB);
7217 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7218 .addReg(newval).addReg(ptrA).addReg(ptrB);
7219 BuildMI(BB, dl, TII->get(PPC::BCC))
7220 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7221 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7222 BB->addSuccessor(loop1MBB);
7223 BB->addSuccessor(exitMBB);
7226 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7227 .addReg(dest).addReg(ptrA).addReg(ptrB);
7228 BB->addSuccessor(exitMBB);
7233 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7234 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7235 // We must use 64-bit registers for addresses when targeting 64-bit,
7236 // since we're actually doing arithmetic on them. Other registers
7238 bool is64bit = Subtarget.isPPC64();
7239 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7241 unsigned dest = MI->getOperand(0).getReg();
7242 unsigned ptrA = MI->getOperand(1).getReg();
7243 unsigned ptrB = MI->getOperand(2).getReg();
7244 unsigned oldval = MI->getOperand(3).getReg();
7245 unsigned newval = MI->getOperand(4).getReg();
7246 DebugLoc dl = MI->getDebugLoc();
7248 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7249 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7250 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7251 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7252 F->insert(It, loop1MBB);
7253 F->insert(It, loop2MBB);
7254 F->insert(It, midMBB);
7255 F->insert(It, exitMBB);
7256 exitMBB->splice(exitMBB->begin(), BB,
7257 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7258 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7260 MachineRegisterInfo &RegInfo = F->getRegInfo();
7261 const TargetRegisterClass *RC =
7262 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7263 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7264 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7265 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7266 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7267 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7268 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7269 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7270 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7271 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7272 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7273 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7274 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7275 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7276 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7278 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7279 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7282 // fallthrough --> loopMBB
7283 BB->addSuccessor(loop1MBB);
7285 // The 4-byte load must be aligned, while a char or short may be
7286 // anywhere in the word. Hence all this nasty bookkeeping code.
7287 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7288 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7289 // xori shift, shift1, 24 [16]
7290 // rlwinm ptr, ptr1, 0, 0, 29
7291 // slw newval2, newval, shift
7292 // slw oldval2, oldval,shift
7293 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7294 // slw mask, mask2, shift
7295 // and newval3, newval2, mask
7296 // and oldval3, oldval2, mask
7298 // lwarx tmpDest, ptr
7299 // and tmp, tmpDest, mask
7300 // cmpw tmp, oldval3
7303 // andc tmp2, tmpDest, mask
7304 // or tmp4, tmp2, newval3
7309 // stwcx. tmpDest, ptr
7311 // srw dest, tmpDest, shift
7312 if (ptrA != ZeroReg) {
7313 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7314 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7315 .addReg(ptrA).addReg(ptrB);
7319 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7320 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7321 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7322 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7324 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7325 .addReg(Ptr1Reg).addImm(0).addImm(61);
7327 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7328 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7329 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7330 .addReg(newval).addReg(ShiftReg);
7331 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7332 .addReg(oldval).addReg(ShiftReg);
7334 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7336 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7337 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7338 .addReg(Mask3Reg).addImm(65535);
7340 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7341 .addReg(Mask2Reg).addReg(ShiftReg);
7342 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7343 .addReg(NewVal2Reg).addReg(MaskReg);
7344 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7345 .addReg(OldVal2Reg).addReg(MaskReg);
7348 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7349 .addReg(ZeroReg).addReg(PtrReg);
7350 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7351 .addReg(TmpDestReg).addReg(MaskReg);
7352 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7353 .addReg(TmpReg).addReg(OldVal3Reg);
7354 BuildMI(BB, dl, TII->get(PPC::BCC))
7355 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7356 BB->addSuccessor(loop2MBB);
7357 BB->addSuccessor(midMBB);
7360 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7361 .addReg(TmpDestReg).addReg(MaskReg);
7362 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7363 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7364 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7365 .addReg(ZeroReg).addReg(PtrReg);
7366 BuildMI(BB, dl, TII->get(PPC::BCC))
7367 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7368 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7369 BB->addSuccessor(loop1MBB);
7370 BB->addSuccessor(exitMBB);
7373 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7374 .addReg(ZeroReg).addReg(PtrReg);
7375 BB->addSuccessor(exitMBB);
7380 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7382 } else if (MI->getOpcode() == PPC::FADDrtz) {
7383 // This pseudo performs an FADD with rounding mode temporarily forced
7384 // to round-to-zero. We emit this via custom inserter since the FPSCR
7385 // is not modeled at the SelectionDAG level.
7386 unsigned Dest = MI->getOperand(0).getReg();
7387 unsigned Src1 = MI->getOperand(1).getReg();
7388 unsigned Src2 = MI->getOperand(2).getReg();
7389 DebugLoc dl = MI->getDebugLoc();
7391 MachineRegisterInfo &RegInfo = F->getRegInfo();
7392 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7394 // Save FPSCR value.
7395 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7397 // Set rounding mode to round-to-zero.
7398 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7399 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7401 // Perform addition.
7402 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7404 // Restore FPSCR value.
7405 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7406 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7407 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7408 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7409 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7410 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7411 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7412 PPC::ANDIo8 : PPC::ANDIo;
7413 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7414 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7416 MachineRegisterInfo &RegInfo = F->getRegInfo();
7417 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7418 &PPC::GPRCRegClass :
7419 &PPC::G8RCRegClass);
7421 DebugLoc dl = MI->getDebugLoc();
7422 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7423 .addReg(MI->getOperand(1).getReg()).addImm(1);
7424 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7425 MI->getOperand(0).getReg())
7426 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7428 llvm_unreachable("Unexpected instr type to insert");
7431 MI->eraseFromParent(); // The pseudo instruction is gone now.
7435 //===----------------------------------------------------------------------===//
7436 // Target Optimization Hooks
7437 //===----------------------------------------------------------------------===//
7439 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7440 DAGCombinerInfo &DCI) const {
7441 if (DCI.isAfterLegalizeVectorOps())
7444 EVT VT = Op.getValueType();
7446 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7447 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7448 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7449 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7451 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7452 // For the reciprocal, we need to find the zero of the function:
7453 // F(X) = A X - 1 [which has a zero at X = 1/A]
7455 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7456 // does not require additional intermediate precision]
7458 // Convergence is quadratic, so we essentially double the number of digits
7459 // correct after every iteration. The minimum architected relative
7460 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7461 // 23 digits and double has 52 digits.
7462 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7463 if (VT.getScalarType() == MVT::f64)
7466 SelectionDAG &DAG = DCI.DAG;
7470 DAG.getConstantFP(1.0, VT.getScalarType());
7471 if (VT.isVector()) {
7472 assert(VT.getVectorNumElements() == 4 &&
7473 "Unknown vector type");
7474 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7475 FPOne, FPOne, FPOne, FPOne);
7478 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7479 DCI.AddToWorklist(Est.getNode());
7481 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7482 for (int i = 0; i < Iterations; ++i) {
7483 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7484 DCI.AddToWorklist(NewEst.getNode());
7486 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7487 DCI.AddToWorklist(NewEst.getNode());
7489 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7490 DCI.AddToWorklist(NewEst.getNode());
7492 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7493 DCI.AddToWorklist(Est.getNode());
7502 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7503 DAGCombinerInfo &DCI) const {
7504 if (DCI.isAfterLegalizeVectorOps())
7507 EVT VT = Op.getValueType();
7509 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7510 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7511 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7512 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7514 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7515 // For the reciprocal sqrt, we need to find the zero of the function:
7516 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7518 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7519 // As a result, we precompute A/2 prior to the iteration loop.
7521 // Convergence is quadratic, so we essentially double the number of digits
7522 // correct after every iteration. The minimum architected relative
7523 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7524 // 23 digits and double has 52 digits.
7525 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7526 if (VT.getScalarType() == MVT::f64)
7529 SelectionDAG &DAG = DCI.DAG;
7532 SDValue FPThreeHalves =
7533 DAG.getConstantFP(1.5, VT.getScalarType());
7534 if (VT.isVector()) {
7535 assert(VT.getVectorNumElements() == 4 &&
7536 "Unknown vector type");
7537 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7538 FPThreeHalves, FPThreeHalves,
7539 FPThreeHalves, FPThreeHalves);
7542 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7543 DCI.AddToWorklist(Est.getNode());
7545 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7546 // this entire sequence requires only one FP constant.
7547 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7548 DCI.AddToWorklist(HalfArg.getNode());
7550 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7551 DCI.AddToWorklist(HalfArg.getNode());
7553 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7554 for (int i = 0; i < Iterations; ++i) {
7555 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7556 DCI.AddToWorklist(NewEst.getNode());
7558 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7559 DCI.AddToWorklist(NewEst.getNode());
7561 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7562 DCI.AddToWorklist(NewEst.getNode());
7564 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7565 DCI.AddToWorklist(Est.getNode());
7574 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7575 unsigned Bytes, int Dist,
7576 SelectionDAG &DAG) {
7577 if (VT.getSizeInBits() / 8 != Bytes)
7580 SDValue BaseLoc = Base->getBasePtr();
7581 if (Loc.getOpcode() == ISD::FrameIndex) {
7582 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7584 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7585 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7586 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7587 int FS = MFI->getObjectSize(FI);
7588 int BFS = MFI->getObjectSize(BFI);
7589 if (FS != BFS || FS != (int)Bytes) return false;
7590 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7594 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7595 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7599 const GlobalValue *GV1 = nullptr;
7600 const GlobalValue *GV2 = nullptr;
7601 int64_t Offset1 = 0;
7602 int64_t Offset2 = 0;
7603 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7604 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7605 if (isGA1 && isGA2 && GV1 == GV2)
7606 return Offset1 == (Offset2 + Dist*Bytes);
7610 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7611 // not enforce equality of the chain operands.
7612 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7613 unsigned Bytes, int Dist,
7614 SelectionDAG &DAG) {
7615 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7616 EVT VT = LS->getMemoryVT();
7617 SDValue Loc = LS->getBasePtr();
7618 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7621 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7623 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7624 default: return false;
7625 case Intrinsic::ppc_altivec_lvx:
7626 case Intrinsic::ppc_altivec_lvxl:
7629 case Intrinsic::ppc_altivec_lvebx:
7632 case Intrinsic::ppc_altivec_lvehx:
7635 case Intrinsic::ppc_altivec_lvewx:
7640 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7643 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7645 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7646 default: return false;
7647 case Intrinsic::ppc_altivec_stvx:
7648 case Intrinsic::ppc_altivec_stvxl:
7651 case Intrinsic::ppc_altivec_stvebx:
7654 case Intrinsic::ppc_altivec_stvehx:
7657 case Intrinsic::ppc_altivec_stvewx:
7662 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7668 // Return true is there is a nearyby consecutive load to the one provided
7669 // (regardless of alignment). We search up and down the chain, looking though
7670 // token factors and other loads (but nothing else). As a result, a true result
7671 // indicates that it is safe to create a new consecutive load adjacent to the
7673 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7674 SDValue Chain = LD->getChain();
7675 EVT VT = LD->getMemoryVT();
7677 SmallSet<SDNode *, 16> LoadRoots;
7678 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7679 SmallSet<SDNode *, 16> Visited;
7681 // First, search up the chain, branching to follow all token-factor operands.
7682 // If we find a consecutive load, then we're done, otherwise, record all
7683 // nodes just above the top-level loads and token factors.
7684 while (!Queue.empty()) {
7685 SDNode *ChainNext = Queue.pop_back_val();
7686 if (!Visited.insert(ChainNext))
7689 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7690 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7693 if (!Visited.count(ChainLD->getChain().getNode()))
7694 Queue.push_back(ChainLD->getChain().getNode());
7695 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7696 for (const SDUse &O : ChainNext->ops())
7697 if (!Visited.count(O.getNode()))
7698 Queue.push_back(O.getNode());
7700 LoadRoots.insert(ChainNext);
7703 // Second, search down the chain, starting from the top-level nodes recorded
7704 // in the first phase. These top-level nodes are the nodes just above all
7705 // loads and token factors. Starting with their uses, recursively look though
7706 // all loads (just the chain uses) and token factors to find a consecutive
7711 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7712 IE = LoadRoots.end(); I != IE; ++I) {
7713 Queue.push_back(*I);
7715 while (!Queue.empty()) {
7716 SDNode *LoadRoot = Queue.pop_back_val();
7717 if (!Visited.insert(LoadRoot))
7720 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7721 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7724 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7725 UE = LoadRoot->use_end(); UI != UE; ++UI)
7726 if (((isa<MemSDNode>(*UI) &&
7727 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7728 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7729 Queue.push_back(*UI);
7736 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7737 DAGCombinerInfo &DCI) const {
7738 SelectionDAG &DAG = DCI.DAG;
7741 assert(Subtarget.useCRBits() &&
7742 "Expecting to be tracking CR bits");
7743 // If we're tracking CR bits, we need to be careful that we don't have:
7744 // trunc(binary-ops(zext(x), zext(y)))
7746 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7747 // such that we're unnecessarily moving things into GPRs when it would be
7748 // better to keep them in CR bits.
7750 // Note that trunc here can be an actual i1 trunc, or can be the effective
7751 // truncation that comes from a setcc or select_cc.
7752 if (N->getOpcode() == ISD::TRUNCATE &&
7753 N->getValueType(0) != MVT::i1)
7756 if (N->getOperand(0).getValueType() != MVT::i32 &&
7757 N->getOperand(0).getValueType() != MVT::i64)
7760 if (N->getOpcode() == ISD::SETCC ||
7761 N->getOpcode() == ISD::SELECT_CC) {
7762 // If we're looking at a comparison, then we need to make sure that the
7763 // high bits (all except for the first) don't matter the result.
7765 cast<CondCodeSDNode>(N->getOperand(
7766 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7767 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7769 if (ISD::isSignedIntSetCC(CC)) {
7770 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7771 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7773 } else if (ISD::isUnsignedIntSetCC(CC)) {
7774 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7775 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7776 !DAG.MaskedValueIsZero(N->getOperand(1),
7777 APInt::getHighBitsSet(OpBits, OpBits-1)))
7780 // This is neither a signed nor an unsigned comparison, just make sure
7781 // that the high bits are equal.
7782 APInt Op1Zero, Op1One;
7783 APInt Op2Zero, Op2One;
7784 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7785 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7787 // We don't really care about what is known about the first bit (if
7788 // anything), so clear it in all masks prior to comparing them.
7789 Op1Zero.clearBit(0); Op1One.clearBit(0);
7790 Op2Zero.clearBit(0); Op2One.clearBit(0);
7792 if (Op1Zero != Op2Zero || Op1One != Op2One)
7797 // We now know that the higher-order bits are irrelevant, we just need to
7798 // make sure that all of the intermediate operations are bit operations, and
7799 // all inputs are extensions.
7800 if (N->getOperand(0).getOpcode() != ISD::AND &&
7801 N->getOperand(0).getOpcode() != ISD::OR &&
7802 N->getOperand(0).getOpcode() != ISD::XOR &&
7803 N->getOperand(0).getOpcode() != ISD::SELECT &&
7804 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7805 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7806 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7807 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7808 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7811 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7812 N->getOperand(1).getOpcode() != ISD::AND &&
7813 N->getOperand(1).getOpcode() != ISD::OR &&
7814 N->getOperand(1).getOpcode() != ISD::XOR &&
7815 N->getOperand(1).getOpcode() != ISD::SELECT &&
7816 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7817 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7818 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7819 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7820 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7823 SmallVector<SDValue, 4> Inputs;
7824 SmallVector<SDValue, 8> BinOps, PromOps;
7825 SmallPtrSet<SDNode *, 16> Visited;
7827 for (unsigned i = 0; i < 2; ++i) {
7828 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7829 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7830 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7831 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7832 isa<ConstantSDNode>(N->getOperand(i)))
7833 Inputs.push_back(N->getOperand(i));
7835 BinOps.push_back(N->getOperand(i));
7837 if (N->getOpcode() == ISD::TRUNCATE)
7841 // Visit all inputs, collect all binary operations (and, or, xor and
7842 // select) that are all fed by extensions.
7843 while (!BinOps.empty()) {
7844 SDValue BinOp = BinOps.back();
7847 if (!Visited.insert(BinOp.getNode()))
7850 PromOps.push_back(BinOp);
7852 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7853 // The condition of the select is not promoted.
7854 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7856 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7859 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7860 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7861 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7862 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7863 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7864 Inputs.push_back(BinOp.getOperand(i));
7865 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7866 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7867 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7868 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7869 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7870 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7871 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7872 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7873 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7874 BinOps.push_back(BinOp.getOperand(i));
7876 // We have an input that is not an extension or another binary
7877 // operation; we'll abort this transformation.
7883 // Make sure that this is a self-contained cluster of operations (which
7884 // is not quite the same thing as saying that everything has only one
7886 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7887 if (isa<ConstantSDNode>(Inputs[i]))
7890 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7891 UE = Inputs[i].getNode()->use_end();
7894 if (User != N && !Visited.count(User))
7897 // Make sure that we're not going to promote the non-output-value
7898 // operand(s) or SELECT or SELECT_CC.
7899 // FIXME: Although we could sometimes handle this, and it does occur in
7900 // practice that one of the condition inputs to the select is also one of
7901 // the outputs, we currently can't deal with this.
7902 if (User->getOpcode() == ISD::SELECT) {
7903 if (User->getOperand(0) == Inputs[i])
7905 } else if (User->getOpcode() == ISD::SELECT_CC) {
7906 if (User->getOperand(0) == Inputs[i] ||
7907 User->getOperand(1) == Inputs[i])
7913 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7914 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7915 UE = PromOps[i].getNode()->use_end();
7918 if (User != N && !Visited.count(User))
7921 // Make sure that we're not going to promote the non-output-value
7922 // operand(s) or SELECT or SELECT_CC.
7923 // FIXME: Although we could sometimes handle this, and it does occur in
7924 // practice that one of the condition inputs to the select is also one of
7925 // the outputs, we currently can't deal with this.
7926 if (User->getOpcode() == ISD::SELECT) {
7927 if (User->getOperand(0) == PromOps[i])
7929 } else if (User->getOpcode() == ISD::SELECT_CC) {
7930 if (User->getOperand(0) == PromOps[i] ||
7931 User->getOperand(1) == PromOps[i])
7937 // Replace all inputs with the extension operand.
7938 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7939 // Constants may have users outside the cluster of to-be-promoted nodes,
7940 // and so we need to replace those as we do the promotions.
7941 if (isa<ConstantSDNode>(Inputs[i]))
7944 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7947 // Replace all operations (these are all the same, but have a different
7948 // (i1) return type). DAG.getNode will validate that the types of
7949 // a binary operator match, so go through the list in reverse so that
7950 // we've likely promoted both operands first. Any intermediate truncations or
7951 // extensions disappear.
7952 while (!PromOps.empty()) {
7953 SDValue PromOp = PromOps.back();
7956 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7957 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7958 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7959 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7960 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7961 PromOp.getOperand(0).getValueType() != MVT::i1) {
7962 // The operand is not yet ready (see comment below).
7963 PromOps.insert(PromOps.begin(), PromOp);
7967 SDValue RepValue = PromOp.getOperand(0);
7968 if (isa<ConstantSDNode>(RepValue))
7969 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7971 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7976 switch (PromOp.getOpcode()) {
7977 default: C = 0; break;
7978 case ISD::SELECT: C = 1; break;
7979 case ISD::SELECT_CC: C = 2; break;
7982 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7983 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7984 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7985 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7986 // The to-be-promoted operands of this node have not yet been
7987 // promoted (this should be rare because we're going through the
7988 // list backward, but if one of the operands has several users in
7989 // this cluster of to-be-promoted nodes, it is possible).
7990 PromOps.insert(PromOps.begin(), PromOp);
7994 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7995 PromOp.getNode()->op_end());
7997 // If there are any constant inputs, make sure they're replaced now.
7998 for (unsigned i = 0; i < 2; ++i)
7999 if (isa<ConstantSDNode>(Ops[C+i]))
8000 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8002 DAG.ReplaceAllUsesOfValueWith(PromOp,
8003 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8006 // Now we're left with the initial truncation itself.
8007 if (N->getOpcode() == ISD::TRUNCATE)
8008 return N->getOperand(0);
8010 // Otherwise, this is a comparison. The operands to be compared have just
8011 // changed type (to i1), but everything else is the same.
8012 return SDValue(N, 0);
8015 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8016 DAGCombinerInfo &DCI) const {
8017 SelectionDAG &DAG = DCI.DAG;
8020 // If we're tracking CR bits, we need to be careful that we don't have:
8021 // zext(binary-ops(trunc(x), trunc(y)))
8023 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8024 // such that we're unnecessarily moving things into CR bits that can more
8025 // efficiently stay in GPRs. Note that if we're not certain that the high
8026 // bits are set as required by the final extension, we still may need to do
8027 // some masking to get the proper behavior.
8029 // This same functionality is important on PPC64 when dealing with
8030 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8031 // the return values of functions. Because it is so similar, it is handled
8034 if (N->getValueType(0) != MVT::i32 &&
8035 N->getValueType(0) != MVT::i64)
8038 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8039 Subtarget.useCRBits()) ||
8040 (N->getOperand(0).getValueType() == MVT::i32 &&
8041 Subtarget.isPPC64())))
8044 if (N->getOperand(0).getOpcode() != ISD::AND &&
8045 N->getOperand(0).getOpcode() != ISD::OR &&
8046 N->getOperand(0).getOpcode() != ISD::XOR &&
8047 N->getOperand(0).getOpcode() != ISD::SELECT &&
8048 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8051 SmallVector<SDValue, 4> Inputs;
8052 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8053 SmallPtrSet<SDNode *, 16> Visited;
8055 // Visit all inputs, collect all binary operations (and, or, xor and
8056 // select) that are all fed by truncations.
8057 while (!BinOps.empty()) {
8058 SDValue BinOp = BinOps.back();
8061 if (!Visited.insert(BinOp.getNode()))
8064 PromOps.push_back(BinOp);
8066 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8067 // The condition of the select is not promoted.
8068 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8070 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8073 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8074 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8075 Inputs.push_back(BinOp.getOperand(i));
8076 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8077 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8078 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8079 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8080 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8081 BinOps.push_back(BinOp.getOperand(i));
8083 // We have an input that is not a truncation or another binary
8084 // operation; we'll abort this transformation.
8090 // Make sure that this is a self-contained cluster of operations (which
8091 // is not quite the same thing as saying that everything has only one
8093 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8094 if (isa<ConstantSDNode>(Inputs[i]))
8097 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8098 UE = Inputs[i].getNode()->use_end();
8101 if (User != N && !Visited.count(User))
8104 // Make sure that we're not going to promote the non-output-value
8105 // operand(s) or SELECT or SELECT_CC.
8106 // FIXME: Although we could sometimes handle this, and it does occur in
8107 // practice that one of the condition inputs to the select is also one of
8108 // the outputs, we currently can't deal with this.
8109 if (User->getOpcode() == ISD::SELECT) {
8110 if (User->getOperand(0) == Inputs[i])
8112 } else if (User->getOpcode() == ISD::SELECT_CC) {
8113 if (User->getOperand(0) == Inputs[i] ||
8114 User->getOperand(1) == Inputs[i])
8120 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8121 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8122 UE = PromOps[i].getNode()->use_end();
8125 if (User != N && !Visited.count(User))
8128 // Make sure that we're not going to promote the non-output-value
8129 // operand(s) or SELECT or SELECT_CC.
8130 // FIXME: Although we could sometimes handle this, and it does occur in
8131 // practice that one of the condition inputs to the select is also one of
8132 // the outputs, we currently can't deal with this.
8133 if (User->getOpcode() == ISD::SELECT) {
8134 if (User->getOperand(0) == PromOps[i])
8136 } else if (User->getOpcode() == ISD::SELECT_CC) {
8137 if (User->getOperand(0) == PromOps[i] ||
8138 User->getOperand(1) == PromOps[i])
8144 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8145 bool ReallyNeedsExt = false;
8146 if (N->getOpcode() != ISD::ANY_EXTEND) {
8147 // If all of the inputs are not already sign/zero extended, then
8148 // we'll still need to do that at the end.
8149 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8150 if (isa<ConstantSDNode>(Inputs[i]))
8154 Inputs[i].getOperand(0).getValueSizeInBits();
8155 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8157 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8158 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8159 APInt::getHighBitsSet(OpBits,
8160 OpBits-PromBits))) ||
8161 (N->getOpcode() == ISD::SIGN_EXTEND &&
8162 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8163 (OpBits-(PromBits-1)))) {
8164 ReallyNeedsExt = true;
8170 // Replace all inputs, either with the truncation operand, or a
8171 // truncation or extension to the final output type.
8172 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8173 // Constant inputs need to be replaced with the to-be-promoted nodes that
8174 // use them because they might have users outside of the cluster of
8176 if (isa<ConstantSDNode>(Inputs[i]))
8179 SDValue InSrc = Inputs[i].getOperand(0);
8180 if (Inputs[i].getValueType() == N->getValueType(0))
8181 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8182 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8183 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8184 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8185 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8186 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8187 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8189 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8190 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8193 // Replace all operations (these are all the same, but have a different
8194 // (promoted) return type). DAG.getNode will validate that the types of
8195 // a binary operator match, so go through the list in reverse so that
8196 // we've likely promoted both operands first.
8197 while (!PromOps.empty()) {
8198 SDValue PromOp = PromOps.back();
8202 switch (PromOp.getOpcode()) {
8203 default: C = 0; break;
8204 case ISD::SELECT: C = 1; break;
8205 case ISD::SELECT_CC: C = 2; break;
8208 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8209 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8210 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8211 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8212 // The to-be-promoted operands of this node have not yet been
8213 // promoted (this should be rare because we're going through the
8214 // list backward, but if one of the operands has several users in
8215 // this cluster of to-be-promoted nodes, it is possible).
8216 PromOps.insert(PromOps.begin(), PromOp);
8220 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8221 PromOp.getNode()->op_end());
8223 // If this node has constant inputs, then they'll need to be promoted here.
8224 for (unsigned i = 0; i < 2; ++i) {
8225 if (!isa<ConstantSDNode>(Ops[C+i]))
8227 if (Ops[C+i].getValueType() == N->getValueType(0))
8230 if (N->getOpcode() == ISD::SIGN_EXTEND)
8231 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8232 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8233 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8235 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8238 DAG.ReplaceAllUsesOfValueWith(PromOp,
8239 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8242 // Now we're left with the initial extension itself.
8243 if (!ReallyNeedsExt)
8244 return N->getOperand(0);
8246 // To zero extend, just mask off everything except for the first bit (in the
8248 if (N->getOpcode() == ISD::ZERO_EXTEND)
8249 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8250 DAG.getConstant(APInt::getLowBitsSet(
8251 N->getValueSizeInBits(0), PromBits),
8252 N->getValueType(0)));
8254 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8255 "Invalid extension type");
8256 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8258 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8259 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8260 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8261 N->getOperand(0), ShiftCst), ShiftCst);
8264 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8265 DAGCombinerInfo &DCI) const {
8266 const TargetMachine &TM = getTargetMachine();
8267 SelectionDAG &DAG = DCI.DAG;
8269 switch (N->getOpcode()) {
8272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8273 if (C->isNullValue()) // 0 << V -> 0.
8274 return N->getOperand(0);
8278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8279 if (C->isNullValue()) // 0 >>u V -> 0.
8280 return N->getOperand(0);
8284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8285 if (C->isNullValue() || // 0 >>s V -> 0.
8286 C->isAllOnesValue()) // -1 >>s V -> -1.
8287 return N->getOperand(0);
8290 case ISD::SIGN_EXTEND:
8291 case ISD::ZERO_EXTEND:
8292 case ISD::ANY_EXTEND:
8293 return DAGCombineExtBoolTrunc(N, DCI);
8296 case ISD::SELECT_CC:
8297 return DAGCombineTruncBoolExt(N, DCI);
8299 assert(TM.Options.UnsafeFPMath &&
8300 "Reciprocal estimates require UnsafeFPMath");
8302 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8304 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8306 DCI.AddToWorklist(RV.getNode());
8307 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8308 N->getOperand(0), RV);
8310 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8311 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8313 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8316 DCI.AddToWorklist(RV.getNode());
8317 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8318 N->getValueType(0), RV);
8319 DCI.AddToWorklist(RV.getNode());
8320 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8321 N->getOperand(0), RV);
8323 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8324 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8326 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8329 DCI.AddToWorklist(RV.getNode());
8330 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8331 N->getValueType(0), RV,
8332 N->getOperand(1).getOperand(1));
8333 DCI.AddToWorklist(RV.getNode());
8334 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8335 N->getOperand(0), RV);
8339 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8341 DCI.AddToWorklist(RV.getNode());
8342 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8343 N->getOperand(0), RV);
8349 assert(TM.Options.UnsafeFPMath &&
8350 "Reciprocal estimates require UnsafeFPMath");
8352 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8354 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8356 DCI.AddToWorklist(RV.getNode());
8357 RV = DAGCombineFastRecip(RV, DCI);
8359 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8360 // this case and force the answer to 0.
8362 EVT VT = RV.getValueType();
8364 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8365 if (VT.isVector()) {
8366 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8367 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8371 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8372 N->getOperand(0), Zero, ISD::SETEQ);
8373 DCI.AddToWorklist(ZeroCmp.getNode());
8374 DCI.AddToWorklist(RV.getNode());
8376 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8384 case ISD::SINT_TO_FP:
8385 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8386 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8387 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8388 // We allow the src/dst to be either f32/f64, but the intermediate
8389 // type must be i64.
8390 if (N->getOperand(0).getValueType() == MVT::i64 &&
8391 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8392 SDValue Val = N->getOperand(0).getOperand(0);
8393 if (Val.getValueType() == MVT::f32) {
8394 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8395 DCI.AddToWorklist(Val.getNode());
8398 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8399 DCI.AddToWorklist(Val.getNode());
8400 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8401 DCI.AddToWorklist(Val.getNode());
8402 if (N->getValueType(0) == MVT::f32) {
8403 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8404 DAG.getIntPtrConstant(0));
8405 DCI.AddToWorklist(Val.getNode());
8408 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8409 // If the intermediate type is i32, we can avoid the load/store here
8416 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8417 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8418 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8419 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8420 N->getOperand(1).getValueType() == MVT::i32 &&
8421 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8422 SDValue Val = N->getOperand(1).getOperand(0);
8423 if (Val.getValueType() == MVT::f32) {
8424 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8425 DCI.AddToWorklist(Val.getNode());
8427 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8428 DCI.AddToWorklist(Val.getNode());
8431 N->getOperand(0), Val, N->getOperand(2),
8432 DAG.getValueType(N->getOperand(1).getValueType())
8435 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8436 DAG.getVTList(MVT::Other), Ops,
8437 cast<StoreSDNode>(N)->getMemoryVT(),
8438 cast<StoreSDNode>(N)->getMemOperand());
8439 DCI.AddToWorklist(Val.getNode());
8443 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8444 if (cast<StoreSDNode>(N)->isUnindexed() &&
8445 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8446 N->getOperand(1).getNode()->hasOneUse() &&
8447 (N->getOperand(1).getValueType() == MVT::i32 ||
8448 N->getOperand(1).getValueType() == MVT::i16 ||
8449 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8450 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8451 N->getOperand(1).getValueType() == MVT::i64))) {
8452 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8453 // Do an any-extend to 32-bits if this is a half-word input.
8454 if (BSwapOp.getValueType() == MVT::i16)
8455 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8458 N->getOperand(0), BSwapOp, N->getOperand(2),
8459 DAG.getValueType(N->getOperand(1).getValueType())
8462 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8463 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8464 cast<StoreSDNode>(N)->getMemOperand());
8468 LoadSDNode *LD = cast<LoadSDNode>(N);
8469 EVT VT = LD->getValueType(0);
8470 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8471 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8472 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8473 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8474 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8475 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8476 LD->getAlignment() < ABIAlignment) {
8477 // This is a type-legal unaligned Altivec load.
8478 SDValue Chain = LD->getChain();
8479 SDValue Ptr = LD->getBasePtr();
8480 bool isLittleEndian = Subtarget.isLittleEndian();
8482 // This implements the loading of unaligned vectors as described in
8483 // the venerable Apple Velocity Engine overview. Specifically:
8484 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8485 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8487 // The general idea is to expand a sequence of one or more unaligned
8488 // loads into an alignment-based permutation-control instruction (lvsl
8489 // or lvsr), a series of regular vector loads (which always truncate
8490 // their input address to an aligned address), and a series of
8491 // permutations. The results of these permutations are the requested
8492 // loaded values. The trick is that the last "extra" load is not taken
8493 // from the address you might suspect (sizeof(vector) bytes after the
8494 // last requested load), but rather sizeof(vector) - 1 bytes after the
8495 // last requested vector. The point of this is to avoid a page fault if
8496 // the base address happened to be aligned. This works because if the
8497 // base address is aligned, then adding less than a full vector length
8498 // will cause the last vector in the sequence to be (re)loaded.
8499 // Otherwise, the next vector will be fetched as you might suspect was
8502 // We might be able to reuse the permutation generation from
8503 // a different base address offset from this one by an aligned amount.
8504 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8505 // optimization later.
8506 Intrinsic::ID Intr = (isLittleEndian ?
8507 Intrinsic::ppc_altivec_lvsr :
8508 Intrinsic::ppc_altivec_lvsl);
8509 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8511 // Create the new MMO for the new base load. It is like the original MMO,
8512 // but represents an area in memory almost twice the vector size centered
8513 // on the original address. If the address is unaligned, we might start
8514 // reading up to (sizeof(vector)-1) bytes below the address of the
8515 // original unaligned load.
8516 MachineFunction &MF = DAG.getMachineFunction();
8517 MachineMemOperand *BaseMMO =
8518 MF.getMachineMemOperand(LD->getMemOperand(),
8519 -LD->getMemoryVT().getStoreSize()+1,
8520 2*LD->getMemoryVT().getStoreSize()-1);
8522 // Create the new base load.
8523 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8525 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8527 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8528 DAG.getVTList(MVT::v4i32, MVT::Other),
8529 BaseLoadOps, MVT::v4i32, BaseMMO);
8531 // Note that the value of IncOffset (which is provided to the next
8532 // load's pointer info offset value, and thus used to calculate the
8533 // alignment), and the value of IncValue (which is actually used to
8534 // increment the pointer value) are different! This is because we
8535 // require the next load to appear to be aligned, even though it
8536 // is actually offset from the base pointer by a lesser amount.
8537 int IncOffset = VT.getSizeInBits() / 8;
8538 int IncValue = IncOffset;
8540 // Walk (both up and down) the chain looking for another load at the real
8541 // (aligned) offset (the alignment of the other load does not matter in
8542 // this case). If found, then do not use the offset reduction trick, as
8543 // that will prevent the loads from being later combined (as they would
8544 // otherwise be duplicates).
8545 if (!findConsecutiveLoad(LD, DAG))
8548 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8549 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8551 MachineMemOperand *ExtraMMO =
8552 MF.getMachineMemOperand(LD->getMemOperand(),
8553 1, 2*LD->getMemoryVT().getStoreSize()-1);
8554 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8556 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8557 DAG.getVTList(MVT::v4i32, MVT::Other),
8558 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8560 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8561 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8563 // Because vperm has a big-endian bias, we must reverse the order
8564 // of the input vectors and complement the permute control vector
8565 // when generating little endian code. We have already handled the
8566 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8567 // and ExtraLoad here.
8570 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8571 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8573 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8574 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8576 if (VT != MVT::v4i32)
8577 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8579 // The output of the permutation is our loaded result, the TokenFactor is
8581 DCI.CombineTo(N, Perm, TF);
8582 return SDValue(N, 0);
8586 case ISD::INTRINSIC_WO_CHAIN: {
8587 bool isLittleEndian = Subtarget.isLittleEndian();
8588 Intrinsic::ID Intr = (isLittleEndian ?
8589 Intrinsic::ppc_altivec_lvsr :
8590 Intrinsic::ppc_altivec_lvsl);
8591 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8592 N->getOperand(1)->getOpcode() == ISD::ADD) {
8593 SDValue Add = N->getOperand(1);
8595 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8596 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8597 Add.getValueType().getScalarType().getSizeInBits()))) {
8598 SDNode *BasePtr = Add->getOperand(0).getNode();
8599 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8600 UE = BasePtr->use_end(); UI != UE; ++UI) {
8601 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8602 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8604 // We've found another LVSL/LVSR, and this address is an aligned
8605 // multiple of that one. The results will be the same, so use the
8606 // one we've just found instead.
8608 return SDValue(*UI, 0);
8617 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8618 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8619 N->getOperand(0).hasOneUse() &&
8620 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8621 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8622 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8623 N->getValueType(0) == MVT::i64))) {
8624 SDValue Load = N->getOperand(0);
8625 LoadSDNode *LD = cast<LoadSDNode>(Load);
8626 // Create the byte-swapping load.
8628 LD->getChain(), // Chain
8629 LD->getBasePtr(), // Ptr
8630 DAG.getValueType(N->getValueType(0)) // VT
8633 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8634 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8635 MVT::i64 : MVT::i32, MVT::Other),
8636 Ops, LD->getMemoryVT(), LD->getMemOperand());
8638 // If this is an i16 load, insert the truncate.
8639 SDValue ResVal = BSLoad;
8640 if (N->getValueType(0) == MVT::i16)
8641 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8643 // First, combine the bswap away. This makes the value produced by the
8645 DCI.CombineTo(N, ResVal);
8647 // Next, combine the load away, we give it a bogus result value but a real
8648 // chain result. The result value is dead because the bswap is dead.
8649 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8651 // Return N so it doesn't get rechecked!
8652 return SDValue(N, 0);
8656 case PPCISD::VCMP: {
8657 // If a VCMPo node already exists with exactly the same operands as this
8658 // node, use its result instead of this node (VCMPo computes both a CR6 and
8659 // a normal output).
8661 if (!N->getOperand(0).hasOneUse() &&
8662 !N->getOperand(1).hasOneUse() &&
8663 !N->getOperand(2).hasOneUse()) {
8665 // Scan all of the users of the LHS, looking for VCMPo's that match.
8666 SDNode *VCMPoNode = nullptr;
8668 SDNode *LHSN = N->getOperand(0).getNode();
8669 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8671 if (UI->getOpcode() == PPCISD::VCMPo &&
8672 UI->getOperand(1) == N->getOperand(1) &&
8673 UI->getOperand(2) == N->getOperand(2) &&
8674 UI->getOperand(0) == N->getOperand(0)) {
8679 // If there is no VCMPo node, or if the flag value has a single use, don't
8681 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8684 // Look at the (necessarily single) use of the flag value. If it has a
8685 // chain, this transformation is more complex. Note that multiple things
8686 // could use the value result, which we should ignore.
8687 SDNode *FlagUser = nullptr;
8688 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8689 FlagUser == nullptr; ++UI) {
8690 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8692 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8693 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8700 // If the user is a MFOCRF instruction, we know this is safe.
8701 // Otherwise we give up for right now.
8702 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8703 return SDValue(VCMPoNode, 0);
8708 SDValue Cond = N->getOperand(1);
8709 SDValue Target = N->getOperand(2);
8711 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8712 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8713 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8715 // We now need to make the intrinsic dead (it cannot be instruction
8717 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8718 assert(Cond.getNode()->hasOneUse() &&
8719 "Counter decrement has more than one use");
8721 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8722 N->getOperand(0), Target);
8727 // If this is a branch on an altivec predicate comparison, lower this so
8728 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8729 // lowering is done pre-legalize, because the legalizer lowers the predicate
8730 // compare down to code that is difficult to reassemble.
8731 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8732 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8734 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8735 // value. If so, pass-through the AND to get to the intrinsic.
8736 if (LHS.getOpcode() == ISD::AND &&
8737 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8738 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8739 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8740 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8741 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8743 LHS = LHS.getOperand(0);
8745 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8746 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8747 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8748 isa<ConstantSDNode>(RHS)) {
8749 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8750 "Counter decrement comparison is not EQ or NE");
8752 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8753 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8754 (CC == ISD::SETNE && !Val);
8756 // We now need to make the intrinsic dead (it cannot be instruction
8758 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8759 assert(LHS.getNode()->hasOneUse() &&
8760 "Counter decrement has more than one use");
8762 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8763 N->getOperand(0), N->getOperand(4));
8769 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8770 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8771 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8772 assert(isDot && "Can't compare against a vector result!");
8774 // If this is a comparison against something other than 0/1, then we know
8775 // that the condition is never/always true.
8776 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8777 if (Val != 0 && Val != 1) {
8778 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8779 return N->getOperand(0);
8780 // Always !=, turn it into an unconditional branch.
8781 return DAG.getNode(ISD::BR, dl, MVT::Other,
8782 N->getOperand(0), N->getOperand(4));
8785 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8787 // Create the PPCISD altivec 'dot' comparison node.
8789 LHS.getOperand(2), // LHS of compare
8790 LHS.getOperand(3), // RHS of compare
8791 DAG.getConstant(CompareOpc, MVT::i32)
8793 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8794 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8796 // Unpack the result based on how the target uses it.
8797 PPC::Predicate CompOpc;
8798 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8799 default: // Can't happen, don't crash on invalid number though.
8800 case 0: // Branch on the value of the EQ bit of CR6.
8801 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8803 case 1: // Branch on the inverted value of the EQ bit of CR6.
8804 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8806 case 2: // Branch on the value of the LT bit of CR6.
8807 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8809 case 3: // Branch on the inverted value of the LT bit of CR6.
8810 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8814 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8815 DAG.getConstant(CompOpc, MVT::i32),
8816 DAG.getRegister(PPC::CR6, MVT::i32),
8817 N->getOperand(4), CompNode.getValue(1));
8826 //===----------------------------------------------------------------------===//
8827 // Inline Assembly Support
8828 //===----------------------------------------------------------------------===//
8830 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8833 const SelectionDAG &DAG,
8834 unsigned Depth) const {
8835 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8836 switch (Op.getOpcode()) {
8838 case PPCISD::LBRX: {
8839 // lhbrx is known to have the top bits cleared out.
8840 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8841 KnownZero = 0xFFFF0000;
8844 case ISD::INTRINSIC_WO_CHAIN: {
8845 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8847 case Intrinsic::ppc_altivec_vcmpbfp_p:
8848 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8849 case Intrinsic::ppc_altivec_vcmpequb_p:
8850 case Intrinsic::ppc_altivec_vcmpequh_p:
8851 case Intrinsic::ppc_altivec_vcmpequw_p:
8852 case Intrinsic::ppc_altivec_vcmpgefp_p:
8853 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8854 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8855 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8856 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8857 case Intrinsic::ppc_altivec_vcmpgtub_p:
8858 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8859 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8860 KnownZero = ~1U; // All bits but the low one are known to be zero.
8868 /// getConstraintType - Given a constraint, return the type of
8869 /// constraint it is for this target.
8870 PPCTargetLowering::ConstraintType
8871 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8872 if (Constraint.size() == 1) {
8873 switch (Constraint[0]) {
8880 return C_RegisterClass;
8882 // FIXME: While Z does indicate a memory constraint, it specifically
8883 // indicates an r+r address (used in conjunction with the 'y' modifier
8884 // in the replacement string). Currently, we're forcing the base
8885 // register to be r0 in the asm printer (which is interpreted as zero)
8886 // and forming the complete address in the second register. This is
8890 } else if (Constraint == "wc") { // individual CR bits.
8891 return C_RegisterClass;
8892 } else if (Constraint == "wa" || Constraint == "wd" ||
8893 Constraint == "wf" || Constraint == "ws") {
8894 return C_RegisterClass; // VSX registers.
8896 return TargetLowering::getConstraintType(Constraint);
8899 /// Examine constraint type and operand type and determine a weight value.
8900 /// This object must already have been set up with the operand type
8901 /// and the current alternative constraint selected.
8902 TargetLowering::ConstraintWeight
8903 PPCTargetLowering::getSingleConstraintMatchWeight(
8904 AsmOperandInfo &info, const char *constraint) const {
8905 ConstraintWeight weight = CW_Invalid;
8906 Value *CallOperandVal = info.CallOperandVal;
8907 // If we don't have a value, we can't do a match,
8908 // but allow it at the lowest weight.
8909 if (!CallOperandVal)
8911 Type *type = CallOperandVal->getType();
8913 // Look at the constraint type.
8914 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8915 return CW_Register; // an individual CR bit.
8916 else if ((StringRef(constraint) == "wa" ||
8917 StringRef(constraint) == "wd" ||
8918 StringRef(constraint) == "wf") &&
8921 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8924 switch (*constraint) {
8926 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8929 if (type->isIntegerTy())
8930 weight = CW_Register;
8933 if (type->isFloatTy())
8934 weight = CW_Register;
8937 if (type->isDoubleTy())
8938 weight = CW_Register;
8941 if (type->isVectorTy())
8942 weight = CW_Register;
8945 weight = CW_Register;
8954 std::pair<unsigned, const TargetRegisterClass*>
8955 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8957 if (Constraint.size() == 1) {
8958 // GCC RS6000 Constraint Letters
8959 switch (Constraint[0]) {
8961 if (VT == MVT::i64 && Subtarget.isPPC64())
8962 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8963 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8965 if (VT == MVT::i64 && Subtarget.isPPC64())
8966 return std::make_pair(0U, &PPC::G8RCRegClass);
8967 return std::make_pair(0U, &PPC::GPRCRegClass);
8969 if (VT == MVT::f32 || VT == MVT::i32)
8970 return std::make_pair(0U, &PPC::F4RCRegClass);
8971 if (VT == MVT::f64 || VT == MVT::i64)
8972 return std::make_pair(0U, &PPC::F8RCRegClass);
8975 return std::make_pair(0U, &PPC::VRRCRegClass);
8977 return std::make_pair(0U, &PPC::CRRCRegClass);
8979 } else if (Constraint == "wc") { // an individual CR bit.
8980 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8981 } else if (Constraint == "wa" || Constraint == "wd" ||
8982 Constraint == "wf") {
8983 return std::make_pair(0U, &PPC::VSRCRegClass);
8984 } else if (Constraint == "ws") {
8985 return std::make_pair(0U, &PPC::VSFRCRegClass);
8988 std::pair<unsigned, const TargetRegisterClass*> R =
8989 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8991 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8992 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8993 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8995 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8996 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8997 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8998 PPC::GPRCRegClass.contains(R.first)) {
8999 const TargetRegisterInfo *TRI =
9000 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9001 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9002 PPC::sub_32, &PPC::G8RCRegClass),
9003 &PPC::G8RCRegClass);
9010 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9011 /// vector. If it is invalid, don't add anything to Ops.
9012 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9013 std::string &Constraint,
9014 std::vector<SDValue>&Ops,
9015 SelectionDAG &DAG) const {
9018 // Only support length 1 constraints.
9019 if (Constraint.length() > 1) return;
9021 char Letter = Constraint[0];
9032 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9033 if (!CST) return; // Must be an immediate to match.
9034 unsigned Value = CST->getZExtValue();
9036 default: llvm_unreachable("Unknown constraint letter!");
9037 case 'I': // "I" is a signed 16-bit constant.
9038 if ((short)Value == (int)Value)
9039 Result = DAG.getTargetConstant(Value, Op.getValueType());
9041 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9042 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9043 if ((short)Value == 0)
9044 Result = DAG.getTargetConstant(Value, Op.getValueType());
9046 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9047 if ((Value >> 16) == 0)
9048 Result = DAG.getTargetConstant(Value, Op.getValueType());
9050 case 'M': // "M" is a constant that is greater than 31.
9052 Result = DAG.getTargetConstant(Value, Op.getValueType());
9054 case 'N': // "N" is a positive constant that is an exact power of two.
9055 if ((int)Value > 0 && isPowerOf2_32(Value))
9056 Result = DAG.getTargetConstant(Value, Op.getValueType());
9058 case 'O': // "O" is the constant zero.
9060 Result = DAG.getTargetConstant(Value, Op.getValueType());
9062 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9063 if ((short)-Value == (int)-Value)
9064 Result = DAG.getTargetConstant(Value, Op.getValueType());
9071 if (Result.getNode()) {
9072 Ops.push_back(Result);
9076 // Handle standard constraint letters.
9077 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9080 // isLegalAddressingMode - Return true if the addressing mode represented
9081 // by AM is legal for this target, for a load/store of the specified type.
9082 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9084 // FIXME: PPC does not allow r+i addressing modes for vectors!
9086 // PPC allows a sign-extended 16-bit immediate field.
9087 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9090 // No global is ever allowed as a base.
9094 // PPC only support r+r,
9096 case 0: // "r+i" or just "i", depending on HasBaseReg.
9099 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9101 // Otherwise we have r+r or r+i.
9104 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9106 // Allow 2*r as r+r.
9109 // No other scales are supported.
9116 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9117 SelectionDAG &DAG) const {
9118 MachineFunction &MF = DAG.getMachineFunction();
9119 MachineFrameInfo *MFI = MF.getFrameInfo();
9120 MFI->setReturnAddressIsTaken(true);
9122 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9126 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9128 // Make sure the function does not optimize away the store of the RA to
9130 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9131 FuncInfo->setLRStoreRequired();
9132 bool isPPC64 = Subtarget.isPPC64();
9133 bool isDarwinABI = Subtarget.isDarwinABI();
9136 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9139 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9140 isPPC64? MVT::i64 : MVT::i32);
9141 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9142 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9144 MachinePointerInfo(), false, false, false, 0);
9147 // Just load the return address off the stack.
9148 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9149 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9150 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9153 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9154 SelectionDAG &DAG) const {
9156 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9158 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9159 bool isPPC64 = PtrVT == MVT::i64;
9161 MachineFunction &MF = DAG.getMachineFunction();
9162 MachineFrameInfo *MFI = MF.getFrameInfo();
9163 MFI->setFrameAddressIsTaken(true);
9165 // Naked functions never have a frame pointer, and so we use r1. For all
9166 // other functions, this decision must be delayed until during PEI.
9168 if (MF.getFunction()->getAttributes().hasAttribute(
9169 AttributeSet::FunctionIndex, Attribute::Naked))
9170 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9172 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9174 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9177 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9178 FrameAddr, MachinePointerInfo(), false, false,
9183 // FIXME? Maybe this could be a TableGen attribute on some registers and
9184 // this table could be generated automatically from RegInfo.
9185 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9187 bool isPPC64 = Subtarget.isPPC64();
9188 bool isDarwinABI = Subtarget.isDarwinABI();
9190 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9191 (!isPPC64 && VT != MVT::i32))
9192 report_fatal_error("Invalid register global variable type");
9194 bool is64Bit = isPPC64 && VT == MVT::i64;
9195 unsigned Reg = StringSwitch<unsigned>(RegName)
9196 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9197 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9198 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9199 (is64Bit ? PPC::X13 : PPC::R13))
9204 report_fatal_error("Invalid register name global variable");
9208 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9209 // The PowerPC target isn't yet aware of offsets.
9213 /// getOptimalMemOpType - Returns the target specific optimal type for load
9214 /// and store operations as a result of memset, memcpy, and memmove
9215 /// lowering. If DstAlign is zero that means it's safe to destination
9216 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9217 /// means there isn't a need to check it against alignment requirement,
9218 /// probably because the source does not need to be loaded. If 'IsMemset' is
9219 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9220 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9221 /// source is constant so it does not need to be loaded.
9222 /// It returns EVT::Other if the type should be determined using generic
9223 /// target-independent logic.
9224 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9225 unsigned DstAlign, unsigned SrcAlign,
9226 bool IsMemset, bool ZeroMemset,
9228 MachineFunction &MF) const {
9229 if (Subtarget.isPPC64()) {
9236 /// \brief Returns true if it is beneficial to convert a load of a constant
9237 /// to just the constant itself.
9238 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9240 assert(Ty->isIntegerTy());
9242 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9243 if (BitSize == 0 || BitSize > 64)
9248 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9249 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9251 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9252 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9253 return NumBits1 == 64 && NumBits2 == 32;
9256 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9257 if (!VT1.isInteger() || !VT2.isInteger())
9259 unsigned NumBits1 = VT1.getSizeInBits();
9260 unsigned NumBits2 = VT2.getSizeInBits();
9261 return NumBits1 == 64 && NumBits2 == 32;
9264 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9265 return isInt<16>(Imm) || isUInt<16>(Imm);
9268 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9269 return isInt<16>(Imm) || isUInt<16>(Imm);
9272 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9276 if (DisablePPCUnaligned)
9279 // PowerPC supports unaligned memory access for simple non-vector types.
9280 // Although accessing unaligned addresses is not as efficient as accessing
9281 // aligned addresses, it is generally more efficient than manual expansion,
9282 // and generally only traps for software emulation when crossing page
9288 if (VT.getSimpleVT().isVector()) {
9289 if (Subtarget.hasVSX()) {
9290 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9297 if (VT == MVT::ppcf128)
9306 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9307 VT = VT.getScalarType();
9312 switch (VT.getSimpleVT().SimpleTy) {
9324 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9325 EVT VT , unsigned DefinedValues) const {
9326 if (VT == MVT::v2i64)
9329 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9332 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9333 if (DisableILPPref || Subtarget.enableMachineScheduler())
9334 return TargetLowering::getSchedulingPreference(N);
9339 // Create a fast isel object.
9341 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9342 const TargetLibraryInfo *LibInfo) const {
9343 return PPC::createFastISel(FuncInfo, LibInfo);