1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 DebugLoc dl = MI->getDebugLoc();
108 unsigned UsedRegMask = 0;
109 for (unsigned i = 0; i != 32; ++i)
110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
111 UsedRegMask |= 1 << (31-i);
113 // Live in and live out values already must be in the mask, so don't bother
115 for (MachineRegisterInfo::livein_iterator
116 I = MF->getRegInfo().livein_begin(),
117 E = MF->getRegInfo().livein_end(); I != E; ++I) {
118 unsigned RegNo = getPPCRegisterNumbering(I->first);
119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
123 // Live out registers appear as use operands on return instructions.
124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
125 UsedRegMask != 0 && BI != BE; ++BI) {
126 const MachineBasicBlock &MBB = *BI;
127 if (MBB.empty() || !MBB.back().isReturn())
129 const MachineInstr &Ret = MBB.back();
130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
131 const MachineOperand &MO = Ret.getOperand(I);
132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg());
135 UsedRegMask &= ~(1 << (31-RegNo));
139 // If no registers are used, turn this into a copy.
140 if (UsedRegMask == 0) {
141 // Remove all VRSAVE code.
142 RemoveVRSaveCode(MI);
146 unsigned SrcReg = MI->getOperand(1).getReg();
147 unsigned DstReg = MI->getOperand(0).getReg();
149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
150 if (DstReg != SrcReg)
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
153 .addImm(UsedRegMask);
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
156 .addReg(SrcReg, RegState::Kill)
157 .addImm(UsedRegMask);
158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
159 if (DstReg != SrcReg)
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 .addImm(UsedRegMask >> 16);
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
165 .addReg(SrcReg, RegState::Kill)
166 .addImm(UsedRegMask >> 16);
168 if (DstReg != SrcReg)
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
171 .addImm(UsedRegMask >> 16);
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
174 .addReg(SrcReg, RegState::Kill)
175 .addImm(UsedRegMask >> 16);
177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
178 .addReg(DstReg, RegState::Kill)
179 .addImm(UsedRegMask & 0xFFFF);
182 // Remove the old UPDATE_VRSAVE instruction.
183 MI->eraseFromParent();
186 static bool spillsCR(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->isCRSpilled();
191 static bool hasSpills(const MachineFunction &MF) {
192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
193 return FuncInfo->hasSpills();
196 static bool hasNonRISpills(const MachineFunction &MF) {
197 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
198 return FuncInfo->hasNonRISpills();
201 /// determineFrameLayout - Determine the size of the frame and maximum call
203 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
205 bool UseEstimate) const {
206 MachineFrameInfo *MFI = MF.getFrameInfo();
208 // Get the number of bytes to allocate from the FrameInfo
210 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
212 // Get the alignments provided by the target, and the maximum alignment
213 // (if any) of the fixed frame objects.
214 unsigned MaxAlign = MFI->getMaxAlignment();
215 unsigned TargetAlign = getStackAlignment();
216 unsigned AlignMask = TargetAlign - 1; //
218 // If we are a leaf function, and use up to 224 bytes of stack space,
219 // don't have a frame pointer, calls, or dynamic alloca then we do not need
220 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit
221 // SVR4, we also require a stack frame if we need to spill the CR,
222 // since this spill area is addressed relative to the stack pointer.
223 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
224 // stackless code if all local vars are reg-allocated.
225 bool DisableRedZone = MF.getFunction()->getAttributes().
226 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
227 if (!DisableRedZone &&
228 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
229 !Subtarget.isSVR4ABI() || // allocated locals.
231 FrameSize <= 224 && // Fits in red zone.
232 !MFI->hasVarSizedObjects() && // No dynamic alloca.
233 !MFI->adjustsStack() && // No calls.
234 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave.
235 Subtarget.isSVR4ABI()
237 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
240 MFI->setStackSize(0);
244 // Get the maximum call frame size of all the calls.
245 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
247 // Maximum call frame needs to be at least big enough for linkage and 8 args.
248 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
249 Subtarget.isDarwinABI());
250 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
252 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
253 // that allocations will be aligned.
254 if (MFI->hasVarSizedObjects())
255 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
257 // Update maximum call frame size.
259 MFI->setMaxCallFrameSize(maxCallFrameSize);
261 // Include call frame size in total.
262 FrameSize += maxCallFrameSize;
264 // Make sure the frame is aligned.
265 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
267 // Update frame info.
269 MFI->setStackSize(FrameSize);
274 // hasFP - Return true if the specified function actually has a dedicated frame
276 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
277 const MachineFrameInfo *MFI = MF.getFrameInfo();
278 // FIXME: This is pretty much broken by design: hasFP() might be called really
279 // early, before the stack layout was calculated and thus hasFP() might return
280 // true or false here depending on the time of call.
281 return (MFI->getStackSize()) && needsFP(MF);
284 // needsFP - Return true if the specified function should have a dedicated frame
285 // pointer register. This is true if the function has variable sized allocas or
286 // if frame pointer elimination is disabled.
287 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
288 const MachineFrameInfo *MFI = MF.getFrameInfo();
290 // Naked functions have no stack frame pushed, so we don't have a frame
292 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
296 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
297 MFI->hasVarSizedObjects() ||
298 (MF.getTarget().Options.GuaranteedTailCallOpt &&
299 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
302 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
303 bool is31 = needsFP(MF);
304 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
305 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
307 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
309 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
311 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
312 MachineOperand &MO = MBBI->getOperand(I);
316 switch (MO.getReg()) {
328 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
329 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
330 MachineBasicBlock::iterator MBBI = MBB.begin();
331 MachineFrameInfo *MFI = MF.getFrameInfo();
332 const PPCInstrInfo &TII =
333 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
335 MachineModuleInfo &MMI = MF.getMMI();
337 bool needsFrameMoves = MMI.hasDebugInfo() ||
338 MF.getFunction()->needsUnwindTableEntry();
340 // Prepare for frame info.
341 MCSymbol *FrameLabel = 0;
343 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
345 if (!Subtarget.isSVR4ABI())
346 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
347 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
348 HandleVRSaveUpdate(MBBI, TII);
353 // Move MBBI back to the beginning of the function.
356 // Work out frame sizes.
357 unsigned FrameSize = determineFrameLayout(MF);
358 int NegFrameSize = -FrameSize;
360 if (MFI->isFrameAddressTaken())
361 replaceFPWithRealFP(MF);
363 // Get processor type.
364 bool isPPC64 = Subtarget.isPPC64();
365 // Get operating system
366 bool isDarwinABI = Subtarget.isDarwinABI();
367 // Check if the link register (LR) must be saved.
368 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
369 bool MustSaveLR = FI->mustSaveLR();
370 // Do we have a frame pointer for this function?
371 bool HasFP = hasFP(MF);
373 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
377 if (Subtarget.isSVR4ABI()) {
378 MachineFrameInfo *FFI = MF.getFrameInfo();
379 int FPIndex = FI->getFramePointerSaveIndex();
380 assert(FPIndex && "No Frame Pointer Save Slot!");
381 FPOffset = FFI->getObjectOffset(FPIndex);
383 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
389 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
392 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
398 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
400 .addImm(LROffset / 4)
404 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
407 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
408 // offsets of R1 is not allowed.
409 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
421 // Skip if a leaf routine.
422 if (!FrameSize) return;
424 // Get stack alignments.
425 unsigned TargetAlign = getStackAlignment();
426 unsigned MaxAlign = MFI->getMaxAlignment();
428 // Adjust stack pointer: r1 += NegFrameSize.
429 // If there is a preferred stack alignment, align R1 now
432 if (ALIGN_STACK && MaxAlign > TargetAlign) {
433 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
434 "Invalid alignment!");
435 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
437 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
440 .addImm(32 - Log2_32(MaxAlign))
442 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
443 .addReg(PPC::R0, RegState::Kill)
444 .addImm(NegFrameSize);
445 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
446 .addReg(PPC::R1, RegState::Kill)
449 } else if (isInt<16>(NegFrameSize)) {
450 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
452 .addImm(NegFrameSize)
455 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
456 .addImm(NegFrameSize >> 16);
457 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
458 .addReg(PPC::R0, RegState::Kill)
459 .addImm(NegFrameSize & 0xFFFF);
460 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
461 .addReg(PPC::R1, RegState::Kill)
466 if (ALIGN_STACK && MaxAlign > TargetAlign) {
467 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
468 "Invalid alignment!");
469 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
471 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
474 .addImm(64 - Log2_32(MaxAlign));
475 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
477 .addImm(NegFrameSize);
478 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
479 .addReg(PPC::X1, RegState::Kill)
482 } else if (isInt<16>(NegFrameSize)) {
483 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
485 .addImm(NegFrameSize / 4)
488 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
489 .addImm(NegFrameSize >> 16);
490 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
491 .addReg(PPC::X0, RegState::Kill)
492 .addImm(NegFrameSize & 0xFFFF);
493 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
494 .addReg(PPC::X1, RegState::Kill)
500 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
502 // Add the "machine moves" for the instructions we generated above, but in
504 if (needsFrameMoves) {
505 // Mark effective beginning of when frame pointer becomes valid.
506 FrameLabel = MMI.getContext().CreateTempSymbol();
507 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
509 // Show update of SP.
511 MachineLocation SPDst(MachineLocation::VirtualFP);
512 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
513 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
515 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
516 Moves.push_back(MachineMove(FrameLabel, SP, SP));
520 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
521 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
522 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
526 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
527 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
528 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
532 MCSymbol *ReadyLabel = 0;
534 // If there is a frame pointer, copy R1 into R31
537 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
541 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
546 if (needsFrameMoves) {
547 ReadyLabel = MMI.getContext().CreateTempSymbol();
549 // Mark effective beginning of when frame pointer is ready.
550 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
552 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
553 (isPPC64 ? PPC::X1 : PPC::R1));
554 MachineLocation FPSrc(MachineLocation::VirtualFP);
555 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
559 if (needsFrameMoves) {
560 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
562 // Add callee saved registers to move list.
563 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
564 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
565 unsigned Reg = CSI[I].getReg();
566 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
568 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
569 // subregisters of CR2. We just need to emit a move of CR2.
570 if (PPC::CRBITRCRegClass.contains(Reg))
573 // For SVR4, don't emit a move for the CR spill slot if we haven't
575 if (Subtarget.isSVR4ABI()
576 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
580 // For 64-bit SVR4 when we have spilled CRs, the spill location
581 // is SP+8, not a frame-relative slot.
582 if (Subtarget.isSVR4ABI()
583 && Subtarget.isPPC64()
584 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
585 MachineLocation CSDst(PPC::X1, 8);
586 MachineLocation CSSrc(PPC::CR2);
587 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
591 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
592 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
593 MachineLocation CSSrc(Reg);
594 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
599 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
600 MachineBasicBlock &MBB) const {
601 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
602 assert(MBBI != MBB.end() && "Returning block has no terminator");
603 const PPCInstrInfo &TII =
604 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
606 unsigned RetOpcode = MBBI->getOpcode();
609 assert((RetOpcode == PPC::BLR ||
610 RetOpcode == PPC::TCRETURNri ||
611 RetOpcode == PPC::TCRETURNdi ||
612 RetOpcode == PPC::TCRETURNai ||
613 RetOpcode == PPC::TCRETURNri8 ||
614 RetOpcode == PPC::TCRETURNdi8 ||
615 RetOpcode == PPC::TCRETURNai8) &&
616 "Can only insert epilog into returning blocks");
618 // Get alignment info so we know how to restore r1
619 const MachineFrameInfo *MFI = MF.getFrameInfo();
620 unsigned TargetAlign = getStackAlignment();
621 unsigned MaxAlign = MFI->getMaxAlignment();
623 // Get the number of bytes allocated from the FrameInfo.
624 int FrameSize = MFI->getStackSize();
626 // Get processor type.
627 bool isPPC64 = Subtarget.isPPC64();
628 // Get operating system
629 bool isDarwinABI = Subtarget.isDarwinABI();
630 // Check if the link register (LR) has been saved.
631 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
632 bool MustSaveLR = FI->mustSaveLR();
633 // Do we have a frame pointer for this function?
634 bool HasFP = hasFP(MF);
636 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
640 if (Subtarget.isSVR4ABI()) {
641 MachineFrameInfo *FFI = MF.getFrameInfo();
642 int FPIndex = FI->getFramePointerSaveIndex();
643 assert(FPIndex && "No Frame Pointer Save Slot!");
644 FPOffset = FFI->getObjectOffset(FPIndex);
646 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
650 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
651 RetOpcode == PPC::TCRETURNdi ||
652 RetOpcode == PPC::TCRETURNai ||
653 RetOpcode == PPC::TCRETURNri8 ||
654 RetOpcode == PPC::TCRETURNdi8 ||
655 RetOpcode == PPC::TCRETURNai8;
658 int MaxTCRetDelta = FI->getTailCallSPDelta();
659 MachineOperand &StackAdjust = MBBI->getOperand(1);
660 assert(StackAdjust.isImm() && "Expecting immediate value.");
661 // Adjust stack pointer.
662 int StackAdj = StackAdjust.getImm();
663 int Delta = StackAdj - MaxTCRetDelta;
664 assert((Delta >= 0) && "Delta must be positive");
666 FrameSize += (StackAdj +Delta);
668 FrameSize += StackAdj;
672 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
673 // on entry to the function. Add this offset back now.
675 // If this function contained a fastcc call and GuaranteedTailCallOpt is
676 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
677 // call which invalidates the stack pointer value in SP(0). So we use the
678 // value of R31 in this case.
679 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
680 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
681 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
682 .addReg(PPC::R31).addImm(FrameSize);
683 } else if(FI->hasFastCall()) {
684 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
685 .addImm(FrameSize >> 16);
686 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
687 .addReg(PPC::R0, RegState::Kill)
688 .addImm(FrameSize & 0xFFFF);
689 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
693 } else if (isInt<16>(FrameSize) &&
694 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
695 !MFI->hasVarSizedObjects()) {
696 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
697 .addReg(PPC::R1).addImm(FrameSize);
699 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
700 .addImm(0).addReg(PPC::R1);
703 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
704 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
705 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
706 .addReg(PPC::X31).addImm(FrameSize);
707 } else if(FI->hasFastCall()) {
708 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
709 .addImm(FrameSize >> 16);
710 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
711 .addReg(PPC::X0, RegState::Kill)
712 .addImm(FrameSize & 0xFFFF);
713 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
717 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
718 !MFI->hasVarSizedObjects()) {
719 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
720 .addReg(PPC::X1).addImm(FrameSize);
722 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
723 .addImm(0).addReg(PPC::X1);
730 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
731 .addImm(LROffset/4).addReg(PPC::X1);
734 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
735 .addImm(FPOffset/4).addReg(PPC::X1);
738 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
741 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
742 .addImm(LROffset).addReg(PPC::R1);
745 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
746 .addImm(FPOffset).addReg(PPC::R1);
749 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
752 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
754 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
755 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
756 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
757 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
758 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
759 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
760 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
761 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
762 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
763 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
764 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
766 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
767 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
768 .addReg(StackReg).addImm(CallerAllocatedAmt);
770 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
771 .addImm(CallerAllocatedAmt >> 16);
772 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
773 .addReg(TmpReg, RegState::Kill)
774 .addImm(CallerAllocatedAmt & 0xFFFF);
775 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
780 } else if (RetOpcode == PPC::TCRETURNdi) {
781 MBBI = MBB.getLastNonDebugInstr();
782 MachineOperand &JumpTarget = MBBI->getOperand(0);
783 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
784 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
785 } else if (RetOpcode == PPC::TCRETURNri) {
786 MBBI = MBB.getLastNonDebugInstr();
787 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
788 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
789 } else if (RetOpcode == PPC::TCRETURNai) {
790 MBBI = MBB.getLastNonDebugInstr();
791 MachineOperand &JumpTarget = MBBI->getOperand(0);
792 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
793 } else if (RetOpcode == PPC::TCRETURNdi8) {
794 MBBI = MBB.getLastNonDebugInstr();
795 MachineOperand &JumpTarget = MBBI->getOperand(0);
796 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
797 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
798 } else if (RetOpcode == PPC::TCRETURNri8) {
799 MBBI = MBB.getLastNonDebugInstr();
800 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
801 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
802 } else if (RetOpcode == PPC::TCRETURNai8) {
803 MBBI = MBB.getLastNonDebugInstr();
804 MachineOperand &JumpTarget = MBBI->getOperand(0);
805 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
809 /// MustSaveLR - Return true if this function requires that we save the LR
810 /// register onto the stack in the prolog and restore it in the epilog of the
812 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
813 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
815 // We need a save/restore of LR if there is any def of LR (which is
816 // defined by calls, including the PIC setup sequence), or if there is
817 // some use of the LR stack slot (e.g. for builtin_return_address).
818 // (LR comes in 32 and 64 bit versions.)
819 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
820 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
824 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
825 RegScavenger *) const {
826 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
828 // Save and clear the LR state.
829 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
830 unsigned LR = RegInfo->getRARegister();
831 FI->setMustSaveLR(MustSaveLR(MF, LR));
832 MachineRegisterInfo &MRI = MF.getRegInfo();
833 MRI.setPhysRegUnused(LR);
835 // Save R31 if necessary
836 int FPSI = FI->getFramePointerSaveIndex();
837 bool isPPC64 = Subtarget.isPPC64();
838 bool isDarwinABI = Subtarget.isDarwinABI();
839 MachineFrameInfo *MFI = MF.getFrameInfo();
841 // If the frame pointer save index hasn't been defined yet.
842 if (!FPSI && needsFP(MF)) {
843 // Find out what the fix offset of the frame pointer save area.
844 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
845 // Allocate the frame index for frame pointer save area.
846 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
848 FI->setFramePointerSaveIndex(FPSI);
851 // Reserve stack space to move the linkage area to in case of a tail call.
853 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
854 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
855 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
858 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
859 // function uses CR 2, 3, or 4.
860 if (!isPPC64 && !isDarwinABI &&
861 (MRI.isPhysRegUsed(PPC::CR2) ||
862 MRI.isPhysRegUsed(PPC::CR3) ||
863 MRI.isPhysRegUsed(PPC::CR4))) {
864 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
865 FI->setCRSpillFrameIndex(FrameIdx);
869 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
870 RegScavenger *RS) const {
871 // Early exit if not using the SVR4 ABI.
872 if (!Subtarget.isSVR4ABI()) {
873 addScavengingSpillSlot(MF, RS);
877 // Get callee saved register information.
878 MachineFrameInfo *FFI = MF.getFrameInfo();
879 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
881 // Early exit if no callee saved registers are modified!
882 if (CSI.empty() && !needsFP(MF)) {
883 addScavengingSpillSlot(MF, RS);
887 unsigned MinGPR = PPC::R31;
888 unsigned MinG8R = PPC::X31;
889 unsigned MinFPR = PPC::F31;
890 unsigned MinVR = PPC::V31;
892 bool HasGPSaveArea = false;
893 bool HasG8SaveArea = false;
894 bool HasFPSaveArea = false;
895 bool HasVRSAVESaveArea = false;
896 bool HasVRSaveArea = false;
898 SmallVector<CalleeSavedInfo, 18> GPRegs;
899 SmallVector<CalleeSavedInfo, 18> G8Regs;
900 SmallVector<CalleeSavedInfo, 18> FPRegs;
901 SmallVector<CalleeSavedInfo, 18> VRegs;
903 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
904 unsigned Reg = CSI[i].getReg();
905 if (PPC::GPRCRegClass.contains(Reg)) {
906 HasGPSaveArea = true;
908 GPRegs.push_back(CSI[i]);
913 } else if (PPC::G8RCRegClass.contains(Reg)) {
914 HasG8SaveArea = true;
916 G8Regs.push_back(CSI[i]);
921 } else if (PPC::F8RCRegClass.contains(Reg)) {
922 HasFPSaveArea = true;
924 FPRegs.push_back(CSI[i]);
929 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
930 PPC::CRRCRegClass.contains(Reg)) {
931 ; // do nothing, as we already know whether CRs are spilled
932 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
933 HasVRSAVESaveArea = true;
934 } else if (PPC::VRRCRegClass.contains(Reg)) {
935 HasVRSaveArea = true;
937 VRegs.push_back(CSI[i]);
943 llvm_unreachable("Unknown RegisterClass!");
947 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
949 int64_t LowerBound = 0;
951 // Take into account stack space reserved for tail calls.
953 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
954 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
955 LowerBound = TCSPDelta;
958 // The Floating-point register save area is right below the back chain word
959 // of the previous stack frame.
961 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
962 int FI = FPRegs[i].getFrameIdx();
964 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
967 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
970 // Check whether the frame pointer register is allocated. If so, make sure it
971 // is spilled to the correct offset.
973 HasGPSaveArea = true;
975 int FI = PFI->getFramePointerSaveIndex();
976 assert(FI && "No Frame Pointer Save Slot!");
978 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
981 // General register save area starts right below the Floating-point
982 // register save area.
983 if (HasGPSaveArea || HasG8SaveArea) {
984 // Move general register save area spill slots down, taking into account
985 // the size of the Floating-point register save area.
986 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
987 int FI = GPRegs[i].getFrameIdx();
989 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
992 // Move general register save area spill slots down, taking into account
993 // the size of the Floating-point register save area.
994 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
995 int FI = G8Regs[i].getFrameIdx();
997 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1001 std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
1002 getPPCRegisterNumbering(MinG8R));
1004 if (Subtarget.isPPC64()) {
1005 LowerBound -= (31 - MinReg + 1) * 8;
1007 LowerBound -= (31 - MinReg + 1) * 4;
1011 // For 32-bit only, the CR save area is below the general register
1012 // save area. For 64-bit SVR4, the CR save area is addressed relative
1013 // to the stack pointer and hence does not need an adjustment here.
1014 // Only CR2 (the first nonvolatile spilled) has an associated frame
1015 // index so that we have a single uniform save area.
1016 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1017 // Adjust the frame index of the CR spill slot.
1018 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1019 unsigned Reg = CSI[i].getReg();
1021 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1022 // Leave Darwin logic as-is.
1023 || (!Subtarget.isSVR4ABI() &&
1024 (PPC::CRBITRCRegClass.contains(Reg) ||
1025 PPC::CRRCRegClass.contains(Reg)))) {
1026 int FI = CSI[i].getFrameIdx();
1028 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1032 LowerBound -= 4; // The CR save area is always 4 bytes long.
1035 if (HasVRSAVESaveArea) {
1036 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1037 // which have the VRSAVE register class?
1038 // Adjust the frame index of the VRSAVE spill slot.
1039 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1040 unsigned Reg = CSI[i].getReg();
1042 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1043 int FI = CSI[i].getFrameIdx();
1045 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1049 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1052 if (HasVRSaveArea) {
1053 // Insert alignment padding, we need 16-byte alignment.
1054 LowerBound = (LowerBound - 15) & ~(15);
1056 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1057 int FI = VRegs[i].getFrameIdx();
1059 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1063 addScavengingSpillSlot(MF, RS);
1067 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1068 RegScavenger *RS) const {
1069 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1070 // a large stack, which will require scavenging a register to materialize a
1073 // We need to have a scavenger spill slot for spills if the frame size is
1074 // large. In case there is no free register for large-offset addressing,
1075 // this slot is used for the necessary emergency spill. Also, we need the
1076 // slot for dynamic stack allocations.
1078 // The scavenger might be invoked if the frame offset does not fit into
1079 // the 16-bit immediate. We don't know the complete frame size here
1080 // because we've not yet computed callee-saved register spills or the
1081 // needed alignment padding.
1082 unsigned StackSize = determineFrameLayout(MF, false, true);
1083 MachineFrameInfo *MFI = MF.getFrameInfo();
1084 if (MFI->hasVarSizedObjects() || spillsCR(MF) || hasNonRISpills(MF) ||
1085 (hasSpills(MF) && !isInt<16>(StackSize))) {
1086 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1087 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1088 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1089 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1096 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1097 MachineBasicBlock::iterator MI,
1098 const std::vector<CalleeSavedInfo> &CSI,
1099 const TargetRegisterInfo *TRI) const {
1101 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1102 // Return false otherwise to maintain pre-existing behavior.
1103 if (!Subtarget.isSVR4ABI())
1106 MachineFunction *MF = MBB.getParent();
1107 const PPCInstrInfo &TII =
1108 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1110 bool CRSpilled = false;
1112 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1113 unsigned Reg = CSI[i].getReg();
1114 // CR2 through CR4 are the nonvolatile CR fields.
1115 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1117 if (CRSpilled && IsCRField)
1120 // Add the callee-saved register as live-in; it's killed at the spill.
1123 // Insert the spill to the stack frame.
1126 // The first time we see a CR field, store the whole CR into the
1127 // save slot via GPR12 (available in the prolog for 32- and 64-bit).
1128 if (Subtarget.isPPC64()) {
1130 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12));
1131 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW))
1133 getKillRegState(true))
1137 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1138 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1139 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
1140 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1142 getKillRegState(true)),
1143 CSI[i].getFrameIdx()));
1146 // Record that we spill the CR in this function.
1147 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1148 FuncInfo->setSpillsCR();
1150 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1151 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1152 CSI[i].getFrameIdx(), RC, TRI);
1159 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1160 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1161 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1163 MachineFunction *MF = MBB.getParent();
1164 const PPCInstrInfo &TII =
1165 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1167 unsigned RestoreOp, MoveReg;
1171 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12)
1174 RestoreOp = PPC::MTCRF8;
1177 // 32-bit: FP-relative
1178 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1180 CSI[CSIIndex].getFrameIdx()));
1181 RestoreOp = PPC::MTCRF;
1186 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1190 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1194 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1198 void PPCFrameLowering::
1199 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1200 MachineBasicBlock::iterator I) const {
1201 const PPCInstrInfo &TII =
1202 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1203 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1204 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1205 // Add (actually subtract) back the amount the callee popped on return.
1206 if (int CalleeAmt = I->getOperand(1).getImm()) {
1207 bool is64Bit = Subtarget.isPPC64();
1209 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1210 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1211 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1212 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1213 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1214 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1215 MachineInstr *MI = I;
1216 DebugLoc dl = MI->getDebugLoc();
1218 if (isInt<16>(CalleeAmt)) {
1219 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1220 .addReg(StackReg, RegState::Kill)
1223 MachineBasicBlock::iterator MBBI = I;
1224 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1225 .addImm(CalleeAmt >> 16);
1226 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1227 .addReg(TmpReg, RegState::Kill)
1228 .addImm(CalleeAmt & 0xFFFF);
1229 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1230 .addReg(StackReg, RegState::Kill)
1235 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1240 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1241 MachineBasicBlock::iterator MI,
1242 const std::vector<CalleeSavedInfo> &CSI,
1243 const TargetRegisterInfo *TRI) const {
1245 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1246 // Return false otherwise to maintain pre-existing behavior.
1247 if (!Subtarget.isSVR4ABI())
1250 MachineFunction *MF = MBB.getParent();
1251 const PPCInstrInfo &TII =
1252 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1253 bool CR2Spilled = false;
1254 bool CR3Spilled = false;
1255 bool CR4Spilled = false;
1256 unsigned CSIIndex = 0;
1258 // Initialize insertion-point logic; we will be restoring in reverse
1260 MachineBasicBlock::iterator I = MI, BeforeI = I;
1261 bool AtStart = I == MBB.begin();
1266 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1267 unsigned Reg = CSI[i].getReg();
1269 if (Reg == PPC::CR2) {
1271 // The spill slot is associated only with CR2, which is the
1272 // first nonvolatile spilled. Save it here.
1275 } else if (Reg == PPC::CR3) {
1278 } else if (Reg == PPC::CR4) {
1282 // When we first encounter a non-CR register after seeing at
1283 // least one CR register, restore all spilled CRs together.
1284 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1285 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1286 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1287 MBB, I, CSI, CSIIndex);
1288 CR2Spilled = CR3Spilled = CR4Spilled = false;
1291 // Default behavior for non-CR saves.
1292 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1293 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1295 assert(I != MBB.begin() &&
1296 "loadRegFromStackSlot didn't insert any code!");
1299 // Insert in reverse order.
1308 // If we haven't yet spilled the CRs, do so now.
1309 if (CR2Spilled || CR3Spilled || CR4Spilled)
1310 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1311 MBB, I, CSI, CSIIndex);