1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bitcode to native PowerPC.
13 //===----------------------------------------------------------------------===//
16 #include "PPCRelocations.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/JITCodeEmitter.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/Module.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOptions.h"
30 class PPCCodeEmitter : public MachineFunctionPass {
33 MachineModuleInfo *MMI;
35 void getAnalysisUsage(AnalysisUsage &AU) const {
36 AU.addRequired<MachineModuleInfo>();
37 MachineFunctionPass::getAnalysisUsage(AU);
42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43 /// its address in the function into this pointer.
44 void *MovePCtoLROffset;
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
50 /// getBinaryCodeForInstr - This function, generated by the
51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52 /// machine instructions.
53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
56 MachineRelocation GetRelocation(const MachineOperand &MO,
57 unsigned RelocID) const;
59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60 unsigned getMachineOpValue(const MachineInstr &MI,
61 const MachineOperand &MO) const;
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
71 unsigned getTLSOffsetEncoding(const MachineInstr &MI, unsigned OpNo) const;
72 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
74 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
76 /// runOnMachineFunction - emits the given MachineFunction to memory
78 bool runOnMachineFunction(MachineFunction &MF);
80 /// emitBasicBlock - emits the given MachineBasicBlock to memory
82 void emitBasicBlock(MachineBasicBlock &MBB);
86 char PPCCodeEmitter::ID = 0;
88 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
89 /// to the specified MCE object.
90 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
91 JITCodeEmitter &JCE) {
92 return new PPCCodeEmitter(TM, JCE);
95 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
96 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
97 MF.getTarget().getRelocationModel() != Reloc::Static) &&
98 "JIT relocation model must be set to static or default!");
100 MMI = &getAnalysis<MachineModuleInfo>();
101 MCE.setModuleInfo(MMI);
103 MovePCtoLROffset = 0;
104 MCE.startFunction(MF);
105 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
107 } while (MCE.finishFunction(MF));
112 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
113 MCE.StartMachineBasicBlock(&MBB);
115 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
116 const MachineInstr &MI = *I;
117 MCE.processDebugLoc(MI.getDebugLoc(), true);
118 switch (MI.getOpcode()) {
120 MCE.emitWordBE(getBinaryCodeForInstr(MI));
122 case TargetOpcode::PROLOG_LABEL:
123 case TargetOpcode::EH_LABEL:
124 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
126 case TargetOpcode::IMPLICIT_DEF:
127 case TargetOpcode::KILL:
128 break; // pseudo opcode, no side effects
129 case PPC::MovePCtoLR:
130 case PPC::MovePCtoLR8:
131 assert(TM.getRelocationModel() == Reloc::PIC_);
132 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
133 MCE.emitWordBE(0x48000005); // bl 1
136 MCE.processDebugLoc(MI.getDebugLoc(), false);
140 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
141 unsigned OpNo) const {
142 const MachineOperand &MO = MI.getOperand(OpNo);
143 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 ||
144 MI.getOpcode() == PPC::MFOCRF) &&
145 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
146 return 0x80 >> getPPCRegisterNumbering(MO.getReg());
149 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
150 unsigned RelocID) const {
151 // If in PIC mode, we need to encode the negated address of the
152 // 'movepctolr' into the unrelocated field. After relocation, we'll have
153 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
154 // field, we get &gv. This doesn't happen for branch relocations, which are
155 // always implicitly pc relative.
157 if (TM.getRelocationModel() == Reloc::PIC_) {
158 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
159 Cst = -(intptr_t)MovePCtoLROffset - 4;
163 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
164 const_cast<GlobalValue *>(MO.getGlobal()),
165 Cst, isa<Function>(MO.getGlobal()));
167 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
168 RelocID, MO.getSymbolName(), Cst);
170 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
171 RelocID, MO.getIndex(), Cst);
174 return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
175 RelocID, MO.getMBB());
178 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
179 RelocID, MO.getIndex(), Cst);
182 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
183 unsigned OpNo) const {
184 const MachineOperand &MO = MI.getOperand(OpNo);
185 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
187 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
191 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
192 unsigned OpNo) const {
193 const MachineOperand &MO = MI.getOperand(OpNo);
194 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
198 unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI,
199 unsigned OpNo) const {
200 const MachineOperand &MO = MI.getOperand(OpNo);
201 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
203 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high));
207 unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
208 unsigned OpNo) const {
209 const MachineOperand &MO = MI.getOperand(OpNo);
210 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
212 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
216 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
217 unsigned OpNo) const {
218 // Encode (imm, reg) as a memri, which has the low 16-bits as the
219 // displacement and the next 5 bits as the register #.
220 assert(MI.getOperand(OpNo+1).isReg());
221 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
223 const MachineOperand &MO = MI.getOperand(OpNo);
225 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
227 // Add a fixup for the displacement field.
228 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
232 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
233 unsigned OpNo) const {
234 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
235 // displacement and the next 5 bits as the register #.
236 assert(MI.getOperand(OpNo+1).isReg());
237 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
239 const MachineOperand &MO = MI.getOperand(OpNo);
241 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits;
243 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
248 unsigned PPCCodeEmitter::getTLSOffsetEncoding(const MachineInstr &MI,
249 unsigned OpNo) const {
250 llvm_unreachable("TLS not supported on the old JIT.");
255 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
256 unsigned OpNo) const {
257 llvm_unreachable("TLS not supported on the old JIT.");
262 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
263 const MachineOperand &MO) const {
266 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
267 // The GPR operand should come through here though.
268 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 &&
269 MI.getOpcode() != PPC::MFOCRF) ||
270 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
271 return getPPCRegisterNumbering(MO.getReg());
275 "Relocation required in an instruction that we cannot encode!");
279 #include "PPCGenCodeEmitter.inc"