1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bytecode to native PowerPC.
13 //===----------------------------------------------------------------------===//
15 #include "PPCTargetMachine.h"
16 #include "PPCRelocations.h"
18 #include "llvm/Module.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/CodeGen/MachineCodeEmitter.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Target/TargetOptions.h"
30 class PPCCodeEmitter : public MachineFunctionPass {
32 MachineCodeEmitter &MCE;
34 // Tracks which instruction references which BasicBlock
35 std::vector<std::pair<MachineBasicBlock*, unsigned*> > BBRefs;
36 // Tracks where each BasicBlock starts
37 std::map<MachineBasicBlock*, long> BBLocations;
39 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
41 int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
44 PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
47 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
49 /// runOnMachineFunction - emits the given MachineFunction to memory
51 bool runOnMachineFunction(MachineFunction &MF);
53 /// emitBasicBlock - emits the given MachineBasicBlock to memory
55 void emitBasicBlock(MachineBasicBlock &MBB);
57 /// emitWord - write a 32-bit word to memory at the current PC
59 void emitWord(unsigned w) { MCE.emitWord(w); }
61 /// getValueBit - return the particular bit of Val
63 unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
65 /// getBinaryCodeForInstr - This function, generated by the
66 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
67 /// machine instructions.
69 unsigned getBinaryCodeForInstr(MachineInstr &MI);
73 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
74 /// machine code emitted. This uses a MachineCodeEmitter object to handle
75 /// actually outputting the machine code and resolving things like the address
76 /// of functions. This method should returns true if machine code emission is
79 bool PPCTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
80 MachineCodeEmitter &MCE) {
81 // Machine code emitter pass for PowerPC
82 PM.add(new PPCCodeEmitter(*this, MCE));
83 // Delete machine code for this function after emitting it
84 PM.add(createMachineCodeDeleter());
88 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
89 MCE.startFunction(MF);
90 MCE.emitConstantPool(MF.getConstantPool());
91 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
93 MCE.finishFunction(MF);
95 // Resolve branches to BasicBlocks for the entire function
96 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
97 intptr_t Location = BBLocations[BBRefs[i].first];
98 unsigned *Ref = BBRefs[i].second;
99 DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
101 unsigned Instr = *Ref;
102 intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
104 switch (Instr >> 26) {
105 default: assert(0 && "Unknown branch user!");
106 case 18: // This is B or BL
107 *Ref |= (BranchTargetDisp & ((1 << 24)-1)) << 2;
109 case 16: // This is BLT,BLE,BEQ,BGE,BGT,BNE, or other bcx instruction
110 *Ref |= (BranchTargetDisp & ((1 << 14)-1)) << 2;
120 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
121 assert(!PICEnabled && "CodeEmitter does not support PIC!");
122 BBLocations[&MBB] = MCE.getCurrentPCValue();
123 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
124 MachineInstr &MI = *I;
125 unsigned Opcode = MI.getOpcode();
126 switch (MI.getOpcode()) {
128 emitWord(getBinaryCodeForInstr(*I));
130 case PPC::IMPLICIT_DEF_GPR:
131 case PPC::IMPLICIT_DEF_F8:
132 case PPC::IMPLICIT_DEF_F4:
133 break; // pseudo opcode, no side effects
134 case PPC::MovePCtoLR:
135 assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
141 static unsigned enumRegToMachineReg(unsigned enumReg) {
143 case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
144 case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
145 case PPC::R2 : case PPC::F2 : case PPC::CR2: return 2;
146 case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
147 case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
148 case PPC::R5 : case PPC::F5 : case PPC::CR5: return 5;
149 case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
150 case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
151 case PPC::R8 : case PPC::F8 : return 8;
152 case PPC::R9 : case PPC::F9 : return 9;
153 case PPC::R10: case PPC::F10: return 10;
154 case PPC::R11: case PPC::F11: return 11;
155 case PPC::R12: case PPC::F12: return 12;
156 case PPC::R13: case PPC::F13: return 13;
157 case PPC::R14: case PPC::F14: return 14;
158 case PPC::R15: case PPC::F15: return 15;
159 case PPC::R16: case PPC::F16: return 16;
160 case PPC::R17: case PPC::F17: return 17;
161 case PPC::R18: case PPC::F18: return 18;
162 case PPC::R19: case PPC::F19: return 19;
163 case PPC::R20: case PPC::F20: return 20;
164 case PPC::R21: case PPC::F21: return 21;
165 case PPC::R22: case PPC::F22: return 22;
166 case PPC::R23: case PPC::F23: return 23;
167 case PPC::R24: case PPC::F24: return 24;
168 case PPC::R25: case PPC::F25: return 25;
169 case PPC::R26: case PPC::F26: return 26;
170 case PPC::R27: case PPC::F27: return 27;
171 case PPC::R28: case PPC::F28: return 28;
172 case PPC::R29: case PPC::F29: return 29;
173 case PPC::R30: case PPC::F30: return 30;
174 case PPC::R31: case PPC::F31: return 31;
176 std::cerr << "Unhandled reg in enumRegToRealReg!\n";
181 int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
183 int rv = 0; // Return value; defaults to 0 for unhandled cases
184 // or things that get fixed up later by the JIT.
185 if (MO.isRegister()) {
186 rv = enumRegToMachineReg(MO.getReg());
188 // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
189 // register, not the register number directly.
190 if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
191 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
194 } else if (MO.isImmediate()) {
195 rv = MO.getImmedValue();
196 } else if (MO.isGlobalAddress() || MO.isExternalSymbol()) {
197 bool isExternal = MO.isExternalSymbol() ||
198 MO.getGlobal()->hasWeakLinkage() ||
199 MO.getGlobal()->hasLinkOnceLinkage() ||
200 (MO.getGlobal()->isExternal() &&
201 !MO.getGlobal()->hasNotBeenReadFromBytecode());
203 if (MI.getOpcode() == PPC::BL)
204 Reloc = PPC::reloc_pcrel_bx;
206 switch (MI.getOpcode()) {
207 default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
210 Reloc = PPC::reloc_absolute_ptr_high; // Pointer to stub
212 Reloc = PPC::reloc_absolute_high; // Pointer to symbol
215 assert(!isExternal && "Something in the ISEL changed\n");
216 Reloc = PPC::reloc_absolute_low;
230 Reloc = PPC::reloc_absolute_ptr_low;
232 Reloc = PPC::reloc_absolute_low;
236 if (MO.isGlobalAddress())
237 MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
238 Reloc, MO.getGlobal(), 0));
240 MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
241 Reloc, MO.getSymbolName(), 0));
242 } else if (MO.isMachineBasicBlock()) {
243 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
244 BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC));
245 } else if (MO.isConstantPoolIndex()) {
246 unsigned index = MO.getConstantPoolIndex();
247 unsigned Opcode = MI.getOpcode();
248 rv = MCE.getConstantPoolEntryAddress(index);
249 if (Opcode == PPC::LIS || Opcode == PPC::ADDIS) {
250 // lis wants hi16(addr)
251 if ((short)rv < 0) rv += 1 << 16;
253 } else if (Opcode == PPC::LWZ || Opcode == PPC::LA ||
255 Opcode == PPC::LFS || Opcode == PPC::LFD) {
256 // These load opcodes want lo16(addr)
259 assert(0 && "Unknown constant pool using instruction!");
262 std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
269 #include "PPCGenCodeEmitter.inc"