1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
55 "Enable Altivec instructions">;
56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57 "Enable the MFOCRF instruction">;
58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59 "Enable the fsqrt instruction">;
60 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
61 "Enable the stfiwx instruction">;
62 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
63 "Enable the fri[mnpz] instructions">;
64 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
65 "Enable the isel instruction">;
66 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
67 "Enable the popcnt[dw] instructions">;
68 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
69 "Enable the ldbrx instruction">;
70 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
71 "Enable Book E instructions">;
72 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
73 "Enable QPX instructions">;
75 // Note: Future features to add when support is extended to more
78 // CMPB p6, p6x, p7 cmpb
79 // DFP p6, p6x, p7 decimal floating-point instructions
80 // FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz
81 // FRE p5 through p7 fre (vs. fres, available since p3)
82 // FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)
83 // LFIWAX p6, p6x, p7 lfiwax
85 // POPCNTB p5 through p7 popcntb and related instructions
86 // RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates
87 // VSX p7 vector-scalar instruction set
89 //===----------------------------------------------------------------------===//
90 // Register File Description
91 //===----------------------------------------------------------------------===//
93 include "PPCRegisterInfo.td"
94 include "PPCSchedule.td"
95 include "PPCInstrInfo.td"
97 //===----------------------------------------------------------------------===//
98 // PowerPC processors supported.
101 def : Processor<"generic", G3Itineraries, [Directive32]>;
102 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
104 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
106 def : Processor<"601", G3Itineraries, [Directive601]>;
107 def : Processor<"602", G3Itineraries, [Directive602]>;
108 def : Processor<"603", G3Itineraries, [Directive603]>;
109 def : Processor<"603e", G3Itineraries, [Directive603]>;
110 def : Processor<"603ev", G3Itineraries, [Directive603]>;
111 def : Processor<"604", G3Itineraries, [Directive604]>;
112 def : Processor<"604e", G3Itineraries, [Directive604]>;
113 def : Processor<"620", G3Itineraries, [Directive620]>;
114 def : Processor<"750", G4Itineraries, [Directive750]>;
115 def : Processor<"g3", G3Itineraries, [Directive750]>;
116 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
117 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
118 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
119 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
120 def : Processor<"970", G5Itineraries,
121 [Directive970, FeatureAltivec,
122 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
123 Feature64Bit /*, Feature64BitRegs */]>;
124 def : Processor<"g5", G5Itineraries,
125 [Directive970, FeatureAltivec,
126 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
127 Feature64Bit /*, Feature64BitRegs */]>;
128 def : ProcessorModel<"e500mc", PPCE500mcModel,
129 [DirectiveE500mc, FeatureMFOCRF,
130 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
131 def : ProcessorModel<"e5500", PPCE5500Model,
132 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
133 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
134 def : Processor<"a2", PPCA2Itineraries,
135 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
136 FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
137 FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
138 Feature64Bit /*, Feature64BitRegs */]>;
139 def : Processor<"a2q", PPCA2Itineraries,
140 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
141 FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
142 FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
143 Feature64Bit /*, Feature64BitRegs */, FeatureQPX]>;
144 def : Processor<"pwr3", G5Itineraries,
145 [DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
146 FeatureSTFIWX, Feature64Bit]>;
147 def : Processor<"pwr4", G5Itineraries,
148 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
149 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
150 def : Processor<"pwr5", G5Itineraries,
151 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
152 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
153 def : Processor<"pwr5x", G5Itineraries,
154 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
155 FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
157 def : Processor<"pwr6", G5Itineraries,
158 [DirectivePwr6, FeatureAltivec,
159 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
160 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
161 def : Processor<"pwr6x", G5Itineraries,
162 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
163 FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
165 def : Processor<"pwr7", G5Itineraries,
166 [DirectivePwr7, FeatureAltivec,
167 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
168 FeatureFPRND, FeatureISEL, FeaturePOPCNTD,
169 FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */]>;
170 def : Processor<"ppc", G3Itineraries, [Directive32]>;
171 def : Processor<"ppc64", G5Itineraries,
172 [Directive64, FeatureAltivec,
173 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
174 Feature64Bit /*, Feature64BitRegs */]>;
177 //===----------------------------------------------------------------------===//
178 // Calling Conventions
179 //===----------------------------------------------------------------------===//
181 include "PPCCallingConv.td"
183 def PPCInstrInfo : InstrInfo {
184 let isLittleEndianEncoding = 1;
187 def PPCAsmWriter : AsmWriter {
188 string AsmWriterClassName = "InstPrinter";
189 bit isMCAsmWriter = 1;
193 // Information about the instructions.
194 let InstructionSet = PPCInstrInfo;
196 let AssemblyWriters = [PPCAsmWriter];