lib/Target/PowerPC/PPC.td

   1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37
  38 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  39                                         "Enable 64-bit instructions">;
  40 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  41                               "Enable 64-bit registers usage for ppc32 [beta]">;
  42 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  43                                         "Enable Altivec instructions">;
  44 def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
  45                                         "Enable GPUL instructions">;
  46 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  47                                         "Enable the fsqrt instruction">;
  48 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  49                                         "Enable the stfiwx instruction">;
  50 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  51                                         "Enable Book E instructions">;
  52
  53 //===----------------------------------------------------------------------===//
  54 // Register File Description
  55 //===----------------------------------------------------------------------===//
  56
  57 include "PPCRegisterInfo.td"
  58 include "PPCSchedule.td"
  59 include "PPCInstrInfo.td"
  60
  61 //===----------------------------------------------------------------------===//
  62 // PowerPC processors supported.
  63 //
  64
  65 def : Processor<"generic", G3Itineraries, [Directive32]>;
  66 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
  67 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
  68 def : Processor<"601", G3Itineraries, [Directive601]>;
  69 def : Processor<"602", G3Itineraries, [Directive602]>;
  70 def : Processor<"603", G3Itineraries, [Directive603]>;
  71 def : Processor<"603e", G3Itineraries, [Directive603]>;
  72 def : Processor<"603ev", G3Itineraries, [Directive603]>;
  73 def : Processor<"604", G3Itineraries, [Directive604]>;
  74 def : Processor<"604e", G3Itineraries, [Directive604]>;
  75 def : Processor<"620", G3Itineraries, [Directive620]>;
  76 def : Processor<"g3", G3Itineraries, [Directive7400]>;
  77 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
  78 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
  79 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  80 def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
  81 def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
  82 def : Processor<"970", G5Itineraries,
  83                   [Directive970, FeatureAltivec,
  84                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  85                    Feature64Bit /*, Feature64BitRegs */]>;
  86 def : Processor<"g5", G5Itineraries,
  87                   [Directive970, FeatureAltivec,
  88                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  89                    Feature64Bit /*, Feature64BitRegs */]>;
  90 def : Processor<"ppc", G3Itineraries, [Directive32]>;
  91 def : Processor<"ppc64", G5Itineraries,
  92                   [Directive64, FeatureAltivec,
  93                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  94                    Feature64Bit /*, Feature64BitRegs */]>;
  95
  96
  97 //===----------------------------------------------------------------------===//
  98 // Calling Conventions
  99 //===----------------------------------------------------------------------===//
 100
 101 include "PPCCallingConv.td"
 102
 103 def PPCInstrInfo : InstrInfo {
 104   let isLittleEndianEncoding = 1;
 105 }
 106
 107 def PPCAsmWriter : AsmWriter {
 108   string AsmWriterClassName  = "InstPrinter";
 109   bit isMCAsmWriter = 1;
 110 }
 111
 112 def PPC : Target {
 113   // Information about the instructions.
 114   let InstructionSet = PPCInstrInfo;
 115
 116   let AssemblyWriters = [PPCAsmWriter];
 117 }