lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  54                               "Enable 64-bit registers usage for ppc32 [beta]">;
  55 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  56                               "Use condition-register bits individually">;
  57 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  58                                         "Enable Altivec instructions">;
  59 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  60                                         "Enable SPE instructions">;
  61 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  62                                         "Enable the MFOCRF instruction">;
  63 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  64                                         "Enable the fsqrt instruction">;
  65 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  66                                         "Enable the fcpsgn instruction">;
  67 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  68                                         "Enable the fre instruction">;
  69 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  70                                         "Enable the fres instruction">;
  71 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  72                                         "Enable the frsqrte instruction">;
  73 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  74                                         "Enable the frsqrtes instruction">;
  75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  76                               "Assume higher precision reciprocal estimates">;
  77 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  78                                         "Enable the stfiwx instruction">;
  79 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  80                                         "Enable the lfiwax instruction">;
  81 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  82                                         "Enable the fri[mnpz] instructions">;
  83 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  84   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  85 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  86                                         "Enable the isel instruction">;
  87 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  88                                         "Enable the popcnt[dw] instructions">;
  89 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  90                                         "Enable the ldbrx instruction">;
  91 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
  92                                         "Enable the cmpb instruction">;
  93 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
  94                                         "Enable icbt instruction">;
  95 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  96                                         "Enable Book E instructions",
  97                                         [FeatureICBT]>;
  98 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
  99                               "Has only the msync instruction instead of sync",
 100                               [FeatureBookE]>;
 101 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 102                                         "Enable E500/E500mc instructions">;
 103 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 104                                         "Enable PPC 4xx instructions">;
 105 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 106                                         "Enable PPC 6xx instructions">;
 107 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 108                                         "Enable QPX instructions">;
 109 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 110                                         "Enable VSX instructions",
 111                                         [FeatureAltivec]>;
 112 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 113                                         "Enable POWER8 Altivec instructions",
 114                                         [FeatureAltivec]>;
 115 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 116                                         "Enable POWER8 Crypto instructions",
 117                                         [FeatureP8Altivec]>;
 118 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 119                                         "Enable POWER8 vector instructions",
 120                                         [FeatureVSX, FeatureP8Altivec]>;
 121
 122 def FeatureInvariantFunctionDescriptors :
 123   SubtargetFeature<"invariant-function-descriptors",
 124                    "HasInvariantFunctionDescriptors", "true",
 125                    "Assume function descriptors are invariant">;
 126
 127 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
 128                                         "Treat mftb as deprecated">;
 129 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 130   "Treat vector data stream cache control instructions as deprecated">;
 131
 132 // Note: Future features to add when support is extended to more
 133 // recent ISA levels:
 134 //
 135 // DFP          p6, p6x, p7        decimal floating-point instructions
 136 // POPCNTB      p5 through p7      popcntb and related instructions
 137
 138 //===----------------------------------------------------------------------===//
 139 // Classes used for relation maps.
 140 //===----------------------------------------------------------------------===//
 141 // RecFormRel - Filter class used to relate non-record-form instructions with
 142 // their record-form variants.
 143 class RecFormRel;
 144
 145 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 146 // FMA instruction forms with their corresponding factor-killing forms.
 147 class AltVSXFMARel {
 148   bit IsVSXFMAAlt = 0;
 149 }
 150
 151 //===----------------------------------------------------------------------===//
 152 // Relation Map Definitions.
 153 //===----------------------------------------------------------------------===//
 154
 155 def getRecordFormOpcode : InstrMapping {
 156   let FilterClass = "RecFormRel";
 157   // Instructions with the same BaseName and Interpretation64Bit values
 158   // form a row.
 159   let RowFields = ["BaseName", "Interpretation64Bit"];
 160   // Instructions with the same RC value form a column.
 161   let ColFields = ["RC"];
 162   // The key column are the non-record-form instructions.
 163   let KeyCol = ["0"];
 164   // Value columns RC=1
 165   let ValueCols = [["1"]];
 166 }
 167
 168 def getNonRecordFormOpcode : InstrMapping {
 169   let FilterClass = "RecFormRel";
 170   // Instructions with the same BaseName and Interpretation64Bit values
 171   // form a row.
 172   let RowFields = ["BaseName", "Interpretation64Bit"];
 173   // Instructions with the same RC value form a column.
 174   let ColFields = ["RC"];
 175   // The key column are the record-form instructions.
 176   let KeyCol = ["1"];
 177   // Value columns are RC=0
 178   let ValueCols = [["0"]];
 179 }
 180
 181 def getAltVSXFMAOpcode : InstrMapping {
 182   let FilterClass = "AltVSXFMARel";
 183   // Instructions with the same BaseName and Interpretation64Bit values
 184   // form a row.
 185   let RowFields = ["BaseName"];
 186   // Instructions with the same RC value form a column.
 187   let ColFields = ["IsVSXFMAAlt"];
 188   // The key column are the (default) addend-killing instructions.
 189   let KeyCol = ["0"];
 190   // Value columns IsVSXFMAAlt=1
 191   let ValueCols = [["1"]];
 192 }
 193
 194 //===----------------------------------------------------------------------===//
 195 // Register File Description
 196 //===----------------------------------------------------------------------===//
 197
 198 include "PPCRegisterInfo.td"
 199 include "PPCSchedule.td"
 200 include "PPCInstrInfo.td"
 201
 202 //===----------------------------------------------------------------------===//
 203 // PowerPC processors supported.
 204 //
 205
 206 def : Processor<"generic", G3Itineraries, [Directive32]>;
 207 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 208                                           FeatureFRES, FeatureFRSQRTE,
 209                                           FeatureICBT, FeatureBookE,
 210                                           FeatureMSYNC, DeprecatedMFTB]>;
 211 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 212                                           FeatureFRES, FeatureFRSQRTE,
 213                                           FeatureICBT, FeatureBookE,
 214                                           FeatureMSYNC, DeprecatedMFTB]>;
 215 def : Processor<"601", G3Itineraries, [Directive601]>;
 216 def : Processor<"602", G3Itineraries, [Directive602]>;
 217 def : Processor<"603", G3Itineraries, [Directive603,
 218                                        FeatureFRES, FeatureFRSQRTE]>;
 219 def : Processor<"603e", G3Itineraries, [Directive603,
 220                                         FeatureFRES, FeatureFRSQRTE]>;
 221 def : Processor<"603ev", G3Itineraries, [Directive603,
 222                                          FeatureFRES, FeatureFRSQRTE]>;
 223 def : Processor<"604", G3Itineraries, [Directive604,
 224                                        FeatureFRES, FeatureFRSQRTE]>;
 225 def : Processor<"604e", G3Itineraries, [Directive604,
 226                                         FeatureFRES, FeatureFRSQRTE]>;
 227 def : Processor<"620", G3Itineraries, [Directive620,
 228                                        FeatureFRES, FeatureFRSQRTE]>;
 229 def : Processor<"750", G4Itineraries, [Directive750,
 230                                        FeatureFRES, FeatureFRSQRTE]>;
 231 def : Processor<"g3", G3Itineraries, [Directive750,
 232                                       FeatureFRES, FeatureFRSQRTE]>;
 233 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 234                                         FeatureFRES, FeatureFRSQRTE]>;
 235 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 236                                       FeatureFRES, FeatureFRSQRTE]>;
 237 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 238                                             FeatureFRES, FeatureFRSQRTE]>;
 239 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 240                                            FeatureFRES, FeatureFRSQRTE]>;
 241
 242 /*  Since new processors generally contain a superset of features of those that
 243     came before them, the idea is to make implementations of new processors
 244     less error prone and easier to read.
 245     Namely:
 246         list<SubtargetFeature> Power8FeatureList = ...
 247         list<SubtargetFeature> FutureProcessorSpecificFeatureList =
 248             [ features that Power8 does not support ]
 249         list<SubtargetFeature> FutureProcessorFeatureList =
 250             !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
 251
 252     Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 253     well as providing a single point of definition if the feature set will be
 254     used elsewhere.
 255
 256 */
 257 def ProcessorFeatures {
 258     list<SubtargetFeature> Power8FeatureList =
 259         [DirectivePwr8, FeatureAltivec, FeatureP8Altivec, FeatureVSX,
 260         FeatureP8Vector, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt,
 261         FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 262         FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 263         FeatureFPRND, FeatureFPCVT, FeatureISEL,
 264         FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, FeatureP8Crypto,
 265         Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
 266         DeprecatedMFTB, DeprecatedDST];
 267 }
 268
 269 def : ProcessorModel<"970", G5Model,
 270                   [Directive970, FeatureAltivec,
 271                    FeatureMFOCRF, FeatureFSqrt,
 272                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 273                    Feature64Bit /*, Feature64BitRegs */]>;
 274 def : ProcessorModel<"g5", G5Model,
 275                   [Directive970, FeatureAltivec,
 276                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 277                    FeatureFRES, FeatureFRSQRTE,
 278                    Feature64Bit /*, Feature64BitRegs */,
 279                    DeprecatedMFTB, DeprecatedDST]>;
 280 def : ProcessorModel<"e500mc", PPCE500mcModel,
 281                   [DirectiveE500mc, FeatureMFOCRF,
 282                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 283                    FeatureISEL, DeprecatedMFTB]>;
 284 def : ProcessorModel<"e5500", PPCE5500Model,
 285                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 286                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 287                    FeatureISEL, DeprecatedMFTB]>;
 288 def : ProcessorModel<"a2", PPCA2Model,
 289                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 290                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 291                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 292                    FeatureSTFIWX, FeatureLFIWAX,
 293                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 294                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 295                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 296 def : ProcessorModel<"a2q", PPCA2Model,
 297                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 298                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 299                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 300                    FeatureSTFIWX, FeatureLFIWAX,
 301                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 302                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 303                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 304 def : ProcessorModel<"pwr3", G5Model,
 305                   [DirectivePwr3, FeatureAltivec,
 306                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 307                    FeatureSTFIWX, Feature64Bit]>;
 308 def : ProcessorModel<"pwr4", G5Model,
 309                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 310                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 311                    FeatureSTFIWX, Feature64Bit]>;
 312 def : ProcessorModel<"pwr5", G5Model,
 313                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 314                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 315                    FeatureFRSQRTE, FeatureFRSQRTES,
 316                    FeatureSTFIWX, Feature64Bit,
 317                    DeprecatedMFTB, DeprecatedDST]>;
 318 def : ProcessorModel<"pwr5x", G5Model,
 319                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 320                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 321                    FeatureFRSQRTE, FeatureFRSQRTES,
 322                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 323                    DeprecatedMFTB, DeprecatedDST]>;
 324 def : ProcessorModel<"pwr6", G5Model,
 325                   [DirectivePwr6, FeatureAltivec,
 326                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 327                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 328                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 329                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 330                    DeprecatedMFTB, DeprecatedDST]>;
 331 def : ProcessorModel<"pwr6x", G5Model,
 332                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 333                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 334                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 335                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 336                    FeatureFPRND, Feature64Bit,
 337                    DeprecatedMFTB, DeprecatedDST]>;
 338 def : ProcessorModel<"pwr7", P7Model,
 339                   [DirectivePwr7, FeatureAltivec, FeatureVSX,
 340                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 341                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 342                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 343                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 344                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
 345                    Feature64Bit /*, Feature64BitRegs */,
 346                    DeprecatedMFTB, DeprecatedDST]>;
 347 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 348 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 349 def : ProcessorModel<"ppc64", G5Model,
 350                   [Directive64, FeatureAltivec,
 351                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 352                    FeatureFRSQRTE, FeatureSTFIWX,
 353                    Feature64Bit /*, Feature64BitRegs */]>;
 354 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 355
 356 //===----------------------------------------------------------------------===//
 357 // Calling Conventions
 358 //===----------------------------------------------------------------------===//
 359
 360 include "PPCCallingConv.td"
 361
 362 def PPCInstrInfo : InstrInfo {
 363   let isLittleEndianEncoding = 1;
 364
 365   // FIXME: Unset this when no longer needed!
 366   let decodePositionallyEncodedOperands = 1;
 367
 368   let noNamedPositionallyEncodedOperands = 1;
 369 }
 370
 371 def PPCAsmParser : AsmParser {
 372   let ShouldEmitMatchRegisterName = 0;
 373 }
 374
 375 def PPCAsmParserVariant : AsmParserVariant {
 376   int Variant = 0;
 377
 378   // We do not use hard coded registers in asm strings.  However, some
 379   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 380   // so that those are not misinterpreted as registers.
 381   string RegisterPrefix = "%";
 382 }
 383
 384 def PPC : Target {
 385   // Information about the instructions.
 386   let InstructionSet = PPCInstrInfo;
 387
 388   let AssemblyParsers = [PPCAsmParser];
 389   let AssemblyParserVariants = [PPCAsmParserVariant];
 390 }