lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  54                               "Enable 64-bit registers usage for ppc32 [beta]">;
  55 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  56                               "Use condition-register bits individually">;
  57 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  58                                         "Enable Altivec instructions">;
  59 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  60                                         "Enable SPE instructions">;
  61 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  62                                         "Enable the MFOCRF instruction">;
  63 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  64                                         "Enable the fsqrt instruction">;
  65 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  66                                         "Enable the fcpsgn instruction">;
  67 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  68                                         "Enable the fre instruction">;
  69 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  70                                         "Enable the fres instruction">;
  71 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  72                                         "Enable the frsqrte instruction">;
  73 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  74                                         "Enable the frsqrtes instruction">;
  75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  76                               "Assume higher precision reciprocal estimates">;
  77 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  78                                         "Enable the stfiwx instruction">;
  79 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  80                                         "Enable the lfiwax instruction">;
  81 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  82                                         "Enable the fri[mnpz] instructions">;
  83 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  84   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  85 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  86                                         "Enable the isel instruction">;
  87 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  88                                         "Enable the popcnt[dw] instructions">;
  89 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  90                                         "Enable the ldbrx instruction">;
  91 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  92                                         "Enable Book E instructions">;
  93 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
  94                               "Has only the msync instruction instead of sync",
  95                               [FeatureBookE]>;
  96 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
  97                                         "Enable E500/E500mc instructions">;
  98 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
  99                                         "Enable PPC 4xx instructions">;
 100 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 101                                         "Enable PPC 6xx instructions">;
 102 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 103                                         "Enable QPX instructions">;
 104 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 105                                         "Enable VSX instructions",
 106                                         [FeatureAltivec]>;
 107
 108 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
 109                                         "Treat mftb as deprecated">;
 110 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 111   "Treat vector data stream cache control instructions as deprecated">;
 112
 113 // Note: Future features to add when support is extended to more
 114 // recent ISA levels:
 115 //
 116 // CMPB         p6, p6x, p7        cmpb
 117 // DFP          p6, p6x, p7        decimal floating-point instructions
 118 // POPCNTB      p5 through p7      popcntb and related instructions
 119 // VSX          p7                 vector-scalar instruction set
 120
 121 //===----------------------------------------------------------------------===//
 122 // ABI Selection                                                              //
 123 //===----------------------------------------------------------------------===//
 124
 125 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
 126                                     "Use the ELFv1 ABI">;
 127
 128 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
 129                                     "Use the ELFv2 ABI">;
 130
 131 //===----------------------------------------------------------------------===//
 132 // Classes used for relation maps.
 133 //===----------------------------------------------------------------------===//
 134 // RecFormRel - Filter class used to relate non-record-form instructions with
 135 // their record-form variants.
 136 class RecFormRel;
 137
 138 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 139 // FMA instruction forms with their corresponding factor-killing forms.
 140 class AltVSXFMARel {
 141   bit IsVSXFMAAlt = 0;
 142 }
 143
 144 //===----------------------------------------------------------------------===//
 145 // Relation Map Definitions.
 146 //===----------------------------------------------------------------------===//
 147
 148 def getRecordFormOpcode : InstrMapping {
 149   let FilterClass = "RecFormRel";
 150   // Instructions with the same BaseName and Interpretation64Bit values
 151   // form a row.
 152   let RowFields = ["BaseName", "Interpretation64Bit"];
 153   // Instructions with the same RC value form a column.
 154   let ColFields = ["RC"];
 155   // The key column are the non-record-form instructions.
 156   let KeyCol = ["0"];
 157   // Value columns RC=1
 158   let ValueCols = [["1"]];
 159 }
 160
 161 def getNonRecordFormOpcode : InstrMapping {
 162   let FilterClass = "RecFormRel";
 163   // Instructions with the same BaseName and Interpretation64Bit values
 164   // form a row.
 165   let RowFields = ["BaseName", "Interpretation64Bit"];
 166   // Instructions with the same RC value form a column.
 167   let ColFields = ["RC"];
 168   // The key column are the record-form instructions.
 169   let KeyCol = ["1"];
 170   // Value columns are RC=0
 171   let ValueCols = [["0"]];
 172 }
 173
 174 def getAltVSXFMAOpcode : InstrMapping {
 175   let FilterClass = "AltVSXFMARel";
 176   // Instructions with the same BaseName and Interpretation64Bit values
 177   // form a row.
 178   let RowFields = ["BaseName"];
 179   // Instructions with the same RC value form a column.
 180   let ColFields = ["IsVSXFMAAlt"];
 181   // The key column are the (default) addend-killing instructions.
 182   let KeyCol = ["0"];
 183   // Value columns IsVSXFMAAlt=1
 184   let ValueCols = [["1"]];
 185 }
 186
 187 //===----------------------------------------------------------------------===//
 188 // Register File Description
 189 //===----------------------------------------------------------------------===//
 190
 191 include "PPCRegisterInfo.td"
 192 include "PPCSchedule.td"
 193 include "PPCInstrInfo.td"
 194
 195 //===----------------------------------------------------------------------===//
 196 // PowerPC processors supported.
 197 //
 198
 199 def : Processor<"generic", G3Itineraries, [Directive32]>;
 200 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 201                                           FeatureFRES, FeatureFRSQRTE,
 202                                           FeatureBookE, FeatureMSYNC,
 203                                           DeprecatedMFTB]>;
 204 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 205                                           FeatureFRES, FeatureFRSQRTE,
 206                                           FeatureBookE, FeatureMSYNC,
 207                                           DeprecatedMFTB]>;
 208 def : Processor<"601", G3Itineraries, [Directive601]>;
 209 def : Processor<"602", G3Itineraries, [Directive602]>;
 210 def : Processor<"603", G3Itineraries, [Directive603,
 211                                        FeatureFRES, FeatureFRSQRTE]>;
 212 def : Processor<"603e", G3Itineraries, [Directive603,
 213                                         FeatureFRES, FeatureFRSQRTE]>;
 214 def : Processor<"603ev", G3Itineraries, [Directive603,
 215                                          FeatureFRES, FeatureFRSQRTE]>;
 216 def : Processor<"604", G3Itineraries, [Directive604,
 217                                        FeatureFRES, FeatureFRSQRTE]>;
 218 def : Processor<"604e", G3Itineraries, [Directive604,
 219                                         FeatureFRES, FeatureFRSQRTE]>;
 220 def : Processor<"620", G3Itineraries, [Directive620,
 221                                        FeatureFRES, FeatureFRSQRTE]>;
 222 def : Processor<"750", G4Itineraries, [Directive750,
 223                                        FeatureFRES, FeatureFRSQRTE]>;
 224 def : Processor<"g3", G3Itineraries, [Directive750,
 225                                       FeatureFRES, FeatureFRSQRTE]>;
 226 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 227                                         FeatureFRES, FeatureFRSQRTE]>;
 228 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 229                                       FeatureFRES, FeatureFRSQRTE]>;
 230 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 231                                             FeatureFRES, FeatureFRSQRTE]>;
 232 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 233                                            FeatureFRES, FeatureFRSQRTE]>;
 234 def : ProcessorModel<"970", G5Model,
 235                   [Directive970, FeatureAltivec,
 236                    FeatureMFOCRF, FeatureFSqrt,
 237                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 238                    Feature64Bit /*, Feature64BitRegs */]>;
 239 def : ProcessorModel<"g5", G5Model,
 240                   [Directive970, FeatureAltivec,
 241                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 242                    FeatureFRES, FeatureFRSQRTE,
 243                    Feature64Bit /*, Feature64BitRegs */,
 244                    DeprecatedMFTB, DeprecatedDST]>;
 245 def : ProcessorModel<"e500mc", PPCE500mcModel,
 246                   [DirectiveE500mc, FeatureMFOCRF,
 247                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 248                    DeprecatedMFTB]>;
 249 def : ProcessorModel<"e5500", PPCE5500Model,
 250                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 251                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 252                    DeprecatedMFTB]>;
 253 def : ProcessorModel<"a2", PPCA2Model,
 254                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 255                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 256                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 257                    FeatureSTFIWX, FeatureLFIWAX,
 258                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 259                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 260                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 261 def : ProcessorModel<"a2q", PPCA2Model,
 262                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 263                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 264                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 265                    FeatureSTFIWX, FeatureLFIWAX,
 266                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 267                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 268                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 269 def : ProcessorModel<"pwr3", G5Model,
 270                   [DirectivePwr3, FeatureAltivec,
 271                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 272                    FeatureSTFIWX, Feature64Bit]>;
 273 def : ProcessorModel<"pwr4", G5Model,
 274                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 275                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 276                    FeatureSTFIWX, Feature64Bit]>;
 277 def : ProcessorModel<"pwr5", G5Model,
 278                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 279                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 280                    FeatureFRSQRTE, FeatureFRSQRTES,
 281                    FeatureSTFIWX, Feature64Bit,
 282                    DeprecatedMFTB, DeprecatedDST]>;
 283 def : ProcessorModel<"pwr5x", G5Model,
 284                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 285                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 286                    FeatureFRSQRTE, FeatureFRSQRTES,
 287                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 288                    DeprecatedMFTB, DeprecatedDST]>;
 289 def : ProcessorModel<"pwr6", G5Model,
 290                   [DirectivePwr6, FeatureAltivec,
 291                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 292                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 293                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 294                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 295                    DeprecatedMFTB, DeprecatedDST]>;
 296 def : ProcessorModel<"pwr6x", G5Model,
 297                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 298                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 299                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 300                    FeatureSTFIWX, FeatureLFIWAX,
 301                    FeatureFPRND, Feature64Bit,
 302                    DeprecatedMFTB, DeprecatedDST]>;
 303 def : ProcessorModel<"pwr7", P7Model,
 304                   [DirectivePwr7, FeatureAltivec, FeatureVSX,
 305                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 306                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 307                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 308                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 309                    FeaturePOPCNTD, FeatureLDBRX,
 310                    Feature64Bit /*, Feature64BitRegs */,
 311                    DeprecatedMFTB, DeprecatedDST]>;
 312 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
 313                   [DirectivePwr8, FeatureAltivec, FeatureVSX,
 314                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 315                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 316                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 317                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 318                    FeaturePOPCNTD, FeatureLDBRX,
 319                    Feature64Bit /*, Feature64BitRegs */,
 320                    DeprecatedMFTB, DeprecatedDST]>;
 321 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 322 def : ProcessorModel<"ppc64", G5Model,
 323                   [Directive64, FeatureAltivec,
 324                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 325                    FeatureFRSQRTE, FeatureSTFIWX,
 326                    Feature64Bit /*, Feature64BitRegs */]>;
 327 def : ProcessorModel<"ppc64le", G5Model,
 328                   [Directive64, FeatureAltivec,
 329                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 330                    FeatureFRSQRTE, FeatureSTFIWX,
 331                    Feature64Bit /*, Feature64BitRegs */]>;
 332
 333 //===----------------------------------------------------------------------===//
 334 // Calling Conventions
 335 //===----------------------------------------------------------------------===//
 336
 337 include "PPCCallingConv.td"
 338
 339 def PPCInstrInfo : InstrInfo {
 340   let isLittleEndianEncoding = 1;
 341
 342   // FIXME: Unset this when no longer needed!
 343   let decodePositionallyEncodedOperands = 1;
 344
 345   let noNamedPositionallyEncodedOperands = 1;
 346 }
 347
 348 def PPCAsmParser : AsmParser {
 349   let ShouldEmitMatchRegisterName = 0;
 350 }
 351
 352 def PPCAsmParserVariant : AsmParserVariant {
 353   int Variant = 0;
 354
 355   // We do not use hard coded registers in asm strings.  However, some
 356   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 357   // so that those are not misinterpreted as registers.
 358   string RegisterPrefix = "%";
 359 }
 360
 361 def PPC : Target {
 362   // Information about the instructions.
 363   let InstructionSet = PPCInstrInfo;
 364
 365   let AssemblyParsers = [PPCAsmParser];
 366   let AssemblyParserVariants = [PPCAsmParserVariant];
 367 }