lib/Target/PowerPC/PPC.td

   1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "../Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 def Feature64Bit     : SubtargetFeature<"64bit",
  23                                         "Enable 64-bit instructions">;
  24 def Feature64BitRegs : SubtargetFeature<"64bitregs",
  25                                         "Enable 64-bit registers [beta]">;
  26 def FeatureAltivec   : SubtargetFeature<"altivec",
  27                                         "Enable Altivec instructions">;
  28 def FeatureGPUL      : SubtargetFeature<"gpul",
  29                                         "Enable GPUL instructions">;
  30 def FeatureFSqrt     : SubtargetFeature<"fsqrt",
  31                                         "Enable the fsqrt instruction">;
  32
  33 //===----------------------------------------------------------------------===//
  34 // Register File Description
  35 //===----------------------------------------------------------------------===//
  36
  37 include "PPCRegisterInfo.td"
  38 include "PPCSchedule.td"
  39 include "PPCInstrInfo.td"
  40
  41 //===----------------------------------------------------------------------===//
  42 // PowerPC processors supported.
  43 //
  44
  45 def : Processor<"generic", G3Itineraries, []>;
  46 def : Processor<"601", G3Itineraries, []>;
  47 def : Processor<"602", G3Itineraries, []>;
  48 def : Processor<"603", G3Itineraries, []>;
  49 def : Processor<"603e", G3Itineraries, []>;
  50 def : Processor<"603ev", G3Itineraries, []>;
  51 def : Processor<"604", G3Itineraries, []>;
  52 def : Processor<"604e", G3Itineraries, []>;
  53 def : Processor<"620", G3Itineraries, []>;
  54 def : Processor<"g3", G3Itineraries, []>;
  55 def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
  56 def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
  57 def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
  58 def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
  59 def : Processor<"750", G3Itineraries, []>;
  60 def : Processor<"970", G5Itineraries,
  61                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
  62                    Feature64Bit /*, Feature64BitRegs */]>;
  63 def : Processor<"g5", G5Itineraries,
  64                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
  65                    Feature64Bit /*, Feature64BitRegs */]>;
  66
  67
  68 def PPC : Target {
  69   // Pointers on PPC are 32-bits in size.
  70   let PointerType = i32;
  71
  72   // According to the Mach-O Runtime ABI, these regs are nonvolatile across
  73   // calls
  74   let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
  75     R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
  76     F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
  77     F30, F31, CR2, CR3, CR4, LR];
  78
  79   // Pull in Instruction Info:
  80   let InstructionSet = PowerPCInstrInfo;
  81 }