lib/Target/PowerPC/PPC.td

   1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "../Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  23                                         "Enable 64-bit instructions">;
  24 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  25                               "Enable 64-bit registers usage for ppc32 [beta]">;
  26 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  27                                         "Enable Altivec instructions">;
  28 def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
  29                                         "Enable GPUL instructions">;
  30 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  31                                         "Enable the fsqrt instruction">;
  32 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  33                                         "Enable the stfiwx instruction">;
  34
  35 //===----------------------------------------------------------------------===//
  36 // Register File Description
  37 //===----------------------------------------------------------------------===//
  38
  39 include "PPCRegisterInfo.td"
  40 include "PPCSchedule.td"
  41 include "PPCInstrInfo.td"
  42
  43 //===----------------------------------------------------------------------===//
  44 // PowerPC processors supported.
  45 //
  46
  47 def : Processor<"generic", G3Itineraries, []>;
  48 def : Processor<"601", G3Itineraries, []>;
  49 def : Processor<"602", G3Itineraries, []>;
  50 def : Processor<"603", G3Itineraries, []>;
  51 def : Processor<"603e", G3Itineraries, []>;
  52 def : Processor<"603ev", G3Itineraries, []>;
  53 def : Processor<"604", G3Itineraries, []>;
  54 def : Processor<"604e", G3Itineraries, []>;
  55 def : Processor<"620", G3Itineraries, []>;
  56 def : Processor<"g3", G3Itineraries, []>;
  57 def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
  58 def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
  59 def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
  60 def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
  61 def : Processor<"750", G3Itineraries, []>;
  62 def : Processor<"970", G5Itineraries,
  63                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  64                    Feature64Bit /*, Feature64BitRegs */]>;
  65 def : Processor<"g5", G5Itineraries,
  66                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  67                    Feature64Bit /*, Feature64BitRegs */]>;
  68
  69
  70 def PPCInstrInfo : InstrInfo {
  71   // Define how we want to layout our TargetSpecific information field... This
  72   // should be kept up-to-date with the fields in the PPCInstrInfo.h file.
  73   let TSFlagsFields = ["PPC970_First",
  74                        "PPC970_Single",
  75                        "PPC970_Cracked",
  76                        "PPC970_Unit"];
  77   let TSFlagsShifts = [0, 1, 2, 3];
  78
  79   let isLittleEndianEncoding = 1;
  80 }
  81
  82
  83 def PPC : Target {
  84   // Information about the instructions.
  85   let InstructionSet = PPCInstrInfo;
  86 }