1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
60 "Enable the MFOCRF instruction">;
61 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
62 "Enable the fsqrt instruction">;
63 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
64 "Enable the fcpsgn instruction">;
65 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
66 "Enable the fre instruction">;
67 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
68 "Enable the fres instruction">;
69 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
70 "Enable the frsqrte instruction">;
71 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
72 "Enable the frsqrtes instruction">;
73 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
74 "Assume higher precision reciprocal estimates">;
75 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
76 "Enable the stfiwx instruction">;
77 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
78 "Enable the lfiwax instruction">;
79 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
80 "Enable the fri[mnpz] instructions">;
81 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
82 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
83 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
84 "Enable the isel instruction">;
85 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
86 "Enable the popcnt[dw] instructions">;
87 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
88 "Enable the ldbrx instruction">;
89 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
90 "Enable Book E instructions">;
91 def FeatureE500 : SubtargetFeature<"E500", "IsE500", "true",
92 "Enable E500/E500mc instructions">;
93 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
94 "Enable PPC 4xx instructions">;
95 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
96 "Enable QPX instructions">;
97 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
98 "Enable VSX instructions",
101 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
102 "Treat mftb as deprecated">;
103 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
104 "Treat vector data stream cache control instructions as deprecated">;
106 // Note: Future features to add when support is extended to more
107 // recent ISA levels:
109 // CMPB p6, p6x, p7 cmpb
110 // DFP p6, p6x, p7 decimal floating-point instructions
111 // POPCNTB p5 through p7 popcntb and related instructions
112 // VSX p7 vector-scalar instruction set
114 //===----------------------------------------------------------------------===//
116 //===----------------------------------------------------------------------===//
118 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
119 "Use the ELFv1 ABI">;
121 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
122 "Use the ELFv2 ABI">;
124 //===----------------------------------------------------------------------===//
125 // Classes used for relation maps.
126 //===----------------------------------------------------------------------===//
127 // RecFormRel - Filter class used to relate non-record-form instructions with
128 // their record-form variants.
131 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
132 // FMA instruction forms with their corresponding factor-killing forms.
137 //===----------------------------------------------------------------------===//
138 // Relation Map Definitions.
139 //===----------------------------------------------------------------------===//
141 def getRecordFormOpcode : InstrMapping {
142 let FilterClass = "RecFormRel";
143 // Instructions with the same BaseName and Interpretation64Bit values
145 let RowFields = ["BaseName", "Interpretation64Bit"];
146 // Instructions with the same RC value form a column.
147 let ColFields = ["RC"];
148 // The key column are the non-record-form instructions.
150 // Value columns RC=1
151 let ValueCols = [["1"]];
154 def getNonRecordFormOpcode : InstrMapping {
155 let FilterClass = "RecFormRel";
156 // Instructions with the same BaseName and Interpretation64Bit values
158 let RowFields = ["BaseName", "Interpretation64Bit"];
159 // Instructions with the same RC value form a column.
160 let ColFields = ["RC"];
161 // The key column are the record-form instructions.
163 // Value columns are RC=0
164 let ValueCols = [["0"]];
167 def getAltVSXFMAOpcode : InstrMapping {
168 let FilterClass = "AltVSXFMARel";
169 // Instructions with the same BaseName and Interpretation64Bit values
171 let RowFields = ["BaseName"];
172 // Instructions with the same RC value form a column.
173 let ColFields = ["IsVSXFMAAlt"];
174 // The key column are the (default) addend-killing instructions.
176 // Value columns IsVSXFMAAlt=1
177 let ValueCols = [["1"]];
180 //===----------------------------------------------------------------------===//
181 // Register File Description
182 //===----------------------------------------------------------------------===//
184 include "PPCRegisterInfo.td"
185 include "PPCSchedule.td"
186 include "PPCInstrInfo.td"
188 //===----------------------------------------------------------------------===//
189 // PowerPC processors supported.
192 def : Processor<"generic", G3Itineraries, [Directive32]>;
193 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
194 FeatureFRES, FeatureFRSQRTE,
195 FeatureBookE, DeprecatedMFTB]>;
196 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
197 FeatureFRES, FeatureFRSQRTE,
198 FeatureBookE, DeprecatedMFTB]>;
199 def : Processor<"601", G3Itineraries, [Directive601]>;
200 def : Processor<"602", G3Itineraries, [Directive602]>;
201 def : Processor<"603", G3Itineraries, [Directive603,
202 FeatureFRES, FeatureFRSQRTE]>;
203 def : Processor<"603e", G3Itineraries, [Directive603,
204 FeatureFRES, FeatureFRSQRTE]>;
205 def : Processor<"603ev", G3Itineraries, [Directive603,
206 FeatureFRES, FeatureFRSQRTE]>;
207 def : Processor<"604", G3Itineraries, [Directive604,
208 FeatureFRES, FeatureFRSQRTE]>;
209 def : Processor<"604e", G3Itineraries, [Directive604,
210 FeatureFRES, FeatureFRSQRTE]>;
211 def : Processor<"620", G3Itineraries, [Directive620,
212 FeatureFRES, FeatureFRSQRTE]>;
213 def : Processor<"750", G4Itineraries, [Directive750,
214 FeatureFRES, FeatureFRSQRTE]>;
215 def : Processor<"g3", G3Itineraries, [Directive750,
216 FeatureFRES, FeatureFRSQRTE]>;
217 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
218 FeatureFRES, FeatureFRSQRTE]>;
219 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
220 FeatureFRES, FeatureFRSQRTE]>;
221 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
222 FeatureFRES, FeatureFRSQRTE]>;
223 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
224 FeatureFRES, FeatureFRSQRTE]>;
225 def : ProcessorModel<"970", G5Model,
226 [Directive970, FeatureAltivec,
227 FeatureMFOCRF, FeatureFSqrt,
228 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
229 Feature64Bit /*, Feature64BitRegs */]>;
230 def : ProcessorModel<"g5", G5Model,
231 [Directive970, FeatureAltivec,
232 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
233 FeatureFRES, FeatureFRSQRTE,
234 Feature64Bit /*, Feature64BitRegs */,
235 DeprecatedMFTB, DeprecatedDST]>;
236 def : ProcessorModel<"e500mc", PPCE500mcModel,
237 [DirectiveE500mc, FeatureMFOCRF,
238 FeatureSTFIWX, FeatureBookE, FeatureISEL,
240 def : ProcessorModel<"e5500", PPCE5500Model,
241 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
242 FeatureSTFIWX, FeatureBookE, FeatureISEL,
244 def : ProcessorModel<"a2", PPCA2Model,
245 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
246 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
247 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
248 FeatureSTFIWX, FeatureLFIWAX,
249 FeatureFPRND, FeatureFPCVT, FeatureISEL,
250 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
251 /*, Feature64BitRegs */, DeprecatedMFTB]>;
252 def : ProcessorModel<"a2q", PPCA2Model,
253 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
254 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
255 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
256 FeatureSTFIWX, FeatureLFIWAX,
257 FeatureFPRND, FeatureFPCVT, FeatureISEL,
258 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
259 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
260 def : ProcessorModel<"pwr3", G5Model,
261 [DirectivePwr3, FeatureAltivec,
262 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
263 FeatureSTFIWX, Feature64Bit]>;
264 def : ProcessorModel<"pwr4", G5Model,
265 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
266 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
267 FeatureSTFIWX, Feature64Bit]>;
268 def : ProcessorModel<"pwr5", G5Model,
269 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
270 FeatureFSqrt, FeatureFRE, FeatureFRES,
271 FeatureFRSQRTE, FeatureFRSQRTES,
272 FeatureSTFIWX, Feature64Bit,
273 DeprecatedMFTB, DeprecatedDST]>;
274 def : ProcessorModel<"pwr5x", G5Model,
275 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
276 FeatureFSqrt, FeatureFRE, FeatureFRES,
277 FeatureFRSQRTE, FeatureFRSQRTES,
278 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
279 DeprecatedMFTB, DeprecatedDST]>;
280 def : ProcessorModel<"pwr6", G5Model,
281 [DirectivePwr6, FeatureAltivec,
282 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
283 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
284 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
285 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
286 DeprecatedMFTB, DeprecatedDST]>;
287 def : ProcessorModel<"pwr6x", G5Model,
288 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
289 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
290 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
291 FeatureSTFIWX, FeatureLFIWAX,
292 FeatureFPRND, Feature64Bit,
293 DeprecatedMFTB, DeprecatedDST]>;
294 def : ProcessorModel<"pwr7", P7Model,
295 [DirectivePwr7, FeatureAltivec,
296 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
297 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
298 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
299 FeatureFPRND, FeatureFPCVT, FeatureISEL,
300 FeaturePOPCNTD, FeatureLDBRX,
301 Feature64Bit /*, Feature64BitRegs */,
302 DeprecatedMFTB, DeprecatedDST]>;
303 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
304 [DirectivePwr8, FeatureAltivec,
305 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
306 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
307 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
308 FeatureFPRND, FeatureFPCVT, FeatureISEL,
309 FeaturePOPCNTD, FeatureLDBRX,
310 Feature64Bit /*, Feature64BitRegs */,
311 DeprecatedMFTB, DeprecatedDST]>;
312 def : Processor<"ppc", G3Itineraries, [Directive32]>;
313 def : ProcessorModel<"ppc64", G5Model,
314 [Directive64, FeatureAltivec,
315 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
316 FeatureFRSQRTE, FeatureSTFIWX,
317 Feature64Bit /*, Feature64BitRegs */]>;
318 def : ProcessorModel<"ppc64le", G5Model,
319 [Directive64, FeatureAltivec,
320 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
321 FeatureFRSQRTE, FeatureSTFIWX,
322 Feature64Bit /*, Feature64BitRegs */]>;
324 //===----------------------------------------------------------------------===//
325 // Calling Conventions
326 //===----------------------------------------------------------------------===//
328 include "PPCCallingConv.td"
330 def PPCInstrInfo : InstrInfo {
331 let isLittleEndianEncoding = 1;
333 // FIXME: Unset this when no longer needed!
334 let decodePositionallyEncodedOperands = 1;
336 let noNamedPositionallyEncodedOperands = 1;
339 def PPCAsmParser : AsmParser {
340 let ShouldEmitMatchRegisterName = 0;
343 def PPCAsmParserVariant : AsmParserVariant {
346 // We do not use hard coded registers in asm strings. However, some
347 // InstAlias definitions use immediate literals. Set RegisterPrefix
348 // so that those are not misinterpreted as registers.
349 string RegisterPrefix = "%";
353 // Information about the instructions.
354 let InstructionSet = PPCInstrInfo;
356 let AssemblyParsers = [PPCAsmParser];
357 let AssemblyParserVariants = [PPCAsmParserVariant];