lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  54                               "Enable 64-bit registers usage for ppc32 [beta]">;
  55 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  56                               "Use condition-register bits individually">;
  57 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  58                                         "Enable Altivec instructions">;
  59 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  60                                         "Enable SPE instructions">;
  61 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  62                                         "Enable the MFOCRF instruction">;
  63 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  64                                         "Enable the fsqrt instruction">;
  65 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  66                                         "Enable the fcpsgn instruction">;
  67 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  68                                         "Enable the fre instruction">;
  69 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  70                                         "Enable the fres instruction">;
  71 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  72                                         "Enable the frsqrte instruction">;
  73 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  74                                         "Enable the frsqrtes instruction">;
  75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  76                               "Assume higher precision reciprocal estimates">;
  77 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  78                                         "Enable the stfiwx instruction">;
  79 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  80                                         "Enable the lfiwax instruction">;
  81 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  82                                         "Enable the fri[mnpz] instructions">;
  83 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  84   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  85 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  86                                         "Enable the isel instruction">;
  87 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  88                                         "Enable the popcnt[dw] instructions">;
  89 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  90                                         "Enable the ldbrx instruction">;
  91 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  92                                         "Enable Book E instructions">;
  93 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
  94                               "Has only the msync instruction instead of sync",
  95                               [FeatureBookE]>;
  96 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
  97                                         "Enable E500/E500mc instructions">;
  98 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
  99                                         "Enable PPC 4xx instructions">;
 100 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 101                                         "Enable PPC 6xx instructions">;
 102 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 103                                         "Enable QPX instructions">;
 104 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 105                                         "Enable VSX instructions",
 106                                         [FeatureAltivec]>;
 107 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 108                                         "Enable POWER8 vector instructions",
 109                                         [FeatureVSX, FeatureAltivec]>;
 110
 111 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
 112                                         "Treat mftb as deprecated">;
 113 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 114   "Treat vector data stream cache control instructions as deprecated">;
 115
 116 // Note: Future features to add when support is extended to more
 117 // recent ISA levels:
 118 //
 119 // CMPB         p6, p6x, p7        cmpb
 120 // DFP          p6, p6x, p7        decimal floating-point instructions
 121 // POPCNTB      p5 through p7      popcntb and related instructions
 122
 123 //===----------------------------------------------------------------------===//
 124 // ABI Selection                                                              //
 125 //===----------------------------------------------------------------------===//
 126
 127 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
 128                                     "Use the ELFv1 ABI">;
 129
 130 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
 131                                     "Use the ELFv2 ABI">;
 132
 133 //===----------------------------------------------------------------------===//
 134 // Classes used for relation maps.
 135 //===----------------------------------------------------------------------===//
 136 // RecFormRel - Filter class used to relate non-record-form instructions with
 137 // their record-form variants.
 138 class RecFormRel;
 139
 140 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 141 // FMA instruction forms with their corresponding factor-killing forms.
 142 class AltVSXFMARel {
 143   bit IsVSXFMAAlt = 0;
 144 }
 145
 146 //===----------------------------------------------------------------------===//
 147 // Relation Map Definitions.
 148 //===----------------------------------------------------------------------===//
 149
 150 def getRecordFormOpcode : InstrMapping {
 151   let FilterClass = "RecFormRel";
 152   // Instructions with the same BaseName and Interpretation64Bit values
 153   // form a row.
 154   let RowFields = ["BaseName", "Interpretation64Bit"];
 155   // Instructions with the same RC value form a column.
 156   let ColFields = ["RC"];
 157   // The key column are the non-record-form instructions.
 158   let KeyCol = ["0"];
 159   // Value columns RC=1
 160   let ValueCols = [["1"]];
 161 }
 162
 163 def getNonRecordFormOpcode : InstrMapping {
 164   let FilterClass = "RecFormRel";
 165   // Instructions with the same BaseName and Interpretation64Bit values
 166   // form a row.
 167   let RowFields = ["BaseName", "Interpretation64Bit"];
 168   // Instructions with the same RC value form a column.
 169   let ColFields = ["RC"];
 170   // The key column are the record-form instructions.
 171   let KeyCol = ["1"];
 172   // Value columns are RC=0
 173   let ValueCols = [["0"]];
 174 }
 175
 176 def getAltVSXFMAOpcode : InstrMapping {
 177   let FilterClass = "AltVSXFMARel";
 178   // Instructions with the same BaseName and Interpretation64Bit values
 179   // form a row.
 180   let RowFields = ["BaseName"];
 181   // Instructions with the same RC value form a column.
 182   let ColFields = ["IsVSXFMAAlt"];
 183   // The key column are the (default) addend-killing instructions.
 184   let KeyCol = ["0"];
 185   // Value columns IsVSXFMAAlt=1
 186   let ValueCols = [["1"]];
 187 }
 188
 189 //===----------------------------------------------------------------------===//
 190 // Register File Description
 191 //===----------------------------------------------------------------------===//
 192
 193 include "PPCRegisterInfo.td"
 194 include "PPCSchedule.td"
 195 include "PPCInstrInfo.td"
 196
 197 //===----------------------------------------------------------------------===//
 198 // PowerPC processors supported.
 199 //
 200
 201 def : Processor<"generic", G3Itineraries, [Directive32]>;
 202 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 203                                           FeatureFRES, FeatureFRSQRTE,
 204                                           FeatureBookE, FeatureMSYNC,
 205                                           DeprecatedMFTB]>;
 206 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 207                                           FeatureFRES, FeatureFRSQRTE,
 208                                           FeatureBookE, FeatureMSYNC,
 209                                           DeprecatedMFTB]>;
 210 def : Processor<"601", G3Itineraries, [Directive601]>;
 211 def : Processor<"602", G3Itineraries, [Directive602]>;
 212 def : Processor<"603", G3Itineraries, [Directive603,
 213                                        FeatureFRES, FeatureFRSQRTE]>;
 214 def : Processor<"603e", G3Itineraries, [Directive603,
 215                                         FeatureFRES, FeatureFRSQRTE]>;
 216 def : Processor<"603ev", G3Itineraries, [Directive603,
 217                                          FeatureFRES, FeatureFRSQRTE]>;
 218 def : Processor<"604", G3Itineraries, [Directive604,
 219                                        FeatureFRES, FeatureFRSQRTE]>;
 220 def : Processor<"604e", G3Itineraries, [Directive604,
 221                                         FeatureFRES, FeatureFRSQRTE]>;
 222 def : Processor<"620", G3Itineraries, [Directive620,
 223                                        FeatureFRES, FeatureFRSQRTE]>;
 224 def : Processor<"750", G4Itineraries, [Directive750,
 225                                        FeatureFRES, FeatureFRSQRTE]>;
 226 def : Processor<"g3", G3Itineraries, [Directive750,
 227                                       FeatureFRES, FeatureFRSQRTE]>;
 228 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 229                                         FeatureFRES, FeatureFRSQRTE]>;
 230 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 231                                       FeatureFRES, FeatureFRSQRTE]>;
 232 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 233                                             FeatureFRES, FeatureFRSQRTE]>;
 234 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 235                                            FeatureFRES, FeatureFRSQRTE]>;
 236 def : ProcessorModel<"970", G5Model,
 237                   [Directive970, FeatureAltivec,
 238                    FeatureMFOCRF, FeatureFSqrt,
 239                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 240                    Feature64Bit /*, Feature64BitRegs */]>;
 241 def : ProcessorModel<"g5", G5Model,
 242                   [Directive970, FeatureAltivec,
 243                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 244                    FeatureFRES, FeatureFRSQRTE,
 245                    Feature64Bit /*, Feature64BitRegs */,
 246                    DeprecatedMFTB, DeprecatedDST]>;
 247 def : ProcessorModel<"e500mc", PPCE500mcModel,
 248                   [DirectiveE500mc, FeatureMFOCRF,
 249                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 250                    DeprecatedMFTB]>;
 251 def : ProcessorModel<"e5500", PPCE5500Model,
 252                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 253                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 254                    DeprecatedMFTB]>;
 255 def : ProcessorModel<"a2", PPCA2Model,
 256                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 257                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 258                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 259                    FeatureSTFIWX, FeatureLFIWAX,
 260                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 261                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 262                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 263 def : ProcessorModel<"a2q", PPCA2Model,
 264                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 265                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 266                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 267                    FeatureSTFIWX, FeatureLFIWAX,
 268                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 269                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 270                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 271 def : ProcessorModel<"pwr3", G5Model,
 272                   [DirectivePwr3, FeatureAltivec,
 273                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 274                    FeatureSTFIWX, Feature64Bit]>;
 275 def : ProcessorModel<"pwr4", G5Model,
 276                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 277                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 278                    FeatureSTFIWX, Feature64Bit]>;
 279 def : ProcessorModel<"pwr5", G5Model,
 280                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 281                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 282                    FeatureFRSQRTE, FeatureFRSQRTES,
 283                    FeatureSTFIWX, Feature64Bit,
 284                    DeprecatedMFTB, DeprecatedDST]>;
 285 def : ProcessorModel<"pwr5x", G5Model,
 286                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 287                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 288                    FeatureFRSQRTE, FeatureFRSQRTES,
 289                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 290                    DeprecatedMFTB, DeprecatedDST]>;
 291 def : ProcessorModel<"pwr6", G5Model,
 292                   [DirectivePwr6, FeatureAltivec,
 293                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 294                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 295                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 296                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 297                    DeprecatedMFTB, DeprecatedDST]>;
 298 def : ProcessorModel<"pwr6x", G5Model,
 299                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 300                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 301                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 302                    FeatureSTFIWX, FeatureLFIWAX,
 303                    FeatureFPRND, Feature64Bit,
 304                    DeprecatedMFTB, DeprecatedDST]>;
 305 def : ProcessorModel<"pwr7", P7Model,
 306                   [DirectivePwr7, FeatureAltivec, FeatureVSX,
 307                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 308                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 309                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 310                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 311                    FeaturePOPCNTD, FeatureLDBRX,
 312                    Feature64Bit /*, Feature64BitRegs */,
 313                    DeprecatedMFTB, DeprecatedDST]>;
 314 def : ProcessorModel<"pwr8", P8Model,
 315                   [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector,
 316                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 317                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 318                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 319                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 320                    FeaturePOPCNTD, FeatureLDBRX,
 321                    Feature64Bit /*, Feature64BitRegs */,
 322                    DeprecatedMFTB, DeprecatedDST]>;
 323 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 324 def : ProcessorModel<"ppc64", G5Model,
 325                   [Directive64, FeatureAltivec,
 326                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 327                    FeatureFRSQRTE, FeatureSTFIWX,
 328                    Feature64Bit /*, Feature64BitRegs */]>;
 329 def : ProcessorModel<"ppc64le", G5Model,
 330                   [Directive64, FeatureAltivec,
 331                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 332                    FeatureFRSQRTE, FeatureSTFIWX,
 333                    Feature64Bit /*, Feature64BitRegs */]>;
 334
 335 //===----------------------------------------------------------------------===//
 336 // Calling Conventions
 337 //===----------------------------------------------------------------------===//
 338
 339 include "PPCCallingConv.td"
 340
 341 def PPCInstrInfo : InstrInfo {
 342   let isLittleEndianEncoding = 1;
 343
 344   // FIXME: Unset this when no longer needed!
 345   let decodePositionallyEncodedOperands = 1;
 346
 347   let noNamedPositionallyEncodedOperands = 1;
 348 }
 349
 350 def PPCAsmParser : AsmParser {
 351   let ShouldEmitMatchRegisterName = 0;
 352 }
 353
 354 def PPCAsmParserVariant : AsmParserVariant {
 355   int Variant = 0;
 356
 357   // We do not use hard coded registers in asm strings.  However, some
 358   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 359   // so that those are not misinterpreted as registers.
 360   string RegisterPrefix = "%";
 361 }
 362
 363 def PPC : Target {
 364   // Information about the instructions.
 365   let InstructionSet = PPCInstrInfo;
 366
 367   let AssemblyParsers = [PPCAsmParser];
 368   let AssemblyParserVariants = [PPCAsmParserVariant];
 369 }