lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  39 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  40
  41 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  42                                         "Enable 64-bit instructions">;
  43 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  44                               "Enable 64-bit registers usage for ppc32 [beta]">;
  45 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  46                                         "Enable Altivec instructions">;
  47 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  48                                         "Enable the MFOCRF instruction">;
  49 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  50                                         "Enable the fsqrt instruction">;
  51 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  52                                         "Enable the stfiwx instruction">;
  53 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  54                                         "Enable the isel instruction">;
  55 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  56                                         "Enable Book E instructions">;
  57
  58 //===----------------------------------------------------------------------===//
  59 // Register File Description
  60 //===----------------------------------------------------------------------===//
  61
  62 include "PPCRegisterInfo.td"
  63 include "PPCSchedule.td"
  64 include "PPCInstrInfo.td"
  65
  66 //===----------------------------------------------------------------------===//
  67 // PowerPC processors supported.
  68 //
  69
  70 def : Processor<"generic", G3Itineraries, [Directive32]>;
  71 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
  72                                            FeatureBookE]>;
  73 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
  74                                            FeatureBookE]>;
  75 def : Processor<"601", G3Itineraries, [Directive601]>;
  76 def : Processor<"602", G3Itineraries, [Directive602]>;
  77 def : Processor<"603", G3Itineraries, [Directive603]>;
  78 def : Processor<"603e", G3Itineraries, [Directive603]>;
  79 def : Processor<"603ev", G3Itineraries, [Directive603]>;
  80 def : Processor<"604", G3Itineraries, [Directive604]>;
  81 def : Processor<"604e", G3Itineraries, [Directive604]>;
  82 def : Processor<"620", G3Itineraries, [Directive620]>;
  83 def : Processor<"750", G4Itineraries, [Directive750]>;
  84 def : Processor<"g3", G3Itineraries, [Directive750]>;
  85 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
  86 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
  87 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  88 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  89 def : Processor<"970", G5Itineraries,
  90                   [Directive970, FeatureAltivec,
  91                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
  92                    Feature64Bit /*, Feature64BitRegs */]>;
  93 def : Processor<"g5", G5Itineraries,
  94                   [Directive970, FeatureAltivec,
  95                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
  96                    Feature64Bit /*, Feature64BitRegs */]>;
  97 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
  98                                          FeatureMFOCRF, FeatureFSqrt,
  99                                          FeatureSTFIWX, FeatureISEL,
 100                                          Feature64Bit
 101                                      /*, Feature64BitRegs */]>;
 102 def : Processor<"pwr6", G5Itineraries,
 103                   [DirectivePwr6, FeatureAltivec,
 104                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 105                    Feature64Bit /*, Feature64BitRegs */]>;
 106 def : Processor<"pwr7", G5Itineraries,
 107                   [DirectivePwr7, FeatureAltivec,
 108                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 109                    FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;
 110 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 111 def : Processor<"ppc64", G5Itineraries,
 112                   [Directive64, FeatureAltivec,
 113                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 114                    Feature64Bit /*, Feature64BitRegs */]>;
 115
 116
 117 //===----------------------------------------------------------------------===//
 118 // Calling Conventions
 119 //===----------------------------------------------------------------------===//
 120
 121 include "PPCCallingConv.td"
 122
 123 def PPCInstrInfo : InstrInfo {
 124   let isLittleEndianEncoding = 1;
 125 }
 126
 127 def PPCAsmWriter : AsmWriter {
 128   string AsmWriterClassName  = "InstPrinter";
 129   bit isMCAsmWriter = 1;
 130 }
 131
 132 def PPC : Target {
 133   // Information about the instructions.
 134   let InstructionSet = PPCInstrInfo;
 135
 136   let AssemblyWriters = [PPCAsmWriter];
 137 }