lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49
  50 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  51                                         "Enable 64-bit instructions">;
  52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  53                               "Enable 64-bit registers usage for ppc32 [beta]">;
  54 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  55                                         "Enable Altivec instructions">;
  56 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  57                                         "Enable the MFOCRF instruction">;
  58 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  59                                         "Enable the fsqrt instruction">;
  60 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  61                                         "Enable the stfiwx instruction">;
  62 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  63                                         "Enable the lfiwax instruction">;
  64 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  65                                         "Enable the fri[mnpz] instructions">;
  66 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  67   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  68 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  69                                         "Enable the isel instruction">;
  70 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  71                                         "Enable the popcnt[dw] instructions">;
  72 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  73                                         "Enable the ldbrx instruction">;
  74 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  75                                         "Enable Book E instructions">;
  76 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
  77                                         "Enable QPX instructions">;
  78
  79 // Note: Future features to add when support is extended to more
  80 // recent ISA levels:
  81 //
  82 // CMPB         p6, p6x, p7        cmpb
  83 // DFP          p6, p6x, p7        decimal floating-point instructions
  84 // FRE          p5 through p7      fre (vs. fres, available since p3)
  85 // FRSQRTES     p5 through p7      frsqrtes (vs. frsqrte, available since p3)
  86 // POPCNTB      p5 through p7      popcntb and related instructions
  87 // RECIP_PREC   p6, p6x, p7        higher precision reciprocal estimates
  88 // VSX          p7                 vector-scalar instruction set
  89
  90 //===----------------------------------------------------------------------===//
  91 // Register File Description
  92 //===----------------------------------------------------------------------===//
  93
  94 include "PPCRegisterInfo.td"
  95 include "PPCSchedule.td"
  96 include "PPCInstrInfo.td"
  97
  98 //===----------------------------------------------------------------------===//
  99 // PowerPC processors supported.
 100 //
 101
 102 def : Processor<"generic", G3Itineraries, [Directive32]>;
 103 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
 104                                            FeatureBookE]>;
 105 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
 106                                            FeatureBookE]>;
 107 def : Processor<"601", G3Itineraries, [Directive601]>;
 108 def : Processor<"602", G3Itineraries, [Directive602]>;
 109 def : Processor<"603", G3Itineraries, [Directive603]>;
 110 def : Processor<"603e", G3Itineraries, [Directive603]>;
 111 def : Processor<"603ev", G3Itineraries, [Directive603]>;
 112 def : Processor<"604", G3Itineraries, [Directive604]>;
 113 def : Processor<"604e", G3Itineraries, [Directive604]>;
 114 def : Processor<"620", G3Itineraries, [Directive620]>;
 115 def : Processor<"750", G4Itineraries, [Directive750]>;
 116 def : Processor<"g3", G3Itineraries, [Directive750]>;
 117 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
 118 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
 119 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
 120 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
 121 def : Processor<"970", G5Itineraries,
 122                   [Directive970, FeatureAltivec,
 123                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 124                    Feature64Bit /*, Feature64BitRegs */]>;
 125 def : Processor<"g5", G5Itineraries,
 126                   [Directive970, FeatureAltivec,
 127                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 128                    Feature64Bit /*, Feature64BitRegs */]>;
 129 def : ProcessorModel<"e500mc", PPCE500mcModel,
 130                   [DirectiveE500mc, FeatureMFOCRF,
 131                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 132 def : ProcessorModel<"e5500", PPCE5500Model,
 133                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 134                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 135 def : Processor<"a2", PPCA2Itineraries,
 136                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 137                    FeatureFSqrt, FeatureSTFIWX, FeatureLFIWAX,
 138                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 139                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 140                /*, Feature64BitRegs */]>;
 141 def : Processor<"a2q", PPCA2Itineraries,
 142                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 143                    FeatureFSqrt, FeatureSTFIWX, FeatureLFIWAX,
 144                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 145                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 146                /*, Feature64BitRegs */, FeatureQPX]>;
 147 def : Processor<"pwr3", G5Itineraries,
 148                   [DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
 149                    FeatureSTFIWX, Feature64Bit]>;
 150 def : Processor<"pwr4", G5Itineraries,
 151                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 152                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 153 def : Processor<"pwr5", G5Itineraries,
 154                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 155                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 156 def : Processor<"pwr5x", G5Itineraries,
 157                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 158                    FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
 159                    Feature64Bit]>;
 160 def : Processor<"pwr6", G5Itineraries,
 161                   [DirectivePwr6, FeatureAltivec,
 162                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 163                    FeatureLFIWAX, FeatureFPRND, Feature64Bit
 164                /*, Feature64BitRegs */]>;
 165 def : Processor<"pwr6x", G5Itineraries,
 166                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 167                    FeatureFSqrt, FeatureSTFIWX, FeatureLFIWAX,
 168                    FeatureFPRND, Feature64Bit]>;
 169 def : Processor<"pwr7", G5Itineraries,
 170                   [DirectivePwr7, FeatureAltivec,
 171                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 172                    FeatureLFIWAX, FeatureFPRND, FeatureFPCVT,
 173                    FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
 174                    Feature64Bit /*, Feature64BitRegs */]>;
 175 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 176 def : Processor<"ppc64", G5Itineraries,
 177                   [Directive64, FeatureAltivec,
 178                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 179                    Feature64Bit /*, Feature64BitRegs */]>;
 180
 181
 182 //===----------------------------------------------------------------------===//
 183 // Calling Conventions
 184 //===----------------------------------------------------------------------===//
 185
 186 include "PPCCallingConv.td"
 187
 188 def PPCInstrInfo : InstrInfo {
 189   let isLittleEndianEncoding = 1;
 190 }
 191
 192 def PPCAsmWriter : AsmWriter {
 193   string AsmWriterClassName  = "InstPrinter";
 194   bit isMCAsmWriter = 1;
 195 }
 196
 197 def PPC : Target {
 198   // Information about the instructions.
 199   let InstructionSet = PPCInstrInfo;
 200
 201   let AssemblyWriters = [PPCAsmWriter];
 202 }