1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "PPCInstPrinter.h"
16 #include "MCTargetDesc/PPCMCTargetDesc.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/raw_ostream.h"
24 #include "PPCGenAsmWriter.inc"
26 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
27 OS << getRegisterName(RegNo);
30 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
32 // Check for slwi/srwi mnemonics.
33 if (MI->getOpcode() == PPC::RLWINM) {
34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
37 bool useSubstituteMnemonic = false;
38 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
39 O << "\tslwi "; useSubstituteMnemonic = true;
41 if (SH <= 31 && MB == (32-SH) && ME == 31) {
42 O << "\tsrwi "; useSubstituteMnemonic = true;
45 if (useSubstituteMnemonic) {
46 printOperand(MI, 0, O);
48 printOperand(MI, 1, O);
49 O << ", " << (unsigned int)SH;
51 printAnnotation(O, Annot);
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
59 printOperand(MI, 0, O);
61 printOperand(MI, 1, O);
62 printAnnotation(O, Annot);
66 if (MI->getOpcode() == PPC::RLDICR) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
69 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
72 printOperand(MI, 0, O);
74 printOperand(MI, 1, O);
75 O << ", " << (unsigned int)SH;
76 printAnnotation(O, Annot);
81 printInstruction(MI, O);
82 printAnnotation(O, Annot);
86 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
88 const char *Modifier) {
89 unsigned Code = MI->getOperand(OpNo).getImm();
91 if (StringRef(Modifier) == "cc") {
92 switch ((PPC::Predicate)Code) {
93 case PPC::PRED_LT_MINUS:
94 case PPC::PRED_LT_PLUS:
98 case PPC::PRED_LE_MINUS:
99 case PPC::PRED_LE_PLUS:
103 case PPC::PRED_EQ_MINUS:
104 case PPC::PRED_EQ_PLUS:
108 case PPC::PRED_GE_MINUS:
109 case PPC::PRED_GE_PLUS:
113 case PPC::PRED_GT_MINUS:
114 case PPC::PRED_GT_PLUS:
118 case PPC::PRED_NE_MINUS:
119 case PPC::PRED_NE_PLUS:
123 case PPC::PRED_UN_MINUS:
124 case PPC::PRED_UN_PLUS:
128 case PPC::PRED_NU_MINUS:
129 case PPC::PRED_NU_PLUS:
134 llvm_unreachable("Invalid predicate code");
137 if (StringRef(Modifier) == "pm") {
138 switch ((PPC::Predicate)Code) {
148 case PPC::PRED_LT_MINUS:
149 case PPC::PRED_LE_MINUS:
150 case PPC::PRED_EQ_MINUS:
151 case PPC::PRED_GE_MINUS:
152 case PPC::PRED_GT_MINUS:
153 case PPC::PRED_NE_MINUS:
154 case PPC::PRED_UN_MINUS:
155 case PPC::PRED_NU_MINUS:
158 case PPC::PRED_LT_PLUS:
159 case PPC::PRED_LE_PLUS:
160 case PPC::PRED_EQ_PLUS:
161 case PPC::PRED_GE_PLUS:
162 case PPC::PRED_GT_PLUS:
163 case PPC::PRED_NE_PLUS:
164 case PPC::PRED_UN_PLUS:
165 case PPC::PRED_NU_PLUS:
169 llvm_unreachable("Invalid predicate code");
172 assert(StringRef(Modifier) == "reg" &&
173 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
174 printOperand(MI, OpNo+1, O);
177 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
179 int Value = MI->getOperand(OpNo).getImm();
180 Value = SignExtend32<5>(Value);
184 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
186 unsigned int Value = MI->getOperand(OpNo).getImm();
187 assert(Value <= 31 && "Invalid u5imm argument!");
188 O << (unsigned int)Value;
191 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
193 unsigned int Value = MI->getOperand(OpNo).getImm();
194 assert(Value <= 63 && "Invalid u6imm argument!");
195 O << (unsigned int)Value;
198 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
200 if (MI->getOperand(OpNo).isImm())
201 O << (short)MI->getOperand(OpNo).getImm();
203 printOperand(MI, OpNo, O);
206 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
208 O << (unsigned short)MI->getOperand(OpNo).getImm();
211 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
213 if (!MI->getOperand(OpNo).isImm())
214 return printOperand(MI, OpNo, O);
216 // Branches can take an immediate operand. This is used by the branch
217 // selection pass to print .+8, an eight byte displacement from the PC.
219 printAbsBranchOperand(MI, OpNo, O);
222 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
224 if (!MI->getOperand(OpNo).isImm())
225 return printOperand(MI, OpNo, O);
227 O << (int)MI->getOperand(OpNo).getImm()*4;
231 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
233 unsigned CCReg = MI->getOperand(OpNo).getReg();
236 default: llvm_unreachable("Unknown CR register");
237 case PPC::CR0: RegNo = 0; break;
238 case PPC::CR1: RegNo = 1; break;
239 case PPC::CR2: RegNo = 2; break;
240 case PPC::CR3: RegNo = 3; break;
241 case PPC::CR4: RegNo = 4; break;
242 case PPC::CR5: RegNo = 5; break;
243 case PPC::CR6: RegNo = 6; break;
244 case PPC::CR7: RegNo = 7; break;
246 O << (0x80 >> RegNo);
249 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
251 printS16ImmOperand(MI, OpNo, O);
253 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
256 printOperand(MI, OpNo+1, O);
260 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
262 // When used as the base register, r0 reads constant zero rather than
263 // the value contained in the register. For this reason, the darwin
264 // assembler requires that we print r0 as 0 (no r) when used as the base.
265 if (MI->getOperand(OpNo).getReg() == PPC::R0)
268 printOperand(MI, OpNo, O);
270 printOperand(MI, OpNo+1, O);
275 /// stripRegisterPrefix - This method strips the character prefix from a
276 /// register name so that only the number is left. Used by for linux asm.
277 static const char *stripRegisterPrefix(const char *RegName) {
278 switch (RegName[0]) {
281 case 'v': return RegName + 1;
282 case 'c': if (RegName[1] == 'r') return RegName + 2;
288 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
290 const MCOperand &Op = MI->getOperand(OpNo);
292 const char *RegName = getRegisterName(Op.getReg());
293 // The linux and AIX assembler does not take register prefixes.
294 if (!isDarwinSyntax())
295 RegName = stripRegisterPrefix(RegName);
306 assert(Op.isExpr() && "unknown operand kind in printOperand");