1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "PPCInstPrinter.h"
16 #include "MCTargetDesc/PPCBaseInfo.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/raw_ostream.h"
24 #include "PPCGenAsmWriter.inc"
26 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
27 OS << getRegisterName(RegNo);
30 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
32 // Check for slwi/srwi mnemonics.
33 if (MI->getOpcode() == PPC::RLWINM) {
34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
37 bool useSubstituteMnemonic = false;
38 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
39 O << "\tslwi "; useSubstituteMnemonic = true;
41 if (SH <= 31 && MB == (32-SH) && ME == 31) {
42 O << "\tsrwi "; useSubstituteMnemonic = true;
45 if (useSubstituteMnemonic) {
46 printOperand(MI, 0, O);
48 printOperand(MI, 1, O);
49 O << ", " << (unsigned int)SH;
51 printAnnotation(O, Annot);
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
59 printOperand(MI, 0, O);
61 printOperand(MI, 1, O);
62 printAnnotation(O, Annot);
66 if (MI->getOpcode() == PPC::RLDICR) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
69 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
72 printOperand(MI, 0, O);
74 printOperand(MI, 1, O);
75 O << ", " << (unsigned int)SH;
76 printAnnotation(O, Annot);
81 printInstruction(MI, O);
82 printAnnotation(O, Annot);
86 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
88 const char *Modifier) {
89 unsigned Code = MI->getOperand(OpNo).getImm();
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg();
94 default: llvm_unreachable("Unknown CR register");
95 case PPC::CR0: RegNo = 0; break;
96 case PPC::CR1: RegNo = 1; break;
97 case PPC::CR2: RegNo = 2; break;
98 case PPC::CR3: RegNo = 3; break;
99 case PPC::CR4: RegNo = 4; break;
100 case PPC::CR5: RegNo = 5; break;
101 case PPC::CR6: RegNo = 6; break;
102 case PPC::CR7: RegNo = 7; break;
105 // Print the CR bit number. The Code is ((BI << 5) | BO) for a
106 // BCC, but we must have the positive form here (BO == 12)
107 unsigned BI = Code >> 5;
108 assert((Code & 0xF) == 12 &&
109 "BO in predicate bit must have the positive form");
111 unsigned Value = 4*RegNo + BI;
116 if (StringRef(Modifier) == "cc") {
117 switch ((PPC::Predicate)Code) {
118 case PPC::PRED_LT: O << "lt"; return;
119 case PPC::PRED_LE: O << "le"; return;
120 case PPC::PRED_EQ: O << "eq"; return;
121 case PPC::PRED_GE: O << "ge"; return;
122 case PPC::PRED_GT: O << "gt"; return;
123 case PPC::PRED_NE: O << "ne"; return;
124 case PPC::PRED_UN: O << "un"; return;
125 case PPC::PRED_NU: O << "nu"; return;
129 assert(StringRef(Modifier) == "reg" &&
130 "Need to specify 'cc' or 'reg' as predicate op modifier!");
131 printOperand(MI, OpNo+1, O);
134 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
136 int Value = MI->getOperand(OpNo).getImm();
137 Value = SignExtend32<5>(Value);
141 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
143 unsigned int Value = MI->getOperand(OpNo).getImm();
144 assert(Value <= 31 && "Invalid u5imm argument!");
145 O << (unsigned int)Value;
148 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
150 unsigned int Value = MI->getOperand(OpNo).getImm();
151 assert(Value <= 63 && "Invalid u6imm argument!");
152 O << (unsigned int)Value;
155 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
157 O << (short)MI->getOperand(OpNo).getImm();
160 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
162 O << (unsigned short)MI->getOperand(OpNo).getImm();
165 void PPCInstPrinter::printS16X4ImmOperand(const MCInst *MI, unsigned OpNo,
167 if (MI->getOperand(OpNo).isImm())
168 O << (short)(MI->getOperand(OpNo).getImm()*4);
170 printOperand(MI, OpNo, O);
173 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
175 if (!MI->getOperand(OpNo).isImm())
176 return printOperand(MI, OpNo, O);
178 // Branches can take an immediate operand. This is used by the branch
179 // selection pass to print $+8, an eight byte displacement from the PC.
181 printAbsAddrOperand(MI, OpNo, O);
184 void PPCInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
186 O << (int)MI->getOperand(OpNo).getImm()*4;
190 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
192 unsigned CCReg = MI->getOperand(OpNo).getReg();
195 default: llvm_unreachable("Unknown CR register");
196 case PPC::CR0: RegNo = 0; break;
197 case PPC::CR1: RegNo = 1; break;
198 case PPC::CR2: RegNo = 2; break;
199 case PPC::CR3: RegNo = 3; break;
200 case PPC::CR4: RegNo = 4; break;
201 case PPC::CR5: RegNo = 5; break;
202 case PPC::CR6: RegNo = 6; break;
203 case PPC::CR7: RegNo = 7; break;
205 O << (0x80 >> RegNo);
208 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
210 printSymbolLo(MI, OpNo, O);
212 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
215 printOperand(MI, OpNo+1, O);
219 void PPCInstPrinter::printMemRegImmShifted(const MCInst *MI, unsigned OpNo,
221 if (MI->getOperand(OpNo).isImm())
222 printS16X4ImmOperand(MI, OpNo, O);
224 printSymbolLo(MI, OpNo, O);
227 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
230 printOperand(MI, OpNo+1, O);
235 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
237 // When used as the base register, r0 reads constant zero rather than
238 // the value contained in the register. For this reason, the darwin
239 // assembler requires that we print r0 as 0 (no r) when used as the base.
240 if (MI->getOperand(OpNo).getReg() == PPC::R0)
243 printOperand(MI, OpNo, O);
245 printOperand(MI, OpNo+1, O);
250 /// stripRegisterPrefix - This method strips the character prefix from a
251 /// register name so that only the number is left. Used by for linux asm.
252 static const char *stripRegisterPrefix(const char *RegName) {
253 switch (RegName[0]) {
256 case 'v': return RegName + 1;
257 case 'c': if (RegName[1] == 'r') return RegName + 2;
263 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
265 const MCOperand &Op = MI->getOperand(OpNo);
267 const char *RegName = getRegisterName(Op.getReg());
268 // The linux and AIX assembler does not take register prefixes.
269 if (!isDarwinSyntax())
270 RegName = stripRegisterPrefix(RegName);
281 assert(Op.isExpr() && "unknown operand kind in printOperand");
285 void PPCInstPrinter::printSymbolLo(const MCInst *MI, unsigned OpNo,
287 if (MI->getOperand(OpNo).isImm())
288 return printS16ImmOperand(MI, OpNo, O);
290 // FIXME: This is a terrible hack because we can't encode lo16() as an operand
291 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower.
292 if (MI->getOperand(OpNo).isExpr() &&
293 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) {
295 printOperand(MI, OpNo, O);
298 printOperand(MI, OpNo, O);
302 void PPCInstPrinter::printSymbolHi(const MCInst *MI, unsigned OpNo,
304 if (MI->getOperand(OpNo).isImm())
305 return printS16ImmOperand(MI, OpNo, O);
307 // FIXME: This is a terrible hack because we can't encode lo16() as an operand
308 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower.
309 if (MI->getOperand(OpNo).isExpr() &&
310 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) {
312 printOperand(MI, OpNo, O);
315 printOperand(MI, OpNo, O);