1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCDisassembler.h"
12 #include "llvm/MC/MCFixedLenDisassembler.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/Support/MemoryObject.h"
16 #include "llvm/Support/TargetRegistry.h"
20 #define DEBUG_TYPE "ppc-disassembler"
22 typedef MCDisassembler::DecodeStatus DecodeStatus;
25 class PPCDisassembler : public MCDisassembler {
27 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
28 : MCDisassembler(STI, Ctx) {}
29 virtual ~PPCDisassembler() {}
31 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
32 const MemoryObject &Region, uint64_t Address,
34 raw_ostream &CStream) const override;
36 } // end anonymous namespace
38 static MCDisassembler *createPPCDisassembler(const Target &T,
39 const MCSubtargetInfo &STI,
41 return new PPCDisassembler(STI, Ctx);
44 extern "C" void LLVMInitializePowerPCDisassembler() {
45 // Register the disassembler for each target.
46 TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
47 createPPCDisassembler);
48 TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
49 createPPCDisassembler);
50 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
51 createPPCDisassembler);
54 // FIXME: These can be generated by TableGen from the existing register
57 static const unsigned CRRegs[] = {
58 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
59 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
62 static const unsigned CRBITRegs[] = {
63 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
64 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
65 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
66 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
67 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
68 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
69 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
70 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
73 static const unsigned FRegs[] = {
74 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
75 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
76 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
77 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
78 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
79 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
80 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
81 PPC::F28, PPC::F29, PPC::F30, PPC::F31
84 static const unsigned VRegs[] = {
85 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
86 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
87 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
88 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
89 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
90 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
91 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
92 PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 static const unsigned VSRegs[] = {
96 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
97 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
98 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
99 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
100 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
101 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
102 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
103 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
105 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
106 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
107 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
108 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
109 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
110 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
111 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
112 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
115 static const unsigned VSFRegs[] = {
116 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
117 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
118 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
119 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
120 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
121 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
122 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
123 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
125 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
126 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
127 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
128 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
129 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
130 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
131 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
132 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 static const unsigned GPRegs[] = {
136 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
137 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
138 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
139 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
140 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
141 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
142 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
143 PPC::R28, PPC::R29, PPC::R30, PPC::R31
146 static const unsigned GP0Regs[] = {
147 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
148 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
149 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
150 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
151 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
152 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
153 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
154 PPC::R28, PPC::R29, PPC::R30, PPC::R31
157 static const unsigned G8Regs[] = {
158 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
159 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
160 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
161 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
162 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
163 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
164 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
165 PPC::X28, PPC::X29, PPC::X30, PPC::X31
168 template <std::size_t N>
169 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
170 const unsigned (&Regs)[N]) {
171 assert(RegNo < N && "Invalid register number");
172 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
173 return MCDisassembler::Success;
176 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
178 const void *Decoder) {
179 return decodeRegisterClass(Inst, RegNo, CRRegs);
182 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
184 const void *Decoder) {
185 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
188 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
190 const void *Decoder) {
191 return decodeRegisterClass(Inst, RegNo, FRegs);
194 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
196 const void *Decoder) {
197 return decodeRegisterClass(Inst, RegNo, FRegs);
200 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
202 const void *Decoder) {
203 return decodeRegisterClass(Inst, RegNo, VRegs);
206 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
208 const void *Decoder) {
209 return decodeRegisterClass(Inst, RegNo, VSRegs);
212 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
214 const void *Decoder) {
215 return decodeRegisterClass(Inst, RegNo, VSFRegs);
218 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
220 const void *Decoder) {
221 return decodeRegisterClass(Inst, RegNo, GPRegs);
224 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
226 const void *Decoder) {
227 return decodeRegisterClass(Inst, RegNo, GP0Regs);
230 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
232 const void *Decoder) {
233 return decodeRegisterClass(Inst, RegNo, G8Regs);
236 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
237 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
240 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
241 int64_t Address, const void *Decoder) {
242 assert(isUInt<N>(Imm) && "Invalid immediate");
243 Inst.addOperand(MCOperand::CreateImm(Imm));
244 return MCDisassembler::Success;
248 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
249 int64_t Address, const void *Decoder) {
250 assert(isUInt<N>(Imm) && "Invalid immediate");
251 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
252 return MCDisassembler::Success;
255 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
256 int64_t Address, const void *Decoder) {
257 // Decode the memri field (imm, reg), which has the low 16-bits as the
258 // displacement and the next 5 bits as the register #.
260 uint64_t Base = Imm >> 16;
261 uint64_t Disp = Imm & 0xFFFF;
263 assert(Base < 32 && "Invalid base register");
265 switch (Inst.getOpcode()) {
273 // Add the tied output operand.
274 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
281 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
285 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
286 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
287 return MCDisassembler::Success;
290 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
291 int64_t Address, const void *Decoder) {
292 // Decode the memrix field (imm, reg), which has the low 14-bits as the
293 // displacement and the next 5 bits as the register #.
295 uint64_t Base = Imm >> 14;
296 uint64_t Disp = Imm & 0x3FFF;
298 assert(Base < 32 && "Invalid base register");
300 if (Inst.getOpcode() == PPC::LDU)
301 // Add the tied output operand.
302 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
303 else if (Inst.getOpcode() == PPC::STDU)
304 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
306 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
307 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
308 return MCDisassembler::Success;
311 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
312 int64_t Address, const void *Decoder) {
313 // The cr bit encoding is 0x80 >> cr_reg_num.
315 unsigned Zeros = countTrailingZeros(Imm);
316 assert(Zeros < 8 && "Invalid CR bit value");
318 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
319 return MCDisassembler::Success;
322 #include "PPCGenDisassemblerTables.inc"
324 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
325 const MemoryObject &Region,
326 uint64_t Address, raw_ostream &OS,
327 raw_ostream &CS) const {
328 // Get the four bytes of the instruction.
331 if (Region.readBytes(Address, Size, Bytes) == -1) {
333 return MCDisassembler::Fail;
336 // The instruction is big-endian encoded.
338 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
340 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);