1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
33 static unsigned RRegs[32] = {
34 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
35 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
36 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
37 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41 PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 static unsigned RRegsNoR0[32] = {
45 PPC::R1, PPC::R2, PPC::R3,
46 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
47 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
48 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52 PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 static unsigned XRegs[32] = {
55 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
56 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
57 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
58 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62 PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 static unsigned XRegsNoX0[32] = {
66 PPC::X1, PPC::X2, PPC::X3,
67 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
68 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
69 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73 PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 static unsigned FRegs[32] = {
76 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
77 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
78 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
79 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83 PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 static unsigned VRegs[32] = {
86 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
87 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
88 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
89 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93 PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 static unsigned CRBITRegs[32] = {
96 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
105 static unsigned CRRegs[8] = {
106 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
110 // Evaluate an expression containing condition register
111 // or condition register field symbols. Returns positive
112 // value on success, or -1 on error.
114 EvaluateCRExpr(const MCExpr *E) {
115 switch (E->getKind()) {
119 case MCExpr::Constant: {
120 int64_t Res = cast<MCConstantExpr>(E)->getValue();
121 return Res < 0 ? -1 : Res;
124 case MCExpr::SymbolRef: {
125 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126 StringRef Name = SRE->getSymbol().getName();
128 if (Name == "lt") return 0;
129 if (Name == "gt") return 1;
130 if (Name == "eq") return 2;
131 if (Name == "so") return 3;
132 if (Name == "un") return 3;
134 if (Name == "cr0") return 0;
135 if (Name == "cr1") return 1;
136 if (Name == "cr2") return 2;
137 if (Name == "cr3") return 3;
138 if (Name == "cr4") return 4;
139 if (Name == "cr5") return 5;
140 if (Name == "cr6") return 6;
141 if (Name == "cr7") return 7;
149 case MCExpr::Binary: {
150 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
155 if (LHSVal < 0 || RHSVal < 0)
158 switch (BE->getOpcode()) {
160 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
164 return Res < 0 ? -1 : Res;
168 llvm_unreachable("Invalid expression kind!");
173 class PPCAsmParser : public MCTargetAsmParser {
174 MCSubtargetInfo &STI;
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
184 bool isPPC64() const { return IsPPC64; }
186 bool MatchRegisterName(const AsmToken &Tok,
187 unsigned &RegNo, int64_t &IntVal);
189 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
191 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192 PPCMCExpr::VariantKind &Variant);
193 bool ParseExpression(const MCExpr *&EVal);
195 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
197 bool ParseDirectiveWord(unsigned Size, SMLoc L);
198 bool ParseDirectiveTC(unsigned Size, SMLoc L);
200 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
201 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
202 MCStreamer &Out, unsigned &ErrorInfo,
203 bool MatchingInlineAsm);
205 void ProcessInstruction(MCInst &Inst,
206 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
208 /// @name Auto-generated Match Functions
211 #define GET_ASSEMBLER_HEADER
212 #include "PPCGenAsmMatcher.inc"
218 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
219 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
220 // Check for 64-bit vs. 32-bit pointer mode.
221 Triple TheTriple(STI.getTargetTriple());
222 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
223 // Initialize the set of available features.
224 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
227 virtual bool ParseInstruction(ParseInstructionInfo &Info,
228 StringRef Name, SMLoc NameLoc,
229 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 virtual bool ParseDirective(AsmToken DirectiveID);
234 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
236 struct PPCOperand : public MCParsedAsmOperand {
244 SMLoc StartLoc, EndLoc;
258 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
262 const MCSymbolRefExpr *Sym;
269 struct TLSRegOp TLSReg;
272 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
274 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
276 StartLoc = o.StartLoc;
295 /// getStartLoc - Get the location of the first token of this operand.
296 SMLoc getStartLoc() const { return StartLoc; }
298 /// getEndLoc - Get the location of the last token of this operand.
299 SMLoc getEndLoc() const { return EndLoc; }
301 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
302 bool isPPC64() const { return IsPPC64; }
304 int64_t getImm() const {
305 assert(Kind == Immediate && "Invalid access!");
309 const MCExpr *getExpr() const {
310 assert(Kind == Expression && "Invalid access!");
314 int64_t getExprCRVal() const {
315 assert(Kind == Expression && "Invalid access!");
319 const MCExpr *getTLSReg() const {
320 assert(Kind == TLSRegister && "Invalid access!");
324 unsigned getReg() const {
325 assert(isRegNumber() && "Invalid access!");
326 return (unsigned) Imm.Val;
329 unsigned getCCReg() const {
330 assert(isCCRegNumber() && "Invalid access!");
331 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
334 unsigned getCRBit() const {
335 assert(isCRBitNumber() && "Invalid access!");
336 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
339 unsigned getCRBitMask() const {
340 assert(isCRBitMask() && "Invalid access!");
341 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
344 bool isToken() const { return Kind == Token; }
345 bool isImm() const { return Kind == Immediate || Kind == Expression; }
346 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
347 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
348 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
349 bool isU16Imm() const { return Kind == Expression ||
350 (Kind == Immediate && isUInt<16>(getImm())); }
351 bool isS16Imm() const { return Kind == Expression ||
352 (Kind == Immediate && isInt<16>(getImm())); }
353 bool isS16ImmX4() const { return Kind == Expression ||
354 (Kind == Immediate && isInt<16>(getImm()) &&
355 (getImm() & 3) == 0); }
356 bool isS17Imm() const { return Kind == Expression ||
357 (Kind == Immediate && isInt<17>(getImm())); }
358 bool isTLSReg() const { return Kind == TLSRegister; }
359 bool isDirectBr() const { return Kind == Expression ||
360 (Kind == Immediate && isInt<26>(getImm()) &&
361 (getImm() & 3) == 0); }
362 bool isCondBr() const { return Kind == Expression ||
363 (Kind == Immediate && isInt<16>(getImm()) &&
364 (getImm() & 3) == 0); }
365 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
366 bool isCCRegNumber() const { return (Kind == Expression
367 && isUInt<3>(getExprCRVal())) ||
369 && isUInt<3>(getImm())); }
370 bool isCRBitNumber() const { return (Kind == Expression
371 && isUInt<5>(getExprCRVal())) ||
373 && isUInt<5>(getImm())); }
374 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
375 isPowerOf2_32(getImm()); }
376 bool isMem() const { return false; }
377 bool isReg() const { return false; }
379 void addRegOperands(MCInst &Inst, unsigned N) const {
380 llvm_unreachable("addRegOperands");
383 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
384 assert(N == 1 && "Invalid number of operands!");
385 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
388 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
389 assert(N == 1 && "Invalid number of operands!");
390 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
393 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
394 assert(N == 1 && "Invalid number of operands!");
395 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
398 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
399 assert(N == 1 && "Invalid number of operands!");
400 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
403 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
405 addRegG8RCOperands(Inst, N);
407 addRegGPRCOperands(Inst, N);
410 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
412 addRegG8RCNoX0Operands(Inst, N);
414 addRegGPRCNoR0Operands(Inst, N);
417 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
418 assert(N == 1 && "Invalid number of operands!");
419 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
422 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
423 assert(N == 1 && "Invalid number of operands!");
424 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
427 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
428 assert(N == 1 && "Invalid number of operands!");
429 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
432 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
433 assert(N == 1 && "Invalid number of operands!");
434 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
437 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
438 assert(N == 1 && "Invalid number of operands!");
439 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
442 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
443 assert(N == 1 && "Invalid number of operands!");
444 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
447 void addImmOperands(MCInst &Inst, unsigned N) const {
448 assert(N == 1 && "Invalid number of operands!");
449 if (Kind == Immediate)
450 Inst.addOperand(MCOperand::CreateImm(getImm()));
452 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
455 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
456 assert(N == 1 && "Invalid number of operands!");
457 if (Kind == Immediate)
458 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
460 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
463 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
464 assert(N == 1 && "Invalid number of operands!");
465 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
468 StringRef getToken() const {
469 assert(Kind == Token && "Invalid access!");
470 return StringRef(Tok.Data, Tok.Length);
473 virtual void print(raw_ostream &OS) const;
475 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
476 PPCOperand *Op = new PPCOperand(Token);
477 Op->Tok.Data = Str.data();
478 Op->Tok.Length = Str.size();
481 Op->IsPPC64 = IsPPC64;
485 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
486 PPCOperand *Op = new PPCOperand(Immediate);
490 Op->IsPPC64 = IsPPC64;
494 static PPCOperand *CreateExpr(const MCExpr *Val,
495 SMLoc S, SMLoc E, bool IsPPC64) {
496 PPCOperand *Op = new PPCOperand(Expression);
498 Op->Expr.CRVal = EvaluateCRExpr(Val);
501 Op->IsPPC64 = IsPPC64;
505 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
506 SMLoc S, SMLoc E, bool IsPPC64) {
507 PPCOperand *Op = new PPCOperand(TLSRegister);
508 Op->TLSReg.Sym = Sym;
511 Op->IsPPC64 = IsPPC64;
515 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
516 SMLoc S, SMLoc E, bool IsPPC64) {
517 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
518 return CreateImm(CE->getValue(), S, E, IsPPC64);
520 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
521 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
522 return CreateTLSReg(SRE, S, E, IsPPC64);
524 return CreateExpr(Val, S, E, IsPPC64);
528 } // end anonymous namespace.
530 void PPCOperand::print(raw_ostream &OS) const {
533 OS << "'" << getToken() << "'";
539 getExpr()->print(OS);
542 getTLSReg()->print(OS);
549 ProcessInstruction(MCInst &Inst,
550 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
551 int Opcode = Inst.getOpcode();
555 TmpInst.setOpcode(PPC::LA);
556 TmpInst.addOperand(Inst.getOperand(0));
557 TmpInst.addOperand(Inst.getOperand(2));
558 TmpInst.addOperand(Inst.getOperand(1));
564 int64_t N = Inst.getOperand(2).getImm();
565 TmpInst.setOpcode(PPC::ADDI);
566 TmpInst.addOperand(Inst.getOperand(0));
567 TmpInst.addOperand(Inst.getOperand(1));
568 TmpInst.addOperand(MCOperand::CreateImm(-N));
574 int64_t N = Inst.getOperand(2).getImm();
575 TmpInst.setOpcode(PPC::ADDIS);
576 TmpInst.addOperand(Inst.getOperand(0));
577 TmpInst.addOperand(Inst.getOperand(1));
578 TmpInst.addOperand(MCOperand::CreateImm(-N));
584 int64_t N = Inst.getOperand(2).getImm();
585 TmpInst.setOpcode(PPC::ADDIC);
586 TmpInst.addOperand(Inst.getOperand(0));
587 TmpInst.addOperand(Inst.getOperand(1));
588 TmpInst.addOperand(MCOperand::CreateImm(-N));
594 int64_t N = Inst.getOperand(2).getImm();
595 TmpInst.setOpcode(PPC::ADDICo);
596 TmpInst.addOperand(Inst.getOperand(0));
597 TmpInst.addOperand(Inst.getOperand(1));
598 TmpInst.addOperand(MCOperand::CreateImm(-N));
605 int64_t N = Inst.getOperand(2).getImm();
606 int64_t B = Inst.getOperand(3).getImm();
607 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
608 TmpInst.addOperand(Inst.getOperand(0));
609 TmpInst.addOperand(Inst.getOperand(1));
610 TmpInst.addOperand(MCOperand::CreateImm(B));
611 TmpInst.addOperand(MCOperand::CreateImm(0));
612 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
619 int64_t N = Inst.getOperand(2).getImm();
620 int64_t B = Inst.getOperand(3).getImm();
621 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
622 TmpInst.addOperand(Inst.getOperand(0));
623 TmpInst.addOperand(Inst.getOperand(1));
624 TmpInst.addOperand(MCOperand::CreateImm(B + N));
625 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
626 TmpInst.addOperand(MCOperand::CreateImm(31));
633 int64_t N = Inst.getOperand(2).getImm();
634 int64_t B = Inst.getOperand(3).getImm();
635 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
636 TmpInst.addOperand(Inst.getOperand(0));
637 TmpInst.addOperand(Inst.getOperand(0));
638 TmpInst.addOperand(Inst.getOperand(1));
639 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
640 TmpInst.addOperand(MCOperand::CreateImm(B));
641 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
648 int64_t N = Inst.getOperand(2).getImm();
649 int64_t B = Inst.getOperand(3).getImm();
650 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
651 TmpInst.addOperand(Inst.getOperand(0));
652 TmpInst.addOperand(Inst.getOperand(0));
653 TmpInst.addOperand(Inst.getOperand(1));
654 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
655 TmpInst.addOperand(MCOperand::CreateImm(B));
656 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
663 int64_t N = Inst.getOperand(2).getImm();
664 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
665 TmpInst.addOperand(Inst.getOperand(0));
666 TmpInst.addOperand(Inst.getOperand(1));
667 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
668 TmpInst.addOperand(MCOperand::CreateImm(0));
669 TmpInst.addOperand(MCOperand::CreateImm(31));
676 int64_t N = Inst.getOperand(2).getImm();
677 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
678 TmpInst.addOperand(Inst.getOperand(0));
679 TmpInst.addOperand(Inst.getOperand(1));
680 TmpInst.addOperand(MCOperand::CreateImm(N));
681 TmpInst.addOperand(MCOperand::CreateImm(0));
682 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
689 int64_t N = Inst.getOperand(2).getImm();
690 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
691 TmpInst.addOperand(Inst.getOperand(0));
692 TmpInst.addOperand(Inst.getOperand(1));
693 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
694 TmpInst.addOperand(MCOperand::CreateImm(N));
695 TmpInst.addOperand(MCOperand::CreateImm(31));
702 int64_t N = Inst.getOperand(2).getImm();
703 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
704 TmpInst.addOperand(Inst.getOperand(0));
705 TmpInst.addOperand(Inst.getOperand(1));
706 TmpInst.addOperand(MCOperand::CreateImm(0));
707 TmpInst.addOperand(MCOperand::CreateImm(0));
708 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
713 case PPC::CLRLSLWIo: {
715 int64_t B = Inst.getOperand(2).getImm();
716 int64_t N = Inst.getOperand(3).getImm();
717 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
718 TmpInst.addOperand(Inst.getOperand(0));
719 TmpInst.addOperand(Inst.getOperand(1));
720 TmpInst.addOperand(MCOperand::CreateImm(N));
721 TmpInst.addOperand(MCOperand::CreateImm(B - N));
722 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
729 int64_t N = Inst.getOperand(2).getImm();
730 int64_t B = Inst.getOperand(3).getImm();
731 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
732 TmpInst.addOperand(Inst.getOperand(0));
733 TmpInst.addOperand(Inst.getOperand(1));
734 TmpInst.addOperand(MCOperand::CreateImm(B));
735 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
742 int64_t N = Inst.getOperand(2).getImm();
743 int64_t B = Inst.getOperand(3).getImm();
744 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
745 TmpInst.addOperand(Inst.getOperand(0));
746 TmpInst.addOperand(Inst.getOperand(1));
747 TmpInst.addOperand(MCOperand::CreateImm(B + N));
748 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
755 int64_t N = Inst.getOperand(2).getImm();
756 int64_t B = Inst.getOperand(3).getImm();
757 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
758 TmpInst.addOperand(Inst.getOperand(0));
759 TmpInst.addOperand(Inst.getOperand(0));
760 TmpInst.addOperand(Inst.getOperand(1));
761 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
762 TmpInst.addOperand(MCOperand::CreateImm(B));
769 int64_t N = Inst.getOperand(2).getImm();
770 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
771 TmpInst.addOperand(Inst.getOperand(0));
772 TmpInst.addOperand(Inst.getOperand(1));
773 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
774 TmpInst.addOperand(MCOperand::CreateImm(0));
781 int64_t N = Inst.getOperand(2).getImm();
782 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
783 TmpInst.addOperand(Inst.getOperand(0));
784 TmpInst.addOperand(Inst.getOperand(1));
785 TmpInst.addOperand(MCOperand::CreateImm(N));
786 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
793 int64_t N = Inst.getOperand(2).getImm();
794 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
795 TmpInst.addOperand(Inst.getOperand(0));
796 TmpInst.addOperand(Inst.getOperand(1));
797 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
798 TmpInst.addOperand(MCOperand::CreateImm(N));
805 int64_t N = Inst.getOperand(2).getImm();
806 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
807 TmpInst.addOperand(Inst.getOperand(0));
808 TmpInst.addOperand(Inst.getOperand(1));
809 TmpInst.addOperand(MCOperand::CreateImm(0));
810 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
815 case PPC::CLRLSLDIo: {
817 int64_t B = Inst.getOperand(2).getImm();
818 int64_t N = Inst.getOperand(3).getImm();
819 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
820 TmpInst.addOperand(Inst.getOperand(0));
821 TmpInst.addOperand(Inst.getOperand(1));
822 TmpInst.addOperand(MCOperand::CreateImm(N));
823 TmpInst.addOperand(MCOperand::CreateImm(B - N));
831 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
832 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
833 MCStreamer &Out, unsigned &ErrorInfo,
834 bool MatchingInlineAsm) {
837 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
840 // Post-process instructions (typically extended mnemonics)
841 ProcessInstruction(Inst, Operands);
843 Out.EmitInstruction(Inst);
845 case Match_MissingFeature:
846 return Error(IDLoc, "instruction use requires an option to be enabled");
847 case Match_MnemonicFail:
848 return Error(IDLoc, "unrecognized instruction mnemonic");
849 case Match_InvalidOperand: {
850 SMLoc ErrorLoc = IDLoc;
851 if (ErrorInfo != ~0U) {
852 if (ErrorInfo >= Operands.size())
853 return Error(IDLoc, "too few operands for instruction");
855 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
856 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
859 return Error(ErrorLoc, "invalid operand for instruction");
863 llvm_unreachable("Implement any new match types added!");
867 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
868 if (Tok.is(AsmToken::Identifier)) {
869 StringRef Name = Tok.getString();
871 if (Name.equals_lower("lr")) {
872 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
875 } else if (Name.equals_lower("ctr")) {
876 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
879 } else if (Name.equals_lower("vrsave")) {
883 } else if (Name.substr(0, 1).equals_lower("r") &&
884 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
885 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
887 } else if (Name.substr(0, 1).equals_lower("f") &&
888 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
889 RegNo = FRegs[IntVal];
891 } else if (Name.substr(0, 1).equals_lower("v") &&
892 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
893 RegNo = VRegs[IntVal];
895 } else if (Name.substr(0, 2).equals_lower("cr") &&
896 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
897 RegNo = CRRegs[IntVal];
906 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
907 const AsmToken &Tok = Parser.getTok();
908 StartLoc = Tok.getLoc();
909 EndLoc = Tok.getEndLoc();
913 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
914 Parser.Lex(); // Eat identifier token.
918 return Error(StartLoc, "invalid register name");
921 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
922 /// the expression and check for VK_PPC_LO/HI/HA
923 /// symbol variants. If all symbols with modifier use the same
924 /// variant, return the corresponding PPCMCExpr::VariantKind,
925 /// and a modified expression using the default symbol variant.
926 /// Otherwise, return NULL.
927 const MCExpr *PPCAsmParser::
928 ExtractModifierFromExpr(const MCExpr *E,
929 PPCMCExpr::VariantKind &Variant) {
930 MCContext &Context = getParser().getContext();
931 Variant = PPCMCExpr::VK_PPC_None;
933 switch (E->getKind()) {
935 case MCExpr::Constant:
938 case MCExpr::SymbolRef: {
939 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
941 switch (SRE->getKind()) {
942 case MCSymbolRefExpr::VK_PPC_LO:
943 Variant = PPCMCExpr::VK_PPC_LO;
945 case MCSymbolRefExpr::VK_PPC_HI:
946 Variant = PPCMCExpr::VK_PPC_HI;
948 case MCSymbolRefExpr::VK_PPC_HA:
949 Variant = PPCMCExpr::VK_PPC_HA;
951 case MCSymbolRefExpr::VK_PPC_HIGHER:
952 Variant = PPCMCExpr::VK_PPC_HIGHER;
954 case MCSymbolRefExpr::VK_PPC_HIGHERA:
955 Variant = PPCMCExpr::VK_PPC_HIGHERA;
957 case MCSymbolRefExpr::VK_PPC_HIGHEST:
958 Variant = PPCMCExpr::VK_PPC_HIGHEST;
960 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
961 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
967 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
970 case MCExpr::Unary: {
971 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
972 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
975 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
978 case MCExpr::Binary: {
979 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
980 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
981 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
982 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
987 if (!LHS) LHS = BE->getLHS();
988 if (!RHS) RHS = BE->getRHS();
990 if (LHSVariant == PPCMCExpr::VK_PPC_None)
991 Variant = RHSVariant;
992 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
993 Variant = LHSVariant;
994 else if (LHSVariant == RHSVariant)
995 Variant = LHSVariant;
999 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1003 llvm_unreachable("Invalid expression kind!");
1006 /// Parse an expression. This differs from the default "parseExpression"
1007 /// in that it handles complex \code @l/@ha \endcode modifiers.
1009 ParseExpression(const MCExpr *&EVal) {
1010 if (getParser().parseExpression(EVal))
1013 PPCMCExpr::VariantKind Variant;
1014 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1016 EVal = PPCMCExpr::Create(Variant, E, getParser().getContext());
1022 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1023 SMLoc S = Parser.getTok().getLoc();
1024 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1028 // Attempt to parse the next token as an immediate
1029 switch (getLexer().getKind()) {
1030 // Special handling for register names. These are interpreted
1031 // as immediates corresponding to the register number.
1032 case AsmToken::Percent:
1033 Parser.Lex(); // Eat the '%'.
1036 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1037 Parser.Lex(); // Eat the identifier token.
1038 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1039 Operands.push_back(Op);
1042 return Error(S, "invalid register name");
1044 // All other expressions
1045 case AsmToken::LParen:
1046 case AsmToken::Plus:
1047 case AsmToken::Minus:
1048 case AsmToken::Integer:
1049 case AsmToken::Identifier:
1051 case AsmToken::Dollar:
1052 if (!ParseExpression(EVal))
1056 return Error(S, "unknown operand");
1059 // Push the parsed operand into the list of operands
1060 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1061 Operands.push_back(Op);
1063 // Check whether this is a TLS call expression
1064 bool TLSCall = false;
1065 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1066 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1068 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1069 const MCExpr *TLSSym;
1071 Parser.Lex(); // Eat the '('.
1072 S = Parser.getTok().getLoc();
1073 if (ParseExpression(TLSSym))
1074 return Error(S, "invalid TLS call expression");
1075 if (getLexer().isNot(AsmToken::RParen))
1076 return Error(Parser.getTok().getLoc(), "missing ')'");
1077 E = Parser.getTok().getLoc();
1078 Parser.Lex(); // Eat the ')'.
1080 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1081 Operands.push_back(Op);
1084 // Otherwise, check for D-form memory operands
1085 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1086 Parser.Lex(); // Eat the '('.
1087 S = Parser.getTok().getLoc();
1090 switch (getLexer().getKind()) {
1091 case AsmToken::Percent:
1092 Parser.Lex(); // Eat the '%'.
1094 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1095 return Error(S, "invalid register name");
1096 Parser.Lex(); // Eat the identifier token.
1099 case AsmToken::Integer:
1100 if (getParser().parseAbsoluteExpression(IntVal) ||
1101 IntVal < 0 || IntVal > 31)
1102 return Error(S, "invalid register number");
1106 return Error(S, "invalid memory operand");
1109 if (getLexer().isNot(AsmToken::RParen))
1110 return Error(Parser.getTok().getLoc(), "missing ')'");
1111 E = Parser.getTok().getLoc();
1112 Parser.Lex(); // Eat the ')'.
1114 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1115 Operands.push_back(Op);
1121 /// Parse an instruction mnemonic followed by its operands.
1123 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1124 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1125 // The first operand is the token for the instruction name.
1126 // If the next character is a '+' or '-', we need to add it to the
1127 // instruction name, to match what TableGen is doing.
1128 if (getLexer().is(AsmToken::Plus)) {
1130 char *NewOpcode = new char[Name.size() + 1];
1131 memcpy(NewOpcode, Name.data(), Name.size());
1132 NewOpcode[Name.size()] = '+';
1133 Name = StringRef(NewOpcode, Name.size() + 1);
1135 if (getLexer().is(AsmToken::Minus)) {
1137 char *NewOpcode = new char[Name.size() + 1];
1138 memcpy(NewOpcode, Name.data(), Name.size());
1139 NewOpcode[Name.size()] = '-';
1140 Name = StringRef(NewOpcode, Name.size() + 1);
1142 // If the instruction ends in a '.', we need to create a separate
1143 // token for it, to match what TableGen is doing.
1144 size_t Dot = Name.find('.');
1145 StringRef Mnemonic = Name.slice(0, Dot);
1146 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1147 if (Dot != StringRef::npos) {
1148 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1149 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1150 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1153 // If there are no more operands then finish
1154 if (getLexer().is(AsmToken::EndOfStatement))
1157 // Parse the first operand
1158 if (ParseOperand(Operands))
1161 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1162 getLexer().is(AsmToken::Comma)) {
1163 // Consume the comma token
1166 // Parse the next operand
1167 if (ParseOperand(Operands))
1174 /// ParseDirective parses the PPC specific directives
1175 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1176 StringRef IDVal = DirectiveID.getIdentifier();
1177 if (IDVal == ".word")
1178 return ParseDirectiveWord(4, DirectiveID.getLoc());
1180 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1184 /// ParseDirectiveWord
1185 /// ::= .word [ expression (, expression)* ]
1186 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1187 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1189 const MCExpr *Value;
1190 if (getParser().parseExpression(Value))
1193 getParser().getStreamer().EmitValue(Value, Size);
1195 if (getLexer().is(AsmToken::EndOfStatement))
1198 if (getLexer().isNot(AsmToken::Comma))
1199 return Error(L, "unexpected token in directive");
1208 /// ParseDirectiveTC
1209 /// ::= .tc [ symbol (, expression)* ]
1210 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1211 // Skip TC symbol, which is only used with XCOFF.
1212 while (getLexer().isNot(AsmToken::EndOfStatement)
1213 && getLexer().isNot(AsmToken::Comma))
1215 if (getLexer().isNot(AsmToken::Comma))
1216 return Error(L, "unexpected token in directive");
1219 // Align to word size.
1220 getParser().getStreamer().EmitValueToAlignment(Size);
1222 // Emit expressions.
1223 return ParseDirectiveWord(Size, L);
1226 /// Force static initialization.
1227 extern "C" void LLVMInitializePowerPCAsmParser() {
1228 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1229 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1232 #define GET_REGISTER_MATCHER
1233 #define GET_MATCHER_IMPLEMENTATION
1234 #include "PPCGenAsmMatcher.inc"