1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
35 static const MCPhysReg RRegs[32] = {
36 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
37 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
38 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
39 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 static const MCPhysReg RRegsNoR0[32] = {
47 PPC::R1, PPC::R2, PPC::R3,
48 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
49 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
50 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54 PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 static const MCPhysReg XRegs[32] = {
57 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
58 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
59 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
60 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64 PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 static const MCPhysReg XRegsNoX0[32] = {
68 PPC::X1, PPC::X2, PPC::X3,
69 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
70 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
71 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75 PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 static const MCPhysReg FRegs[32] = {
78 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
79 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
80 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
81 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85 PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 static const MCPhysReg VRegs[32] = {
88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95 PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static const MCPhysReg VSRegs[64] = {
98 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
99 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
100 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
101 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
108 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
109 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
110 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 static const MCPhysReg VSFRegs[64] = {
117 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
118 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
119 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
120 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
127 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
128 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
129 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 static unsigned QFRegs[32] = {
136 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
137 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
138 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
139 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
140 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
141 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
142 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
143 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
145 static const MCPhysReg CRBITRegs[32] = {
146 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
147 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
148 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
149 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
150 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
151 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
152 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
153 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
155 static const MCPhysReg CRRegs[8] = {
156 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
157 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
160 // Evaluate an expression containing condition register
161 // or condition register field symbols. Returns positive
162 // value on success, or -1 on error.
164 EvaluateCRExpr(const MCExpr *E) {
165 switch (E->getKind()) {
169 case MCExpr::Constant: {
170 int64_t Res = cast<MCConstantExpr>(E)->getValue();
171 return Res < 0 ? -1 : Res;
174 case MCExpr::SymbolRef: {
175 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
176 StringRef Name = SRE->getSymbol().getName();
178 if (Name == "lt") return 0;
179 if (Name == "gt") return 1;
180 if (Name == "eq") return 2;
181 if (Name == "so") return 3;
182 if (Name == "un") return 3;
184 if (Name == "cr0") return 0;
185 if (Name == "cr1") return 1;
186 if (Name == "cr2") return 2;
187 if (Name == "cr3") return 3;
188 if (Name == "cr4") return 4;
189 if (Name == "cr5") return 5;
190 if (Name == "cr6") return 6;
191 if (Name == "cr7") return 7;
199 case MCExpr::Binary: {
200 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
201 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
202 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
205 if (LHSVal < 0 || RHSVal < 0)
208 switch (BE->getOpcode()) {
210 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
211 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
214 return Res < 0 ? -1 : Res;
218 llvm_unreachable("Invalid expression kind!");
225 class PPCAsmParser : public MCTargetAsmParser {
226 MCSubtargetInfo &STI;
227 const MCInstrInfo &MII;
231 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
232 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
234 bool isPPC64() const { return IsPPC64; }
235 bool isDarwin() const { return IsDarwin; }
237 bool MatchRegisterName(const AsmToken &Tok,
238 unsigned &RegNo, int64_t &IntVal);
240 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
242 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
243 PPCMCExpr::VariantKind &Variant);
244 const MCExpr *FixupVariantKind(const MCExpr *E);
245 bool ParseExpression(const MCExpr *&EVal);
246 bool ParseDarwinExpression(const MCExpr *&EVal);
248 bool ParseOperand(OperandVector &Operands);
250 bool ParseDirectiveWord(unsigned Size, SMLoc L);
251 bool ParseDirectiveTC(unsigned Size, SMLoc L);
252 bool ParseDirectiveMachine(SMLoc L);
253 bool ParseDarwinDirectiveMachine(SMLoc L);
254 bool ParseDirectiveAbiVersion(SMLoc L);
255 bool ParseDirectiveLocalEntry(SMLoc L);
257 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
258 OperandVector &Operands, MCStreamer &Out,
260 bool MatchingInlineAsm) override;
262 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
264 /// @name Auto-generated Match Functions
267 #define GET_ASSEMBLER_HEADER
268 #include "PPCGenAsmMatcher.inc"
274 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
275 const MCInstrInfo &_MII, const MCTargetOptions &Options)
276 : MCTargetAsmParser(), STI(_STI), MII(_MII) {
277 // Check for 64-bit vs. 32-bit pointer mode.
278 Triple TheTriple(STI.getTargetTriple());
279 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
280 TheTriple.getArch() == Triple::ppc64le);
281 IsDarwin = TheTriple.isMacOSX();
282 // Initialize the set of available features.
283 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
286 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
287 SMLoc NameLoc, OperandVector &Operands) override;
289 bool ParseDirective(AsmToken DirectiveID) override;
291 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
292 unsigned Kind) override;
294 const MCExpr *applyModifierToExpr(const MCExpr *E,
295 MCSymbolRefExpr::VariantKind,
296 MCContext &Ctx) override;
299 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
301 struct PPCOperand : public MCParsedAsmOperand {
310 SMLoc StartLoc, EndLoc;
324 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
328 const MCSymbolRefExpr *Sym;
335 struct TLSRegOp TLSReg;
338 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
340 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
342 StartLoc = o.StartLoc;
350 case ContextImmediate:
362 /// getStartLoc - Get the location of the first token of this operand.
363 SMLoc getStartLoc() const override { return StartLoc; }
365 /// getEndLoc - Get the location of the last token of this operand.
366 SMLoc getEndLoc() const override { return EndLoc; }
368 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
369 bool isPPC64() const { return IsPPC64; }
371 int64_t getImm() const {
372 assert(Kind == Immediate && "Invalid access!");
375 int64_t getImmS16Context() const {
376 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
377 if (Kind == Immediate)
379 return static_cast<int16_t>(Imm.Val);
381 int64_t getImmU16Context() const {
382 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
386 const MCExpr *getExpr() const {
387 assert(Kind == Expression && "Invalid access!");
391 int64_t getExprCRVal() const {
392 assert(Kind == Expression && "Invalid access!");
396 const MCExpr *getTLSReg() const {
397 assert(Kind == TLSRegister && "Invalid access!");
401 unsigned getReg() const override {
402 assert(isRegNumber() && "Invalid access!");
403 return (unsigned) Imm.Val;
406 unsigned getVSReg() const {
407 assert(isVSRegNumber() && "Invalid access!");
408 return (unsigned) Imm.Val;
411 unsigned getCCReg() const {
412 assert(isCCRegNumber() && "Invalid access!");
413 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
416 unsigned getCRBit() const {
417 assert(isCRBitNumber() && "Invalid access!");
418 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
421 unsigned getCRBitMask() const {
422 assert(isCRBitMask() && "Invalid access!");
423 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
426 bool isToken() const override { return Kind == Token; }
427 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
428 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
429 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
430 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
431 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
432 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
433 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
434 bool isU6ImmX2() const { return Kind == Immediate &&
435 isUInt<6>(getImm()) &&
436 (getImm() & 1) == 0; }
437 bool isU7ImmX4() const { return Kind == Immediate &&
438 isUInt<7>(getImm()) &&
439 (getImm() & 3) == 0; }
440 bool isU8ImmX8() const { return Kind == Immediate &&
441 isUInt<8>(getImm()) &&
442 (getImm() & 7) == 0; }
443 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
444 bool isU16Imm() const {
449 case ContextImmediate:
450 return isUInt<16>(getImmU16Context());
455 bool isS16Imm() const {
460 case ContextImmediate:
461 return isInt<16>(getImmS16Context());
466 bool isS16ImmX4() const { return Kind == Expression ||
467 (Kind == Immediate && isInt<16>(getImm()) &&
468 (getImm() & 3) == 0); }
469 bool isS17Imm() const {
474 case ContextImmediate:
475 return isInt<17>(getImmS16Context());
480 bool isTLSReg() const { return Kind == TLSRegister; }
481 bool isDirectBr() const {
482 if (Kind == Expression)
484 if (Kind != Immediate)
486 // Operand must be 64-bit aligned, signed 27-bit immediate.
487 if ((getImm() & 3) != 0)
489 if (isInt<26>(getImm()))
492 // In 32-bit mode, large 32-bit quantities wrap around.
493 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
498 bool isCondBr() const { return Kind == Expression ||
499 (Kind == Immediate && isInt<16>(getImm()) &&
500 (getImm() & 3) == 0); }
501 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
502 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
503 bool isCCRegNumber() const { return (Kind == Expression
504 && isUInt<3>(getExprCRVal())) ||
506 && isUInt<3>(getImm())); }
507 bool isCRBitNumber() const { return (Kind == Expression
508 && isUInt<5>(getExprCRVal())) ||
510 && isUInt<5>(getImm())); }
511 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
512 isPowerOf2_32(getImm()); }
513 bool isMem() const override { return false; }
514 bool isReg() const override { return false; }
516 void addRegOperands(MCInst &Inst, unsigned N) const {
517 llvm_unreachable("addRegOperands");
520 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
521 assert(N == 1 && "Invalid number of operands!");
522 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
525 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
526 assert(N == 1 && "Invalid number of operands!");
527 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
530 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 1 && "Invalid number of operands!");
532 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
535 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
536 assert(N == 1 && "Invalid number of operands!");
537 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
540 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
542 addRegG8RCOperands(Inst, N);
544 addRegGPRCOperands(Inst, N);
547 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
549 addRegG8RCNoX0Operands(Inst, N);
551 addRegGPRCNoR0Operands(Inst, N);
554 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
555 assert(N == 1 && "Invalid number of operands!");
556 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
559 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
560 assert(N == 1 && "Invalid number of operands!");
561 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
564 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
565 assert(N == 1 && "Invalid number of operands!");
566 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
569 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
570 assert(N == 1 && "Invalid number of operands!");
571 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
574 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
575 assert(N == 1 && "Invalid number of operands!");
576 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
579 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
580 assert(N == 1 && "Invalid number of operands!");
581 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
584 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
585 assert(N == 1 && "Invalid number of operands!");
586 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
589 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
590 assert(N == 1 && "Invalid number of operands!");
591 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
594 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
595 assert(N == 1 && "Invalid number of operands!");
596 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
599 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 1 && "Invalid number of operands!");
601 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
604 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
605 assert(N == 1 && "Invalid number of operands!");
606 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
609 void addImmOperands(MCInst &Inst, unsigned N) const {
610 assert(N == 1 && "Invalid number of operands!");
611 if (Kind == Immediate)
612 Inst.addOperand(MCOperand::CreateImm(getImm()));
614 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
617 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
618 assert(N == 1 && "Invalid number of operands!");
621 Inst.addOperand(MCOperand::CreateImm(getImm()));
623 case ContextImmediate:
624 Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
627 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
632 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
633 assert(N == 1 && "Invalid number of operands!");
636 Inst.addOperand(MCOperand::CreateImm(getImm()));
638 case ContextImmediate:
639 Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
642 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
647 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
648 assert(N == 1 && "Invalid number of operands!");
649 if (Kind == Immediate)
650 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
652 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
655 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
656 assert(N == 1 && "Invalid number of operands!");
657 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
660 StringRef getToken() const {
661 assert(Kind == Token && "Invalid access!");
662 return StringRef(Tok.Data, Tok.Length);
665 void print(raw_ostream &OS) const override;
667 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
669 auto Op = make_unique<PPCOperand>(Token);
670 Op->Tok.Data = Str.data();
671 Op->Tok.Length = Str.size();
674 Op->IsPPC64 = IsPPC64;
678 static std::unique_ptr<PPCOperand>
679 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
680 // Allocate extra memory for the string and copy it.
681 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
682 // deleter which will destroy them by simply using "delete", not correctly
683 // calling operator delete on this extra memory after calling the dtor
685 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
686 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
687 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
688 Op->Tok.Length = Str.size();
689 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
692 Op->IsPPC64 = IsPPC64;
696 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
698 auto Op = make_unique<PPCOperand>(Immediate);
702 Op->IsPPC64 = IsPPC64;
706 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
707 SMLoc E, bool IsPPC64) {
708 auto Op = make_unique<PPCOperand>(Expression);
710 Op->Expr.CRVal = EvaluateCRExpr(Val);
713 Op->IsPPC64 = IsPPC64;
717 static std::unique_ptr<PPCOperand>
718 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
719 auto Op = make_unique<PPCOperand>(TLSRegister);
720 Op->TLSReg.Sym = Sym;
723 Op->IsPPC64 = IsPPC64;
727 static std::unique_ptr<PPCOperand>
728 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
729 auto Op = make_unique<PPCOperand>(ContextImmediate);
733 Op->IsPPC64 = IsPPC64;
737 static std::unique_ptr<PPCOperand>
738 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
739 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
740 return CreateImm(CE->getValue(), S, E, IsPPC64);
742 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
743 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
744 return CreateTLSReg(SRE, S, E, IsPPC64);
746 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
748 if (TE->EvaluateAsConstant(Res))
749 return CreateContextImm(Res, S, E, IsPPC64);
752 return CreateExpr(Val, S, E, IsPPC64);
756 } // end anonymous namespace.
758 void PPCOperand::print(raw_ostream &OS) const {
761 OS << "'" << getToken() << "'";
764 case ContextImmediate:
768 getExpr()->print(OS);
771 getTLSReg()->print(OS);
777 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
779 Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
782 const MCExpr *Expr = Op.getExpr();
783 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
784 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
785 Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
788 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
789 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
790 const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
791 BinExpr->getLHS(), Ctx);
792 Inst.addOperand(MCOperand::CreateExpr(NE));
796 Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
799 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
800 const OperandVector &Operands) {
801 int Opcode = Inst.getOpcode();
805 TmpInst.setOpcode(PPC::LA);
806 TmpInst.addOperand(Inst.getOperand(0));
807 TmpInst.addOperand(Inst.getOperand(2));
808 TmpInst.addOperand(Inst.getOperand(1));
814 TmpInst.setOpcode(PPC::ADDI);
815 TmpInst.addOperand(Inst.getOperand(0));
816 TmpInst.addOperand(Inst.getOperand(1));
817 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
823 TmpInst.setOpcode(PPC::ADDIS);
824 TmpInst.addOperand(Inst.getOperand(0));
825 TmpInst.addOperand(Inst.getOperand(1));
826 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
832 TmpInst.setOpcode(PPC::ADDIC);
833 TmpInst.addOperand(Inst.getOperand(0));
834 TmpInst.addOperand(Inst.getOperand(1));
835 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
841 TmpInst.setOpcode(PPC::ADDICo);
842 TmpInst.addOperand(Inst.getOperand(0));
843 TmpInst.addOperand(Inst.getOperand(1));
844 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
851 int64_t N = Inst.getOperand(2).getImm();
852 int64_t B = Inst.getOperand(3).getImm();
853 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
854 TmpInst.addOperand(Inst.getOperand(0));
855 TmpInst.addOperand(Inst.getOperand(1));
856 TmpInst.addOperand(MCOperand::CreateImm(B));
857 TmpInst.addOperand(MCOperand::CreateImm(0));
858 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
865 int64_t N = Inst.getOperand(2).getImm();
866 int64_t B = Inst.getOperand(3).getImm();
867 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
868 TmpInst.addOperand(Inst.getOperand(0));
869 TmpInst.addOperand(Inst.getOperand(1));
870 TmpInst.addOperand(MCOperand::CreateImm(B + N));
871 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
872 TmpInst.addOperand(MCOperand::CreateImm(31));
879 int64_t N = Inst.getOperand(2).getImm();
880 int64_t B = Inst.getOperand(3).getImm();
881 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
882 TmpInst.addOperand(Inst.getOperand(0));
883 TmpInst.addOperand(Inst.getOperand(0));
884 TmpInst.addOperand(Inst.getOperand(1));
885 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
886 TmpInst.addOperand(MCOperand::CreateImm(B));
887 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
894 int64_t N = Inst.getOperand(2).getImm();
895 int64_t B = Inst.getOperand(3).getImm();
896 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
897 TmpInst.addOperand(Inst.getOperand(0));
898 TmpInst.addOperand(Inst.getOperand(0));
899 TmpInst.addOperand(Inst.getOperand(1));
900 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
901 TmpInst.addOperand(MCOperand::CreateImm(B));
902 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
909 int64_t N = Inst.getOperand(2).getImm();
910 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
911 TmpInst.addOperand(Inst.getOperand(0));
912 TmpInst.addOperand(Inst.getOperand(1));
913 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
914 TmpInst.addOperand(MCOperand::CreateImm(0));
915 TmpInst.addOperand(MCOperand::CreateImm(31));
922 int64_t N = Inst.getOperand(2).getImm();
923 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
924 TmpInst.addOperand(Inst.getOperand(0));
925 TmpInst.addOperand(Inst.getOperand(1));
926 TmpInst.addOperand(MCOperand::CreateImm(N));
927 TmpInst.addOperand(MCOperand::CreateImm(0));
928 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
935 int64_t N = Inst.getOperand(2).getImm();
936 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
937 TmpInst.addOperand(Inst.getOperand(0));
938 TmpInst.addOperand(Inst.getOperand(1));
939 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
940 TmpInst.addOperand(MCOperand::CreateImm(N));
941 TmpInst.addOperand(MCOperand::CreateImm(31));
948 int64_t N = Inst.getOperand(2).getImm();
949 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
950 TmpInst.addOperand(Inst.getOperand(0));
951 TmpInst.addOperand(Inst.getOperand(1));
952 TmpInst.addOperand(MCOperand::CreateImm(0));
953 TmpInst.addOperand(MCOperand::CreateImm(0));
954 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
959 case PPC::CLRLSLWIo: {
961 int64_t B = Inst.getOperand(2).getImm();
962 int64_t N = Inst.getOperand(3).getImm();
963 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
964 TmpInst.addOperand(Inst.getOperand(0));
965 TmpInst.addOperand(Inst.getOperand(1));
966 TmpInst.addOperand(MCOperand::CreateImm(N));
967 TmpInst.addOperand(MCOperand::CreateImm(B - N));
968 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
975 int64_t N = Inst.getOperand(2).getImm();
976 int64_t B = Inst.getOperand(3).getImm();
977 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
978 TmpInst.addOperand(Inst.getOperand(0));
979 TmpInst.addOperand(Inst.getOperand(1));
980 TmpInst.addOperand(MCOperand::CreateImm(B));
981 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
988 int64_t N = Inst.getOperand(2).getImm();
989 int64_t B = Inst.getOperand(3).getImm();
990 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
991 TmpInst.addOperand(Inst.getOperand(0));
992 TmpInst.addOperand(Inst.getOperand(1));
993 TmpInst.addOperand(MCOperand::CreateImm(B + N));
994 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1001 int64_t N = Inst.getOperand(2).getImm();
1002 int64_t B = Inst.getOperand(3).getImm();
1003 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1004 TmpInst.addOperand(Inst.getOperand(0));
1005 TmpInst.addOperand(Inst.getOperand(0));
1006 TmpInst.addOperand(Inst.getOperand(1));
1007 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1008 TmpInst.addOperand(MCOperand::CreateImm(B));
1013 case PPC::ROTRDIo: {
1015 int64_t N = Inst.getOperand(2).getImm();
1016 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1017 TmpInst.addOperand(Inst.getOperand(0));
1018 TmpInst.addOperand(Inst.getOperand(1));
1019 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1020 TmpInst.addOperand(MCOperand::CreateImm(0));
1027 int64_t N = Inst.getOperand(2).getImm();
1028 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1029 TmpInst.addOperand(Inst.getOperand(0));
1030 TmpInst.addOperand(Inst.getOperand(1));
1031 TmpInst.addOperand(MCOperand::CreateImm(N));
1032 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1039 int64_t N = Inst.getOperand(2).getImm();
1040 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1041 TmpInst.addOperand(Inst.getOperand(0));
1042 TmpInst.addOperand(Inst.getOperand(1));
1043 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1044 TmpInst.addOperand(MCOperand::CreateImm(N));
1049 case PPC::CLRRDIo: {
1051 int64_t N = Inst.getOperand(2).getImm();
1052 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1053 TmpInst.addOperand(Inst.getOperand(0));
1054 TmpInst.addOperand(Inst.getOperand(1));
1055 TmpInst.addOperand(MCOperand::CreateImm(0));
1056 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1061 case PPC::CLRLSLDIo: {
1063 int64_t B = Inst.getOperand(2).getImm();
1064 int64_t N = Inst.getOperand(3).getImm();
1065 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1066 TmpInst.addOperand(Inst.getOperand(0));
1067 TmpInst.addOperand(Inst.getOperand(1));
1068 TmpInst.addOperand(MCOperand::CreateImm(N));
1069 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1076 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1077 OperandVector &Operands,
1078 MCStreamer &Out, uint64_t &ErrorInfo,
1079 bool MatchingInlineAsm) {
1082 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1084 // Post-process instructions (typically extended mnemonics)
1085 ProcessInstruction(Inst, Operands);
1087 Out.EmitInstruction(Inst, STI);
1089 case Match_MissingFeature:
1090 return Error(IDLoc, "instruction use requires an option to be enabled");
1091 case Match_MnemonicFail:
1092 return Error(IDLoc, "unrecognized instruction mnemonic");
1093 case Match_InvalidOperand: {
1094 SMLoc ErrorLoc = IDLoc;
1095 if (ErrorInfo != ~0ULL) {
1096 if (ErrorInfo >= Operands.size())
1097 return Error(IDLoc, "too few operands for instruction");
1099 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1100 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1103 return Error(ErrorLoc, "invalid operand for instruction");
1107 llvm_unreachable("Implement any new match types added!");
1111 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1112 if (Tok.is(AsmToken::Identifier)) {
1113 StringRef Name = Tok.getString();
1115 if (Name.equals_lower("lr")) {
1116 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1119 } else if (Name.equals_lower("ctr")) {
1120 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1123 } else if (Name.equals_lower("vrsave")) {
1124 RegNo = PPC::VRSAVE;
1127 } else if (Name.startswith_lower("r") &&
1128 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1129 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1131 } else if (Name.startswith_lower("f") &&
1132 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1133 RegNo = FRegs[IntVal];
1135 } else if (Name.startswith_lower("v") &&
1136 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1137 RegNo = VRegs[IntVal];
1139 } else if (Name.startswith_lower("cr") &&
1140 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1141 RegNo = CRRegs[IntVal];
1150 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1151 MCAsmParser &Parser = getParser();
1152 const AsmToken &Tok = Parser.getTok();
1153 StartLoc = Tok.getLoc();
1154 EndLoc = Tok.getEndLoc();
1158 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1159 Parser.Lex(); // Eat identifier token.
1163 return Error(StartLoc, "invalid register name");
1166 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1167 /// the expression and check for VK_PPC_LO/HI/HA
1168 /// symbol variants. If all symbols with modifier use the same
1169 /// variant, return the corresponding PPCMCExpr::VariantKind,
1170 /// and a modified expression using the default symbol variant.
1171 /// Otherwise, return NULL.
1172 const MCExpr *PPCAsmParser::
1173 ExtractModifierFromExpr(const MCExpr *E,
1174 PPCMCExpr::VariantKind &Variant) {
1175 MCContext &Context = getParser().getContext();
1176 Variant = PPCMCExpr::VK_PPC_None;
1178 switch (E->getKind()) {
1179 case MCExpr::Target:
1180 case MCExpr::Constant:
1183 case MCExpr::SymbolRef: {
1184 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1186 switch (SRE->getKind()) {
1187 case MCSymbolRefExpr::VK_PPC_LO:
1188 Variant = PPCMCExpr::VK_PPC_LO;
1190 case MCSymbolRefExpr::VK_PPC_HI:
1191 Variant = PPCMCExpr::VK_PPC_HI;
1193 case MCSymbolRefExpr::VK_PPC_HA:
1194 Variant = PPCMCExpr::VK_PPC_HA;
1196 case MCSymbolRefExpr::VK_PPC_HIGHER:
1197 Variant = PPCMCExpr::VK_PPC_HIGHER;
1199 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1200 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1202 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1203 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1205 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1206 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1212 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1215 case MCExpr::Unary: {
1216 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1217 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1220 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1223 case MCExpr::Binary: {
1224 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1225 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1226 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1227 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1232 if (!LHS) LHS = BE->getLHS();
1233 if (!RHS) RHS = BE->getRHS();
1235 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1236 Variant = RHSVariant;
1237 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1238 Variant = LHSVariant;
1239 else if (LHSVariant == RHSVariant)
1240 Variant = LHSVariant;
1244 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1248 llvm_unreachable("Invalid expression kind!");
1251 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1252 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1253 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1254 /// FIXME: This is a hack.
1255 const MCExpr *PPCAsmParser::
1256 FixupVariantKind(const MCExpr *E) {
1257 MCContext &Context = getParser().getContext();
1259 switch (E->getKind()) {
1260 case MCExpr::Target:
1261 case MCExpr::Constant:
1264 case MCExpr::SymbolRef: {
1265 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1266 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1268 switch (SRE->getKind()) {
1269 case MCSymbolRefExpr::VK_TLSGD:
1270 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1272 case MCSymbolRefExpr::VK_TLSLD:
1273 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1278 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1281 case MCExpr::Unary: {
1282 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1283 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1284 if (Sub == UE->getSubExpr())
1286 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1289 case MCExpr::Binary: {
1290 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1291 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1292 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1293 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1295 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1299 llvm_unreachable("Invalid expression kind!");
1302 /// ParseExpression. This differs from the default "parseExpression" in that
1303 /// it handles modifiers.
1305 ParseExpression(const MCExpr *&EVal) {
1308 return ParseDarwinExpression(EVal);
1311 // Handle \code @l/@ha \endcode
1312 if (getParser().parseExpression(EVal))
1315 EVal = FixupVariantKind(EVal);
1317 PPCMCExpr::VariantKind Variant;
1318 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1320 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1325 /// ParseDarwinExpression. (MachO Platforms)
1326 /// This differs from the default "parseExpression" in that it handles detection
1327 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1328 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1329 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1330 /// for this to be done at a higher level.
1332 ParseDarwinExpression(const MCExpr *&EVal) {
1333 MCAsmParser &Parser = getParser();
1334 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1335 switch (getLexer().getKind()) {
1338 case AsmToken::Identifier:
1339 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1340 // something starting with any other char should be part of the
1341 // asm syntax. If handwritten asm includes an identifier like lo16,
1342 // then all bets are off - but no-one would do that, right?
1343 StringRef poss = Parser.getTok().getString();
1344 if (poss.equals_lower("lo16")) {
1345 Variant = PPCMCExpr::VK_PPC_LO;
1346 } else if (poss.equals_lower("hi16")) {
1347 Variant = PPCMCExpr::VK_PPC_HI;
1348 } else if (poss.equals_lower("ha16")) {
1349 Variant = PPCMCExpr::VK_PPC_HA;
1351 if (Variant != PPCMCExpr::VK_PPC_None) {
1352 Parser.Lex(); // Eat the xx16
1353 if (getLexer().isNot(AsmToken::LParen))
1354 return Error(Parser.getTok().getLoc(), "expected '('");
1355 Parser.Lex(); // Eat the '('
1360 if (getParser().parseExpression(EVal))
1363 if (Variant != PPCMCExpr::VK_PPC_None) {
1364 if (getLexer().isNot(AsmToken::RParen))
1365 return Error(Parser.getTok().getLoc(), "expected ')'");
1366 Parser.Lex(); // Eat the ')'
1367 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1373 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1375 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1376 MCAsmParser &Parser = getParser();
1377 SMLoc S = Parser.getTok().getLoc();
1378 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1381 // Attempt to parse the next token as an immediate
1382 switch (getLexer().getKind()) {
1383 // Special handling for register names. These are interpreted
1384 // as immediates corresponding to the register number.
1385 case AsmToken::Percent:
1386 Parser.Lex(); // Eat the '%'.
1389 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1390 Parser.Lex(); // Eat the identifier token.
1391 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1394 return Error(S, "invalid register name");
1396 case AsmToken::Identifier:
1397 // Note that non-register-name identifiers from the compiler will begin
1398 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1399 // identifiers like r31foo - so we fall through in the event that parsing
1400 // a register name fails.
1404 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1405 Parser.Lex(); // Eat the identifier token.
1406 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1410 // Fall-through to process non-register-name identifiers as expression.
1411 // All other expressions
1412 case AsmToken::LParen:
1413 case AsmToken::Plus:
1414 case AsmToken::Minus:
1415 case AsmToken::Integer:
1417 case AsmToken::Dollar:
1418 case AsmToken::Exclaim:
1419 case AsmToken::Tilde:
1420 if (!ParseExpression(EVal))
1424 return Error(S, "unknown operand");
1427 // Push the parsed operand into the list of operands
1428 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1430 // Check whether this is a TLS call expression
1431 bool TLSCall = false;
1432 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1433 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1435 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1436 const MCExpr *TLSSym;
1438 Parser.Lex(); // Eat the '('.
1439 S = Parser.getTok().getLoc();
1440 if (ParseExpression(TLSSym))
1441 return Error(S, "invalid TLS call expression");
1442 if (getLexer().isNot(AsmToken::RParen))
1443 return Error(Parser.getTok().getLoc(), "missing ')'");
1444 E = Parser.getTok().getLoc();
1445 Parser.Lex(); // Eat the ')'.
1447 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1450 // Otherwise, check for D-form memory operands
1451 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1452 Parser.Lex(); // Eat the '('.
1453 S = Parser.getTok().getLoc();
1456 switch (getLexer().getKind()) {
1457 case AsmToken::Percent:
1458 Parser.Lex(); // Eat the '%'.
1460 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1461 return Error(S, "invalid register name");
1462 Parser.Lex(); // Eat the identifier token.
1465 case AsmToken::Integer:
1467 if (getParser().parseAbsoluteExpression(IntVal) ||
1468 IntVal < 0 || IntVal > 31)
1469 return Error(S, "invalid register number");
1471 return Error(S, "unexpected integer value");
1475 case AsmToken::Identifier:
1478 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1479 Parser.Lex(); // Eat the identifier token.
1486 return Error(S, "invalid memory operand");
1489 if (getLexer().isNot(AsmToken::RParen))
1490 return Error(Parser.getTok().getLoc(), "missing ')'");
1491 E = Parser.getTok().getLoc();
1492 Parser.Lex(); // Eat the ')'.
1494 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1500 /// Parse an instruction mnemonic followed by its operands.
1501 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1502 SMLoc NameLoc, OperandVector &Operands) {
1503 // The first operand is the token for the instruction name.
1504 // If the next character is a '+' or '-', we need to add it to the
1505 // instruction name, to match what TableGen is doing.
1506 std::string NewOpcode;
1507 if (getLexer().is(AsmToken::Plus)) {
1513 if (getLexer().is(AsmToken::Minus)) {
1519 // If the instruction ends in a '.', we need to create a separate
1520 // token for it, to match what TableGen is doing.
1521 size_t Dot = Name.find('.');
1522 StringRef Mnemonic = Name.slice(0, Dot);
1523 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1525 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1527 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1528 if (Dot != StringRef::npos) {
1529 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1530 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1531 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1533 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1535 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1538 // If there are no more operands then finish
1539 if (getLexer().is(AsmToken::EndOfStatement))
1542 // Parse the first operand
1543 if (ParseOperand(Operands))
1546 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1547 getLexer().is(AsmToken::Comma)) {
1548 // Consume the comma token
1551 // Parse the next operand
1552 if (ParseOperand(Operands))
1559 /// ParseDirective parses the PPC specific directives
1560 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1561 StringRef IDVal = DirectiveID.getIdentifier();
1563 if (IDVal == ".word")
1564 return ParseDirectiveWord(2, DirectiveID.getLoc());
1565 if (IDVal == ".llong")
1566 return ParseDirectiveWord(8, DirectiveID.getLoc());
1568 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1569 if (IDVal == ".machine")
1570 return ParseDirectiveMachine(DirectiveID.getLoc());
1571 if (IDVal == ".abiversion")
1572 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1573 if (IDVal == ".localentry")
1574 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1576 if (IDVal == ".machine")
1577 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1582 /// ParseDirectiveWord
1583 /// ::= .word [ expression (, expression)* ]
1584 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1585 MCAsmParser &Parser = getParser();
1586 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1588 const MCExpr *Value;
1589 if (getParser().parseExpression(Value))
1592 getParser().getStreamer().EmitValue(Value, Size);
1594 if (getLexer().is(AsmToken::EndOfStatement))
1597 if (getLexer().isNot(AsmToken::Comma))
1598 return Error(L, "unexpected token in directive");
1607 /// ParseDirectiveTC
1608 /// ::= .tc [ symbol (, expression)* ]
1609 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1610 MCAsmParser &Parser = getParser();
1611 // Skip TC symbol, which is only used with XCOFF.
1612 while (getLexer().isNot(AsmToken::EndOfStatement)
1613 && getLexer().isNot(AsmToken::Comma))
1615 if (getLexer().isNot(AsmToken::Comma)) {
1616 Error(L, "unexpected token in directive");
1621 // Align to word size.
1622 getParser().getStreamer().EmitValueToAlignment(Size);
1624 // Emit expressions.
1625 return ParseDirectiveWord(Size, L);
1628 /// ParseDirectiveMachine (ELF platforms)
1629 /// ::= .machine [ cpu | "push" | "pop" ]
1630 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1631 MCAsmParser &Parser = getParser();
1632 if (getLexer().isNot(AsmToken::Identifier) &&
1633 getLexer().isNot(AsmToken::String)) {
1634 Error(L, "unexpected token in directive");
1638 StringRef CPU = Parser.getTok().getIdentifier();
1641 // FIXME: Right now, the parser always allows any available
1642 // instruction, so the .machine directive is not useful.
1643 // Implement ".machine any" (by doing nothing) for the benefit
1644 // of existing assembler code. Likewise, we can then implement
1645 // ".machine push" and ".machine pop" as no-op.
1646 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1647 Error(L, "unrecognized machine type");
1651 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1652 Error(L, "unexpected token in directive");
1655 PPCTargetStreamer &TStreamer =
1656 *static_cast<PPCTargetStreamer *>(
1657 getParser().getStreamer().getTargetStreamer());
1658 TStreamer.emitMachine(CPU);
1663 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1664 /// ::= .machine cpu-identifier
1665 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1666 MCAsmParser &Parser = getParser();
1667 if (getLexer().isNot(AsmToken::Identifier) &&
1668 getLexer().isNot(AsmToken::String)) {
1669 Error(L, "unexpected token in directive");
1673 StringRef CPU = Parser.getTok().getIdentifier();
1676 // FIXME: this is only the 'default' set of cpu variants.
1677 // However we don't act on this information at present, this is simply
1678 // allowing parsing to proceed with minimal sanity checking.
1679 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1680 Error(L, "unrecognized cpu type");
1684 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1685 Error(L, "wrong cpu type specified for 64bit");
1688 if (!isPPC64() && CPU == "ppc64") {
1689 Error(L, "wrong cpu type specified for 32bit");
1693 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1694 Error(L, "unexpected token in directive");
1701 /// ParseDirectiveAbiVersion
1702 /// ::= .abiversion constant-expression
1703 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1705 if (getParser().parseAbsoluteExpression(AbiVersion)){
1706 Error(L, "expected constant expression");
1709 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1710 Error(L, "unexpected token in directive");
1714 PPCTargetStreamer &TStreamer =
1715 *static_cast<PPCTargetStreamer *>(
1716 getParser().getStreamer().getTargetStreamer());
1717 TStreamer.emitAbiVersion(AbiVersion);
1722 /// ParseDirectiveLocalEntry
1723 /// ::= .localentry symbol, expression
1724 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1726 if (getParser().parseIdentifier(Name)) {
1727 Error(L, "expected identifier in directive");
1730 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1732 if (getLexer().isNot(AsmToken::Comma)) {
1733 Error(L, "unexpected token in directive");
1739 if (getParser().parseExpression(Expr)) {
1740 Error(L, "expected expression");
1744 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1745 Error(L, "unexpected token in directive");
1749 PPCTargetStreamer &TStreamer =
1750 *static_cast<PPCTargetStreamer *>(
1751 getParser().getStreamer().getTargetStreamer());
1752 TStreamer.emitLocalEntry(Sym, Expr);
1759 /// Force static initialization.
1760 extern "C" void LLVMInitializePowerPCAsmParser() {
1761 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1762 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1763 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1766 #define GET_REGISTER_MATCHER
1767 #define GET_MATCHER_IMPLEMENTATION
1768 #include "PPCGenAsmMatcher.inc"
1770 // Define this matcher function after the auto-generated include so we
1771 // have the match class enum definitions.
1772 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1774 // If the kind is a token for a literal immediate, check if our asm
1775 // operand matches. This is for InstAliases which have a fixed-value
1776 // immediate in the syntax.
1779 case MCK_0: ImmVal = 0; break;
1780 case MCK_1: ImmVal = 1; break;
1781 case MCK_2: ImmVal = 2; break;
1782 case MCK_3: ImmVal = 3; break;
1783 case MCK_4: ImmVal = 4; break;
1784 case MCK_5: ImmVal = 5; break;
1785 case MCK_6: ImmVal = 6; break;
1786 case MCK_7: ImmVal = 7; break;
1787 default: return Match_InvalidOperand;
1790 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1791 if (Op.isImm() && Op.getImm() == ImmVal)
1792 return Match_Success;
1794 return Match_InvalidOperand;
1798 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1799 MCSymbolRefExpr::VariantKind Variant,
1802 case MCSymbolRefExpr::VK_PPC_LO:
1803 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1804 case MCSymbolRefExpr::VK_PPC_HI:
1805 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1806 case MCSymbolRefExpr::VK_PPC_HA:
1807 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1808 case MCSymbolRefExpr::VK_PPC_HIGHER:
1809 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1810 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1811 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1812 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1813 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1814 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1815 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);