1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
36 static unsigned RRegs[32] = {
37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 static unsigned RRegsNoR0[32] = {
48 PPC::R1, PPC::R2, PPC::R3,
49 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
50 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 static unsigned XRegs[32] = {
58 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65 PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 static unsigned XRegsNoX0[32] = {
69 PPC::X1, PPC::X2, PPC::X3,
70 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76 PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 static unsigned FRegs[32] = {
79 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86 PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 static unsigned VRegs[32] = {
89 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
90 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96 PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 static unsigned CRBITRegs[32] = {
99 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
100 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
101 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
102 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
103 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
104 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
105 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
106 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
108 static unsigned CRRegs[8] = {
109 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
110 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
113 // Evaluate an expression containing condition register
114 // or condition register field symbols. Returns positive
115 // value on success, or -1 on error.
117 EvaluateCRExpr(const MCExpr *E) {
118 switch (E->getKind()) {
122 case MCExpr::Constant: {
123 int64_t Res = cast<MCConstantExpr>(E)->getValue();
124 return Res < 0 ? -1 : Res;
127 case MCExpr::SymbolRef: {
128 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
129 StringRef Name = SRE->getSymbol().getName();
131 if (Name == "lt") return 0;
132 if (Name == "gt") return 1;
133 if (Name == "eq") return 2;
134 if (Name == "so") return 3;
135 if (Name == "un") return 3;
137 if (Name == "cr0") return 0;
138 if (Name == "cr1") return 1;
139 if (Name == "cr2") return 2;
140 if (Name == "cr3") return 3;
141 if (Name == "cr4") return 4;
142 if (Name == "cr5") return 5;
143 if (Name == "cr6") return 6;
144 if (Name == "cr7") return 7;
152 case MCExpr::Binary: {
153 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
154 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
155 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
158 if (LHSVal < 0 || RHSVal < 0)
161 switch (BE->getOpcode()) {
163 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
164 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
167 return Res < 0 ? -1 : Res;
171 llvm_unreachable("Invalid expression kind!");
176 class PPCAsmParser : public MCTargetAsmParser {
177 MCSubtargetInfo &STI;
179 const MCInstrInfo &MII;
183 MCAsmParser &getParser() const { return Parser; }
184 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
186 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
187 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
189 bool isPPC64() const { return IsPPC64; }
190 bool isDarwin() const { return IsDarwin; }
192 bool MatchRegisterName(const AsmToken &Tok,
193 unsigned &RegNo, int64_t &IntVal);
195 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
197 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
198 PPCMCExpr::VariantKind &Variant);
199 const MCExpr *FixupVariantKind(const MCExpr *E);
200 bool ParseExpression(const MCExpr *&EVal);
201 bool ParseDarwinExpression(const MCExpr *&EVal);
203 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
205 bool ParseDirectiveWord(unsigned Size, SMLoc L);
206 bool ParseDirectiveTC(unsigned Size, SMLoc L);
207 bool ParseDirectiveMachine(SMLoc L);
208 bool ParseDarwinDirectiveMachine(SMLoc L);
210 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
211 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
212 MCStreamer &Out, unsigned &ErrorInfo,
213 bool MatchingInlineAsm);
215 void ProcessInstruction(MCInst &Inst,
216 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
218 /// @name Auto-generated Match Functions
221 #define GET_ASSEMBLER_HEADER
222 #include "PPCGenAsmMatcher.inc"
228 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
229 const MCInstrInfo &_MII)
230 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
231 // Check for 64-bit vs. 32-bit pointer mode.
232 Triple TheTriple(STI.getTargetTriple());
233 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
234 TheTriple.getArch() == Triple::ppc64le);
235 IsDarwin = TheTriple.isMacOSX();
236 // Initialize the set of available features.
237 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
240 virtual bool ParseInstruction(ParseInstructionInfo &Info,
241 StringRef Name, SMLoc NameLoc,
242 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
244 virtual bool ParseDirective(AsmToken DirectiveID);
246 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
248 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
249 MCSymbolRefExpr::VariantKind,
253 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
255 struct PPCOperand : public MCParsedAsmOperand {
263 SMLoc StartLoc, EndLoc;
277 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
281 const MCSymbolRefExpr *Sym;
288 struct TLSRegOp TLSReg;
291 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
293 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
295 StartLoc = o.StartLoc;
314 /// getStartLoc - Get the location of the first token of this operand.
315 SMLoc getStartLoc() const { return StartLoc; }
317 /// getEndLoc - Get the location of the last token of this operand.
318 SMLoc getEndLoc() const { return EndLoc; }
320 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
321 bool isPPC64() const { return IsPPC64; }
323 int64_t getImm() const {
324 assert(Kind == Immediate && "Invalid access!");
328 const MCExpr *getExpr() const {
329 assert(Kind == Expression && "Invalid access!");
333 int64_t getExprCRVal() const {
334 assert(Kind == Expression && "Invalid access!");
338 const MCExpr *getTLSReg() const {
339 assert(Kind == TLSRegister && "Invalid access!");
343 unsigned getReg() const {
344 assert(isRegNumber() && "Invalid access!");
345 return (unsigned) Imm.Val;
348 unsigned getCCReg() const {
349 assert(isCCRegNumber() && "Invalid access!");
350 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
353 unsigned getCRBit() const {
354 assert(isCRBitNumber() && "Invalid access!");
355 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
358 unsigned getCRBitMask() const {
359 assert(isCRBitMask() && "Invalid access!");
360 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
363 bool isToken() const { return Kind == Token; }
364 bool isImm() const { return Kind == Immediate || Kind == Expression; }
365 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
366 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
367 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
368 bool isU16Imm() const { return Kind == Expression ||
369 (Kind == Immediate && isUInt<16>(getImm())); }
370 bool isS16Imm() const { return Kind == Expression ||
371 (Kind == Immediate && isInt<16>(getImm())); }
372 bool isS16ImmX4() const { return Kind == Expression ||
373 (Kind == Immediate && isInt<16>(getImm()) &&
374 (getImm() & 3) == 0); }
375 bool isS17Imm() const { return Kind == Expression ||
376 (Kind == Immediate && isInt<17>(getImm())); }
377 bool isTLSReg() const { return Kind == TLSRegister; }
378 bool isDirectBr() const { return Kind == Expression ||
379 (Kind == Immediate && isInt<26>(getImm()) &&
380 (getImm() & 3) == 0); }
381 bool isCondBr() const { return Kind == Expression ||
382 (Kind == Immediate && isInt<16>(getImm()) &&
383 (getImm() & 3) == 0); }
384 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
385 bool isCCRegNumber() const { return (Kind == Expression
386 && isUInt<3>(getExprCRVal())) ||
388 && isUInt<3>(getImm())); }
389 bool isCRBitNumber() const { return (Kind == Expression
390 && isUInt<5>(getExprCRVal())) ||
392 && isUInt<5>(getImm())); }
393 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
394 isPowerOf2_32(getImm()); }
395 bool isMem() const { return false; }
396 bool isReg() const { return false; }
398 void addRegOperands(MCInst &Inst, unsigned N) const {
399 llvm_unreachable("addRegOperands");
402 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
403 assert(N == 1 && "Invalid number of operands!");
404 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
407 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
408 assert(N == 1 && "Invalid number of operands!");
409 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
412 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
413 assert(N == 1 && "Invalid number of operands!");
414 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
417 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
418 assert(N == 1 && "Invalid number of operands!");
419 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
422 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
424 addRegG8RCOperands(Inst, N);
426 addRegGPRCOperands(Inst, N);
429 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
431 addRegG8RCNoX0Operands(Inst, N);
433 addRegGPRCNoR0Operands(Inst, N);
436 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
437 assert(N == 1 && "Invalid number of operands!");
438 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
441 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
442 assert(N == 1 && "Invalid number of operands!");
443 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
446 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
447 assert(N == 1 && "Invalid number of operands!");
448 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
451 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
452 assert(N == 1 && "Invalid number of operands!");
453 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
456 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
457 assert(N == 1 && "Invalid number of operands!");
458 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
461 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
462 assert(N == 1 && "Invalid number of operands!");
463 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
466 void addImmOperands(MCInst &Inst, unsigned N) const {
467 assert(N == 1 && "Invalid number of operands!");
468 if (Kind == Immediate)
469 Inst.addOperand(MCOperand::CreateImm(getImm()));
471 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
474 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
475 assert(N == 1 && "Invalid number of operands!");
476 if (Kind == Immediate)
477 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
479 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
482 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
483 assert(N == 1 && "Invalid number of operands!");
484 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
487 StringRef getToken() const {
488 assert(Kind == Token && "Invalid access!");
489 return StringRef(Tok.Data, Tok.Length);
492 virtual void print(raw_ostream &OS) const;
494 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
495 PPCOperand *Op = new PPCOperand(Token);
496 Op->Tok.Data = Str.data();
497 Op->Tok.Length = Str.size();
500 Op->IsPPC64 = IsPPC64;
504 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
506 // Allocate extra memory for the string and copy it.
507 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
508 PPCOperand *Op = new (Mem) PPCOperand(Token);
509 Op->Tok.Data = (const char *)(Op + 1);
510 Op->Tok.Length = Str.size();
511 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
514 Op->IsPPC64 = IsPPC64;
518 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
519 PPCOperand *Op = new PPCOperand(Immediate);
523 Op->IsPPC64 = IsPPC64;
527 static PPCOperand *CreateExpr(const MCExpr *Val,
528 SMLoc S, SMLoc E, bool IsPPC64) {
529 PPCOperand *Op = new PPCOperand(Expression);
531 Op->Expr.CRVal = EvaluateCRExpr(Val);
534 Op->IsPPC64 = IsPPC64;
538 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
539 SMLoc S, SMLoc E, bool IsPPC64) {
540 PPCOperand *Op = new PPCOperand(TLSRegister);
541 Op->TLSReg.Sym = Sym;
544 Op->IsPPC64 = IsPPC64;
548 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
549 SMLoc S, SMLoc E, bool IsPPC64) {
550 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
551 return CreateImm(CE->getValue(), S, E, IsPPC64);
553 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
554 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
555 return CreateTLSReg(SRE, S, E, IsPPC64);
557 return CreateExpr(Val, S, E, IsPPC64);
561 } // end anonymous namespace.
563 void PPCOperand::print(raw_ostream &OS) const {
566 OS << "'" << getToken() << "'";
572 getExpr()->print(OS);
575 getTLSReg()->print(OS);
582 ProcessInstruction(MCInst &Inst,
583 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
584 int Opcode = Inst.getOpcode();
588 TmpInst.setOpcode(PPC::LA);
589 TmpInst.addOperand(Inst.getOperand(0));
590 TmpInst.addOperand(Inst.getOperand(2));
591 TmpInst.addOperand(Inst.getOperand(1));
597 int64_t N = Inst.getOperand(2).getImm();
598 TmpInst.setOpcode(PPC::ADDI);
599 TmpInst.addOperand(Inst.getOperand(0));
600 TmpInst.addOperand(Inst.getOperand(1));
601 TmpInst.addOperand(MCOperand::CreateImm(-N));
607 int64_t N = Inst.getOperand(2).getImm();
608 TmpInst.setOpcode(PPC::ADDIS);
609 TmpInst.addOperand(Inst.getOperand(0));
610 TmpInst.addOperand(Inst.getOperand(1));
611 TmpInst.addOperand(MCOperand::CreateImm(-N));
617 int64_t N = Inst.getOperand(2).getImm();
618 TmpInst.setOpcode(PPC::ADDIC);
619 TmpInst.addOperand(Inst.getOperand(0));
620 TmpInst.addOperand(Inst.getOperand(1));
621 TmpInst.addOperand(MCOperand::CreateImm(-N));
627 int64_t N = Inst.getOperand(2).getImm();
628 TmpInst.setOpcode(PPC::ADDICo);
629 TmpInst.addOperand(Inst.getOperand(0));
630 TmpInst.addOperand(Inst.getOperand(1));
631 TmpInst.addOperand(MCOperand::CreateImm(-N));
638 int64_t N = Inst.getOperand(2).getImm();
639 int64_t B = Inst.getOperand(3).getImm();
640 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
641 TmpInst.addOperand(Inst.getOperand(0));
642 TmpInst.addOperand(Inst.getOperand(1));
643 TmpInst.addOperand(MCOperand::CreateImm(B));
644 TmpInst.addOperand(MCOperand::CreateImm(0));
645 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
652 int64_t N = Inst.getOperand(2).getImm();
653 int64_t B = Inst.getOperand(3).getImm();
654 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
655 TmpInst.addOperand(Inst.getOperand(0));
656 TmpInst.addOperand(Inst.getOperand(1));
657 TmpInst.addOperand(MCOperand::CreateImm(B + N));
658 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
659 TmpInst.addOperand(MCOperand::CreateImm(31));
666 int64_t N = Inst.getOperand(2).getImm();
667 int64_t B = Inst.getOperand(3).getImm();
668 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
669 TmpInst.addOperand(Inst.getOperand(0));
670 TmpInst.addOperand(Inst.getOperand(0));
671 TmpInst.addOperand(Inst.getOperand(1));
672 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
673 TmpInst.addOperand(MCOperand::CreateImm(B));
674 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
681 int64_t N = Inst.getOperand(2).getImm();
682 int64_t B = Inst.getOperand(3).getImm();
683 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
684 TmpInst.addOperand(Inst.getOperand(0));
685 TmpInst.addOperand(Inst.getOperand(0));
686 TmpInst.addOperand(Inst.getOperand(1));
687 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
688 TmpInst.addOperand(MCOperand::CreateImm(B));
689 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
696 int64_t N = Inst.getOperand(2).getImm();
697 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
698 TmpInst.addOperand(Inst.getOperand(0));
699 TmpInst.addOperand(Inst.getOperand(1));
700 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
701 TmpInst.addOperand(MCOperand::CreateImm(0));
702 TmpInst.addOperand(MCOperand::CreateImm(31));
709 int64_t N = Inst.getOperand(2).getImm();
710 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
711 TmpInst.addOperand(Inst.getOperand(0));
712 TmpInst.addOperand(Inst.getOperand(1));
713 TmpInst.addOperand(MCOperand::CreateImm(N));
714 TmpInst.addOperand(MCOperand::CreateImm(0));
715 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
722 int64_t N = Inst.getOperand(2).getImm();
723 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
724 TmpInst.addOperand(Inst.getOperand(0));
725 TmpInst.addOperand(Inst.getOperand(1));
726 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
727 TmpInst.addOperand(MCOperand::CreateImm(N));
728 TmpInst.addOperand(MCOperand::CreateImm(31));
735 int64_t N = Inst.getOperand(2).getImm();
736 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
737 TmpInst.addOperand(Inst.getOperand(0));
738 TmpInst.addOperand(Inst.getOperand(1));
739 TmpInst.addOperand(MCOperand::CreateImm(0));
740 TmpInst.addOperand(MCOperand::CreateImm(0));
741 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
746 case PPC::CLRLSLWIo: {
748 int64_t B = Inst.getOperand(2).getImm();
749 int64_t N = Inst.getOperand(3).getImm();
750 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
751 TmpInst.addOperand(Inst.getOperand(0));
752 TmpInst.addOperand(Inst.getOperand(1));
753 TmpInst.addOperand(MCOperand::CreateImm(N));
754 TmpInst.addOperand(MCOperand::CreateImm(B - N));
755 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
762 int64_t N = Inst.getOperand(2).getImm();
763 int64_t B = Inst.getOperand(3).getImm();
764 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
765 TmpInst.addOperand(Inst.getOperand(0));
766 TmpInst.addOperand(Inst.getOperand(1));
767 TmpInst.addOperand(MCOperand::CreateImm(B));
768 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
775 int64_t N = Inst.getOperand(2).getImm();
776 int64_t B = Inst.getOperand(3).getImm();
777 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
778 TmpInst.addOperand(Inst.getOperand(0));
779 TmpInst.addOperand(Inst.getOperand(1));
780 TmpInst.addOperand(MCOperand::CreateImm(B + N));
781 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
788 int64_t N = Inst.getOperand(2).getImm();
789 int64_t B = Inst.getOperand(3).getImm();
790 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
791 TmpInst.addOperand(Inst.getOperand(0));
792 TmpInst.addOperand(Inst.getOperand(0));
793 TmpInst.addOperand(Inst.getOperand(1));
794 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
795 TmpInst.addOperand(MCOperand::CreateImm(B));
802 int64_t N = Inst.getOperand(2).getImm();
803 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
804 TmpInst.addOperand(Inst.getOperand(0));
805 TmpInst.addOperand(Inst.getOperand(1));
806 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
807 TmpInst.addOperand(MCOperand::CreateImm(0));
814 int64_t N = Inst.getOperand(2).getImm();
815 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
816 TmpInst.addOperand(Inst.getOperand(0));
817 TmpInst.addOperand(Inst.getOperand(1));
818 TmpInst.addOperand(MCOperand::CreateImm(N));
819 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
826 int64_t N = Inst.getOperand(2).getImm();
827 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
828 TmpInst.addOperand(Inst.getOperand(0));
829 TmpInst.addOperand(Inst.getOperand(1));
830 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
831 TmpInst.addOperand(MCOperand::CreateImm(N));
838 int64_t N = Inst.getOperand(2).getImm();
839 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
840 TmpInst.addOperand(Inst.getOperand(0));
841 TmpInst.addOperand(Inst.getOperand(1));
842 TmpInst.addOperand(MCOperand::CreateImm(0));
843 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
848 case PPC::CLRLSLDIo: {
850 int64_t B = Inst.getOperand(2).getImm();
851 int64_t N = Inst.getOperand(3).getImm();
852 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
853 TmpInst.addOperand(Inst.getOperand(0));
854 TmpInst.addOperand(Inst.getOperand(1));
855 TmpInst.addOperand(MCOperand::CreateImm(N));
856 TmpInst.addOperand(MCOperand::CreateImm(B - N));
864 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
865 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
866 MCStreamer &Out, unsigned &ErrorInfo,
867 bool MatchingInlineAsm) {
870 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
873 // Post-process instructions (typically extended mnemonics)
874 ProcessInstruction(Inst, Operands);
876 Out.EmitInstruction(Inst, STI);
878 case Match_MissingFeature:
879 return Error(IDLoc, "instruction use requires an option to be enabled");
880 case Match_MnemonicFail:
881 return Error(IDLoc, "unrecognized instruction mnemonic");
882 case Match_InvalidOperand: {
883 SMLoc ErrorLoc = IDLoc;
884 if (ErrorInfo != ~0U) {
885 if (ErrorInfo >= Operands.size())
886 return Error(IDLoc, "too few operands for instruction");
888 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
889 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
892 return Error(ErrorLoc, "invalid operand for instruction");
896 llvm_unreachable("Implement any new match types added!");
900 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
901 if (Tok.is(AsmToken::Identifier)) {
902 StringRef Name = Tok.getString();
904 if (Name.equals_lower("lr")) {
905 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
908 } else if (Name.equals_lower("ctr")) {
909 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
912 } else if (Name.equals_lower("vrsave")) {
916 } else if (Name.startswith_lower("r") &&
917 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
918 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
920 } else if (Name.startswith_lower("f") &&
921 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
922 RegNo = FRegs[IntVal];
924 } else if (Name.startswith_lower("v") &&
925 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
926 RegNo = VRegs[IntVal];
928 } else if (Name.startswith_lower("cr") &&
929 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
930 RegNo = CRRegs[IntVal];
939 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
940 const AsmToken &Tok = Parser.getTok();
941 StartLoc = Tok.getLoc();
942 EndLoc = Tok.getEndLoc();
946 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
947 Parser.Lex(); // Eat identifier token.
951 return Error(StartLoc, "invalid register name");
954 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
955 /// the expression and check for VK_PPC_LO/HI/HA
956 /// symbol variants. If all symbols with modifier use the same
957 /// variant, return the corresponding PPCMCExpr::VariantKind,
958 /// and a modified expression using the default symbol variant.
959 /// Otherwise, return NULL.
960 const MCExpr *PPCAsmParser::
961 ExtractModifierFromExpr(const MCExpr *E,
962 PPCMCExpr::VariantKind &Variant) {
963 MCContext &Context = getParser().getContext();
964 Variant = PPCMCExpr::VK_PPC_None;
966 switch (E->getKind()) {
968 case MCExpr::Constant:
971 case MCExpr::SymbolRef: {
972 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
974 switch (SRE->getKind()) {
975 case MCSymbolRefExpr::VK_PPC_LO:
976 Variant = PPCMCExpr::VK_PPC_LO;
978 case MCSymbolRefExpr::VK_PPC_HI:
979 Variant = PPCMCExpr::VK_PPC_HI;
981 case MCSymbolRefExpr::VK_PPC_HA:
982 Variant = PPCMCExpr::VK_PPC_HA;
984 case MCSymbolRefExpr::VK_PPC_HIGHER:
985 Variant = PPCMCExpr::VK_PPC_HIGHER;
987 case MCSymbolRefExpr::VK_PPC_HIGHERA:
988 Variant = PPCMCExpr::VK_PPC_HIGHERA;
990 case MCSymbolRefExpr::VK_PPC_HIGHEST:
991 Variant = PPCMCExpr::VK_PPC_HIGHEST;
993 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
994 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1000 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1003 case MCExpr::Unary: {
1004 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1005 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1008 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1011 case MCExpr::Binary: {
1012 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1013 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1014 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1015 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1020 if (!LHS) LHS = BE->getLHS();
1021 if (!RHS) RHS = BE->getRHS();
1023 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1024 Variant = RHSVariant;
1025 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1026 Variant = LHSVariant;
1027 else if (LHSVariant == RHSVariant)
1028 Variant = LHSVariant;
1032 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1036 llvm_unreachable("Invalid expression kind!");
1039 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1040 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1041 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1042 /// FIXME: This is a hack.
1043 const MCExpr *PPCAsmParser::
1044 FixupVariantKind(const MCExpr *E) {
1045 MCContext &Context = getParser().getContext();
1047 switch (E->getKind()) {
1048 case MCExpr::Target:
1049 case MCExpr::Constant:
1052 case MCExpr::SymbolRef: {
1053 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1054 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1056 switch (SRE->getKind()) {
1057 case MCSymbolRefExpr::VK_TLSGD:
1058 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1060 case MCSymbolRefExpr::VK_TLSLD:
1061 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1066 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1069 case MCExpr::Unary: {
1070 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1071 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1072 if (Sub == UE->getSubExpr())
1074 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1077 case MCExpr::Binary: {
1078 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1079 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1080 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1081 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1083 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1087 llvm_unreachable("Invalid expression kind!");
1090 /// ParseExpression. This differs from the default "parseExpression" in that
1091 /// it handles modifiers.
1093 ParseExpression(const MCExpr *&EVal) {
1096 return ParseDarwinExpression(EVal);
1099 // Handle \code @l/@ha \endcode
1100 if (getParser().parseExpression(EVal))
1103 EVal = FixupVariantKind(EVal);
1105 PPCMCExpr::VariantKind Variant;
1106 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1108 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1113 /// ParseDarwinExpression. (MachO Platforms)
1114 /// This differs from the default "parseExpression" in that it handles detection
1115 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1116 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1117 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1118 /// for this to be done at a higher level.
1120 ParseDarwinExpression(const MCExpr *&EVal) {
1121 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1122 switch (getLexer().getKind()) {
1125 case AsmToken::Identifier:
1126 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1127 // something starting with any other char should be part of the
1128 // asm syntax. If handwritten asm includes an identifier like lo16,
1129 // then all bets are off - but no-one would do that, right?
1130 StringRef poss = Parser.getTok().getString();
1131 if (poss.equals_lower("lo16")) {
1132 Variant = PPCMCExpr::VK_PPC_LO;
1133 } else if (poss.equals_lower("hi16")) {
1134 Variant = PPCMCExpr::VK_PPC_HI;
1135 } else if (poss.equals_lower("ha16")) {
1136 Variant = PPCMCExpr::VK_PPC_HA;
1138 if (Variant != PPCMCExpr::VK_PPC_None) {
1139 Parser.Lex(); // Eat the xx16
1140 if (getLexer().isNot(AsmToken::LParen))
1141 return Error(Parser.getTok().getLoc(), "expected '('");
1142 Parser.Lex(); // Eat the '('
1147 if (getParser().parseExpression(EVal))
1150 if (Variant != PPCMCExpr::VK_PPC_None) {
1151 if (getLexer().isNot(AsmToken::RParen))
1152 return Error(Parser.getTok().getLoc(), "expected ')'");
1153 Parser.Lex(); // Eat the ')'
1154 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1160 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1163 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1164 SMLoc S = Parser.getTok().getLoc();
1165 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1169 // Attempt to parse the next token as an immediate
1170 switch (getLexer().getKind()) {
1171 // Special handling for register names. These are interpreted
1172 // as immediates corresponding to the register number.
1173 case AsmToken::Percent:
1174 Parser.Lex(); // Eat the '%'.
1177 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1178 Parser.Lex(); // Eat the identifier token.
1179 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1180 Operands.push_back(Op);
1183 return Error(S, "invalid register name");
1185 case AsmToken::Identifier:
1186 // Note that non-register-name identifiers from the compiler will begin
1187 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1188 // identifiers like r31foo - so we fall through in the event that parsing
1189 // a register name fails.
1193 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1194 Parser.Lex(); // Eat the identifier token.
1195 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1196 Operands.push_back(Op);
1200 // Fall-through to process non-register-name identifiers as expression.
1201 // All other expressions
1202 case AsmToken::LParen:
1203 case AsmToken::Plus:
1204 case AsmToken::Minus:
1205 case AsmToken::Integer:
1207 case AsmToken::Dollar:
1208 if (!ParseExpression(EVal))
1212 return Error(S, "unknown operand");
1215 // Push the parsed operand into the list of operands
1216 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1217 Operands.push_back(Op);
1219 // Check whether this is a TLS call expression
1220 bool TLSCall = false;
1221 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1222 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1224 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1225 const MCExpr *TLSSym;
1227 Parser.Lex(); // Eat the '('.
1228 S = Parser.getTok().getLoc();
1229 if (ParseExpression(TLSSym))
1230 return Error(S, "invalid TLS call expression");
1231 if (getLexer().isNot(AsmToken::RParen))
1232 return Error(Parser.getTok().getLoc(), "missing ')'");
1233 E = Parser.getTok().getLoc();
1234 Parser.Lex(); // Eat the ')'.
1236 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1237 Operands.push_back(Op);
1240 // Otherwise, check for D-form memory operands
1241 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1242 Parser.Lex(); // Eat the '('.
1243 S = Parser.getTok().getLoc();
1246 switch (getLexer().getKind()) {
1247 case AsmToken::Percent:
1248 Parser.Lex(); // Eat the '%'.
1250 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1251 return Error(S, "invalid register name");
1252 Parser.Lex(); // Eat the identifier token.
1255 case AsmToken::Integer:
1257 if (getParser().parseAbsoluteExpression(IntVal) ||
1258 IntVal < 0 || IntVal > 31)
1259 return Error(S, "invalid register number");
1261 return Error(S, "unexpected integer value");
1265 case AsmToken::Identifier:
1268 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1269 Parser.Lex(); // Eat the identifier token.
1276 return Error(S, "invalid memory operand");
1279 if (getLexer().isNot(AsmToken::RParen))
1280 return Error(Parser.getTok().getLoc(), "missing ')'");
1281 E = Parser.getTok().getLoc();
1282 Parser.Lex(); // Eat the ')'.
1284 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1285 Operands.push_back(Op);
1291 /// Parse an instruction mnemonic followed by its operands.
1293 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1294 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1295 // The first operand is the token for the instruction name.
1296 // If the next character is a '+' or '-', we need to add it to the
1297 // instruction name, to match what TableGen is doing.
1298 std::string NewOpcode;
1299 if (getLexer().is(AsmToken::Plus)) {
1305 if (getLexer().is(AsmToken::Minus)) {
1311 // If the instruction ends in a '.', we need to create a separate
1312 // token for it, to match what TableGen is doing.
1313 size_t Dot = Name.find('.');
1314 StringRef Mnemonic = Name.slice(0, Dot);
1315 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1317 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1319 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1320 if (Dot != StringRef::npos) {
1321 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1322 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1323 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1325 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1327 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1330 // If there are no more operands then finish
1331 if (getLexer().is(AsmToken::EndOfStatement))
1334 // Parse the first operand
1335 if (ParseOperand(Operands))
1338 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1339 getLexer().is(AsmToken::Comma)) {
1340 // Consume the comma token
1343 // Parse the next operand
1344 if (ParseOperand(Operands))
1351 /// ParseDirective parses the PPC specific directives
1352 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1353 StringRef IDVal = DirectiveID.getIdentifier();
1355 if (IDVal == ".word")
1356 return ParseDirectiveWord(2, DirectiveID.getLoc());
1357 if (IDVal == ".llong")
1358 return ParseDirectiveWord(8, DirectiveID.getLoc());
1360 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1361 if (IDVal == ".machine")
1362 return ParseDirectiveMachine(DirectiveID.getLoc());
1364 if (IDVal == ".machine")
1365 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1370 /// ParseDirectiveWord
1371 /// ::= .word [ expression (, expression)* ]
1372 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1373 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1375 const MCExpr *Value;
1376 if (getParser().parseExpression(Value))
1379 getParser().getStreamer().EmitValue(Value, Size);
1381 if (getLexer().is(AsmToken::EndOfStatement))
1384 if (getLexer().isNot(AsmToken::Comma))
1385 return Error(L, "unexpected token in directive");
1394 /// ParseDirectiveTC
1395 /// ::= .tc [ symbol (, expression)* ]
1396 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1397 // Skip TC symbol, which is only used with XCOFF.
1398 while (getLexer().isNot(AsmToken::EndOfStatement)
1399 && getLexer().isNot(AsmToken::Comma))
1401 if (getLexer().isNot(AsmToken::Comma)) {
1402 Error(L, "unexpected token in directive");
1407 // Align to word size.
1408 getParser().getStreamer().EmitValueToAlignment(Size);
1410 // Emit expressions.
1411 return ParseDirectiveWord(Size, L);
1414 /// ParseDirectiveMachine (ELF platforms)
1415 /// ::= .machine [ cpu | "push" | "pop" ]
1416 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1417 if (getLexer().isNot(AsmToken::Identifier) &&
1418 getLexer().isNot(AsmToken::String)) {
1419 Error(L, "unexpected token in directive");
1423 StringRef CPU = Parser.getTok().getIdentifier();
1426 // FIXME: Right now, the parser always allows any available
1427 // instruction, so the .machine directive is not useful.
1428 // Implement ".machine any" (by doing nothing) for the benefit
1429 // of existing assembler code. Likewise, we can then implement
1430 // ".machine push" and ".machine pop" as no-op.
1431 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1432 Error(L, "unrecognized machine type");
1436 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1437 Error(L, "unexpected token in directive");
1440 PPCTargetStreamer &TStreamer =
1441 *static_cast<PPCTargetStreamer *>(
1442 getParser().getStreamer().getTargetStreamer());
1443 TStreamer.emitMachine(CPU);
1448 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1449 /// ::= .machine cpu-identifier
1450 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1451 if (getLexer().isNot(AsmToken::Identifier) &&
1452 getLexer().isNot(AsmToken::String)) {
1453 Error(L, "unexpected token in directive");
1457 StringRef CPU = Parser.getTok().getIdentifier();
1460 // FIXME: this is only the 'default' set of cpu variants.
1461 // However we don't act on this information at present, this is simply
1462 // allowing parsing to proceed with minimal sanity checking.
1463 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1464 Error(L, "unrecognized cpu type");
1468 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1469 Error(L, "wrong cpu type specified for 64bit");
1472 if (!isPPC64() && CPU == "ppc64") {
1473 Error(L, "wrong cpu type specified for 32bit");
1477 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1478 Error(L, "unexpected token in directive");
1485 /// Force static initialization.
1486 extern "C" void LLVMInitializePowerPCAsmParser() {
1487 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1488 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1489 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1492 #define GET_REGISTER_MATCHER
1493 #define GET_MATCHER_IMPLEMENTATION
1494 #include "PPCGenAsmMatcher.inc"
1496 // Define this matcher function after the auto-generated include so we
1497 // have the match class enum definitions.
1498 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1500 // If the kind is a token for a literal immediate, check if our asm
1501 // operand matches. This is for InstAliases which have a fixed-value
1502 // immediate in the syntax.
1505 case MCK_0: ImmVal = 0; break;
1506 case MCK_1: ImmVal = 1; break;
1507 case MCK_2: ImmVal = 2; break;
1508 case MCK_3: ImmVal = 3; break;
1509 default: return Match_InvalidOperand;
1512 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1513 if (Op->isImm() && Op->getImm() == ImmVal)
1514 return Match_Success;
1516 return Match_InvalidOperand;
1520 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1521 MCSymbolRefExpr::VariantKind Variant,
1524 case MCSymbolRefExpr::VK_PPC_LO:
1525 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1526 case MCSymbolRefExpr::VK_PPC_HI:
1527 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1528 case MCSymbolRefExpr::VK_PPC_HA:
1529 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1530 case MCSymbolRefExpr::VK_PPC_HIGHER:
1531 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1532 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1533 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1534 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1535 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1536 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1537 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);