1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Instruction Pattern Stuff
22 //===----------------------------------------------------------------------===//
24 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
25 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
26 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
27 return PT->getAddressSpace() <= 255;
32 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
33 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
34 def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
37 def MEMrr : Operand<i32> {
38 let PrintMethod = "printMemOperand";
39 let MIOperandInfo = (ops RRegs32, RRegs32);
41 def MEMri : Operand<i32> {
42 let PrintMethod = "printMemOperand";
43 let MIOperandInfo = (ops RRegs32, i32imm);
45 def MEMii : Operand<i32> {
46 let PrintMethod = "printMemOperand";
47 let MIOperandInfo = (ops i32imm, i32imm);
50 //===----------------------------------------------------------------------===//
51 // PTX Specific Node Definitions
52 //===----------------------------------------------------------------------===//
54 // PTX allow generic 3-reg shifts like shl r0, r1, r2
55 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
56 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
57 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
60 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
62 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
64 //===----------------------------------------------------------------------===//
65 // Instruction Class Templates
66 //===----------------------------------------------------------------------===//
68 multiclass INT3<string opcstr, SDNode opnode> {
69 def rr : InstPTX<(outs RRegs32:$d),
70 (ins RRegs32:$a, RRegs32:$b),
71 !strconcat(opcstr, ".%type\t$d, $a, $b"),
72 [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
73 def ri : InstPTX<(outs RRegs32:$d),
74 (ins RRegs32:$a, i32imm:$b),
75 !strconcat(opcstr, ".%type\t$d, $a, $b"),
76 [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
79 // no %type directive, non-communtable
80 multiclass INT3ntnc<string opcstr, SDNode opnode> {
81 def rr : InstPTX<(outs RRegs32:$d),
82 (ins RRegs32:$a, RRegs32:$b),
83 !strconcat(opcstr, "\t$d, $a, $b"),
84 [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
85 def ri : InstPTX<(outs RRegs32:$d),
86 (ins RRegs32:$a, i32imm:$b),
87 !strconcat(opcstr, "\t$d, $a, $b"),
88 [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
89 def ir : InstPTX<(outs RRegs32:$d),
90 (ins i32imm:$a, RRegs32:$b),
91 !strconcat(opcstr, "\t$d, $a, $b"),
92 [(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
95 multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
96 def rr : InstPTX<(outs RC:$d),
98 !strconcat(opstr, ".%type\t$d, [$a]"),
99 [(set RC:$d, (pat_load ADDRrr:$a))]>;
100 def ri : InstPTX<(outs RC:$d),
102 !strconcat(opstr, ".%type\t$d, [$a]"),
103 [(set RC:$d, (pat_load ADDRri:$a))]>;
104 def ii : InstPTX<(outs RC:$d),
106 !strconcat(opstr, ".%type\t$d, [$a]"),
107 [(set RC:$d, (pat_load ADDRii:$a))]>;
110 //===----------------------------------------------------------------------===//
112 //===----------------------------------------------------------------------===//
114 ///===- Integer Arithmetic Instructions -----------------------------------===//
116 defm ADD : INT3<"add", add>;
117 defm SUB : INT3<"sub", sub>;
119 ///===- Logic and Shift Instructions --------------------------------------===//
121 defm SHL : INT3ntnc<"shl.b32", PTXshl>;
122 defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
123 defm SRA : INT3ntnc<"shr.s32", PTXsra>;
125 ///===- Data Movement and Conversion Instructions -------------------------===//
127 let neverHasSideEffects = 1 in {
128 // rely on isMoveInstr to separate MOVpp, MOVrr, etc.
130 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
132 : InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
135 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
137 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
138 [(set Preds:$d, imm:$a)]>;
140 : InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
141 [(set RRegs32:$d, imm:$a)]>;
144 defm LDg : PTX_LD<"ld.global", RRegs32, load_global>;
146 ///===- Control Flow Instructions -----------------------------------------===//
148 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
149 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
150 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;