1 //===- NVPTXInstrInfo.td - NVPTX Instruction defs -------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "NVPTXInstrFormats.td"
17 def NOP : NVPTXInst<(outs), (ins), "", []>;
19 // List of vector specific properties
20 def isVecLD : VecInstTypeEnum<1>;
21 def isVecST : VecInstTypeEnum<2>;
22 def isVecBuild : VecInstTypeEnum<3>;
23 def isVecShuffle : VecInstTypeEnum<4>;
24 def isVecExtract : VecInstTypeEnum<5>;
25 def isVecInsert : VecInstTypeEnum<6>;
26 def isVecDest : VecInstTypeEnum<7>;
27 def isVecOther : VecInstTypeEnum<15>;
29 //===----------------------------------------------------------------------===//
30 // NVPTX Operand Definitions.
31 //===----------------------------------------------------------------------===//
33 def brtarget : Operand<OtherVT>;
35 // CVT conversion modes
36 // These must match the enum in NVPTX.h
37 def CvtNONE : PatLeaf<(i32 0x0)>;
38 def CvtRNI : PatLeaf<(i32 0x1)>;
39 def CvtRZI : PatLeaf<(i32 0x2)>;
40 def CvtRMI : PatLeaf<(i32 0x3)>;
41 def CvtRPI : PatLeaf<(i32 0x4)>;
42 def CvtRN : PatLeaf<(i32 0x5)>;
43 def CvtRZ : PatLeaf<(i32 0x6)>;
44 def CvtRM : PatLeaf<(i32 0x7)>;
45 def CvtRP : PatLeaf<(i32 0x8)>;
47 def CvtNONE_FTZ : PatLeaf<(i32 0x10)>;
48 def CvtRNI_FTZ : PatLeaf<(i32 0x11)>;
49 def CvtRZI_FTZ : PatLeaf<(i32 0x12)>;
50 def CvtRMI_FTZ : PatLeaf<(i32 0x13)>;
51 def CvtRPI_FTZ : PatLeaf<(i32 0x14)>;
52 def CvtRN_FTZ : PatLeaf<(i32 0x15)>;
53 def CvtRZ_FTZ : PatLeaf<(i32 0x16)>;
54 def CvtRM_FTZ : PatLeaf<(i32 0x17)>;
55 def CvtRP_FTZ : PatLeaf<(i32 0x18)>;
57 def CvtSAT : PatLeaf<(i32 0x20)>;
58 def CvtSAT_FTZ : PatLeaf<(i32 0x30)>;
60 def CvtMode : Operand<i32> {
61 let PrintMethod = "printCvtMode";
65 // These must match the enum in NVPTX.h
66 def CmpEQ : PatLeaf<(i32 0)>;
67 def CmpNE : PatLeaf<(i32 1)>;
68 def CmpLT : PatLeaf<(i32 2)>;
69 def CmpLE : PatLeaf<(i32 3)>;
70 def CmpGT : PatLeaf<(i32 4)>;
71 def CmpGE : PatLeaf<(i32 5)>;
72 def CmpLO : PatLeaf<(i32 6)>;
73 def CmpLS : PatLeaf<(i32 7)>;
74 def CmpHI : PatLeaf<(i32 8)>;
75 def CmpHS : PatLeaf<(i32 9)>;
76 def CmpEQU : PatLeaf<(i32 10)>;
77 def CmpNEU : PatLeaf<(i32 11)>;
78 def CmpLTU : PatLeaf<(i32 12)>;
79 def CmpLEU : PatLeaf<(i32 13)>;
80 def CmpGTU : PatLeaf<(i32 14)>;
81 def CmpGEU : PatLeaf<(i32 15)>;
82 def CmpNUM : PatLeaf<(i32 16)>;
83 def CmpNAN : PatLeaf<(i32 17)>;
85 def CmpEQ_FTZ : PatLeaf<(i32 0x100)>;
86 def CmpNE_FTZ : PatLeaf<(i32 0x101)>;
87 def CmpLT_FTZ : PatLeaf<(i32 0x102)>;
88 def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
89 def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
90 def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
91 def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
92 def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
93 def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
94 def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
95 def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
96 def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
97 def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
98 def CmpLEU_FTZ : PatLeaf<(i32 0x10D)>;
99 def CmpGTU_FTZ : PatLeaf<(i32 0x10E)>;
100 def CmpGEU_FTZ : PatLeaf<(i32 0x10F)>;
101 def CmpNUM_FTZ : PatLeaf<(i32 0x110)>;
102 def CmpNAN_FTZ : PatLeaf<(i32 0x111)>;
104 def CmpMode : Operand<i32> {
105 let PrintMethod = "printCmpMode";
108 def F32ConstZero : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
109 return CurDAG->getTargetConstantFP(0.0, MVT::f32);
111 def F32ConstOne : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
112 return CurDAG->getTargetConstantFP(1.0, MVT::f32);
115 //===----------------------------------------------------------------------===//
116 // NVPTX Instruction Predicate Definitions
117 //===----------------------------------------------------------------------===//
120 def hasAtomRedG32 : Predicate<"Subtarget.hasAtomRedG32()">;
121 def hasAtomRedS32 : Predicate<"Subtarget.hasAtomRedS32()">;
122 def hasAtomRedGen32 : Predicate<"Subtarget.hasAtomRedGen32()">;
123 def useAtomRedG32forGen32 :
124 Predicate<"!Subtarget.hasAtomRedGen32() && Subtarget.hasAtomRedG32()">;
125 def hasBrkPt : Predicate<"Subtarget.hasBrkPt()">;
126 def hasAtomRedG64 : Predicate<"Subtarget.hasAtomRedG64()">;
127 def hasAtomRedS64 : Predicate<"Subtarget.hasAtomRedS64()">;
128 def hasAtomRedGen64 : Predicate<"Subtarget.hasAtomRedGen64()">;
129 def useAtomRedG64forGen64 :
130 Predicate<"!Subtarget.hasAtomRedGen64() && Subtarget.hasAtomRedG64()">;
131 def hasAtomAddF32 : Predicate<"Subtarget.hasAtomAddF32()">;
132 def hasVote : Predicate<"Subtarget.hasVote()">;
133 def hasDouble : Predicate<"Subtarget.hasDouble()">;
134 def reqPTX20 : Predicate<"Subtarget.reqPTX20()">;
135 def hasLDG : Predicate<"Subtarget.hasLDG()">;
136 def hasLDU : Predicate<"Subtarget.hasLDU()">;
137 def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">;
139 def doF32FTZ : Predicate<"UseF32FTZ">;
141 def doFMAF32 : Predicate<"doFMAF32">;
142 def doFMAF32_ftz : Predicate<"(doFMAF32 && UseF32FTZ)">;
143 def doFMAF32AGG : Predicate<"doFMAF32AGG">;
144 def doFMAF32AGG_ftz : Predicate<"(doFMAF32AGG && UseF32FTZ)">;
145 def doFMAF64 : Predicate<"doFMAF64">;
146 def doFMAF64AGG : Predicate<"doFMAF64AGG">;
147 def doFMADF32 : Predicate<"doFMADF32">;
148 def doFMADF32_ftz : Predicate<"(doFMADF32 && UseF32FTZ)">;
150 def doMulWide : Predicate<"doMulWide">;
152 def allowFMA : Predicate<"allowFMA">;
153 def allowFMA_ftz : Predicate<"(allowFMA && UseF32FTZ)">;
155 def do_DIVF32_APPROX : Predicate<"do_DIVF32_PREC==0">;
156 def do_DIVF32_FULL : Predicate<"do_DIVF32_PREC==1">;
158 def do_SQRTF32_APPROX : Predicate<"do_SQRTF32_PREC==0">;
159 def do_SQRTF32_RN : Predicate<"do_SQRTF32_PREC==1">;
161 def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
163 def true : Predicate<"1">;
166 //===----------------------------------------------------------------------===//
167 // Some Common Instruction Class Templates
168 //===----------------------------------------------------------------------===//
170 multiclass I3<string OpcStr, SDNode OpNode> {
171 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
172 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
173 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
175 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
176 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
177 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
178 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
179 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
180 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
182 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
183 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
184 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
185 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
186 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
187 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
189 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
190 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
191 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
194 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
195 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
197 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
198 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
200 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
201 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
202 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
205 multiclass F3<string OpcStr, SDNode OpNode> {
206 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
207 (ins Float64Regs:$a, Float64Regs:$b),
208 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
209 [(set Float64Regs:$dst,
210 (OpNode Float64Regs:$a, Float64Regs:$b))]>,
211 Requires<[allowFMA]>;
212 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
213 (ins Float64Regs:$a, f64imm:$b),
214 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
215 [(set Float64Regs:$dst,
216 (OpNode Float64Regs:$a, fpimm:$b))]>,
217 Requires<[allowFMA]>;
218 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
219 (ins Float32Regs:$a, Float32Regs:$b),
220 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
221 [(set Float32Regs:$dst,
222 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
223 Requires<[allowFMA_ftz]>;
224 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
225 (ins Float32Regs:$a, f32imm:$b),
226 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
227 [(set Float32Regs:$dst,
228 (OpNode Float32Regs:$a, fpimm:$b))]>,
229 Requires<[allowFMA_ftz]>;
230 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
231 (ins Float32Regs:$a, Float32Regs:$b),
232 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
233 [(set Float32Regs:$dst,
234 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
235 Requires<[allowFMA]>;
236 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
237 (ins Float32Regs:$a, f32imm:$b),
238 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
239 [(set Float32Regs:$dst,
240 (OpNode Float32Regs:$a, fpimm:$b))]>,
241 Requires<[allowFMA]>;
244 multiclass F3_rn<string OpcStr, SDNode OpNode> {
245 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
246 (ins Float64Regs:$a, Float64Regs:$b),
247 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
248 [(set Float64Regs:$dst,
249 (OpNode Float64Regs:$a, Float64Regs:$b))]>;
250 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
251 (ins Float64Regs:$a, f64imm:$b),
252 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
253 [(set Float64Regs:$dst,
254 (OpNode Float64Regs:$a, fpimm:$b))]>;
255 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
256 (ins Float32Regs:$a, Float32Regs:$b),
257 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
258 [(set Float32Regs:$dst,
259 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
260 Requires<[doF32FTZ]>;
261 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
262 (ins Float32Regs:$a, f32imm:$b),
263 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
264 [(set Float32Regs:$dst,
265 (OpNode Float32Regs:$a, fpimm:$b))]>,
266 Requires<[doF32FTZ]>;
267 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
268 (ins Float32Regs:$a, Float32Regs:$b),
269 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
270 [(set Float32Regs:$dst,
271 (OpNode Float32Regs:$a, Float32Regs:$b))]>;
272 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
273 (ins Float32Regs:$a, f32imm:$b),
274 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
275 [(set Float32Regs:$dst,
276 (OpNode Float32Regs:$a, fpimm:$b))]>;
279 multiclass F2<string OpcStr, SDNode OpNode> {
280 def f64 : NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$a),
281 !strconcat(OpcStr, ".f64 \t$dst, $a;"),
282 [(set Float64Regs:$dst, (OpNode Float64Regs:$a))]>;
283 def f32_ftz : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
284 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a;"),
285 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>,
286 Requires<[doF32FTZ]>;
287 def f32 : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
288 !strconcat(OpcStr, ".f32 \t$dst, $a;"),
289 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
292 //===----------------------------------------------------------------------===//
293 // NVPTX Instructions.
294 //===----------------------------------------------------------------------===//
296 //-----------------------------------
297 // General Type Conversion
298 //-----------------------------------
300 // Generate a cvt to the given type from all possible types.
301 // Each instance takes a CvtMode immediate that defines the conversion mode to
302 // use. It can be CvtNONE to omit a conversion mode.
303 multiclass CVT_FROM_ALL<string FromName, RegisterClass RC> {
304 def _s16 : NVPTXInst<(outs RC:$dst),
305 (ins Int16Regs:$src, CvtMode:$mode),
306 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
307 FromName, ".s16\t$dst, $src;"),
309 def _u16 : NVPTXInst<(outs RC:$dst),
310 (ins Int16Regs:$src, CvtMode:$mode),
311 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
312 FromName, ".u16\t$dst, $src;"),
314 def _f16 : NVPTXInst<(outs RC:$dst),
315 (ins Int16Regs:$src, CvtMode:$mode),
316 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
317 FromName, ".f16\t$dst, $src;"),
319 def _s32 : NVPTXInst<(outs RC:$dst),
320 (ins Int32Regs:$src, CvtMode:$mode),
321 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
322 FromName, ".s32\t$dst, $src;"),
324 def _u32 : NVPTXInst<(outs RC:$dst),
325 (ins Int32Regs:$src, CvtMode:$mode),
326 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
327 FromName, ".u32\t$dst, $src;"),
329 def _s64 : NVPTXInst<(outs RC:$dst),
330 (ins Int64Regs:$src, CvtMode:$mode),
331 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
332 FromName, ".s64\t$dst, $src;"),
334 def _u64 : NVPTXInst<(outs RC:$dst),
335 (ins Int64Regs:$src, CvtMode:$mode),
336 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
337 FromName, ".u64\t$dst, $src;"),
339 def _f32 : NVPTXInst<(outs RC:$dst),
340 (ins Float32Regs:$src, CvtMode:$mode),
341 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
342 FromName, ".f32\t$dst, $src;"),
344 def _f64 : NVPTXInst<(outs RC:$dst),
345 (ins Float64Regs:$src, CvtMode:$mode),
346 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
347 FromName, ".f64\t$dst, $src;"),
351 // Generate a cvt to all possible types.
352 defm CVT_s16 : CVT_FROM_ALL<"s16", Int16Regs>;
353 defm CVT_u16 : CVT_FROM_ALL<"u16", Int16Regs>;
354 defm CVT_f16 : CVT_FROM_ALL<"f16", Int16Regs>;
355 defm CVT_s32 : CVT_FROM_ALL<"s32", Int32Regs>;
356 defm CVT_u32 : CVT_FROM_ALL<"u32", Int32Regs>;
357 defm CVT_s64 : CVT_FROM_ALL<"s64", Int64Regs>;
358 defm CVT_u64 : CVT_FROM_ALL<"u64", Int64Regs>;
359 defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
360 defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
362 //-----------------------------------
363 // Integer Arithmetic
364 //-----------------------------------
366 multiclass ADD_SUB_i1<SDNode OpNode> {
367 def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
368 "xor.pred \t$dst, $a, $b;",
369 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
370 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
371 "xor.pred \t$dst, $a, $b;",
372 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, (imm):$b))]>;
375 defm ADD_i1 : ADD_SUB_i1<add>;
376 defm SUB_i1 : ADD_SUB_i1<sub>;
379 defm ADD : I3<"add.s", add>;
380 defm SUB : I3<"sub.s", sub>;
382 defm ADDCC : ADD_SUB_INT_32<"add.cc", addc>;
383 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
385 defm ADDCCC : ADD_SUB_INT_32<"addc.cc", adde>;
386 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
388 //mul.wide PTX instruction
389 def SInt32Const : PatLeaf<(imm), [{
390 const APInt &v = N->getAPIntValue();
391 if (v.isSignedIntN(32))
396 def UInt32Const : PatLeaf<(imm), [{
397 const APInt &v = N->getAPIntValue();
403 def SInt16Const : PatLeaf<(imm), [{
404 const APInt &v = N->getAPIntValue();
405 if (v.isSignedIntN(16))
410 def UInt16Const : PatLeaf<(imm), [{
411 const APInt &v = N->getAPIntValue();
417 def Int5Const : PatLeaf<(imm), [{
418 const APInt &v = N->getAPIntValue();
419 // Check if 0 <= v < 32
420 // Only then the result from (x << v) will be i32
421 if (v.sge(0) && v.slt(32))
426 def Int4Const : PatLeaf<(imm), [{
427 const APInt &v = N->getAPIntValue();
428 // Check if 0 <= v < 16
429 // Only then the result from (x << v) will be i16
430 if (v.sge(0) && v.slt(16))
435 def SHL2MUL32 : SDNodeXForm<imm, [{
436 const APInt &v = N->getAPIntValue();
438 return CurDAG->getTargetConstant(temp.shl(v), MVT::i32);
441 def SHL2MUL16 : SDNodeXForm<imm, [{
442 const APInt &v = N->getAPIntValue();
444 return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
447 def MULWIDES64 : NVPTXInst<(outs Int64Regs:$dst),
448 (ins Int32Regs:$a, Int32Regs:$b),
449 "mul.wide.s32 \t$dst, $a, $b;", []>;
450 def MULWIDES64Imm : NVPTXInst<(outs Int64Regs:$dst),
451 (ins Int32Regs:$a, i64imm:$b),
452 "mul.wide.s32 \t$dst, $a, $b;", []>;
454 def MULWIDEU64 : NVPTXInst<(outs Int64Regs:$dst),
455 (ins Int32Regs:$a, Int32Regs:$b),
456 "mul.wide.u32 \t$dst, $a, $b;", []>;
457 def MULWIDEU64Imm : NVPTXInst<(outs Int64Regs:$dst),
458 (ins Int32Regs:$a, i64imm:$b),
459 "mul.wide.u32 \t$dst, $a, $b;", []>;
461 def MULWIDES32 : NVPTXInst<(outs Int32Regs:$dst),
462 (ins Int16Regs:$a, Int16Regs:$b),
463 "mul.wide.s16 \t$dst, $a, $b;", []>;
464 def MULWIDES32Imm : NVPTXInst<(outs Int32Regs:$dst),
465 (ins Int16Regs:$a, i32imm:$b),
466 "mul.wide.s16 \t$dst, $a, $b;", []>;
468 def MULWIDEU32 : NVPTXInst<(outs Int32Regs:$dst),
469 (ins Int16Regs:$a, Int16Regs:$b),
470 "mul.wide.u16 \t$dst, $a, $b;", []>;
471 def MULWIDEU32Imm : NVPTXInst<(outs Int32Regs:$dst),
472 (ins Int16Regs:$a, i32imm:$b),
473 "mul.wide.u16 \t$dst, $a, $b;", []>;
475 def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
476 (MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
477 Requires<[doMulWide]>;
478 def : Pat<(shl (zext Int32Regs:$a), (i32 Int5Const:$b)),
479 (MULWIDEU64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
480 Requires<[doMulWide]>;
482 def : Pat<(shl (sext Int16Regs:$a), (i16 Int4Const:$b)),
483 (MULWIDES32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
484 Requires<[doMulWide]>;
485 def : Pat<(shl (zext Int16Regs:$a), (i16 Int4Const:$b)),
486 (MULWIDEU32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
487 Requires<[doMulWide]>;
489 def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
490 (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
491 Requires<[doMulWide]>;
492 def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
493 (MULWIDES64Imm Int32Regs:$a, (i64 SInt32Const:$b))>,
494 Requires<[doMulWide]>;
496 def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
497 (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>, Requires<[doMulWide]>;
498 def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
499 (MULWIDEU64Imm Int32Regs:$a, (i64 UInt32Const:$b))>,
500 Requires<[doMulWide]>;
502 def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
503 (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
504 def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
505 (MULWIDES32Imm Int16Regs:$a, (i32 SInt16Const:$b))>,
506 Requires<[doMulWide]>;
508 def : Pat<(mul (zext Int16Regs:$a), (zext Int16Regs:$b)),
509 (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
510 def : Pat<(mul (zext Int16Regs:$a), (i32 UInt16Const:$b)),
511 (MULWIDEU32Imm Int16Regs:$a, (i32 UInt16Const:$b))>,
512 Requires<[doMulWide]>;
514 defm MULT : I3<"mul.lo.s", mul>;
516 defm MULTHS : I3<"mul.hi.s", mulhs>;
517 defm MULTHU : I3<"mul.hi.u", mulhu>;
519 defm SDIV : I3<"div.s", sdiv>;
520 defm UDIV : I3<"div.u", udiv>;
522 defm SREM : I3<"rem.s", srem>;
523 // The ri version will not be selected as DAGCombiner::visitSREM will lower it.
524 defm UREM : I3<"rem.u", urem>;
525 // The ri version will not be selected as DAGCombiner::visitUREM will lower it.
527 def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
528 (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
529 "mad.lo.s16 \t$dst, $a, $b, $c;",
530 [(set Int16Regs:$dst, (add
531 (mul Int16Regs:$a, Int16Regs:$b), Int16Regs:$c))]>;
532 def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
533 (ins Int16Regs:$a, Int16Regs:$b, i16imm:$c),
534 "mad.lo.s16 \t$dst, $a, $b, $c;",
535 [(set Int16Regs:$dst, (add
536 (mul Int16Regs:$a, Int16Regs:$b), imm:$c))]>;
537 def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
538 (ins Int16Regs:$a, i16imm:$b, Int16Regs:$c),
539 "mad.lo.s16 \t$dst, $a, $b, $c;",
540 [(set Int16Regs:$dst, (add
541 (mul Int16Regs:$a, imm:$b), Int16Regs:$c))]>;
542 def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
543 (ins Int16Regs:$a, i16imm:$b, i16imm:$c),
544 "mad.lo.s16 \t$dst, $a, $b, $c;",
545 [(set Int16Regs:$dst, (add (mul Int16Regs:$a, imm:$b),
548 def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
549 (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
550 "mad.lo.s32 \t$dst, $a, $b, $c;",
551 [(set Int32Regs:$dst, (add
552 (mul Int32Regs:$a, Int32Regs:$b), Int32Regs:$c))]>;
553 def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
554 (ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
555 "mad.lo.s32 \t$dst, $a, $b, $c;",
556 [(set Int32Regs:$dst, (add
557 (mul Int32Regs:$a, Int32Regs:$b), imm:$c))]>;
558 def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
559 (ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
560 "mad.lo.s32 \t$dst, $a, $b, $c;",
561 [(set Int32Regs:$dst, (add
562 (mul Int32Regs:$a, imm:$b), Int32Regs:$c))]>;
563 def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
564 (ins Int32Regs:$a, i32imm:$b, i32imm:$c),
565 "mad.lo.s32 \t$dst, $a, $b, $c;",
566 [(set Int32Regs:$dst, (add
567 (mul Int32Regs:$a, imm:$b), imm:$c))]>;
569 def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
570 (ins Int64Regs:$a, Int64Regs:$b, Int64Regs:$c),
571 "mad.lo.s64 \t$dst, $a, $b, $c;",
572 [(set Int64Regs:$dst, (add
573 (mul Int64Regs:$a, Int64Regs:$b), Int64Regs:$c))]>;
574 def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
575 (ins Int64Regs:$a, Int64Regs:$b, i64imm:$c),
576 "mad.lo.s64 \t$dst, $a, $b, $c;",
577 [(set Int64Regs:$dst, (add
578 (mul Int64Regs:$a, Int64Regs:$b), imm:$c))]>;
579 def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
580 (ins Int64Regs:$a, i64imm:$b, Int64Regs:$c),
581 "mad.lo.s64 \t$dst, $a, $b, $c;",
582 [(set Int64Regs:$dst, (add
583 (mul Int64Regs:$a, imm:$b), Int64Regs:$c))]>;
584 def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
585 (ins Int64Regs:$a, i64imm:$b, i64imm:$c),
586 "mad.lo.s64 \t$dst, $a, $b, $c;",
587 [(set Int64Regs:$dst, (add
588 (mul Int64Regs:$a, imm:$b), imm:$c))]>;
591 def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
592 "neg.s16 \t$dst, $src;",
593 [(set Int16Regs:$dst, (ineg Int16Regs:$src))]>;
594 def INEG32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
595 "neg.s32 \t$dst, $src;",
596 [(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
597 def INEG64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
598 "neg.s64 \t$dst, $src;",
599 [(set Int64Regs:$dst, (ineg Int64Regs:$src))]>;
601 //-----------------------------------
602 // Floating Point Arithmetic
603 //-----------------------------------
606 def FloatConst1 : PatLeaf<(fpimm), [{
607 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEsingle)
609 float f = (float)N->getValueAPF().convertToFloat();
612 // Constand (double)1.0
613 def DoubleConst1 : PatLeaf<(fpimm), [{
614 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEdouble)
616 double d = (double)N->getValueAPF().convertToDouble();
620 defm FADD : F3<"add", fadd>;
621 defm FSUB : F3<"sub", fsub>;
622 defm FMUL : F3<"mul", fmul>;
624 defm FADD_rn : F3_rn<"add", fadd>;
625 defm FSUB_rn : F3_rn<"sub", fsub>;
626 defm FMUL_rn : F3_rn<"mul", fmul>;
628 defm FABS : F2<"abs", fabs>;
629 defm FNEG : F2<"neg", fneg>;
630 defm FSQRT : F2<"sqrt.rn", fsqrt>;
635 def FDIV641r : NVPTXInst<(outs Float64Regs:$dst),
636 (ins f64imm:$a, Float64Regs:$b),
637 "rcp.rn.f64 \t$dst, $b;",
638 [(set Float64Regs:$dst,
639 (fdiv DoubleConst1:$a, Float64Regs:$b))]>;
640 def FDIV64rr : NVPTXInst<(outs Float64Regs:$dst),
641 (ins Float64Regs:$a, Float64Regs:$b),
642 "div.rn.f64 \t$dst, $a, $b;",
643 [(set Float64Regs:$dst,
644 (fdiv Float64Regs:$a, Float64Regs:$b))]>;
645 def FDIV64ri : NVPTXInst<(outs Float64Regs:$dst),
646 (ins Float64Regs:$a, f64imm:$b),
647 "div.rn.f64 \t$dst, $a, $b;",
648 [(set Float64Regs:$dst,
649 (fdiv Float64Regs:$a, fpimm:$b))]>;
652 // F32 Approximate reciprocal
654 def FDIV321r_ftz : NVPTXInst<(outs Float32Regs:$dst),
655 (ins f32imm:$a, Float32Regs:$b),
656 "rcp.approx.ftz.f32 \t$dst, $b;",
657 [(set Float32Regs:$dst,
658 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
659 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
660 def FDIV321r : NVPTXInst<(outs Float32Regs:$dst),
661 (ins f32imm:$a, Float32Regs:$b),
662 "rcp.approx.f32 \t$dst, $b;",
663 [(set Float32Regs:$dst,
664 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
665 Requires<[do_DIVF32_APPROX]>;
667 // F32 Approximate division
669 def FDIV32approxrr_ftz : NVPTXInst<(outs Float32Regs:$dst),
670 (ins Float32Regs:$a, Float32Regs:$b),
671 "div.approx.ftz.f32 \t$dst, $a, $b;",
672 [(set Float32Regs:$dst,
673 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
674 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
675 def FDIV32approxrr : NVPTXInst<(outs Float32Regs:$dst),
676 (ins Float32Regs:$a, Float32Regs:$b),
677 "div.approx.f32 \t$dst, $a, $b;",
678 [(set Float32Regs:$dst,
679 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
680 Requires<[do_DIVF32_APPROX]>;
682 // F32 Semi-accurate reciprocal
684 // rcp.approx gives the same result as div.full(1.0f, a) and is faster.
686 def FDIV321r_approx_ftz : NVPTXInst<(outs Float32Regs:$dst),
687 (ins f32imm:$a, Float32Regs:$b),
688 "rcp.approx.ftz.f32 \t$dst, $b;",
689 [(set Float32Regs:$dst,
690 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
691 Requires<[do_DIVF32_FULL, doF32FTZ]>;
692 def FDIV321r_approx : NVPTXInst<(outs Float32Regs:$dst),
693 (ins f32imm:$a, Float32Regs:$b),
694 "rcp.approx.f32 \t$dst, $b;",
695 [(set Float32Regs:$dst,
696 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
697 Requires<[do_DIVF32_FULL]>;
699 // F32 Semi-accurate division
701 def FDIV32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
702 (ins Float32Regs:$a, Float32Regs:$b),
703 "div.full.ftz.f32 \t$dst, $a, $b;",
704 [(set Float32Regs:$dst,
705 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
706 Requires<[do_DIVF32_FULL, doF32FTZ]>;
707 def FDIV32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
708 (ins Float32Regs:$a, f32imm:$b),
709 "div.full.ftz.f32 \t$dst, $a, $b;",
710 [(set Float32Regs:$dst,
711 (fdiv Float32Regs:$a, fpimm:$b))]>,
712 Requires<[do_DIVF32_FULL, doF32FTZ]>;
713 def FDIV32rr : NVPTXInst<(outs Float32Regs:$dst),
714 (ins Float32Regs:$a, Float32Regs:$b),
715 "div.full.f32 \t$dst, $a, $b;",
716 [(set Float32Regs:$dst,
717 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
718 Requires<[do_DIVF32_FULL]>;
719 def FDIV32ri : NVPTXInst<(outs Float32Regs:$dst),
720 (ins Float32Regs:$a, f32imm:$b),
721 "div.full.f32 \t$dst, $a, $b;",
722 [(set Float32Regs:$dst,
723 (fdiv Float32Regs:$a, fpimm:$b))]>,
724 Requires<[do_DIVF32_FULL]>;
726 // F32 Accurate reciprocal
728 def FDIV321r_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
729 (ins f32imm:$a, Float32Regs:$b),
730 "rcp.rn.ftz.f32 \t$dst, $b;",
731 [(set Float32Regs:$dst,
732 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
733 Requires<[reqPTX20, doF32FTZ]>;
734 def FDIV321r_prec : NVPTXInst<(outs Float32Regs:$dst),
735 (ins f32imm:$a, Float32Regs:$b),
736 "rcp.rn.f32 \t$dst, $b;",
737 [(set Float32Regs:$dst,
738 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
739 Requires<[reqPTX20]>;
741 // F32 Accurate division
743 def FDIV32rr_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
744 (ins Float32Regs:$a, Float32Regs:$b),
745 "div.rn.ftz.f32 \t$dst, $a, $b;",
746 [(set Float32Regs:$dst,
747 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
748 Requires<[doF32FTZ, reqPTX20]>;
749 def FDIV32ri_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
750 (ins Float32Regs:$a, f32imm:$b),
751 "div.rn.ftz.f32 \t$dst, $a, $b;",
752 [(set Float32Regs:$dst,
753 (fdiv Float32Regs:$a, fpimm:$b))]>,
754 Requires<[doF32FTZ, reqPTX20]>;
755 def FDIV32rr_prec : NVPTXInst<(outs Float32Regs:$dst),
756 (ins Float32Regs:$a, Float32Regs:$b),
757 "div.rn.f32 \t$dst, $a, $b;",
758 [(set Float32Regs:$dst,
759 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
760 Requires<[reqPTX20]>;
761 def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
762 (ins Float32Regs:$a, f32imm:$b),
763 "div.rn.f32 \t$dst, $a, $b;",
764 [(set Float32Regs:$dst,
765 (fdiv Float32Regs:$a, fpimm:$b))]>,
766 Requires<[reqPTX20]>;
769 multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
770 def rrr : NVPTXInst<(outs Float32Regs:$dst),
771 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
772 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
773 [(set Float32Regs:$dst, (fadd
774 (fmul Float32Regs:$a, Float32Regs:$b),
775 Float32Regs:$c))]>, Requires<[Pred]>;
776 // This is to WAR a weird bug in Tablegen that does not automatically
777 // generate the following permutated rule rrr2 from the above rrr.
778 // So we explicitly add it here. This happens to FMA32 only.
779 // See the comments at FMAD32 and FMA32 for more information.
780 def rrr2 : NVPTXInst<(outs Float32Regs:$dst),
781 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
782 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
783 [(set Float32Regs:$dst, (fadd Float32Regs:$c,
784 (fmul Float32Regs:$a, Float32Regs:$b)))]>,
786 def rri : NVPTXInst<(outs Float32Regs:$dst),
787 (ins Float32Regs:$a, Float32Regs:$b, f32imm:$c),
788 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
789 [(set Float32Regs:$dst, (fadd
790 (fmul Float32Regs:$a, Float32Regs:$b), fpimm:$c))]>,
792 def rir : NVPTXInst<(outs Float32Regs:$dst),
793 (ins Float32Regs:$a, f32imm:$b, Float32Regs:$c),
794 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
795 [(set Float32Regs:$dst, (fadd
796 (fmul Float32Regs:$a, fpimm:$b), Float32Regs:$c))]>,
798 def rii : NVPTXInst<(outs Float32Regs:$dst),
799 (ins Float32Regs:$a, f32imm:$b, f32imm:$c),
800 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
801 [(set Float32Regs:$dst, (fadd
802 (fmul Float32Regs:$a, fpimm:$b), fpimm:$c))]>,
806 multiclass FPCONTRACT64<string OpcStr, Predicate Pred> {
807 def rrr : NVPTXInst<(outs Float64Regs:$dst),
808 (ins Float64Regs:$a, Float64Regs:$b, Float64Regs:$c),
809 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
810 [(set Float64Regs:$dst, (fadd
811 (fmul Float64Regs:$a, Float64Regs:$b),
812 Float64Regs:$c))]>, Requires<[Pred]>;
813 def rri : NVPTXInst<(outs Float64Regs:$dst),
814 (ins Float64Regs:$a, Float64Regs:$b, f64imm:$c),
815 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
816 [(set Float64Regs:$dst, (fadd (fmul Float64Regs:$a,
817 Float64Regs:$b), fpimm:$c))]>, Requires<[Pred]>;
818 def rir : NVPTXInst<(outs Float64Regs:$dst),
819 (ins Float64Regs:$a, f64imm:$b, Float64Regs:$c),
820 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
821 [(set Float64Regs:$dst, (fadd
822 (fmul Float64Regs:$a, fpimm:$b), Float64Regs:$c))]>,
824 def rii : NVPTXInst<(outs Float64Regs:$dst),
825 (ins Float64Regs:$a, f64imm:$b, f64imm:$c),
826 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
827 [(set Float64Regs:$dst, (fadd
828 (fmul Float64Regs:$a, fpimm:$b), fpimm:$c))]>,
832 // Due to a unknown reason (most likely a bug in tablegen), tablegen does not
833 // automatically generate the rrr2 rule from
834 // the rrr rule (see FPCONTRACT32) for FMA32, though it does for FMAD32.
835 // If we reverse the order of the following two lines, then rrr2 rule will be
836 // generated for FMA32, but not for rrr.
837 // Therefore, we manually write the rrr2 rule in FPCONTRACT32.
838 defm FMAD32_ftz : FPCONTRACT32<"mad.ftz.f32", doFMADF32_ftz>;
839 defm FMAD32 : FPCONTRACT32<"mad.f32", doFMADF32>;
840 defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doFMAF32_ftz>;
841 defm FMA32 : FPCONTRACT32<"fma.rn.f32", doFMAF32>;
842 defm FMA64 : FPCONTRACT64<"fma.rn.f64", doFMAF64>;
844 // b*c-a => fmad(b, c, -a)
845 multiclass FPCONTRACT32_SUB_PAT_MAD<NVPTXInst Inst, Predicate Pred> {
846 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
847 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
851 // a-b*c => fmad(-b,c, a)
852 // - legal because a-b*c <=> a+(-b*c) <=> a+(-b)*c
853 // b*c-a => fmad(b, c, -a)
854 // - legal because b*c-a <=> b*c+(-a)
855 multiclass FPCONTRACT32_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
856 def : Pat<(fsub Float32Regs:$a, (fmul Float32Regs:$b, Float32Regs:$c)),
857 (Inst (FNEGf32 Float32Regs:$b), Float32Regs:$c, Float32Regs:$a)>,
859 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
860 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
864 // a-b*c => fmad(-b,c, a)
865 // b*c-a => fmad(b, c, -a)
866 multiclass FPCONTRACT64_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
867 def : Pat<(fsub Float64Regs:$a, (fmul Float64Regs:$b, Float64Regs:$c)),
868 (Inst (FNEGf64 Float64Regs:$b), Float64Regs:$c, Float64Regs:$a)>,
871 def : Pat<(fsub (fmul Float64Regs:$b, Float64Regs:$c), Float64Regs:$a),
872 (Inst Float64Regs:$b, Float64Regs:$c, (FNEGf64 Float64Regs:$a))>,
876 defm FMAF32ext_ftz : FPCONTRACT32_SUB_PAT<FMA32_ftzrrr, doFMAF32AGG_ftz>;
877 defm FMAF32ext : FPCONTRACT32_SUB_PAT<FMA32rrr, doFMAF32AGG>;
878 defm FMADF32ext_ftz : FPCONTRACT32_SUB_PAT_MAD<FMAD32_ftzrrr, doFMADF32_ftz>;
879 defm FMADF32ext : FPCONTRACT32_SUB_PAT_MAD<FMAD32rrr, doFMADF32>;
880 defm FMAF64ext : FPCONTRACT64_SUB_PAT<FMA64rrr, doFMAF64AGG>;
882 def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
883 "sin.approx.f32 \t$dst, $src;",
884 [(set Float32Regs:$dst, (fsin Float32Regs:$src))]>;
885 def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
886 "cos.approx.f32 \t$dst, $src;",
887 [(set Float32Regs:$dst, (fcos Float32Regs:$src))]>;
889 // Lower (frem x, y) into (sub x, (mul (floor (div x, y)) y))
890 // e.g. "poor man's fmod()"
893 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
894 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
895 (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRMI_FTZ),
897 Requires<[doF32FTZ]>;
898 def : Pat<(frem Float32Regs:$x, fpimm:$y),
899 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
900 (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRMI_FTZ),
902 Requires<[doF32FTZ]>;
905 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
906 (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
907 (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRMI),
909 def : Pat<(frem Float32Regs:$x, fpimm:$y),
910 (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
911 (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRMI),
915 def : Pat<(frem Float64Regs:$x, Float64Regs:$y),
916 (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
917 (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRMI),
919 def : Pat<(frem Float64Regs:$x, fpimm:$y),
920 (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
921 (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRMI),
924 //-----------------------------------
925 // Logical Arithmetic
926 //-----------------------------------
928 multiclass LOG_FORMAT<string OpcStr, SDNode OpNode> {
929 def b1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
930 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
931 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
932 def b1ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
933 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
934 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, imm:$b))]>;
935 def b16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
936 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
937 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
939 def b16ri: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
940 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
941 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, imm:$b))]>;
942 def b32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
943 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
944 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
946 def b32ri: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
947 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
948 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
949 def b64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
950 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
951 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
953 def b64ri: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
954 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
955 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
958 defm OR : LOG_FORMAT<"or", or>;
959 defm AND : LOG_FORMAT<"and", and>;
960 defm XOR : LOG_FORMAT<"xor", xor>;
962 def NOT1: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
963 "not.pred \t$dst, $src;",
964 [(set Int1Regs:$dst, (not Int1Regs:$src))]>;
965 def NOT16: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
966 "not.b16 \t$dst, $src;",
967 [(set Int16Regs:$dst, (not Int16Regs:$src))]>;
968 def NOT32: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
969 "not.b32 \t$dst, $src;",
970 [(set Int32Regs:$dst, (not Int32Regs:$src))]>;
971 def NOT64: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
972 "not.b64 \t$dst, $src;",
973 [(set Int64Regs:$dst, (not Int64Regs:$src))]>;
975 // For shifts, the second src operand must be 32-bit value
976 multiclass LSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
977 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
979 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
980 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
982 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
983 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
984 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
986 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
988 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
989 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
991 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
992 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
993 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
995 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
996 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
997 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
999 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1001 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1002 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1004 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1005 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1006 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1010 defm SHL : LSHIFT_FORMAT<"shl.b", shl>;
1012 // For shifts, the second src operand must be 32-bit value
1013 // Need to add cvt for the 8-bits.
1014 multiclass RSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1015 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1017 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1018 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1020 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1021 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1022 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1024 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1026 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1027 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1029 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1030 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1031 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1033 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1034 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1035 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1037 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1039 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1040 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1042 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1043 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1044 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1048 defm SRA : RSHIFT_FORMAT<"shr.s", sra>;
1049 defm SRL : RSHIFT_FORMAT<"shr.u", srl>;
1052 def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
1053 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1054 !strconcat("{{\n\t",
1055 !strconcat(".reg .b32 %lhs;\n\t",
1056 !strconcat(".reg .b32 %rhs;\n\t",
1057 !strconcat("shl.b32 \t%lhs, $src, $amt1;\n\t",
1058 !strconcat("shr.b32 \t%rhs, $src, $amt2;\n\t",
1059 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1060 !strconcat("}}", ""))))))),
1063 def SUB_FRM_32 : SDNodeXForm<imm, [{
1064 return CurDAG->getTargetConstant(32-N->getZExtValue(), MVT::i32);
1067 def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
1068 (ROT32imm_sw Int32Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>;
1069 def : Pat<(rotr Int32Regs:$src, (i32 imm:$amt)),
1070 (ROT32imm_sw Int32Regs:$src, (SUB_FRM_32 node:$amt), imm:$amt)>;
1072 def ROTL32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1074 !strconcat("{{\n\t",
1075 !strconcat(".reg .b32 %lhs;\n\t",
1076 !strconcat(".reg .b32 %rhs;\n\t",
1077 !strconcat(".reg .b32 %amt2;\n\t",
1078 !strconcat("shl.b32 \t%lhs, $src, $amt;\n\t",
1079 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1080 !strconcat("shr.b32 \t%rhs, $src, %amt2;\n\t",
1081 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1082 !strconcat("}}", ""))))))))),
1083 [(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>;
1085 def ROTR32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1087 !strconcat("{{\n\t",
1088 !strconcat(".reg .b32 %lhs;\n\t",
1089 !strconcat(".reg .b32 %rhs;\n\t",
1090 !strconcat(".reg .b32 %amt2;\n\t",
1091 !strconcat("shr.b32 \t%lhs, $src, $amt;\n\t",
1092 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1093 !strconcat("shl.b32 \t%rhs, $src, %amt2;\n\t",
1094 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1095 !strconcat("}}", ""))))))))),
1096 [(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>;
1099 def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1100 i32imm:$amt1, i32imm:$amt2),
1101 !strconcat("{{\n\t",
1102 !strconcat(".reg .b64 %lhs;\n\t",
1103 !strconcat(".reg .b64 %rhs;\n\t",
1104 !strconcat("shl.b64 \t%lhs, $src, $amt1;\n\t",
1105 !strconcat("shr.b64 \t%rhs, $src, $amt2;\n\t",
1106 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1107 !strconcat("}}", ""))))))),
1110 def SUB_FRM_64 : SDNodeXForm<imm, [{
1111 return CurDAG->getTargetConstant(64-N->getZExtValue(), MVT::i32);
1114 def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)),
1115 (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>;
1116 def : Pat<(rotr Int64Regs:$src, (i32 imm:$amt)),
1117 (ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>;
1119 def ROTL64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1121 !strconcat("{{\n\t",
1122 !strconcat(".reg .b64 %lhs;\n\t",
1123 !strconcat(".reg .b64 %rhs;\n\t",
1124 !strconcat(".reg .u32 %amt2;\n\t",
1125 !strconcat("shl.b64 \t%lhs, $src, $amt;\n\t",
1126 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1127 !strconcat("shr.b64 \t%rhs, $src, %amt2;\n\t",
1128 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1129 !strconcat("}}", ""))))))))),
1130 [(set Int64Regs:$dst, (rotl Int64Regs:$src, Int32Regs:$amt))]>;
1132 def ROTR64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1134 !strconcat("{{\n\t",
1135 !strconcat(".reg .b64 %lhs;\n\t",
1136 !strconcat(".reg .b64 %rhs;\n\t",
1137 !strconcat(".reg .u32 %amt2;\n\t",
1138 !strconcat("shr.b64 \t%lhs, $src, $amt;\n\t",
1139 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1140 !strconcat("shl.b64 \t%rhs, $src, %amt2;\n\t",
1141 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1142 !strconcat("}}", ""))))))))),
1143 [(set Int64Regs:$dst, (rotr Int64Regs:$src, Int32Regs:$amt))]>;
1146 //-----------------------------------
1147 // General Comparison
1148 //-----------------------------------
1150 // General setp instructions
1151 multiclass SETP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1152 def rr : NVPTXInst<(outs Int1Regs:$dst),
1153 (ins RC:$a, RC:$b, CmpMode:$cmp),
1154 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1156 def ri : NVPTXInst<(outs Int1Regs:$dst),
1157 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1158 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1160 def ir : NVPTXInst<(outs Int1Regs:$dst),
1161 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1162 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1166 defm SETP_b16 : SETP<"b16", Int16Regs, i16imm>;
1167 defm SETP_s16 : SETP<"s16", Int16Regs, i16imm>;
1168 defm SETP_u16 : SETP<"u16", Int16Regs, i16imm>;
1169 defm SETP_b32 : SETP<"b32", Int32Regs, i32imm>;
1170 defm SETP_s32 : SETP<"s32", Int32Regs, i32imm>;
1171 defm SETP_u32 : SETP<"u32", Int32Regs, i32imm>;
1172 defm SETP_b64 : SETP<"b64", Int64Regs, i64imm>;
1173 defm SETP_s64 : SETP<"s64", Int64Regs, i64imm>;
1174 defm SETP_u64 : SETP<"u64", Int64Regs, i64imm>;
1175 defm SETP_f32 : SETP<"f32", Float32Regs, f32imm>;
1176 defm SETP_f64 : SETP<"f64", Float64Regs, f64imm>;
1178 // General set instructions
1179 multiclass SET<string TypeStr, RegisterClass RC, Operand ImmCls> {
1180 def rr : NVPTXInst<(outs Int32Regs:$dst),
1181 (ins RC:$a, RC:$b, CmpMode:$cmp),
1182 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1183 def ri : NVPTXInst<(outs Int32Regs:$dst),
1184 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1185 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1186 def ir : NVPTXInst<(outs Int32Regs:$dst),
1187 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1188 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1191 defm SET_b16 : SET<"b16", Int16Regs, i16imm>;
1192 defm SET_s16 : SET<"s16", Int16Regs, i16imm>;
1193 defm SET_u16 : SET<"u16", Int16Regs, i16imm>;
1194 defm SET_b32 : SET<"b32", Int32Regs, i32imm>;
1195 defm SET_s32 : SET<"s32", Int32Regs, i32imm>;
1196 defm SET_u32 : SET<"u32", Int32Regs, i32imm>;
1197 defm SET_b64 : SET<"b64", Int64Regs, i64imm>;
1198 defm SET_s64 : SET<"s64", Int64Regs, i64imm>;
1199 defm SET_u64 : SET<"u64", Int64Regs, i64imm>;
1200 defm SET_f32 : SET<"f32", Float32Regs, f32imm>;
1201 defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
1203 //-----------------------------------
1204 // General Selection
1205 //-----------------------------------
1207 // General selp instructions
1208 multiclass SELP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1209 def rr : NVPTXInst<(outs RC:$dst),
1210 (ins RC:$a, RC:$b, Int1Regs:$p),
1211 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1212 def ri : NVPTXInst<(outs RC:$dst),
1213 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1214 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1215 def ir : NVPTXInst<(outs RC:$dst),
1216 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1217 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1218 def ii : NVPTXInst<(outs RC:$dst),
1219 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1220 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1223 multiclass SELP_PATTERN<string TypeStr, RegisterClass RC, Operand ImmCls,
1225 def rr : NVPTXInst<(outs RC:$dst),
1226 (ins RC:$a, RC:$b, Int1Regs:$p),
1227 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1228 [(set RC:$dst, (select Int1Regs:$p, RC:$a, RC:$b))]>;
1229 def ri : NVPTXInst<(outs RC:$dst),
1230 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1231 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1232 [(set RC:$dst, (select Int1Regs:$p, RC:$a, ImmNode:$b))]>;
1233 def ir : NVPTXInst<(outs RC:$dst),
1234 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1235 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1236 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, RC:$b))]>;
1237 def ii : NVPTXInst<(outs RC:$dst),
1238 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1239 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1240 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, ImmNode:$b))]>;
1243 defm SELP_b16 : SELP_PATTERN<"b16", Int16Regs, i16imm, imm>;
1244 defm SELP_s16 : SELP<"s16", Int16Regs, i16imm>;
1245 defm SELP_u16 : SELP<"u16", Int16Regs, i16imm>;
1246 defm SELP_b32 : SELP_PATTERN<"b32", Int32Regs, i32imm, imm>;
1247 defm SELP_s32 : SELP<"s32", Int32Regs, i32imm>;
1248 defm SELP_u32 : SELP<"u32", Int32Regs, i32imm>;
1249 defm SELP_b64 : SELP_PATTERN<"b64", Int64Regs, i64imm, imm>;
1250 defm SELP_s64 : SELP<"s64", Int64Regs, i64imm>;
1251 defm SELP_u64 : SELP<"u64", Int64Regs, i64imm>;
1252 defm SELP_f32 : SELP_PATTERN<"f32", Float32Regs, f32imm, fpimm>;
1253 defm SELP_f64 : SELP_PATTERN<"f64", Float64Regs, f64imm, fpimm>;
1255 // Special select for predicate operands
1256 def : Pat<(i1 (select Int1Regs:$p, Int1Regs:$a, Int1Regs:$b)),
1257 (ORb1rr (ANDb1rr Int1Regs:$p, Int1Regs:$a),
1258 (ANDb1rr (NOT1 Int1Regs:$p), Int1Regs:$b))>;
1260 //-----------------------------------
1261 // Data Movement (Load / Store, Move)
1262 //-----------------------------------
1264 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex],
1266 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex],
1269 def MEMri : Operand<i32> {
1270 let PrintMethod = "printMemOperand";
1271 let MIOperandInfo = (ops Int32Regs, i32imm);
1273 def MEMri64 : Operand<i64> {
1274 let PrintMethod = "printMemOperand";
1275 let MIOperandInfo = (ops Int64Regs, i64imm);
1278 def imem : Operand<iPTR> {
1279 let PrintMethod = "printOperand";
1282 def imemAny : Operand<iPTRAny> {
1283 let PrintMethod = "printOperand";
1286 def LdStCode : Operand<i32> {
1287 let PrintMethod = "printLdStCode";
1290 def SDTWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
1291 def Wrapper : SDNode<"NVPTXISD::Wrapper", SDTWrapper>;
1293 def MOV_ADDR : NVPTXInst<(outs Int32Regs:$dst), (ins imem:$a),
1294 "mov.u32 \t$dst, $a;",
1295 [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1297 def MOV_ADDR64 : NVPTXInst<(outs Int64Regs:$dst), (ins imem:$a),
1298 "mov.u64 \t$dst, $a;",
1299 [(set Int64Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1301 // copyPhysreg is hard-coded in NVPTXInstrInfo.cpp
1302 let IsSimpleMove=1 in {
1303 def IMOV1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$sss),
1304 "mov.pred \t$dst, $sss;", []>;
1305 def IMOV16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$sss),
1306 "mov.u16 \t$dst, $sss;", []>;
1307 def IMOV32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$sss),
1308 "mov.u32 \t$dst, $sss;", []>;
1309 def IMOV64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$sss),
1310 "mov.u64 \t$dst, $sss;", []>;
1312 def FMOV32rr: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
1313 "mov.f32 \t$dst, $src;", []>;
1314 def FMOV64rr: NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$src),
1315 "mov.f64 \t$dst, $src;", []>;
1317 def IMOV1ri: NVPTXInst<(outs Int1Regs:$dst), (ins i1imm:$src),
1318 "mov.pred \t$dst, $src;",
1319 [(set Int1Regs:$dst, imm:$src)]>;
1320 def IMOV16ri: NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
1321 "mov.u16 \t$dst, $src;",
1322 [(set Int16Regs:$dst, imm:$src)]>;
1323 def IMOV32ri: NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
1324 "mov.u32 \t$dst, $src;",
1325 [(set Int32Regs:$dst, imm:$src)]>;
1326 def IMOV64i: NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
1327 "mov.u64 \t$dst, $src;",
1328 [(set Int64Regs:$dst, imm:$src)]>;
1330 def FMOV32ri: NVPTXInst<(outs Float32Regs:$dst), (ins f32imm:$src),
1331 "mov.f32 \t$dst, $src;",
1332 [(set Float32Regs:$dst, fpimm:$src)]>;
1333 def FMOV64ri: NVPTXInst<(outs Float64Regs:$dst), (ins f64imm:$src),
1334 "mov.f64 \t$dst, $src;",
1335 [(set Float64Regs:$dst, fpimm:$src)]>;
1337 def : Pat<(i32 (Wrapper texternalsym:$dst)), (IMOV32ri texternalsym:$dst)>;
1339 //---- Copy Frame Index ----
1340 def LEA_ADDRi : NVPTXInst<(outs Int32Regs:$dst), (ins MEMri:$addr),
1341 "add.u32 \t$dst, ${addr:add};",
1342 [(set Int32Regs:$dst, ADDRri:$addr)]>;
1343 def LEA_ADDRi64 : NVPTXInst<(outs Int64Regs:$dst), (ins MEMri64:$addr),
1344 "add.u64 \t$dst, ${addr:add};",
1345 [(set Int64Regs:$dst, ADDRri64:$addr)]>;
1347 //-----------------------------------
1348 // Comparison and Selection
1349 //-----------------------------------
1351 multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
1352 Instruction setp_16rr,
1353 Instruction setp_16ri,
1354 Instruction setp_16ir,
1355 Instruction setp_32rr,
1356 Instruction setp_32ri,
1357 Instruction setp_32ir,
1358 Instruction setp_64rr,
1359 Instruction setp_64ri,
1360 Instruction setp_64ir,
1361 Instruction set_16rr,
1362 Instruction set_16ri,
1363 Instruction set_16ir,
1364 Instruction set_32rr,
1365 Instruction set_32ri,
1366 Instruction set_32ir,
1367 Instruction set_64rr,
1368 Instruction set_64ri,
1369 Instruction set_64ir> {
1371 def : Pat<(i1 (OpNode Int16Regs:$a, Int16Regs:$b)),
1372 (setp_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1373 def : Pat<(i1 (OpNode Int16Regs:$a, imm:$b)),
1374 (setp_16ri Int16Regs:$a, imm:$b, Mode)>;
1375 def : Pat<(i1 (OpNode imm:$a, Int16Regs:$b)),
1376 (setp_16ir imm:$a, Int16Regs:$b, Mode)>;
1378 def : Pat<(i1 (OpNode Int32Regs:$a, Int32Regs:$b)),
1379 (setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1380 def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1381 (setp_32ri Int32Regs:$a, imm:$b, Mode)>;
1382 def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1383 (setp_32ir imm:$a, Int32Regs:$b, Mode)>;
1385 def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
1386 (setp_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1387 def : Pat<(i1 (OpNode Int64Regs:$a, imm:$b)),
1388 (setp_64ri Int64Regs:$a, imm:$b, Mode)>;
1389 def : Pat<(i1 (OpNode imm:$a, Int64Regs:$b)),
1390 (setp_64ir imm:$a, Int64Regs:$b, Mode)>;
1393 def : Pat<(i32 (OpNode Int16Regs:$a, Int16Regs:$b)),
1394 (set_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1395 def : Pat<(i32 (OpNode Int16Regs:$a, imm:$b)),
1396 (set_16ri Int16Regs:$a, imm:$b, Mode)>;
1397 def : Pat<(i32 (OpNode imm:$a, Int16Regs:$b)),
1398 (set_16ir imm:$a, Int16Regs:$b, Mode)>;
1400 def : Pat<(i32 (OpNode Int32Regs:$a, Int32Regs:$b)),
1401 (set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1402 def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
1403 (set_32ri Int32Regs:$a, imm:$b, Mode)>;
1404 def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
1405 (set_32ir imm:$a, Int32Regs:$b, Mode)>;
1407 def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
1408 (set_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1409 def : Pat<(i32 (OpNode Int64Regs:$a, imm:$b)),
1410 (set_64ri Int64Regs:$a, imm:$b, Mode)>;
1411 def : Pat<(i32 (OpNode imm:$a, Int64Regs:$b)),
1412 (set_64ir imm:$a, Int64Regs:$b, Mode)>;
1415 multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
1416 : ISET_FORMAT<OpNode, Mode,
1417 SETP_s16rr, SETP_s16ri, SETP_s16ir,
1418 SETP_s32rr, SETP_s32ri, SETP_s32ir,
1419 SETP_s64rr, SETP_s64ri, SETP_s64ir,
1420 SET_s16rr, SET_s16ri, SET_s16ir,
1421 SET_s32rr, SET_s32ri, SET_s32ir,
1422 SET_s64rr, SET_s64ri, SET_s64ir> {
1423 // TableGen doesn't like empty multiclasses
1424 def : PatLeaf<(i32 0)>;
1427 multiclass ISET_FORMAT_UNSIGNED<PatFrag OpNode, PatLeaf Mode>
1428 : ISET_FORMAT<OpNode, Mode,
1429 SETP_u16rr, SETP_u16ri, SETP_u16ir,
1430 SETP_u32rr, SETP_u32ri, SETP_u32ir,
1431 SETP_u64rr, SETP_u64ri, SETP_u64ir,
1432 SET_u16rr, SET_u16ri, SET_u16ir,
1433 SET_u32rr, SET_u32ri, SET_u32ir,
1434 SET_u64rr, SET_u64ri, SET_u64ir> {
1435 // TableGen doesn't like empty multiclasses
1436 def : PatLeaf<(i32 0)>;
1439 defm : ISET_FORMAT_SIGNED<setgt, CmpGT>;
1440 defm : ISET_FORMAT_UNSIGNED<setugt, CmpGT>;
1441 defm : ISET_FORMAT_SIGNED<setlt, CmpLT>;
1442 defm : ISET_FORMAT_UNSIGNED<setult, CmpLT>;
1443 defm : ISET_FORMAT_SIGNED<setge, CmpGE>;
1444 defm : ISET_FORMAT_UNSIGNED<setuge, CmpGE>;
1445 defm : ISET_FORMAT_SIGNED<setle, CmpLE>;
1446 defm : ISET_FORMAT_UNSIGNED<setule, CmpLE>;
1447 defm : ISET_FORMAT_SIGNED<seteq, CmpEQ>;
1448 defm : ISET_FORMAT_UNSIGNED<setueq, CmpEQ>;
1449 defm : ISET_FORMAT_SIGNED<setne, CmpNE>;
1450 defm : ISET_FORMAT_UNSIGNED<setune, CmpNE>;
1453 def : Pat<(setne Int1Regs:$a, Int1Regs:$b),
1454 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1455 def : Pat<(setune Int1Regs:$a, Int1Regs:$b),
1456 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1458 def : Pat<(seteq Int1Regs:$a, Int1Regs:$b),
1459 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1460 def : Pat<(setueq Int1Regs:$a, Int1Regs:$b),
1461 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1463 // i1 compare -> i32
1464 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1465 (SELP_u32ii -1, 0, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1466 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1467 (SELP_u32ii 0, -1, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1471 multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
1473 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1474 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1475 Requires<[doF32FTZ]>;
1476 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1477 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1478 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1479 (SETP_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1480 Requires<[doF32FTZ]>;
1481 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1482 (SETP_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1483 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1484 (SETP_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1485 Requires<[doF32FTZ]>;
1486 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1487 (SETP_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1490 def : Pat<(i1 (OpNode Float64Regs:$a, Float64Regs:$b)),
1491 (SETP_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1492 def : Pat<(i1 (OpNode Float64Regs:$a, fpimm:$b)),
1493 (SETP_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1494 def : Pat<(i1 (OpNode fpimm:$a, Float64Regs:$b)),
1495 (SETP_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1498 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1499 (SET_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1500 Requires<[doF32FTZ]>;
1501 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1502 (SET_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1503 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1504 (SET_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1505 Requires<[doF32FTZ]>;
1506 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1507 (SET_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1508 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1509 (SET_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1510 Requires<[doF32FTZ]>;
1511 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1512 (SET_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1515 def : Pat<(i32 (OpNode Float64Regs:$a, Float64Regs:$b)),
1516 (SET_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1517 def : Pat<(i32 (OpNode Float64Regs:$a, fpimm:$b)),
1518 (SET_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1519 def : Pat<(i32 (OpNode fpimm:$a, Float64Regs:$b)),
1520 (SET_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1523 defm FSetGT : FSET_FORMAT<setogt, CmpGT, CmpGT_FTZ>;
1524 defm FSetLT : FSET_FORMAT<setolt, CmpLT, CmpLT_FTZ>;
1525 defm FSetGE : FSET_FORMAT<setoge, CmpGE, CmpGE_FTZ>;
1526 defm FSetLE : FSET_FORMAT<setole, CmpLE, CmpLE_FTZ>;
1527 defm FSetEQ : FSET_FORMAT<setoeq, CmpEQ, CmpEQ_FTZ>;
1528 defm FSetNE : FSET_FORMAT<setone, CmpNE, CmpNE_FTZ>;
1530 defm FSetUGT : FSET_FORMAT<setugt, CmpGTU, CmpGTU_FTZ>;
1531 defm FSetULT : FSET_FORMAT<setult, CmpLTU, CmpLTU_FTZ>;
1532 defm FSetUGE : FSET_FORMAT<setuge, CmpGEU, CmpGEU_FTZ>;
1533 defm FSetULE : FSET_FORMAT<setule, CmpLEU, CmpLEU_FTZ>;
1534 defm FSetUEQ : FSET_FORMAT<setueq, CmpEQU, CmpEQU_FTZ>;
1535 defm FSetUNE : FSET_FORMAT<setune, CmpNEU, CmpNEU_FTZ>;
1537 defm FSetNUM : FSET_FORMAT<seto, CmpNUM, CmpNUM_FTZ>;
1538 defm FSetNAN : FSET_FORMAT<setuo, CmpNAN, CmpNAN_FTZ>;
1540 //def ld_param : SDNode<"NVPTXISD::LOAD_PARAM", SDTLoad,
1541 // [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1543 def SDTDeclareParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
1545 def SDTDeclareScalarParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>,
1546 SDTCisInt<1>, SDTCisInt<2>]>;
1547 def SDTLoadParamProfile : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
1548 def SDTLoadParamV2Profile : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisInt<3>]>;
1549 def SDTLoadParamV4Profile : SDTypeProfile<4, 2, [SDTCisInt<4>, SDTCisInt<5>]>;
1550 def SDTPrintCallProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1551 def SDTPrintCallUniProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1552 def SDTStoreParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1553 def SDTStoreParamV2Profile : SDTypeProfile<0, 4, [SDTCisInt<0>, SDTCisInt<1>]>;
1554 def SDTStoreParamV4Profile : SDTypeProfile<0, 6, [SDTCisInt<0>, SDTCisInt<1>]>;
1555 def SDTStoreParam32Profile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1556 def SDTCallArgProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1557 def SDTCallArgMarkProfile : SDTypeProfile<0, 0, []>;
1558 def SDTCallVoidProfile : SDTypeProfile<0, 1, []>;
1559 def SDTCallValProfile : SDTypeProfile<1, 0, []>;
1560 def SDTMoveParamProfile : SDTypeProfile<1, 1, []>;
1561 def SDTStoreRetvalProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1562 def SDTStoreRetvalV2Profile : SDTypeProfile<0, 3, [SDTCisInt<0>]>;
1563 def SDTStoreRetvalV4Profile : SDTypeProfile<0, 5, [SDTCisInt<0>]>;
1564 def SDTPseudoUseParamProfile : SDTypeProfile<0, 1, []>;
1566 def DeclareParam : SDNode<"NVPTXISD::DeclareParam", SDTDeclareParamProfile,
1567 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1568 def DeclareScalarParam : SDNode<"NVPTXISD::DeclareScalarParam",
1569 SDTDeclareScalarParamProfile,
1570 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1571 def DeclareRetParam : SDNode<"NVPTXISD::DeclareRetParam",
1572 SDTDeclareParamProfile,
1573 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1574 def DeclareRet : SDNode<"NVPTXISD::DeclareRet", SDTDeclareScalarParamProfile,
1575 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1576 def LoadParam : SDNode<"NVPTXISD::LoadParam", SDTLoadParamProfile,
1577 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1578 def LoadParamV2 : SDNode<"NVPTXISD::LoadParamV2", SDTLoadParamV2Profile,
1579 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1580 def LoadParamV4 : SDNode<"NVPTXISD::LoadParamV4", SDTLoadParamV4Profile,
1581 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1582 def PrintCall : SDNode<"NVPTXISD::PrintCall", SDTPrintCallProfile,
1583 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1584 def PrintCallUni : SDNode<"NVPTXISD::PrintCallUni", SDTPrintCallUniProfile,
1585 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1586 def StoreParam : SDNode<"NVPTXISD::StoreParam", SDTStoreParamProfile,
1587 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1588 def StoreParamV2 : SDNode<"NVPTXISD::StoreParamV2", SDTStoreParamV2Profile,
1589 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1590 def StoreParamV4 : SDNode<"NVPTXISD::StoreParamV4", SDTStoreParamV4Profile,
1591 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1592 def StoreParamU32 : SDNode<"NVPTXISD::StoreParamU32", SDTStoreParam32Profile,
1593 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1594 def StoreParamS32 : SDNode<"NVPTXISD::StoreParamS32", SDTStoreParam32Profile,
1595 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1596 def CallArgBegin : SDNode<"NVPTXISD::CallArgBegin", SDTCallArgMarkProfile,
1597 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1598 def CallArg : SDNode<"NVPTXISD::CallArg", SDTCallArgProfile,
1599 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1600 def LastCallArg : SDNode<"NVPTXISD::LastCallArg", SDTCallArgProfile,
1601 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1602 def CallArgEnd : SDNode<"NVPTXISD::CallArgEnd", SDTCallVoidProfile,
1603 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1604 def CallVoid : SDNode<"NVPTXISD::CallVoid", SDTCallVoidProfile,
1605 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1606 def Prototype : SDNode<"NVPTXISD::Prototype", SDTCallVoidProfile,
1607 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1608 def CallVal : SDNode<"NVPTXISD::CallVal", SDTCallValProfile,
1609 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1610 def MoveParam : SDNode<"NVPTXISD::MoveParam", SDTMoveParamProfile,
1612 def StoreRetval : SDNode<"NVPTXISD::StoreRetval", SDTStoreRetvalProfile,
1613 [SDNPHasChain, SDNPSideEffect]>;
1614 def StoreRetvalV2 : SDNode<"NVPTXISD::StoreRetvalV2", SDTStoreRetvalV2Profile,
1615 [SDNPHasChain, SDNPSideEffect]>;
1616 def StoreRetvalV4 : SDNode<"NVPTXISD::StoreRetvalV4", SDTStoreRetvalV4Profile,
1617 [SDNPHasChain, SDNPSideEffect]>;
1618 def PseudoUseParam : SDNode<"NVPTXISD::PseudoUseParam",
1619 SDTPseudoUseParamProfile,
1620 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1621 def RETURNNode : SDNode<"NVPTXISD::RETURN", SDTCallArgMarkProfile,
1622 [SDNPHasChain, SDNPSideEffect]>;
1624 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1625 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1626 !strconcat(!strconcat("ld.param", opstr),
1627 "\t$dst, [retval0+$b];"),
1630 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1631 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1632 !strconcat(!strconcat("mov", opstr),
1633 "\t$dst, retval$b;"),
1634 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1636 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1637 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1638 !strconcat(!strconcat("ld.param.v2", opstr),
1639 "\t{{$dst, $dst2}}, [retval0+$b];"), []>;
1641 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1642 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1645 !strconcat(!strconcat("ld.param.v4", opstr),
1646 "\t{{$dst, $dst2, $dst3, $dst4}}, [retval0+$b];"), []>;
1648 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1649 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1650 !strconcat(!strconcat("st.param", opstr),
1651 "\t[param$a+$b], $val;"),
1654 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1655 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1656 i32imm:$a, i32imm:$b),
1657 !strconcat(!strconcat("st.param.v2", opstr),
1658 "\t[param$a+$b], {{$val, $val2}};"),
1661 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1662 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1663 regclass:$val3, i32imm:$a, i32imm:$b),
1664 !strconcat(!strconcat("st.param.v4", opstr),
1665 "\t[param$a+$b], {{$val, $val2, $val3, $val4}};"),
1668 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1669 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1670 !strconcat(!strconcat("st.param", opstr),
1671 "\t[func_retval0+$a], $val;"),
1674 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1675 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1676 !strconcat(!strconcat("st.param.v2", opstr),
1677 "\t[func_retval0+$a], {{$val, $val2}};"),
1680 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1682 (ins regclass:$val, regclass:$val2, regclass:$val3,
1683 regclass:$val4, i32imm:$a),
1684 !strconcat(!strconcat("st.param.v4", opstr),
1685 "\t[func_retval0+$a], {{$val, $val2, $val3, $val4}};"),
1688 def PrintCallRetInst1 : NVPTXInst<(outs), (ins),
1690 [(PrintCall (i32 1))]>;
1691 def PrintCallRetInst2 : NVPTXInst<(outs), (ins),
1692 "call (retval0, retval1), ",
1693 [(PrintCall (i32 2))]>;
1694 def PrintCallRetInst3 : NVPTXInst<(outs), (ins),
1695 "call (retval0, retval1, retval2), ",
1696 [(PrintCall (i32 3))]>;
1697 def PrintCallRetInst4 : NVPTXInst<(outs), (ins),
1698 "call (retval0, retval1, retval2, retval3), ",
1699 [(PrintCall (i32 4))]>;
1700 def PrintCallRetInst5 : NVPTXInst<(outs), (ins),
1701 "call (retval0, retval1, retval2, retval3, retval4), ",
1702 [(PrintCall (i32 5))]>;
1703 def PrintCallRetInst6 : NVPTXInst<(outs), (ins),
1704 "call (retval0, retval1, retval2, retval3, retval4, retval5), ",
1705 [(PrintCall (i32 6))]>;
1706 def PrintCallRetInst7 : NVPTXInst<(outs), (ins),
1707 "call (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1708 [(PrintCall (i32 7))]>;
1709 def PrintCallRetInst8 : NVPTXInst<(outs), (ins),
1710 !strconcat("call (retval0, retval1, retval2, retval3, retval4",
1711 ", retval5, retval6, retval7), "),
1712 [(PrintCall (i32 8))]>;
1714 def PrintCallNoRetInst : NVPTXInst<(outs), (ins), "call ",
1715 [(PrintCall (i32 0))]>;
1717 def PrintCallUniRetInst1 : NVPTXInst<(outs), (ins),
1718 "call.uni (retval0), ",
1719 [(PrintCallUni (i32 1))]>;
1720 def PrintCallUniRetInst2 : NVPTXInst<(outs), (ins),
1721 "call.uni (retval0, retval1), ",
1722 [(PrintCallUni (i32 2))]>;
1723 def PrintCallUniRetInst3 : NVPTXInst<(outs), (ins),
1724 "call.uni (retval0, retval1, retval2), ",
1725 [(PrintCallUni (i32 3))]>;
1726 def PrintCallUniRetInst4 : NVPTXInst<(outs), (ins),
1727 "call.uni (retval0, retval1, retval2, retval3), ",
1728 [(PrintCallUni (i32 4))]>;
1729 def PrintCallUniRetInst5 : NVPTXInst<(outs), (ins),
1730 "call.uni (retval0, retval1, retval2, retval3, retval4), ",
1731 [(PrintCallUni (i32 5))]>;
1732 def PrintCallUniRetInst6 : NVPTXInst<(outs), (ins),
1733 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5), ",
1734 [(PrintCallUni (i32 6))]>;
1735 def PrintCallUniRetInst7 : NVPTXInst<(outs), (ins),
1736 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1737 [(PrintCallUni (i32 7))]>;
1738 def PrintCallUniRetInst8 : NVPTXInst<(outs), (ins),
1739 !strconcat("call.uni (retval0, retval1, retval2, retval3, retval4",
1740 ", retval5, retval6, retval7), "),
1741 [(PrintCallUni (i32 8))]>;
1743 def PrintCallUniNoRetInst : NVPTXInst<(outs), (ins), "call.uni ",
1744 [(PrintCallUni (i32 0))]>;
1746 def LoadParamMemI64 : LoadParamMemInst<Int64Regs, ".b64">;
1747 def LoadParamMemI32 : LoadParamMemInst<Int32Regs, ".b32">;
1748 def LoadParamMemI16 : LoadParamMemInst<Int16Regs, ".b16">;
1749 def LoadParamMemI8 : LoadParamMemInst<Int16Regs, ".b8">;
1750 def LoadParamMemV2I64 : LoadParamV2MemInst<Int64Regs, ".b64">;
1751 def LoadParamMemV2I32 : LoadParamV2MemInst<Int32Regs, ".b32">;
1752 def LoadParamMemV2I16 : LoadParamV2MemInst<Int16Regs, ".b16">;
1753 def LoadParamMemV2I8 : LoadParamV2MemInst<Int16Regs, ".b8">;
1754 def LoadParamMemV4I32 : LoadParamV4MemInst<Int32Regs, ".b32">;
1755 def LoadParamMemV4I16 : LoadParamV4MemInst<Int16Regs, ".b16">;
1756 def LoadParamMemV4I8 : LoadParamV4MemInst<Int16Regs, ".b8">;
1757 def LoadParamMemF32 : LoadParamMemInst<Float32Regs, ".f32">;
1758 def LoadParamMemF64 : LoadParamMemInst<Float64Regs, ".f64">;
1759 def LoadParamMemV2F32 : LoadParamV2MemInst<Float32Regs, ".f32">;
1760 def LoadParamMemV2F64 : LoadParamV2MemInst<Float64Regs, ".f64">;
1761 def LoadParamMemV4F32 : LoadParamV4MemInst<Float32Regs, ".f32">;
1763 def StoreParamI64 : StoreParamInst<Int64Regs, ".b64">;
1764 def StoreParamI32 : StoreParamInst<Int32Regs, ".b32">;
1766 def StoreParamI16 : StoreParamInst<Int16Regs, ".b16">;
1767 def StoreParamI8 : StoreParamInst<Int16Regs, ".b8">;
1768 def StoreParamV2I64 : StoreParamV2Inst<Int64Regs, ".b64">;
1769 def StoreParamV2I32 : StoreParamV2Inst<Int32Regs, ".b32">;
1770 def StoreParamV2I16 : StoreParamV2Inst<Int16Regs, ".b16">;
1771 def StoreParamV2I8 : StoreParamV2Inst<Int16Regs, ".b8">;
1773 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1774 //def StoreParamV4I32 : StoreParamV4Inst<Int32Regs, ".b32">;
1775 def StoreParamV4I32 : NVPTXInst<(outs), (ins Int32Regs:$val, Int32Regs:$val2,
1776 Int32Regs:$val3, Int32Regs:$val4,
1777 i32imm:$a, i32imm:$b),
1778 "st.param.b32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1781 def StoreParamV4I16 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1782 Int16Regs:$val3, Int16Regs:$val4,
1783 i32imm:$a, i32imm:$b),
1784 "st.param.v4.b16\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1787 def StoreParamV4I8 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1788 Int16Regs:$val3, Int16Regs:$val4,
1789 i32imm:$a, i32imm:$b),
1790 "st.param.v4.b8\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1793 def StoreParamF32 : StoreParamInst<Float32Regs, ".f32">;
1794 def StoreParamF64 : StoreParamInst<Float64Regs, ".f64">;
1795 def StoreParamV2F32 : StoreParamV2Inst<Float32Regs, ".f32">;
1796 def StoreParamV2F64 : StoreParamV2Inst<Float64Regs, ".f64">;
1797 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1798 //def StoreParamV4F32 : StoreParamV4Inst<Float32Regs, ".f32">;
1799 def StoreParamV4F32 : NVPTXInst<(outs),
1800 (ins Float32Regs:$val, Float32Regs:$val2,
1801 Float32Regs:$val3, Float32Regs:$val4,
1802 i32imm:$a, i32imm:$b),
1803 "st.param.v4.f32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1807 def StoreRetvalI64 : StoreRetvalInst<Int64Regs, ".b64">;
1808 def StoreRetvalI32 : StoreRetvalInst<Int32Regs, ".b32">;
1809 def StoreRetvalI16 : StoreRetvalInst<Int16Regs, ".b16">;
1810 def StoreRetvalI8 : StoreRetvalInst<Int16Regs, ".b8">;
1811 def StoreRetvalV2I64 : StoreRetvalV2Inst<Int64Regs, ".b64">;
1812 def StoreRetvalV2I32 : StoreRetvalV2Inst<Int32Regs, ".b32">;
1813 def StoreRetvalV2I16 : StoreRetvalV2Inst<Int16Regs, ".b16">;
1814 def StoreRetvalV2I8 : StoreRetvalV2Inst<Int16Regs, ".b8">;
1815 def StoreRetvalV4I32 : StoreRetvalV4Inst<Int32Regs, ".b32">;
1816 def StoreRetvalV4I16 : StoreRetvalV4Inst<Int16Regs, ".b16">;
1817 def StoreRetvalV4I8 : StoreRetvalV4Inst<Int16Regs, ".b8">;
1819 def StoreRetvalF64 : StoreRetvalInst<Float64Regs, ".f64">;
1820 def StoreRetvalF32 : StoreRetvalInst<Float32Regs, ".f32">;
1821 def StoreRetvalV2F64 : StoreRetvalV2Inst<Float64Regs, ".f64">;
1822 def StoreRetvalV2F32 : StoreRetvalV2Inst<Float32Regs, ".f32">;
1823 def StoreRetvalV4F32 : StoreRetvalV4Inst<Float32Regs, ".f32">;
1825 def CallArgBeginInst : NVPTXInst<(outs), (ins), "(", [(CallArgBegin)]>;
1826 def CallArgEndInst1 : NVPTXInst<(outs), (ins), ");", [(CallArgEnd (i32 1))]>;
1827 def CallArgEndInst0 : NVPTXInst<(outs), (ins), ")", [(CallArgEnd (i32 0))]>;
1828 def RETURNInst : NVPTXInst<(outs), (ins), "ret;", [(RETURNNode)]>;
1830 class CallArgInst<NVPTXRegClass regclass> :
1831 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1832 [(CallArg (i32 0), regclass:$a)]>;
1834 class LastCallArgInst<NVPTXRegClass regclass> :
1835 NVPTXInst<(outs), (ins regclass:$a), "$a",
1836 [(LastCallArg (i32 0), regclass:$a)]>;
1838 def CallArgI64 : CallArgInst<Int64Regs>;
1839 def CallArgI32 : CallArgInst<Int32Regs>;
1840 def CallArgI16 : CallArgInst<Int16Regs>;
1842 def CallArgF64 : CallArgInst<Float64Regs>;
1843 def CallArgF32 : CallArgInst<Float32Regs>;
1845 def LastCallArgI64 : LastCallArgInst<Int64Regs>;
1846 def LastCallArgI32 : LastCallArgInst<Int32Regs>;
1847 def LastCallArgI16 : LastCallArgInst<Int16Regs>;
1849 def LastCallArgF64 : LastCallArgInst<Float64Regs>;
1850 def LastCallArgF32 : LastCallArgInst<Float32Regs>;
1852 def CallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a, ",
1853 [(CallArg (i32 0), (i32 imm:$a))]>;
1854 def LastCallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a",
1855 [(LastCallArg (i32 0), (i32 imm:$a))]>;
1857 def CallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a, ",
1858 [(CallArg (i32 1), (i32 imm:$a))]>;
1859 def LastCallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a",
1860 [(LastCallArg (i32 1), (i32 imm:$a))]>;
1862 def CallVoidInst : NVPTXInst<(outs), (ins imem:$addr),
1864 [(CallVoid (Wrapper tglobaladdr:$addr))]>;
1865 def CallVoidInstReg : NVPTXInst<(outs), (ins Int32Regs:$addr),
1867 [(CallVoid Int32Regs:$addr)]>;
1868 def CallVoidInstReg64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
1870 [(CallVoid Int64Regs:$addr)]>;
1871 def PrototypeInst : NVPTXInst<(outs), (ins i32imm:$val),
1872 ", prototype_$val;",
1873 [(Prototype (i32 imm:$val))]>;
1875 def DeclareRetMemInst : NVPTXInst<(outs),
1876 (ins i32imm:$align, i32imm:$size, i32imm:$num),
1877 ".param .align $align .b8 retval$num[$size];",
1878 [(DeclareRetParam (i32 imm:$align), (i32 imm:$size), (i32 imm:$num))]>;
1879 def DeclareRetScalarInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1880 ".param .b$size retval$num;",
1881 [(DeclareRet (i32 1), (i32 imm:$size), (i32 imm:$num))]>;
1882 def DeclareRetRegInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1883 ".reg .b$size retval$num;",
1884 [(DeclareRet (i32 2), (i32 imm:$size), (i32 imm:$num))]>;
1886 def DeclareParamInst : NVPTXInst<(outs),
1887 (ins i32imm:$align, i32imm:$a, i32imm:$size),
1888 ".param .align $align .b8 param$a[$size];",
1889 [(DeclareParam (i32 imm:$align), (i32 imm:$a), (i32 imm:$size))]>;
1890 def DeclareScalarParamInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1891 ".param .b$size param$a;",
1892 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 0))]>;
1893 def DeclareScalarRegInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1894 ".reg .b$size param$a;",
1895 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 1))]>;
1897 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
1898 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
1899 !strconcat(!strconcat("mov", asmstr), "\t$dst, $src;"),
1900 [(set regclass:$dst, (MoveParam regclass:$src))]>;
1902 def MoveParamI64 : MoveParamInst<Int64Regs, ".b64">;
1903 def MoveParamI32 : MoveParamInst<Int32Regs, ".b32">;
1904 def MoveParamI16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
1905 "cvt.u16.u32\t$dst, $src;",
1906 [(set Int16Regs:$dst, (MoveParam Int16Regs:$src))]>;
1907 def MoveParamF64 : MoveParamInst<Float64Regs, ".f64">;
1908 def MoveParamF32 : MoveParamInst<Float32Regs, ".f32">;
1910 class PseudoUseParamInst<NVPTXRegClass regclass> :
1911 NVPTXInst<(outs), (ins regclass:$src),
1912 "// Pseudo use of $src",
1913 [(PseudoUseParam regclass:$src)]>;
1915 def PseudoUseParamI64 : PseudoUseParamInst<Int64Regs>;
1916 def PseudoUseParamI32 : PseudoUseParamInst<Int32Regs>;
1917 def PseudoUseParamI16 : PseudoUseParamInst<Int16Regs>;
1918 def PseudoUseParamF64 : PseudoUseParamInst<Float64Regs>;
1919 def PseudoUseParamF32 : PseudoUseParamInst<Float32Regs>;
1923 // Load / Store Handling
1925 multiclass LD<NVPTXRegClass regclass> {
1926 def _avar : NVPTXInst<(outs regclass:$dst),
1927 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1928 i32imm:$fromWidth, imem:$addr),
1929 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1930 "$fromWidth \t$dst, [$addr];"), []>;
1931 def _areg : NVPTXInst<(outs regclass:$dst),
1932 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1933 i32imm:$fromWidth, Int32Regs:$addr),
1934 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1935 "$fromWidth \t$dst, [$addr];"), []>;
1936 def _areg_64 : NVPTXInst<(outs regclass:$dst),
1937 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1938 i32imm:$fromWidth, Int64Regs:$addr),
1939 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1940 " \t$dst, [$addr];"), []>;
1941 def _ari : NVPTXInst<(outs regclass:$dst),
1942 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1943 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
1944 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1945 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1946 def _ari_64 : NVPTXInst<(outs regclass:$dst),
1947 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1948 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
1949 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1950 " \t$dst, [$addr+$offset];"), []>;
1951 def _asi : NVPTXInst<(outs regclass:$dst),
1952 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1953 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
1954 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1955 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1958 let mayLoad=1, neverHasSideEffects=1 in {
1959 defm LD_i8 : LD<Int16Regs>;
1960 defm LD_i16 : LD<Int16Regs>;
1961 defm LD_i32 : LD<Int32Regs>;
1962 defm LD_i64 : LD<Int64Regs>;
1963 defm LD_f32 : LD<Float32Regs>;
1964 defm LD_f64 : LD<Float64Regs>;
1967 multiclass ST<NVPTXRegClass regclass> {
1968 def _avar : NVPTXInst<(outs),
1969 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1970 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
1971 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1972 " \t[$addr], $src;"), []>;
1973 def _areg : NVPTXInst<(outs),
1974 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1975 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr),
1976 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1977 " \t[$addr], $src;"), []>;
1978 def _areg_64 : NVPTXInst<(outs),
1979 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1980 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
1981 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
1982 "\t[$addr], $src;"), []>;
1983 def _ari : NVPTXInst<(outs),
1984 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1985 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr, i32imm:$offset),
1986 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1987 " \t[$addr+$offset], $src;"), []>;
1988 def _ari_64 : NVPTXInst<(outs),
1989 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1990 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr, i32imm:$offset),
1991 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
1992 "\t[$addr+$offset], $src;"), []>;
1993 def _asi : NVPTXInst<(outs),
1994 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1995 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
1996 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1997 " \t[$addr+$offset], $src;"), []>;
2000 let mayStore=1, neverHasSideEffects=1 in {
2001 defm ST_i8 : ST<Int16Regs>;
2002 defm ST_i16 : ST<Int16Regs>;
2003 defm ST_i32 : ST<Int32Regs>;
2004 defm ST_i64 : ST<Int64Regs>;
2005 defm ST_f32 : ST<Float32Regs>;
2006 defm ST_f64 : ST<Float64Regs>;
2009 // The following is used only in and after vector elementizations.
2010 // Vector elementization happens at the machine instruction level, so the
2011 // following instruction
2012 // never appears in the DAG.
2013 multiclass LD_VEC<NVPTXRegClass regclass> {
2014 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2015 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2016 i32imm:$fromWidth, imem:$addr),
2017 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2018 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2019 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2020 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2021 i32imm:$fromWidth, Int32Regs:$addr),
2022 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2023 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2024 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2025 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2026 i32imm:$fromWidth, Int64Regs:$addr),
2027 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2028 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2029 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2030 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2031 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2032 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2033 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2034 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2035 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2036 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2037 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2038 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2039 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2040 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2041 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2042 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2043 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2044 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2045 regclass:$dst3, regclass:$dst4),
2046 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2047 i32imm:$fromWidth, imem:$addr),
2048 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2049 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2050 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2052 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2053 i32imm:$fromWidth, Int32Regs:$addr),
2054 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2055 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2056 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2057 regclass:$dst3, regclass:$dst4),
2058 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2059 i32imm:$fromWidth, Int64Regs:$addr),
2060 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2061 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2062 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2064 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2065 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2066 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2067 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2069 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2070 regclass:$dst3, regclass:$dst4),
2071 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2072 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2073 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2074 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2076 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2078 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2079 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2080 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2081 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2084 let mayLoad=1, neverHasSideEffects=1 in {
2085 defm LDV_i8 : LD_VEC<Int16Regs>;
2086 defm LDV_i16 : LD_VEC<Int16Regs>;
2087 defm LDV_i32 : LD_VEC<Int32Regs>;
2088 defm LDV_i64 : LD_VEC<Int64Regs>;
2089 defm LDV_f32 : LD_VEC<Float32Regs>;
2090 defm LDV_f64 : LD_VEC<Float64Regs>;
2093 multiclass ST_VEC<NVPTXRegClass regclass> {
2094 def _v2_avar : NVPTXInst<(outs),
2095 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2096 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr),
2097 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2098 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2099 def _v2_areg : NVPTXInst<(outs),
2100 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2101 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr),
2102 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2103 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2104 def _v2_areg_64 : NVPTXInst<(outs),
2105 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2106 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr),
2107 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2108 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2109 def _v2_ari : NVPTXInst<(outs),
2110 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2111 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr,
2113 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2114 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2115 def _v2_ari_64 : NVPTXInst<(outs),
2116 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2117 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr,
2119 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2120 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2121 def _v2_asi : NVPTXInst<(outs),
2122 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2123 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr,
2125 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2126 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2127 def _v4_avar : NVPTXInst<(outs),
2128 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2129 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2130 i32imm:$fromWidth, imem:$addr),
2131 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2132 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2133 def _v4_areg : NVPTXInst<(outs),
2134 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2135 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2136 i32imm:$fromWidth, Int32Regs:$addr),
2137 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2138 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2139 def _v4_areg_64 : NVPTXInst<(outs),
2140 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2141 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2142 i32imm:$fromWidth, Int64Regs:$addr),
2143 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2144 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2145 def _v4_ari : NVPTXInst<(outs),
2146 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2147 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2148 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2149 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2150 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2152 def _v4_ari_64 : NVPTXInst<(outs),
2153 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2154 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2155 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2156 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2157 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2159 def _v4_asi : NVPTXInst<(outs),
2160 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2161 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2162 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2163 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2164 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2167 let mayStore=1, neverHasSideEffects=1 in {
2168 defm STV_i8 : ST_VEC<Int16Regs>;
2169 defm STV_i16 : ST_VEC<Int16Regs>;
2170 defm STV_i32 : ST_VEC<Int32Regs>;
2171 defm STV_i64 : ST_VEC<Int64Regs>;
2172 defm STV_f32 : ST_VEC<Float32Regs>;
2173 defm STV_f64 : ST_VEC<Float64Regs>;
2177 //---- Conversion ----
2179 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
2180 // we cannot specify floating-point literals in isel patterns. Therefore, we
2181 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
2184 def : Pat<(f32 (sint_to_fp Int1Regs:$a)),
2185 (CVT_f32_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2186 def : Pat<(f32 (sint_to_fp Int16Regs:$a)),
2187 (CVT_f32_s16 Int16Regs:$a, CvtRN)>;
2188 def : Pat<(f32 (sint_to_fp Int32Regs:$a)),
2189 (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
2190 def : Pat<(f32 (sint_to_fp Int64Regs:$a)),
2191 (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
2194 def : Pat<(f32 (uint_to_fp Int1Regs:$a)),
2195 (CVT_f32_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2196 def : Pat<(f32 (uint_to_fp Int16Regs:$a)),
2197 (CVT_f32_u16 Int16Regs:$a, CvtRN)>;
2198 def : Pat<(f32 (uint_to_fp Int32Regs:$a)),
2199 (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
2200 def : Pat<(f32 (uint_to_fp Int64Regs:$a)),
2201 (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
2204 def : Pat<(f64 (sint_to_fp Int1Regs:$a)),
2205 (CVT_f64_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2206 def : Pat<(f64 (sint_to_fp Int16Regs:$a)),
2207 (CVT_f64_s16 Int16Regs:$a, CvtRN)>;
2208 def : Pat<(f64 (sint_to_fp Int32Regs:$a)),
2209 (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
2210 def : Pat<(f64 (sint_to_fp Int64Regs:$a)),
2211 (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
2214 def : Pat<(f64 (uint_to_fp Int1Regs:$a)),
2215 (CVT_f64_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2216 def : Pat<(f64 (uint_to_fp Int16Regs:$a)),
2217 (CVT_f64_u16 Int16Regs:$a, CvtRN)>;
2218 def : Pat<(f64 (uint_to_fp Int32Regs:$a)),
2219 (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
2220 def : Pat<(f64 (uint_to_fp Int64Regs:$a)),
2221 (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
2225 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2226 (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2227 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2228 (CVT_s16_f32 Float32Regs:$a, CvtRZI)>;
2229 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2230 (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2231 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2232 (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
2233 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2234 (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2235 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2236 (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
2239 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2240 (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2241 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2242 (CVT_u16_f32 Float32Regs:$a, CvtRZI)>;
2243 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2244 (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2245 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2246 (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
2247 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2248 (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2249 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2250 (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
2253 def : Pat<(i16 (fp_to_sint Float64Regs:$a)),
2254 (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;
2255 def : Pat<(i32 (fp_to_sint Float64Regs:$a)),
2256 (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
2257 def : Pat<(i64 (fp_to_sint Float64Regs:$a)),
2258 (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
2261 def : Pat<(i16 (fp_to_uint Float64Regs:$a)),
2262 (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;
2263 def : Pat<(i32 (fp_to_uint Float64Regs:$a)),
2264 (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
2265 def : Pat<(i64 (fp_to_uint Float64Regs:$a)),
2266 (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
2269 def : Pat<(i16 (sext Int1Regs:$a)),
2270 (SELP_s16ii -1, 0, Int1Regs:$a)>;
2271 def : Pat<(i32 (sext Int1Regs:$a)),
2272 (SELP_s32ii -1, 0, Int1Regs:$a)>;
2273 def : Pat<(i64 (sext Int1Regs:$a)),
2274 (SELP_s64ii -1, 0, Int1Regs:$a)>;
2277 def : Pat<(i16 (zext Int1Regs:$a)),
2278 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2279 def : Pat<(i32 (zext Int1Regs:$a)),
2280 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2281 def : Pat<(i64 (zext Int1Regs:$a)),
2282 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2285 def : Pat<(i16 (anyext Int1Regs:$a)),
2286 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2287 def : Pat<(i32 (anyext Int1Regs:$a)),
2288 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2289 def : Pat<(i64 (anyext Int1Regs:$a)),
2290 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2293 def : Pat<(i32 (sext Int16Regs:$a)),
2294 (CVT_s32_s16 Int16Regs:$a, CvtNONE)>;
2295 def : Pat<(i64 (sext Int16Regs:$a)),
2296 (CVT_s64_s16 Int16Regs:$a, CvtNONE)>;
2299 def : Pat<(i32 (zext Int16Regs:$a)),
2300 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2301 def : Pat<(i64 (zext Int16Regs:$a)),
2302 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2305 def : Pat<(i32 (anyext Int16Regs:$a)),
2306 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2307 def : Pat<(i64 (anyext Int16Regs:$a)),
2308 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2311 def : Pat<(i64 (sext Int32Regs:$a)),
2312 (CVT_s64_s32 Int32Regs:$a, CvtNONE)>;
2315 def : Pat<(i64 (zext Int32Regs:$a)),
2316 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2319 def : Pat<(i64 (anyext Int32Regs:$a)),
2320 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2324 def : Pat<(i32 (trunc Int64Regs:$a)),
2325 (CVT_u32_u64 Int64Regs:$a, CvtNONE)>;
2326 def : Pat<(i16 (trunc Int64Regs:$a)),
2327 (CVT_u16_u64 Int64Regs:$a, CvtNONE)>;
2328 def : Pat<(i1 (trunc Int64Regs:$a)),
2329 (SETP_b64ri (ANDb64ri Int64Regs:$a, 1), 1, CmpEQ)>;
2332 def : Pat<(i16 (trunc Int32Regs:$a)),
2333 (CVT_u16_u32 Int32Regs:$a, CvtNONE)>;
2334 def : Pat<(i1 (trunc Int32Regs:$a)),
2335 (SETP_b32ri (ANDb32ri Int32Regs:$a, 1), 1, CmpEQ)>;
2338 def : Pat<(i1 (trunc Int16Regs:$a)),
2339 (SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
2342 // Select instructions with 32-bit predicates
2343 def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
2344 (SELP_b16rr Int16Regs:$a, Int16Regs:$b,
2345 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2346 def : Pat<(select Int32Regs:$pred, Int32Regs:$a, Int32Regs:$b),
2347 (SELP_b32rr Int32Regs:$a, Int32Regs:$b,
2348 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2349 def : Pat<(select Int32Regs:$pred, Int64Regs:$a, Int64Regs:$b),
2350 (SELP_b64rr Int64Regs:$a, Int64Regs:$b,
2351 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2352 def : Pat<(select Int32Regs:$pred, Float32Regs:$a, Float32Regs:$b),
2353 (SELP_f32rr Float32Regs:$a, Float32Regs:$b,
2354 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2355 def : Pat<(select Int32Regs:$pred, Float64Regs:$a, Float64Regs:$b),
2356 (SELP_f64rr Float64Regs:$a, Float64Regs:$b,
2357 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2360 class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
2361 NVPTXRegClass regclassOut> :
2362 NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
2363 !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
2364 [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
2366 def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
2367 def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
2368 def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
2369 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
2371 // pack a set of smaller int registers to a larger int register
2372 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
2373 (ins Int16Regs:$s1, Int16Regs:$s2,
2374 Int16Regs:$s3, Int16Regs:$s4),
2375 "mov.b64\t$d, {{$s1, $s2, $s3, $s4}};",
2377 def V2I16toI32 : NVPTXInst<(outs Int32Regs:$d),
2378 (ins Int16Regs:$s1, Int16Regs:$s2),
2379 "mov.b32\t$d, {{$s1, $s2}};",
2381 def V2I32toI64 : NVPTXInst<(outs Int64Regs:$d),
2382 (ins Int32Regs:$s1, Int32Regs:$s2),
2383 "mov.b64\t$d, {{$s1, $s2}};",
2385 def V2F32toF64 : NVPTXInst<(outs Float64Regs:$d),
2386 (ins Float32Regs:$s1, Float32Regs:$s2),
2387 "mov.b64\t$d, {{$s1, $s2}};",
2390 // unpack a larger int register to a set of smaller int registers
2391 def I64toV4I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2,
2392 Int16Regs:$d3, Int16Regs:$d4),
2394 "mov.b64\t{{$d1, $d2, $d3, $d4}}, $s;",
2396 def I32toV2I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2),
2398 "mov.b32\t{{$d1, $d2}}, $s;",
2400 def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
2402 "mov.b64\t{{$d1, $d2}}, $s;",
2404 def F64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
2405 (ins Float64Regs:$s),
2406 "mov.b64\t{{$d1, $d2}}, $s;",
2409 // Count leading zeros
2410 def CLZr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2413 def CLZr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2417 // 32-bit has a direct PTX instruction
2418 def : Pat<(ctlz Int32Regs:$a),
2419 (CLZr32 Int32Regs:$a)>;
2420 def : Pat<(ctlz_zero_undef Int32Regs:$a),
2421 (CLZr32 Int32Regs:$a)>;
2423 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2424 // to 64-bit to match the LLVM semantics
2425 def : Pat<(ctlz Int64Regs:$a),
2426 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2427 def : Pat<(ctlz_zero_undef Int64Regs:$a),
2428 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2430 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2431 // to 16-bits (ctlz of a 16-bit value is guaranteed to require less
2432 // than 16 bits to store). We also need to subtract 16 because the
2433 // high-order 16 zeros were counted.
2434 def : Pat<(ctlz Int16Regs:$a),
2435 (SUBi16ri (CVT_u16_u32 (CLZr32
2436 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2438 def : Pat<(ctlz_zero_undef Int16Regs:$a),
2439 (SUBi16ri (CVT_u16_u32 (CLZr32
2440 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2444 def POPCr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2445 "popc.b32\t$d, $a;",
2447 def POPCr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2448 "popc.b64\t$d, $a;",
2451 // 32-bit has a direct PTX instruction
2452 def : Pat<(ctpop Int32Regs:$a),
2453 (POPCr32 Int32Regs:$a)>;
2455 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2456 // to 64-bit to match the LLVM semantics
2457 def : Pat<(ctpop Int64Regs:$a),
2458 (CVT_u64_u32 (POPCr64 Int64Regs:$a), CvtNONE)>;
2460 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2461 // to 16-bits (ctpop of a 16-bit value is guaranteed to require less
2462 // than 16 bits to store)
2463 def : Pat<(ctpop Int16Regs:$a),
2464 (CVT_u16_u32 (POPCr32 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2467 // fround f64 -> f32
2468 def : Pat<(f32 (fround Float64Regs:$a)),
2469 (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
2470 def : Pat<(f32 (fround Float64Regs:$a)),
2471 (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
2473 // fextend f32 -> f64
2474 def : Pat<(f64 (fextend Float32Regs:$a)),
2475 (CVT_f64_f32 Float32Regs:$a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
2476 def : Pat<(f64 (fextend Float32Regs:$a)),
2477 (CVT_f64_f32 Float32Regs:$a, CvtNONE)>;
2479 def retflag : SDNode<"NVPTXISD::RET_FLAG", SDTNone,
2480 [SDNPHasChain, SDNPOptInGlue]>;
2482 //-----------------------------------
2484 //-----------------------------------
2486 let isTerminator=1 in {
2487 let isReturn=1, isBarrier=1 in
2488 def Return : NVPTXInst<(outs), (ins), "ret;", [(retflag)]>;
2491 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2492 "@$a bra \t$target;",
2493 [(brcond Int1Regs:$a, bb:$target)]>;
2495 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2496 "@!$a bra \t$target;",
2499 let isBranch=1, isBarrier=1 in
2500 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
2501 "bra.uni \t$target;",
2505 def : Pat<(brcond Int32Regs:$a, bb:$target),
2506 (CBranch (SETP_u32ri Int32Regs:$a, 0, CmpNE), bb:$target)>;
2508 // SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
2509 // conditional branch if
2510 // the target block is the next block so that the code can fall through to the
2512 // The invertion is done by 'xor condition, 1', which will be translated to
2513 // (setne condition, -1).
2514 // Since ptx supports '@!pred bra target', we should use it.
2515 def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
2516 (CBranchOther Int1Regs:$a, bb:$target)>;
2519 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2520 def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2521 SDTCisVT<1, i32> ]>;
2523 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
2524 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
2525 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_NVPTXCallSeqEnd,
2526 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
2529 def SDT_NVPTXCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2530 def call : SDNode<"NVPTXISD::CALL", SDT_NVPTXCall,
2531 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2532 def calltarget : Operand<i32>;
2534 def CALL : NVPTXInst<(outs), (ins calltarget:$dst),
2535 "call \t$dst, (1);", []>;
2538 def : Pat<(call tglobaladdr:$dst),
2539 (CALL tglobaladdr:$dst)>;
2540 def : Pat<(call texternalsym:$dst),
2541 (CALL texternalsym:$dst)>;
2543 // Pseudo instructions.
2544 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
2545 : NVPTXInst<outs, ins, asmstr, pattern>;
2547 // @TODO: We use some tricks here to emit curly braces. Can we clean this up
2548 // a bit without TableGen modifications?
2549 def Callseq_Start : NVPTXInst<(outs), (ins i32imm:$amt),
2550 "// Callseq Start $amt\n\t{{\n\t.reg .b32 temp_param_reg;\n\t// <end>}}",
2551 [(callseq_start timm:$amt)]>;
2552 def Callseq_End : NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2553 "\n\t//{{\n\t}}// Callseq End $amt1",
2554 [(callseq_end timm:$amt1, timm:$amt2)]>;
2558 def trapinst : NVPTXInst<(outs), (ins),
2562 include "NVPTXIntrinsics.td"
2565 //-----------------------------------
2567 //-----------------------------------
2568 // BSWAP is currently expanded. The following is a more efficient
2569 // - for < sm_20, use vector scalar mov, as tesla support native 16-bit register
2570 // - for sm_20, use pmpt (use vector scalar mov to get the pack and
2571 // unpack). sm_20 supports native 32-bit register, but not native 16-bit