1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "MipsFrameLowering.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsModuleISelDAGToDAG.h"
20 #include "MipsSEFrameLowering.h"
21 #include "MipsSEInstrInfo.h"
22 #include "MipsSEISelLowering.h"
23 #include "MipsSEISelDAGToDAG.h"
24 #include "Mips16FrameLowering.h"
25 #include "Mips16HardFloat.h"
26 #include "Mips16InstrInfo.h"
27 #include "Mips16ISelDAGToDAG.h"
28 #include "Mips16ISelLowering.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Transforms/Scalar.h"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 static std::string computeDataLayout(const MipsSubtarget &ST) {
51 // There are both little and big endian mips.
57 // Pointers are 32 bit on some ABIs.
61 // 8 and 16 bit integers only need no have natural alignment, but try to
62 // align them to 32 bits. 64 bit integers have natural alignment.
63 Ret += "-i8:8:32-i16:16:32-i64:64";
65 // 32 bit registers are always available and the stack is at least 64 bit
66 // aligned. On N64 64 bit registers are also available and the stack is
68 if (ST.isABI_N64() || ST.isABI_N32())
69 Ret += "-n32:64-S128";
76 // On function prologue, the stack is created by decrementing
77 // its pointer. Once decremented, all references are done with positive
78 // offset from the stack/frame pointer, using StackGrowsUp enables
79 // an easier handling.
80 // Using CodeModel::Large enables different CALL behavior.
82 MipsTargetMachine(const Target &T, StringRef TT,
83 StringRef CPU, StringRef FS, const TargetOptions &Options,
84 Reloc::Model RM, CodeModel::Model CM,
87 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
88 Subtarget(TT, CPU, FS, isLittle, RM, this),
89 DL(computeDataLayout(Subtarget)),
90 InstrInfo(MipsInstrInfo::create(*this)),
91 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
92 TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
93 InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
98 void MipsTargetMachine::setHelperClassesMips16() {
99 InstrInfoSE.swap(InstrInfo);
100 FrameLoweringSE.swap(FrameLowering);
101 TLInfoSE.swap(TLInfo);
103 InstrInfo.reset(MipsInstrInfo::create(*this));
104 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
105 TLInfo.reset(MipsTargetLowering::create(*this));
107 InstrInfo16.swap(InstrInfo);
108 FrameLowering16.swap(FrameLowering);
109 TLInfo16.swap(TLInfo);
111 assert(TLInfo && "null target lowering 16");
112 assert(InstrInfo && "null instr info 16");
113 assert(FrameLowering && "null frame lowering 16");
116 void MipsTargetMachine::setHelperClassesMipsSE() {
117 InstrInfo16.swap(InstrInfo);
118 FrameLowering16.swap(FrameLowering);
119 TLInfo16.swap(TLInfo);
121 InstrInfo.reset(MipsInstrInfo::create(*this));
122 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
123 TLInfo.reset(MipsTargetLowering::create(*this));
125 InstrInfoSE.swap(InstrInfo);
126 FrameLoweringSE.swap(FrameLowering);
127 TLInfoSE.swap(TLInfo);
129 assert(TLInfo && "null target lowering in SE");
130 assert(InstrInfo && "null instr info SE");
131 assert(FrameLowering && "null frame lowering SE");
133 void MipsebTargetMachine::anchor() { }
135 MipsebTargetMachine::
136 MipsebTargetMachine(const Target &T, StringRef TT,
137 StringRef CPU, StringRef FS, const TargetOptions &Options,
138 Reloc::Model RM, CodeModel::Model CM,
139 CodeGenOpt::Level OL)
140 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
142 void MipselTargetMachine::anchor() { }
144 MipselTargetMachine::
145 MipselTargetMachine(const Target &T, StringRef TT,
146 StringRef CPU, StringRef FS, const TargetOptions &Options,
147 Reloc::Model RM, CodeModel::Model CM,
148 CodeGenOpt::Level OL)
149 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
152 /// Mips Code Generator Pass Configuration Options.
153 class MipsPassConfig : public TargetPassConfig {
155 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
156 : TargetPassConfig(TM, PM) {
157 // The current implementation of long branch pass requires a scratch
158 // register ($at) to be available before branch instructions. Tail merging
159 // can break this requirement, so disable it when long branch pass is
161 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
164 MipsTargetMachine &getMipsTargetMachine() const {
165 return getTM<MipsTargetMachine>();
168 const MipsSubtarget &getMipsSubtarget() const {
169 return *getMipsTargetMachine().getSubtargetImpl();
172 virtual void addIRPasses();
173 virtual bool addInstSelector();
174 virtual void addMachineSSAOptimization();
175 virtual bool addPreEmitPass();
179 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
180 return new MipsPassConfig(this, PM);
183 void MipsPassConfig::addIRPasses() {
184 TargetPassConfig::addIRPasses();
185 if (getMipsSubtarget().os16())
186 addPass(createMipsOs16(getMipsTargetMachine()));
187 if (getMipsSubtarget().inMips16HardFloat())
188 addPass(createMips16HardFloat(getMipsTargetMachine()));
189 addPass(createPartiallyInlineLibCallsPass());
191 // Install an instruction selector pass using
192 // the ISelDag to gen Mips code.
193 bool MipsPassConfig::addInstSelector() {
194 if (getMipsSubtarget().allowMixed16_32()) {
195 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
196 addPass(createMips16ISelDag(getMipsTargetMachine()));
197 addPass(createMipsSEISelDag(getMipsTargetMachine()));
199 addPass(createMipsISelDag(getMipsTargetMachine()));
204 void MipsPassConfig::addMachineSSAOptimization() {
205 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
206 TargetPassConfig::addMachineSSAOptimization();
209 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
210 if (Subtarget.allowMixed16_32()) {
211 DEBUG(errs() << "No ");
212 //FIXME: The Basic Target Transform Info
213 // pass needs to become a function pass instead of
214 // being an immutable pass and then this method as it exists now
215 // would be unnecessary.
216 PM.add(createNoTargetTransformInfoPass());
218 LLVMTargetMachine::addAnalysisPasses(PM);
219 DEBUG(errs() << "Target Transform Info Pass Added\n");
222 // Implemented by targets that want to run passes immediately before
223 // machine code is emitted. return true if -print-machineinstrs should
224 // print out the code after the passes.
225 bool MipsPassConfig::addPreEmitPass() {
226 MipsTargetMachine &TM = getMipsTargetMachine();
227 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
228 addPass(createMipsDelaySlotFillerPass(TM));
230 if (Subtarget.enableLongBranchPass())
231 addPass(createMipsLongBranchPass(TM));
232 if (Subtarget.inMips16Mode() ||
233 Subtarget.allowMixed16_32())
234 addPass(createMipsConstantIslandPass(TM));
239 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
240 JITCodeEmitter &JCE) {
241 // Machine code emitter pass for Mips.
242 PM.add(createMipsJITCodeEmitterPass(*this, JCE));