1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Transforms/Scalar.h"
38 #define DEBUG_TYPE "mips"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 // On function prologue, the stack is created by decrementing
49 // its pointer. Once decremented, all references are done with positive
50 // offset from the stack/frame pointer, using StackGrowsUp enables
51 // an easier handling.
52 // Using CodeModel::Large enables different CALL behavior.
53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
54 StringRef CPU, StringRef FS,
55 const TargetOptions &Options,
56 Reloc::Model RM, CodeModel::Model CM,
57 CodeGenOpt::Level OL, bool isLittle)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 isLittle(isLittle), Subtarget(nullptr),
60 DefaultSubtarget(TT, CPU, FS, isLittle, this),
61 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
63 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
65 Subtarget = &DefaultSubtarget;
69 void MipsebTargetMachine::anchor() { }
72 MipsebTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS, const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
76 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
78 void MipselTargetMachine::anchor() { }
81 MipselTargetMachine(const Target &T, StringRef TT,
82 StringRef CPU, StringRef FS, const TargetOptions &Options,
83 Reloc::Model RM, CodeModel::Model CM,
85 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
88 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
89 AttributeSet FnAttrs = F.getAttributes();
91 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
93 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
95 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
96 ? CPUAttr.getValueAsString().str()
98 std::string FS = !FSAttr.hasAttribute(Attribute::None)
99 ? FSAttr.getValueAsString().str()
102 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
103 .hasAttribute(Attribute::None);
104 bool hasNoMips16Attr =
105 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
106 .hasAttribute(Attribute::None);
108 // FIXME: This is related to the code below to reset the target options,
109 // we need to know whether or not the soft float flag is set on the
110 // function before we can generate a subtarget. We also need to use
111 // it as a key for the subtarget since that can be the only difference
112 // between two functions.
114 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
115 bool softFloat = !SFAttr.hasAttribute(Attribute::None)
116 ? SFAttr.getValueAsString() == "true"
117 : Options.UseSoftFloat;
120 FS += FS.empty() ? "+mips16" : ",+mips16";
121 else if (hasNoMips16Attr)
122 FS += FS.empty() ? "-mips16" : ",-mips16";
124 auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
125 : "use-soft-float=false")];
127 // This needs to be done before we create a new subtarget since any
128 // creation will depend on the TM and the code generation flags on the
129 // function that reside in TargetOptions.
130 resetTargetOptions(F);
131 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this);
136 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
137 DEBUG(dbgs() << "resetSubtarget\n");
139 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
140 MF->setSubtarget(Subtarget);
145 /// Mips Code Generator Pass Configuration Options.
146 class MipsPassConfig : public TargetPassConfig {
148 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
149 : TargetPassConfig(TM, PM) {
150 // The current implementation of long branch pass requires a scratch
151 // register ($at) to be available before branch instructions. Tail merging
152 // can break this requirement, so disable it when long branch pass is
154 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
157 MipsTargetMachine &getMipsTargetMachine() const {
158 return getTM<MipsTargetMachine>();
161 const MipsSubtarget &getMipsSubtarget() const {
162 return *getMipsTargetMachine().getSubtargetImpl();
165 void addIRPasses() override;
166 bool addInstSelector() override;
167 void addMachineSSAOptimization() override;
168 bool addPreEmitPass() override;
170 bool addPreRegAlloc() override;
175 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
176 return new MipsPassConfig(this, PM);
179 void MipsPassConfig::addIRPasses() {
180 TargetPassConfig::addIRPasses();
181 if (getMipsSubtarget().os16())
182 addPass(createMipsOs16(getMipsTargetMachine()));
183 if (getMipsSubtarget().inMips16HardFloat())
184 addPass(createMips16HardFloat(getMipsTargetMachine()));
186 // Install an instruction selector pass using
187 // the ISelDag to gen Mips code.
188 bool MipsPassConfig::addInstSelector() {
189 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
190 addPass(createMips16ISelDag(getMipsTargetMachine()));
191 addPass(createMipsSEISelDag(getMipsTargetMachine()));
195 void MipsPassConfig::addMachineSSAOptimization() {
196 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
197 TargetPassConfig::addMachineSSAOptimization();
200 bool MipsPassConfig::addPreRegAlloc() {
201 if (getOptLevel() == CodeGenOpt::None) {
202 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
209 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
210 if (Subtarget->allowMixed16_32()) {
211 DEBUG(errs() << "No ");
212 //FIXME: The Basic Target Transform Info
213 // pass needs to become a function pass instead of
214 // being an immutable pass and then this method as it exists now
215 // would be unnecessary.
216 PM.add(createNoTargetTransformInfoPass());
218 LLVMTargetMachine::addAnalysisPasses(PM);
219 DEBUG(errs() << "Target Transform Info Pass Added\n");
222 // Implemented by targets that want to run passes immediately before
223 // machine code is emitted. return true if -print-machineinstrs should
224 // print out the code after the passes.
225 bool MipsPassConfig::addPreEmitPass() {
226 MipsTargetMachine &TM = getMipsTargetMachine();
227 addPass(createMipsDelaySlotFillerPass(TM));
228 addPass(createMipsLongBranchPass(TM));
229 addPass(createMipsConstantIslandPass(TM));