lib/Target/Mips/MipsSEISelLowering.h

   1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Subclass of MipsTargetLowering specialized for mips32/64.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MipsSEISELLOWERING_H
  15 #define MipsSEISELLOWERING_H
  16
  17 #include "MipsISelLowering.h"
  18 #include "MipsRegisterInfo.h"
  19
  20 namespace llvm {
  21   class MipsSETargetLowering : public MipsTargetLowering  {
  22   public:
  23     explicit MipsSETargetLowering(MipsTargetMachine &TM);
  24
  25     virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
  26
  27     virtual MachineBasicBlock *
  28     EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
  29
  30     virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
  31       if (VT == MVT::Untyped)
  32         return Subtarget->hasDSP() ? &Mips::ACRegsDSPRegClass :
  33                                      &Mips::ACRegsRegClass;
  34
  35       return TargetLowering::getRepRegClassFor(VT);
  36     }
  37
  38   private:
  39     virtual bool
  40     isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
  41                                       unsigned NextStackOffset,
  42                                       const MipsFunctionInfo& FI) const;
  43
  44     virtual void
  45     getOpndList(SmallVectorImpl<SDValue> &Ops,
  46                 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
  47                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
  48                 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
  49
  50     MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
  51                                     MachineBasicBlock *BB) const;
  52   };
  53 }
  54
  55 #endif // MipsSEISELLOWERING_H