lib/Target/Mips/MipsSEISelLowering.h

   1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Subclass of MipsTargetLowering specialized for mips32/64.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MipsSEISELLOWERING_H
  15 #define MipsSEISELLOWERING_H
  16
  17 #include "MipsISelLowering.h"
  18 #include "MipsRegisterInfo.h"
  19
  20 namespace llvm {
  21   class MipsSETargetLowering : public MipsTargetLowering  {
  22   public:
  23     explicit MipsSETargetLowering(MipsTargetMachine &TM);
  24
  25     /// \brief Enable MSA support for the given integer type and Register
  26     /// class.
  27     void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
  28     /// \brief Enable MSA support for the given floating-point type and
  29     /// Register class.
  30     void addMSAFloatType(MVT::SimpleValueType Ty,
  31                          const TargetRegisterClass *RC);
  32
  33     bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
  34                                        bool *Fast = nullptr) const override;
  35
  36     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  37
  38     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
  39
  40     MachineBasicBlock *
  41     EmitInstrWithCustomInserter(MachineInstr *MI,
  42                                 MachineBasicBlock *MBB) const override;
  43
  44     bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
  45                             EVT VT) const override {
  46       return false;
  47     }
  48
  49     const TargetRegisterClass *getRepRegClassFor(MVT VT) const override {
  50       if (VT == MVT::Untyped)
  51         return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
  52                                      &Mips::ACC64RegClass;
  53
  54       return TargetLowering::getRepRegClassFor(VT);
  55     }
  56
  57   private:
  58     bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
  59                                      unsigned NextStackOffset,
  60                                      const MipsFunctionInfo& FI) const override;
  61
  62     void
  63     getOpndList(SmallVectorImpl<SDValue> &Ops,
  64                 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
  65                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
  66                 CallLoweringInfo &CLI, SDValue Callee,
  67                 SDValue Chain) const override;
  68
  69     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  70     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  71
  72     SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
  73                         SelectionDAG &DAG) const;
  74
  75     SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  76     SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  77     SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  78     SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  79     SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
  80     /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
  81     /// depending on the indices in the shuffle.
  82     SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
  83
  84     MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
  85                                     MachineBasicBlock *BB) const;
  86     MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
  87                                             MachineBasicBlock *BB,
  88                                             unsigned BranchOp) const;
  89     /// \brief Emit the COPY_FW pseudo instruction
  90     MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
  91                                    MachineBasicBlock *BB) const;
  92     /// \brief Emit the COPY_FD pseudo instruction
  93     MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
  94                                    MachineBasicBlock *BB) const;
  95     /// \brief Emit the INSERT_FW pseudo instruction
  96     MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
  97                                      MachineBasicBlock *BB) const;
  98     /// \brief Emit the INSERT_FD pseudo instruction
  99     MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
 100                                      MachineBasicBlock *BB) const;
 101     /// \brief Emit the FILL_FW pseudo instruction
 102     MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
 103                                    MachineBasicBlock *BB) const;
 104     /// \brief Emit the FILL_FD pseudo instruction
 105     MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
 106                                    MachineBasicBlock *BB) const;
 107     /// \brief Emit the FEXP2_W_1 pseudo instructions.
 108     MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
 109                                      MachineBasicBlock *BB) const;
 110     /// \brief Emit the FEXP2_D_1 pseudo instructions.
 111     MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
 112                                      MachineBasicBlock *BB) const;
 113   };
 114 }
 115
 116 #endif // MipsSEISELLOWERING_H