1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetInstrInfo.h"
26 #define DEBUG_TYPE "mips-isel"
29 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
30 cl::desc("MIPS: Enable tail calls."), cl::init(false));
32 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
33 cl::desc("Expand double precision loads and "
34 "stores to their single precision "
37 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
38 : MipsTargetLowering(TM) {
39 // Set up the register classes
40 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
45 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
46 // Expand all truncating stores and extending loads.
47 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
48 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
50 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
51 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
52 setTruncStoreAction((MVT::SimpleValueType)VT0,
53 (MVT::SimpleValueType)VT1, Expand);
55 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
61 if (Subtarget->hasDSP()) {
62 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
64 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
65 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
67 // Expand all builtin opcodes.
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
69 setOperationAction(Opc, VecTys[i], Expand);
71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
78 setTargetDAGCombine(ISD::SHL);
79 setTargetDAGCombine(ISD::SRA);
80 setTargetDAGCombine(ISD::SRL);
81 setTargetDAGCombine(ISD::SETCC);
82 setTargetDAGCombine(ISD::VSELECT);
85 if (Subtarget->hasDSPR2())
86 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
88 if (Subtarget->hasMSA()) {
89 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
90 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
91 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
92 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
93 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
94 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
95 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
97 setTargetDAGCombine(ISD::AND);
98 setTargetDAGCombine(ISD::OR);
99 setTargetDAGCombine(ISD::SRA);
100 setTargetDAGCombine(ISD::VSELECT);
101 setTargetDAGCombine(ISD::XOR);
104 if (!Subtarget->mipsSEUsesSoftFloat()) {
105 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
107 // When dealing with single precision only, use libcalls
108 if (!Subtarget->isSingleFloat()) {
109 if (Subtarget->isFP64bit())
110 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
112 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
116 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
117 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
118 setOperationAction(ISD::MULHS, MVT::i32, Custom);
119 setOperationAction(ISD::MULHU, MVT::i32, Custom);
121 if (Subtarget->hasCnMips())
122 setOperationAction(ISD::MUL, MVT::i64, Legal);
123 else if (isGP64bit())
124 setOperationAction(ISD::MUL, MVT::i64, Custom);
127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
131 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
132 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
135 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
136 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
144 setTargetDAGCombine(ISD::MUL);
146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
155 computeRegisterProperties();
158 const MipsTargetLowering *
159 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
160 return new MipsSETargetLowering(TM);
163 // Enable MSA support for the given integer type and Register class.
164 void MipsSETargetLowering::
165 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
166 addRegisterClass(Ty, RC);
168 // Expand all builtin opcodes.
169 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
170 setOperationAction(Opc, Ty, Expand);
172 setOperationAction(ISD::BITCAST, Ty, Legal);
173 setOperationAction(ISD::LOAD, Ty, Legal);
174 setOperationAction(ISD::STORE, Ty, Legal);
175 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
176 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
177 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
179 setOperationAction(ISD::ADD, Ty, Legal);
180 setOperationAction(ISD::AND, Ty, Legal);
181 setOperationAction(ISD::CTLZ, Ty, Legal);
182 setOperationAction(ISD::CTPOP, Ty, Legal);
183 setOperationAction(ISD::MUL, Ty, Legal);
184 setOperationAction(ISD::OR, Ty, Legal);
185 setOperationAction(ISD::SDIV, Ty, Legal);
186 setOperationAction(ISD::SREM, Ty, Legal);
187 setOperationAction(ISD::SHL, Ty, Legal);
188 setOperationAction(ISD::SRA, Ty, Legal);
189 setOperationAction(ISD::SRL, Ty, Legal);
190 setOperationAction(ISD::SUB, Ty, Legal);
191 setOperationAction(ISD::UDIV, Ty, Legal);
192 setOperationAction(ISD::UREM, Ty, Legal);
193 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
194 setOperationAction(ISD::VSELECT, Ty, Legal);
195 setOperationAction(ISD::XOR, Ty, Legal);
197 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
198 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
199 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
200 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
201 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
204 setOperationAction(ISD::SETCC, Ty, Legal);
205 setCondCodeAction(ISD::SETNE, Ty, Expand);
206 setCondCodeAction(ISD::SETGE, Ty, Expand);
207 setCondCodeAction(ISD::SETGT, Ty, Expand);
208 setCondCodeAction(ISD::SETUGE, Ty, Expand);
209 setCondCodeAction(ISD::SETUGT, Ty, Expand);
212 // Enable MSA support for the given floating-point type and Register class.
213 void MipsSETargetLowering::
214 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
215 addRegisterClass(Ty, RC);
217 // Expand all builtin opcodes.
218 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
219 setOperationAction(Opc, Ty, Expand);
221 setOperationAction(ISD::LOAD, Ty, Legal);
222 setOperationAction(ISD::STORE, Ty, Legal);
223 setOperationAction(ISD::BITCAST, Ty, Legal);
224 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
225 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
226 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
228 if (Ty != MVT::v8f16) {
229 setOperationAction(ISD::FABS, Ty, Legal);
230 setOperationAction(ISD::FADD, Ty, Legal);
231 setOperationAction(ISD::FDIV, Ty, Legal);
232 setOperationAction(ISD::FEXP2, Ty, Legal);
233 setOperationAction(ISD::FLOG2, Ty, Legal);
234 setOperationAction(ISD::FMA, Ty, Legal);
235 setOperationAction(ISD::FMUL, Ty, Legal);
236 setOperationAction(ISD::FRINT, Ty, Legal);
237 setOperationAction(ISD::FSQRT, Ty, Legal);
238 setOperationAction(ISD::FSUB, Ty, Legal);
239 setOperationAction(ISD::VSELECT, Ty, Legal);
241 setOperationAction(ISD::SETCC, Ty, Legal);
242 setCondCodeAction(ISD::SETOGE, Ty, Expand);
243 setCondCodeAction(ISD::SETOGT, Ty, Expand);
244 setCondCodeAction(ISD::SETUGE, Ty, Expand);
245 setCondCodeAction(ISD::SETUGT, Ty, Expand);
246 setCondCodeAction(ISD::SETGE, Ty, Expand);
247 setCondCodeAction(ISD::SETGT, Ty, Expand);
252 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
255 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
268 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
269 SelectionDAG &DAG) const {
270 switch(Op.getOpcode()) {
271 case ISD::LOAD: return lowerLOAD(Op, DAG);
272 case ISD::STORE: return lowerSTORE(Op, DAG);
273 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
274 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
275 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
276 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
277 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
278 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
279 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
281 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
282 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
283 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
284 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
285 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
286 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
289 return MipsTargetLowering::LowerOperation(Op, DAG);
293 // Transforms a subgraph in CurDAG if the following pattern is found:
294 // (addc multLo, Lo0), (adde multHi, Hi0),
296 // multHi/Lo: product of multiplication
297 // Lo0: initial value of Lo register
298 // Hi0: initial value of Hi register
299 // Return true if pattern matching was successful.
300 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
301 // ADDENode's second operand must be a flag output of an ADDC node in order
302 // for the matching to be successful.
303 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
305 if (ADDCNode->getOpcode() != ISD::ADDC)
308 SDValue MultHi = ADDENode->getOperand(0);
309 SDValue MultLo = ADDCNode->getOperand(0);
310 SDNode *MultNode = MultHi.getNode();
311 unsigned MultOpc = MultHi.getOpcode();
313 // MultHi and MultLo must be generated by the same node,
314 if (MultLo.getNode() != MultNode)
317 // and it must be a multiplication.
318 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
321 // MultLo amd MultHi must be the first and second output of MultNode
323 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
326 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
327 // of the values of MultNode, in which case MultNode will be removed in later
329 // If there exist users other than ADDENode or ADDCNode, this function returns
330 // here, which will result in MultNode being mapped to a single MULT
331 // instruction node rather than a pair of MULT and MADD instructions being
333 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
338 // Initialize accumulator.
339 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
340 ADDCNode->getOperand(1),
341 ADDENode->getOperand(1));
343 // create MipsMAdd(u) node
344 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
346 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
347 MultNode->getOperand(0),// Factor 0
348 MultNode->getOperand(1),// Factor 1
351 // replace uses of adde and addc here
352 if (!SDValue(ADDCNode, 0).use_empty()) {
353 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
354 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
356 if (!SDValue(ADDENode, 0).use_empty()) {
357 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
358 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
365 // Transforms a subgraph in CurDAG if the following pattern is found:
366 // (addc Lo0, multLo), (sube Hi0, multHi),
368 // multHi/Lo: product of multiplication
369 // Lo0: initial value of Lo register
370 // Hi0: initial value of Hi register
371 // Return true if pattern matching was successful.
372 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
373 // SUBENode's second operand must be a flag output of an SUBC node in order
374 // for the matching to be successful.
375 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
377 if (SUBCNode->getOpcode() != ISD::SUBC)
380 SDValue MultHi = SUBENode->getOperand(1);
381 SDValue MultLo = SUBCNode->getOperand(1);
382 SDNode *MultNode = MultHi.getNode();
383 unsigned MultOpc = MultHi.getOpcode();
385 // MultHi and MultLo must be generated by the same node,
386 if (MultLo.getNode() != MultNode)
389 // and it must be a multiplication.
390 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
393 // MultLo amd MultHi must be the first and second output of MultNode
395 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
398 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
399 // of the values of MultNode, in which case MultNode will be removed in later
401 // If there exist users other than SUBENode or SUBCNode, this function returns
402 // here, which will result in MultNode being mapped to a single MULT
403 // instruction node rather than a pair of MULT and MSUB instructions being
405 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
410 // Initialize accumulator.
411 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
412 SUBCNode->getOperand(0),
413 SUBENode->getOperand(0));
415 // create MipsSub(u) node
416 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
418 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
419 MultNode->getOperand(0),// Factor 0
420 MultNode->getOperand(1),// Factor 1
423 // replace uses of sube and subc here
424 if (!SDValue(SUBCNode, 0).use_empty()) {
425 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
426 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
428 if (!SDValue(SUBENode, 0).use_empty()) {
429 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
430 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
436 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
437 TargetLowering::DAGCombinerInfo &DCI,
438 const MipsSubtarget *Subtarget) {
439 if (DCI.isBeforeLegalize())
442 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
444 return SDValue(N, 0);
449 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
451 // Performs the following transformations:
452 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
453 // sign/zero-extension is completely overwritten by the new one performed by
455 // - Removes redundant zero extensions performed by an ISD::AND.
456 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
457 TargetLowering::DAGCombinerInfo &DCI,
458 const MipsSubtarget *Subtarget) {
459 if (!Subtarget->hasMSA())
462 SDValue Op0 = N->getOperand(0);
463 SDValue Op1 = N->getOperand(1);
464 unsigned Op0Opcode = Op0->getOpcode();
466 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
467 // where $d + 1 == 2^n and n == 32
468 // or $d + 1 == 2^n and n <= 32 and ZExt
469 // -> (MipsVExtractZExt $a, $b, $c)
470 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
471 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
472 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
477 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
479 if (Log2IfPositive <= 0)
480 return SDValue(); // Mask+1 is not a power of 2
482 SDValue Op0Op2 = Op0->getOperand(2);
483 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
484 unsigned ExtendTySize = ExtendTy.getSizeInBits();
485 unsigned Log2 = Log2IfPositive;
487 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
488 Log2 == ExtendTySize) {
489 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
490 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
491 Op0->getVTList(), Ops, Op0->getNumOperands());
499 // Determine if the specified node is a constant vector splat.
501 // Returns true and sets Imm if:
502 // * N is a ISD::BUILD_VECTOR representing a constant splat
504 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
505 // differences are that it assumes the MSA has already been checked and the
506 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
507 // must not be in order for binsri.d to be selectable).
508 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
509 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
514 APInt SplatValue, SplatUndef;
515 unsigned SplatBitSize;
518 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
527 // Test whether the given node is an all-ones build_vector.
528 static bool isVectorAllOnes(SDValue N) {
529 // Look through bitcasts. Endianness doesn't matter because we are looking
530 // for an all-ones value.
531 if (N->getOpcode() == ISD::BITCAST)
532 N = N->getOperand(0);
534 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
539 APInt SplatValue, SplatUndef;
540 unsigned SplatBitSize;
543 // Endianness doesn't matter in this context because we are looking for
544 // an all-ones value.
545 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
546 return SplatValue.isAllOnesValue();
551 // Test whether N is the bitwise inverse of OfNode.
552 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
553 if (N->getOpcode() != ISD::XOR)
556 if (isVectorAllOnes(N->getOperand(0)))
557 return N->getOperand(1) == OfNode;
559 if (isVectorAllOnes(N->getOperand(1)))
560 return N->getOperand(0) == OfNode;
565 // Perform combines where ISD::OR is the root node.
567 // Performs the following transformations:
568 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
569 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
571 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
572 TargetLowering::DAGCombinerInfo &DCI,
573 const MipsSubtarget *Subtarget) {
574 if (!Subtarget->hasMSA())
577 EVT Ty = N->getValueType(0);
579 if (!Ty.is128BitVector())
582 SDValue Op0 = N->getOperand(0);
583 SDValue Op1 = N->getOperand(1);
585 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
586 SDValue Op0Op0 = Op0->getOperand(0);
587 SDValue Op0Op1 = Op0->getOperand(1);
588 SDValue Op1Op0 = Op1->getOperand(0);
589 SDValue Op1Op1 = Op1->getOperand(1);
590 bool IsLittleEndian = !Subtarget->isLittle();
592 SDValue IfSet, IfClr, Cond;
593 bool IsConstantMask = false;
596 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
597 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
599 // IfClr will be set if we find a valid match.
600 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
604 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
605 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
607 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
608 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
611 IsConstantMask = true;
614 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
615 // thing again using this mask.
616 // IfClr will be set if we find a valid match.
617 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
621 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
622 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
624 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
625 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
628 IsConstantMask = true;
631 // If IfClr is not yet set, try looking for a non-constant match.
632 // IfClr will be set if we find a valid match amongst the eight
634 if (!IfClr.getNode()) {
635 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
639 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
643 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
647 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
651 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
655 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
659 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
663 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
670 // At this point, IfClr will be set if we have a valid match.
671 if (!IfClr.getNode())
674 assert(Cond.getNode() && IfSet.getNode());
676 // Fold degenerate cases.
677 if (IsConstantMask) {
678 if (Mask.isAllOnesValue())
684 // Transform the DAG into an equivalent VSELECT.
685 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
691 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
692 TargetLowering::DAGCombinerInfo &DCI,
693 const MipsSubtarget *Subtarget) {
694 if (DCI.isBeforeLegalize())
697 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
699 return SDValue(N, 0);
704 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
705 EVT ShiftTy, SelectionDAG &DAG) {
706 // Clear the upper (64 - VT.sizeInBits) bits.
707 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
711 return DAG.getConstant(0, VT);
717 // If c is power of 2, return (shl x, log2(c)).
718 if (isPowerOf2_64(C))
719 return DAG.getNode(ISD::SHL, DL, VT, X,
720 DAG.getConstant(Log2_64(C), ShiftTy));
722 unsigned Log2Ceil = Log2_64_Ceil(C);
723 uint64_t Floor = 1LL << Log2_64(C);
724 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
726 // If |c - floor_c| <= |c - ceil_c|,
727 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
728 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
729 if (C - Floor <= Ceil - C) {
730 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
731 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
732 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
735 // If |c - floor_c| > |c - ceil_c|,
736 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
737 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
738 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
739 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
742 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
743 const TargetLowering::DAGCombinerInfo &DCI,
744 const MipsSETargetLowering *TL) {
745 EVT VT = N->getValueType(0);
747 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
749 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
750 VT, TL->getScalarShiftAmountTy(VT), DAG);
752 return SDValue(N, 0);
755 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
757 const MipsSubtarget *Subtarget) {
758 // See if this is a vector splat immediate node.
759 APInt SplatValue, SplatUndef;
760 unsigned SplatBitSize;
762 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
763 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
765 if (!Subtarget->hasDSP())
769 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
770 EltSize, !Subtarget->isLittle()) ||
771 (SplatBitSize != EltSize) ||
772 (SplatValue.getZExtValue() >= EltSize))
775 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
776 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
779 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
780 TargetLowering::DAGCombinerInfo &DCI,
781 const MipsSubtarget *Subtarget) {
782 EVT Ty = N->getValueType(0);
784 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
787 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
790 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
791 // constant splats into MipsISD::SHRA_DSP for DSPr2.
793 // Performs the following transformations:
794 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
795 // sign/zero-extension is completely overwritten by the new one performed by
796 // the ISD::SRA and ISD::SHL nodes.
797 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
800 // See performDSPShiftCombine for more information about the transformation
802 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
803 TargetLowering::DAGCombinerInfo &DCI,
804 const MipsSubtarget *Subtarget) {
805 EVT Ty = N->getValueType(0);
807 if (Subtarget->hasMSA()) {
808 SDValue Op0 = N->getOperand(0);
809 SDValue Op1 = N->getOperand(1);
811 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
812 // where $d + sizeof($c) == 32
813 // or $d + sizeof($c) <= 32 and SExt
814 // -> (MipsVExtractSExt $a, $b, $c)
815 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
816 SDValue Op0Op0 = Op0->getOperand(0);
817 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
822 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
823 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
826 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
827 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
829 if (TotalBits == 32 ||
830 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
832 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
833 Op0Op0->getOperand(2) };
834 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
835 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
841 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
844 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
848 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
849 TargetLowering::DAGCombinerInfo &DCI,
850 const MipsSubtarget *Subtarget) {
851 EVT Ty = N->getValueType(0);
853 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
856 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
859 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
860 bool IsV216 = (Ty == MVT::v2i16);
864 case ISD::SETNE: return true;
868 case ISD::SETGE: return IsV216;
872 case ISD::SETUGE: return !IsV216;
873 default: return false;
877 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
878 EVT Ty = N->getValueType(0);
880 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
883 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
886 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
887 N->getOperand(1), N->getOperand(2));
890 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
891 EVT Ty = N->getValueType(0);
893 if (Ty.is128BitVector() && Ty.isInteger()) {
894 // Try the following combines:
895 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
896 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
897 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
898 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
899 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
900 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
901 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
902 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
903 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
904 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
906 SDValue Op0 = N->getOperand(0);
908 if (Op0->getOpcode() != ISD::SETCC)
911 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
914 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
916 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
921 SDValue Op1 = N->getOperand(1);
922 SDValue Op2 = N->getOperand(2);
923 SDValue Op0Op0 = Op0->getOperand(0);
924 SDValue Op0Op1 = Op0->getOperand(1);
926 if (Op1 == Op0Op0 && Op2 == Op0Op1)
927 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
929 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
930 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
932 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
933 SDValue SetCC = N->getOperand(0);
935 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
938 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
939 SetCC.getOperand(0), SetCC.getOperand(1),
940 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
946 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
947 const MipsSubtarget *Subtarget) {
948 EVT Ty = N->getValueType(0);
950 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
951 // Try the following combines:
952 // (xor (or $a, $b), (build_vector allones))
953 // (xor (or $a, $b), (bitcast (build_vector allones)))
954 SDValue Op0 = N->getOperand(0);
955 SDValue Op1 = N->getOperand(1);
958 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
960 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
965 if (NotOp->getOpcode() == ISD::OR)
966 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
967 NotOp->getOperand(1));
974 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
975 SelectionDAG &DAG = DCI.DAG;
978 switch (N->getOpcode()) {
980 return performADDECombine(N, DAG, DCI, Subtarget);
982 Val = performANDCombine(N, DAG, DCI, Subtarget);
985 Val = performORCombine(N, DAG, DCI, Subtarget);
988 return performSUBECombine(N, DAG, DCI, Subtarget);
990 return performMULCombine(N, DAG, DCI, this);
992 return performSHLCombine(N, DAG, DCI, Subtarget);
994 return performSRACombine(N, DAG, DCI, Subtarget);
996 return performSRLCombine(N, DAG, DCI, Subtarget);
998 return performVSELECTCombine(N, DAG);
1000 Val = performXORCombine(N, DAG, Subtarget);
1003 Val = performSETCCCombine(N, DAG);
1007 if (Val.getNode()) {
1008 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1009 N->printrWithDepth(dbgs(), &DAG);
1010 dbgs() << "\n=> \n";
1011 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1016 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1020 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1021 MachineBasicBlock *BB) const {
1022 switch (MI->getOpcode()) {
1024 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1025 case Mips::BPOSGE32_PSEUDO:
1026 return emitBPOSGE32(MI, BB);
1027 case Mips::SNZ_B_PSEUDO:
1028 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1029 case Mips::SNZ_H_PSEUDO:
1030 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1031 case Mips::SNZ_W_PSEUDO:
1032 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1033 case Mips::SNZ_D_PSEUDO:
1034 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1035 case Mips::SNZ_V_PSEUDO:
1036 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1037 case Mips::SZ_B_PSEUDO:
1038 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1039 case Mips::SZ_H_PSEUDO:
1040 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1041 case Mips::SZ_W_PSEUDO:
1042 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1043 case Mips::SZ_D_PSEUDO:
1044 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1045 case Mips::SZ_V_PSEUDO:
1046 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1047 case Mips::COPY_FW_PSEUDO:
1048 return emitCOPY_FW(MI, BB);
1049 case Mips::COPY_FD_PSEUDO:
1050 return emitCOPY_FD(MI, BB);
1051 case Mips::INSERT_FW_PSEUDO:
1052 return emitINSERT_FW(MI, BB);
1053 case Mips::INSERT_FD_PSEUDO:
1054 return emitINSERT_FD(MI, BB);
1055 case Mips::FILL_FW_PSEUDO:
1056 return emitFILL_FW(MI, BB);
1057 case Mips::FILL_FD_PSEUDO:
1058 return emitFILL_FD(MI, BB);
1059 case Mips::FEXP2_W_1_PSEUDO:
1060 return emitFEXP2_W_1(MI, BB);
1061 case Mips::FEXP2_D_1_PSEUDO:
1062 return emitFEXP2_D_1(MI, BB);
1066 bool MipsSETargetLowering::
1067 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1068 unsigned NextStackOffset,
1069 const MipsFunctionInfo& FI) const {
1070 if (!EnableMipsTailCalls)
1073 // Return false if either the callee or caller has a byval argument.
1074 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1077 // Return true if the callee's argument area is no larger than the
1079 return NextStackOffset <= FI.getIncomingArgSize();
1082 void MipsSETargetLowering::
1083 getOpndList(SmallVectorImpl<SDValue> &Ops,
1084 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1085 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1086 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1087 Ops.push_back(Callee);
1088 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1089 InternalLinkage, CLI, Callee, Chain);
1092 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1093 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1095 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1096 return MipsTargetLowering::lowerLOAD(Op, DAG);
1098 // Replace a double precision load with two i32 loads and a buildpair64.
1100 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1101 EVT PtrVT = Ptr.getValueType();
1103 // i32 load from lower address.
1104 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1105 MachinePointerInfo(), Nd.isVolatile(),
1106 Nd.isNonTemporal(), Nd.isInvariant(),
1109 // i32 load from higher address.
1110 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1111 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1112 MachinePointerInfo(), Nd.isVolatile(),
1113 Nd.isNonTemporal(), Nd.isInvariant(),
1114 std::min(Nd.getAlignment(), 4U));
1116 if (!Subtarget->isLittle())
1119 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1120 SDValue Ops[2] = {BP, Hi.getValue(1)};
1121 return DAG.getMergeValues(Ops, DL);
1124 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1125 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1127 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1128 return MipsTargetLowering::lowerSTORE(Op, DAG);
1130 // Replace a double precision store with two extractelement64s and i32 stores.
1132 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1133 EVT PtrVT = Ptr.getValueType();
1134 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1135 Val, DAG.getConstant(0, MVT::i32));
1136 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1137 Val, DAG.getConstant(1, MVT::i32));
1139 if (!Subtarget->isLittle())
1142 // i32 store to lower address.
1143 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1144 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1147 // i32 store to higher address.
1148 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1149 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1150 Nd.isVolatile(), Nd.isNonTemporal(),
1151 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1154 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1155 bool HasLo, bool HasHi,
1156 SelectionDAG &DAG) const {
1157 EVT Ty = Op.getOperand(0).getValueType();
1159 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1160 Op.getOperand(0), Op.getOperand(1));
1164 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1166 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1168 if (!HasLo || !HasHi)
1169 return HasLo ? Lo : Hi;
1171 SDValue Vals[] = { Lo, Hi };
1172 return DAG.getMergeValues(Vals, DL);
1176 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1177 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1178 DAG.getConstant(0, MVT::i32));
1179 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1180 DAG.getConstant(1, MVT::i32));
1181 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1184 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1185 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1186 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1187 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1190 // This function expands mips intrinsic nodes which have 64-bit input operands
1191 // or output values.
1193 // out64 = intrinsic-node in64
1195 // lo = copy (extract-element (in64, 0))
1196 // hi = copy (extract-element (in64, 1))
1197 // mips-specific-node
1200 // out64 = merge-values (v0, v1)
1202 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1204 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1205 SmallVector<SDValue, 3> Ops;
1208 // See if Op has a chain input.
1210 Ops.push_back(Op->getOperand(OpNo++));
1212 // The next operand is the intrinsic opcode.
1213 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1215 // See if the next operand has type i64.
1216 SDValue Opnd = Op->getOperand(++OpNo), In64;
1218 if (Opnd.getValueType() == MVT::i64)
1219 In64 = initAccumulator(Opnd, DL, DAG);
1221 Ops.push_back(Opnd);
1223 // Push the remaining operands.
1224 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1225 Ops.push_back(Op->getOperand(OpNo));
1227 // Add In64 to the end of the list.
1229 Ops.push_back(In64);
1232 SmallVector<EVT, 2> ResTys;
1234 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1236 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1239 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1240 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1245 assert(Val->getValueType(1) == MVT::Other);
1246 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1247 return DAG.getMergeValues(Vals, DL);
1250 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1251 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1253 SDValue Vec = Op->getOperand(1);
1254 SDValue Idx = Op->getOperand(2);
1255 EVT ResTy = Op->getValueType(0);
1256 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1258 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1259 DAG.getValueType(EltTy));
1264 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1265 EVT ResVecTy = Op->getValueType(0);
1266 EVT ViaVecTy = ResVecTy;
1269 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1270 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1273 SDValue LaneB = Op->getOperand(2);
1275 if (ResVecTy == MVT::v2i64) {
1276 LaneA = DAG.getConstant(0, MVT::i32);
1277 ViaVecTy = MVT::v4i32;
1281 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1282 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1284 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1285 ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
1287 if (ViaVecTy != ResVecTy)
1288 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1293 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1294 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1297 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1298 bool BigEndian, SelectionDAG &DAG) {
1299 EVT ViaVecTy = VecTy;
1300 SDValue SplatValueA = SplatValue;
1301 SDValue SplatValueB = SplatValue;
1302 SDLoc DL(SplatValue);
1304 if (VecTy == MVT::v2i64) {
1305 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1306 ViaVecTy = MVT::v4i32;
1308 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1309 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1310 DAG.getConstant(32, MVT::i32));
1311 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1314 // We currently hold the parts in little endian order. Swap them if
1317 std::swap(SplatValueA, SplatValueB);
1319 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1320 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1321 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1322 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1324 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1325 ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
1327 if (VecTy != ViaVecTy)
1328 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1333 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1334 unsigned Opc, SDValue Imm,
1336 EVT VecTy = Op->getValueType(0);
1340 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1342 if (VecTy == MVT::v2i64) {
1343 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1344 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1346 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1347 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1350 std::swap(BitImmLoOp, BitImmHiOp);
1353 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1354 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1355 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1359 if (!Exp2Imm.getNode()) {
1360 // We couldnt constant fold, do a vector shift instead
1362 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1363 // only values 0-63 are valid.
1364 if (VecTy == MVT::v2i64)
1365 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1367 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1370 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1373 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1376 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1377 EVT ResTy = Op->getValueType(0);
1379 SDValue One = DAG.getConstant(1, ResTy);
1380 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1382 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1383 DAG.getNOT(DL, Bit, ResTy));
1386 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1388 EVT ResTy = Op->getValueType(0);
1389 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1390 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1391 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1393 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1396 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1397 SelectionDAG &DAG) const {
1400 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1403 case Intrinsic::mips_shilo:
1404 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1405 case Intrinsic::mips_dpau_h_qbl:
1406 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1407 case Intrinsic::mips_dpau_h_qbr:
1408 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1409 case Intrinsic::mips_dpsu_h_qbl:
1410 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1411 case Intrinsic::mips_dpsu_h_qbr:
1412 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1413 case Intrinsic::mips_dpa_w_ph:
1414 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1415 case Intrinsic::mips_dps_w_ph:
1416 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1417 case Intrinsic::mips_dpax_w_ph:
1418 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1419 case Intrinsic::mips_dpsx_w_ph:
1420 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1421 case Intrinsic::mips_mulsa_w_ph:
1422 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1423 case Intrinsic::mips_mult:
1424 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1425 case Intrinsic::mips_multu:
1426 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1427 case Intrinsic::mips_madd:
1428 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1429 case Intrinsic::mips_maddu:
1430 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1431 case Intrinsic::mips_msub:
1432 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1433 case Intrinsic::mips_msubu:
1434 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1435 case Intrinsic::mips_addv_b:
1436 case Intrinsic::mips_addv_h:
1437 case Intrinsic::mips_addv_w:
1438 case Intrinsic::mips_addv_d:
1439 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1441 case Intrinsic::mips_addvi_b:
1442 case Intrinsic::mips_addvi_h:
1443 case Intrinsic::mips_addvi_w:
1444 case Intrinsic::mips_addvi_d:
1445 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1446 lowerMSASplatImm(Op, 2, DAG));
1447 case Intrinsic::mips_and_v:
1448 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1450 case Intrinsic::mips_andi_b:
1451 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1452 lowerMSASplatImm(Op, 2, DAG));
1453 case Intrinsic::mips_bclr_b:
1454 case Intrinsic::mips_bclr_h:
1455 case Intrinsic::mips_bclr_w:
1456 case Intrinsic::mips_bclr_d:
1457 return lowerMSABitClear(Op, DAG);
1458 case Intrinsic::mips_bclri_b:
1459 case Intrinsic::mips_bclri_h:
1460 case Intrinsic::mips_bclri_w:
1461 case Intrinsic::mips_bclri_d:
1462 return lowerMSABitClearImm(Op, DAG);
1463 case Intrinsic::mips_binsli_b:
1464 case Intrinsic::mips_binsli_h:
1465 case Intrinsic::mips_binsli_w:
1466 case Intrinsic::mips_binsli_d: {
1467 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1468 EVT VecTy = Op->getValueType(0);
1469 EVT EltTy = VecTy.getVectorElementType();
1470 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1471 Op->getConstantOperandVal(3));
1472 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1473 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1476 case Intrinsic::mips_binsri_b:
1477 case Intrinsic::mips_binsri_h:
1478 case Intrinsic::mips_binsri_w:
1479 case Intrinsic::mips_binsri_d: {
1480 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1481 EVT VecTy = Op->getValueType(0);
1482 EVT EltTy = VecTy.getVectorElementType();
1483 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1484 Op->getConstantOperandVal(3));
1485 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1486 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1489 case Intrinsic::mips_bmnz_v:
1490 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1491 Op->getOperand(2), Op->getOperand(1));
1492 case Intrinsic::mips_bmnzi_b:
1493 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1494 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1496 case Intrinsic::mips_bmz_v:
1497 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1498 Op->getOperand(1), Op->getOperand(2));
1499 case Intrinsic::mips_bmzi_b:
1500 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1501 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1503 case Intrinsic::mips_bneg_b:
1504 case Intrinsic::mips_bneg_h:
1505 case Intrinsic::mips_bneg_w:
1506 case Intrinsic::mips_bneg_d: {
1507 EVT VecTy = Op->getValueType(0);
1508 SDValue One = DAG.getConstant(1, VecTy);
1510 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1511 DAG.getNode(ISD::SHL, DL, VecTy, One,
1512 Op->getOperand(2)));
1514 case Intrinsic::mips_bnegi_b:
1515 case Intrinsic::mips_bnegi_h:
1516 case Intrinsic::mips_bnegi_w:
1517 case Intrinsic::mips_bnegi_d:
1518 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1519 !Subtarget->isLittle());
1520 case Intrinsic::mips_bnz_b:
1521 case Intrinsic::mips_bnz_h:
1522 case Intrinsic::mips_bnz_w:
1523 case Intrinsic::mips_bnz_d:
1524 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1526 case Intrinsic::mips_bnz_v:
1527 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1529 case Intrinsic::mips_bsel_v:
1530 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1531 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1532 Op->getOperand(1), Op->getOperand(3),
1534 case Intrinsic::mips_bseli_b:
1535 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1536 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1537 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1539 case Intrinsic::mips_bset_b:
1540 case Intrinsic::mips_bset_h:
1541 case Intrinsic::mips_bset_w:
1542 case Intrinsic::mips_bset_d: {
1543 EVT VecTy = Op->getValueType(0);
1544 SDValue One = DAG.getConstant(1, VecTy);
1546 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1547 DAG.getNode(ISD::SHL, DL, VecTy, One,
1548 Op->getOperand(2)));
1550 case Intrinsic::mips_bseti_b:
1551 case Intrinsic::mips_bseti_h:
1552 case Intrinsic::mips_bseti_w:
1553 case Intrinsic::mips_bseti_d:
1554 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1555 !Subtarget->isLittle());
1556 case Intrinsic::mips_bz_b:
1557 case Intrinsic::mips_bz_h:
1558 case Intrinsic::mips_bz_w:
1559 case Intrinsic::mips_bz_d:
1560 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1562 case Intrinsic::mips_bz_v:
1563 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1565 case Intrinsic::mips_ceq_b:
1566 case Intrinsic::mips_ceq_h:
1567 case Intrinsic::mips_ceq_w:
1568 case Intrinsic::mips_ceq_d:
1569 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1570 Op->getOperand(2), ISD::SETEQ);
1571 case Intrinsic::mips_ceqi_b:
1572 case Intrinsic::mips_ceqi_h:
1573 case Intrinsic::mips_ceqi_w:
1574 case Intrinsic::mips_ceqi_d:
1575 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1576 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1577 case Intrinsic::mips_cle_s_b:
1578 case Intrinsic::mips_cle_s_h:
1579 case Intrinsic::mips_cle_s_w:
1580 case Intrinsic::mips_cle_s_d:
1581 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1582 Op->getOperand(2), ISD::SETLE);
1583 case Intrinsic::mips_clei_s_b:
1584 case Intrinsic::mips_clei_s_h:
1585 case Intrinsic::mips_clei_s_w:
1586 case Intrinsic::mips_clei_s_d:
1587 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1588 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1589 case Intrinsic::mips_cle_u_b:
1590 case Intrinsic::mips_cle_u_h:
1591 case Intrinsic::mips_cle_u_w:
1592 case Intrinsic::mips_cle_u_d:
1593 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1594 Op->getOperand(2), ISD::SETULE);
1595 case Intrinsic::mips_clei_u_b:
1596 case Intrinsic::mips_clei_u_h:
1597 case Intrinsic::mips_clei_u_w:
1598 case Intrinsic::mips_clei_u_d:
1599 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1600 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1601 case Intrinsic::mips_clt_s_b:
1602 case Intrinsic::mips_clt_s_h:
1603 case Intrinsic::mips_clt_s_w:
1604 case Intrinsic::mips_clt_s_d:
1605 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1606 Op->getOperand(2), ISD::SETLT);
1607 case Intrinsic::mips_clti_s_b:
1608 case Intrinsic::mips_clti_s_h:
1609 case Intrinsic::mips_clti_s_w:
1610 case Intrinsic::mips_clti_s_d:
1611 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1612 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1613 case Intrinsic::mips_clt_u_b:
1614 case Intrinsic::mips_clt_u_h:
1615 case Intrinsic::mips_clt_u_w:
1616 case Intrinsic::mips_clt_u_d:
1617 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1618 Op->getOperand(2), ISD::SETULT);
1619 case Intrinsic::mips_clti_u_b:
1620 case Intrinsic::mips_clti_u_h:
1621 case Intrinsic::mips_clti_u_w:
1622 case Intrinsic::mips_clti_u_d:
1623 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1624 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1625 case Intrinsic::mips_copy_s_b:
1626 case Intrinsic::mips_copy_s_h:
1627 case Intrinsic::mips_copy_s_w:
1628 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1629 case Intrinsic::mips_copy_s_d:
1631 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1632 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1634 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1635 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1636 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1637 Op->getValueType(0), Op->getOperand(1),
1640 case Intrinsic::mips_copy_u_b:
1641 case Intrinsic::mips_copy_u_h:
1642 case Intrinsic::mips_copy_u_w:
1643 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1644 case Intrinsic::mips_copy_u_d:
1646 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1647 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1649 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1650 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1651 // Note: When i64 is illegal, this results in copy_s.w instructions
1652 // instead of copy_u.w instructions. This makes no difference to the
1653 // behaviour since i64 is only illegal when the register file is 32-bit.
1654 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1655 Op->getValueType(0), Op->getOperand(1),
1658 case Intrinsic::mips_div_s_b:
1659 case Intrinsic::mips_div_s_h:
1660 case Intrinsic::mips_div_s_w:
1661 case Intrinsic::mips_div_s_d:
1662 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1664 case Intrinsic::mips_div_u_b:
1665 case Intrinsic::mips_div_u_h:
1666 case Intrinsic::mips_div_u_w:
1667 case Intrinsic::mips_div_u_d:
1668 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1670 case Intrinsic::mips_fadd_w:
1671 case Intrinsic::mips_fadd_d:
1672 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1674 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1675 case Intrinsic::mips_fceq_w:
1676 case Intrinsic::mips_fceq_d:
1677 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1678 Op->getOperand(2), ISD::SETOEQ);
1679 case Intrinsic::mips_fcle_w:
1680 case Intrinsic::mips_fcle_d:
1681 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1682 Op->getOperand(2), ISD::SETOLE);
1683 case Intrinsic::mips_fclt_w:
1684 case Intrinsic::mips_fclt_d:
1685 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1686 Op->getOperand(2), ISD::SETOLT);
1687 case Intrinsic::mips_fcne_w:
1688 case Intrinsic::mips_fcne_d:
1689 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1690 Op->getOperand(2), ISD::SETONE);
1691 case Intrinsic::mips_fcor_w:
1692 case Intrinsic::mips_fcor_d:
1693 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1694 Op->getOperand(2), ISD::SETO);
1695 case Intrinsic::mips_fcueq_w:
1696 case Intrinsic::mips_fcueq_d:
1697 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1698 Op->getOperand(2), ISD::SETUEQ);
1699 case Intrinsic::mips_fcule_w:
1700 case Intrinsic::mips_fcule_d:
1701 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1702 Op->getOperand(2), ISD::SETULE);
1703 case Intrinsic::mips_fcult_w:
1704 case Intrinsic::mips_fcult_d:
1705 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1706 Op->getOperand(2), ISD::SETULT);
1707 case Intrinsic::mips_fcun_w:
1708 case Intrinsic::mips_fcun_d:
1709 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1710 Op->getOperand(2), ISD::SETUO);
1711 case Intrinsic::mips_fcune_w:
1712 case Intrinsic::mips_fcune_d:
1713 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1714 Op->getOperand(2), ISD::SETUNE);
1715 case Intrinsic::mips_fdiv_w:
1716 case Intrinsic::mips_fdiv_d:
1717 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1719 case Intrinsic::mips_ffint_u_w:
1720 case Intrinsic::mips_ffint_u_d:
1721 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1723 case Intrinsic::mips_ffint_s_w:
1724 case Intrinsic::mips_ffint_s_d:
1725 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1727 case Intrinsic::mips_fill_b:
1728 case Intrinsic::mips_fill_h:
1729 case Intrinsic::mips_fill_w:
1730 case Intrinsic::mips_fill_d: {
1731 SmallVector<SDValue, 16> Ops;
1732 EVT ResTy = Op->getValueType(0);
1734 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1735 Ops.push_back(Op->getOperand(1));
1737 // If ResTy is v2i64 then the type legalizer will break this node down into
1738 // an equivalent v4i32.
1739 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1741 case Intrinsic::mips_fexp2_w:
1742 case Intrinsic::mips_fexp2_d: {
1743 EVT ResTy = Op->getValueType(0);
1745 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1746 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1748 case Intrinsic::mips_flog2_w:
1749 case Intrinsic::mips_flog2_d:
1750 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1751 case Intrinsic::mips_fmadd_w:
1752 case Intrinsic::mips_fmadd_d:
1753 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1754 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1755 case Intrinsic::mips_fmul_w:
1756 case Intrinsic::mips_fmul_d:
1757 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1759 case Intrinsic::mips_fmsub_w:
1760 case Intrinsic::mips_fmsub_d: {
1761 EVT ResTy = Op->getValueType(0);
1762 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1763 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1764 Op->getOperand(2), Op->getOperand(3)));
1766 case Intrinsic::mips_frint_w:
1767 case Intrinsic::mips_frint_d:
1768 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1769 case Intrinsic::mips_fsqrt_w:
1770 case Intrinsic::mips_fsqrt_d:
1771 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1772 case Intrinsic::mips_fsub_w:
1773 case Intrinsic::mips_fsub_d:
1774 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1776 case Intrinsic::mips_ftrunc_u_w:
1777 case Intrinsic::mips_ftrunc_u_d:
1778 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1780 case Intrinsic::mips_ftrunc_s_w:
1781 case Intrinsic::mips_ftrunc_s_d:
1782 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1784 case Intrinsic::mips_ilvev_b:
1785 case Intrinsic::mips_ilvev_h:
1786 case Intrinsic::mips_ilvev_w:
1787 case Intrinsic::mips_ilvev_d:
1788 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1789 Op->getOperand(1), Op->getOperand(2));
1790 case Intrinsic::mips_ilvl_b:
1791 case Intrinsic::mips_ilvl_h:
1792 case Intrinsic::mips_ilvl_w:
1793 case Intrinsic::mips_ilvl_d:
1794 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1795 Op->getOperand(1), Op->getOperand(2));
1796 case Intrinsic::mips_ilvod_b:
1797 case Intrinsic::mips_ilvod_h:
1798 case Intrinsic::mips_ilvod_w:
1799 case Intrinsic::mips_ilvod_d:
1800 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1801 Op->getOperand(1), Op->getOperand(2));
1802 case Intrinsic::mips_ilvr_b:
1803 case Intrinsic::mips_ilvr_h:
1804 case Intrinsic::mips_ilvr_w:
1805 case Intrinsic::mips_ilvr_d:
1806 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1807 Op->getOperand(1), Op->getOperand(2));
1808 case Intrinsic::mips_insert_b:
1809 case Intrinsic::mips_insert_h:
1810 case Intrinsic::mips_insert_w:
1811 case Intrinsic::mips_insert_d:
1812 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1813 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1814 case Intrinsic::mips_insve_b:
1815 case Intrinsic::mips_insve_h:
1816 case Intrinsic::mips_insve_w:
1817 case Intrinsic::mips_insve_d:
1818 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1819 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1820 DAG.getConstant(0, MVT::i32));
1821 case Intrinsic::mips_ldi_b:
1822 case Intrinsic::mips_ldi_h:
1823 case Intrinsic::mips_ldi_w:
1824 case Intrinsic::mips_ldi_d:
1825 return lowerMSASplatImm(Op, 1, DAG);
1826 case Intrinsic::mips_lsa:
1827 case Intrinsic::mips_dlsa: {
1828 EVT ResTy = Op->getValueType(0);
1829 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1830 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1831 Op->getOperand(2), Op->getOperand(3)));
1833 case Intrinsic::mips_maddv_b:
1834 case Intrinsic::mips_maddv_h:
1835 case Intrinsic::mips_maddv_w:
1836 case Intrinsic::mips_maddv_d: {
1837 EVT ResTy = Op->getValueType(0);
1838 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1839 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1840 Op->getOperand(2), Op->getOperand(3)));
1842 case Intrinsic::mips_max_s_b:
1843 case Intrinsic::mips_max_s_h:
1844 case Intrinsic::mips_max_s_w:
1845 case Intrinsic::mips_max_s_d:
1846 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1847 Op->getOperand(1), Op->getOperand(2));
1848 case Intrinsic::mips_max_u_b:
1849 case Intrinsic::mips_max_u_h:
1850 case Intrinsic::mips_max_u_w:
1851 case Intrinsic::mips_max_u_d:
1852 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1853 Op->getOperand(1), Op->getOperand(2));
1854 case Intrinsic::mips_maxi_s_b:
1855 case Intrinsic::mips_maxi_s_h:
1856 case Intrinsic::mips_maxi_s_w:
1857 case Intrinsic::mips_maxi_s_d:
1858 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1859 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1860 case Intrinsic::mips_maxi_u_b:
1861 case Intrinsic::mips_maxi_u_h:
1862 case Intrinsic::mips_maxi_u_w:
1863 case Intrinsic::mips_maxi_u_d:
1864 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1865 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1866 case Intrinsic::mips_min_s_b:
1867 case Intrinsic::mips_min_s_h:
1868 case Intrinsic::mips_min_s_w:
1869 case Intrinsic::mips_min_s_d:
1870 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1871 Op->getOperand(1), Op->getOperand(2));
1872 case Intrinsic::mips_min_u_b:
1873 case Intrinsic::mips_min_u_h:
1874 case Intrinsic::mips_min_u_w:
1875 case Intrinsic::mips_min_u_d:
1876 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1877 Op->getOperand(1), Op->getOperand(2));
1878 case Intrinsic::mips_mini_s_b:
1879 case Intrinsic::mips_mini_s_h:
1880 case Intrinsic::mips_mini_s_w:
1881 case Intrinsic::mips_mini_s_d:
1882 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1883 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1884 case Intrinsic::mips_mini_u_b:
1885 case Intrinsic::mips_mini_u_h:
1886 case Intrinsic::mips_mini_u_w:
1887 case Intrinsic::mips_mini_u_d:
1888 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1889 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1890 case Intrinsic::mips_mod_s_b:
1891 case Intrinsic::mips_mod_s_h:
1892 case Intrinsic::mips_mod_s_w:
1893 case Intrinsic::mips_mod_s_d:
1894 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1896 case Intrinsic::mips_mod_u_b:
1897 case Intrinsic::mips_mod_u_h:
1898 case Intrinsic::mips_mod_u_w:
1899 case Intrinsic::mips_mod_u_d:
1900 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1902 case Intrinsic::mips_mulv_b:
1903 case Intrinsic::mips_mulv_h:
1904 case Intrinsic::mips_mulv_w:
1905 case Intrinsic::mips_mulv_d:
1906 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1908 case Intrinsic::mips_msubv_b:
1909 case Intrinsic::mips_msubv_h:
1910 case Intrinsic::mips_msubv_w:
1911 case Intrinsic::mips_msubv_d: {
1912 EVT ResTy = Op->getValueType(0);
1913 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1914 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1915 Op->getOperand(2), Op->getOperand(3)));
1917 case Intrinsic::mips_nlzc_b:
1918 case Intrinsic::mips_nlzc_h:
1919 case Intrinsic::mips_nlzc_w:
1920 case Intrinsic::mips_nlzc_d:
1921 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1922 case Intrinsic::mips_nor_v: {
1923 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1924 Op->getOperand(1), Op->getOperand(2));
1925 return DAG.getNOT(DL, Res, Res->getValueType(0));
1927 case Intrinsic::mips_nori_b: {
1928 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1930 lowerMSASplatImm(Op, 2, DAG));
1931 return DAG.getNOT(DL, Res, Res->getValueType(0));
1933 case Intrinsic::mips_or_v:
1934 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1936 case Intrinsic::mips_ori_b:
1937 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1938 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1939 case Intrinsic::mips_pckev_b:
1940 case Intrinsic::mips_pckev_h:
1941 case Intrinsic::mips_pckev_w:
1942 case Intrinsic::mips_pckev_d:
1943 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1944 Op->getOperand(1), Op->getOperand(2));
1945 case Intrinsic::mips_pckod_b:
1946 case Intrinsic::mips_pckod_h:
1947 case Intrinsic::mips_pckod_w:
1948 case Intrinsic::mips_pckod_d:
1949 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1950 Op->getOperand(1), Op->getOperand(2));
1951 case Intrinsic::mips_pcnt_b:
1952 case Intrinsic::mips_pcnt_h:
1953 case Intrinsic::mips_pcnt_w:
1954 case Intrinsic::mips_pcnt_d:
1955 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1956 case Intrinsic::mips_shf_b:
1957 case Intrinsic::mips_shf_h:
1958 case Intrinsic::mips_shf_w:
1959 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1960 Op->getOperand(2), Op->getOperand(1));
1961 case Intrinsic::mips_sll_b:
1962 case Intrinsic::mips_sll_h:
1963 case Intrinsic::mips_sll_w:
1964 case Intrinsic::mips_sll_d:
1965 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1967 case Intrinsic::mips_slli_b:
1968 case Intrinsic::mips_slli_h:
1969 case Intrinsic::mips_slli_w:
1970 case Intrinsic::mips_slli_d:
1971 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1972 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1973 case Intrinsic::mips_splat_b:
1974 case Intrinsic::mips_splat_h:
1975 case Intrinsic::mips_splat_w:
1976 case Intrinsic::mips_splat_d:
1977 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1978 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1979 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1980 // Instead we lower to MipsISD::VSHF and match from there.
1981 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1982 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
1984 case Intrinsic::mips_splati_b:
1985 case Intrinsic::mips_splati_h:
1986 case Intrinsic::mips_splati_w:
1987 case Intrinsic::mips_splati_d:
1988 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1989 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1991 case Intrinsic::mips_sra_b:
1992 case Intrinsic::mips_sra_h:
1993 case Intrinsic::mips_sra_w:
1994 case Intrinsic::mips_sra_d:
1995 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1997 case Intrinsic::mips_srai_b:
1998 case Intrinsic::mips_srai_h:
1999 case Intrinsic::mips_srai_w:
2000 case Intrinsic::mips_srai_d:
2001 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2002 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2003 case Intrinsic::mips_srl_b:
2004 case Intrinsic::mips_srl_h:
2005 case Intrinsic::mips_srl_w:
2006 case Intrinsic::mips_srl_d:
2007 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2009 case Intrinsic::mips_srli_b:
2010 case Intrinsic::mips_srli_h:
2011 case Intrinsic::mips_srli_w:
2012 case Intrinsic::mips_srli_d:
2013 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2014 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2015 case Intrinsic::mips_subv_b:
2016 case Intrinsic::mips_subv_h:
2017 case Intrinsic::mips_subv_w:
2018 case Intrinsic::mips_subv_d:
2019 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2021 case Intrinsic::mips_subvi_b:
2022 case Intrinsic::mips_subvi_h:
2023 case Intrinsic::mips_subvi_w:
2024 case Intrinsic::mips_subvi_d:
2025 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2026 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2027 case Intrinsic::mips_vshf_b:
2028 case Intrinsic::mips_vshf_h:
2029 case Intrinsic::mips_vshf_w:
2030 case Intrinsic::mips_vshf_d:
2031 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2032 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2033 case Intrinsic::mips_xor_v:
2034 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2036 case Intrinsic::mips_xori_b:
2037 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2038 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2042 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2044 SDValue ChainIn = Op->getOperand(0);
2045 SDValue Address = Op->getOperand(2);
2046 SDValue Offset = Op->getOperand(3);
2047 EVT ResTy = Op->getValueType(0);
2048 EVT PtrTy = Address->getValueType(0);
2050 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2052 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2056 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2057 SelectionDAG &DAG) const {
2058 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2062 case Intrinsic::mips_extp:
2063 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2064 case Intrinsic::mips_extpdp:
2065 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2066 case Intrinsic::mips_extr_w:
2067 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2068 case Intrinsic::mips_extr_r_w:
2069 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2070 case Intrinsic::mips_extr_rs_w:
2071 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2072 case Intrinsic::mips_extr_s_h:
2073 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2074 case Intrinsic::mips_mthlip:
2075 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2076 case Intrinsic::mips_mulsaq_s_w_ph:
2077 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2078 case Intrinsic::mips_maq_s_w_phl:
2079 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2080 case Intrinsic::mips_maq_s_w_phr:
2081 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2082 case Intrinsic::mips_maq_sa_w_phl:
2083 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2084 case Intrinsic::mips_maq_sa_w_phr:
2085 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2086 case Intrinsic::mips_dpaq_s_w_ph:
2087 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2088 case Intrinsic::mips_dpsq_s_w_ph:
2089 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2090 case Intrinsic::mips_dpaq_sa_l_w:
2091 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2092 case Intrinsic::mips_dpsq_sa_l_w:
2093 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2094 case Intrinsic::mips_dpaqx_s_w_ph:
2095 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2096 case Intrinsic::mips_dpaqx_sa_w_ph:
2097 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2098 case Intrinsic::mips_dpsqx_s_w_ph:
2099 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2100 case Intrinsic::mips_dpsqx_sa_w_ph:
2101 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2102 case Intrinsic::mips_ld_b:
2103 case Intrinsic::mips_ld_h:
2104 case Intrinsic::mips_ld_w:
2105 case Intrinsic::mips_ld_d:
2106 return lowerMSALoadIntr(Op, DAG, Intr);
2110 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2112 SDValue ChainIn = Op->getOperand(0);
2113 SDValue Value = Op->getOperand(2);
2114 SDValue Address = Op->getOperand(3);
2115 SDValue Offset = Op->getOperand(4);
2116 EVT PtrTy = Address->getValueType(0);
2118 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2120 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2124 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2125 SelectionDAG &DAG) const {
2126 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2130 case Intrinsic::mips_st_b:
2131 case Intrinsic::mips_st_h:
2132 case Intrinsic::mips_st_w:
2133 case Intrinsic::mips_st_d:
2134 return lowerMSAStoreIntr(Op, DAG, Intr);
2138 /// \brief Check if the given BuildVectorSDNode is a splat.
2139 /// This method currently relies on DAG nodes being reused when equivalent,
2140 /// so it's possible for this to return false even when isConstantSplat returns
2142 static bool isSplatVector(const BuildVectorSDNode *N) {
2143 unsigned int nOps = N->getNumOperands();
2144 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2146 SDValue Operand0 = N->getOperand(0);
2148 for (unsigned int i = 1; i < nOps; ++i) {
2149 if (N->getOperand(i) != Operand0)
2156 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2158 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2159 // choose to sign-extend but we could have equally chosen zero-extend. The
2160 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2161 // result into this node later (possibly changing it to a zero-extend in the
2163 SDValue MipsSETargetLowering::
2164 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2166 EVT ResTy = Op->getValueType(0);
2167 SDValue Op0 = Op->getOperand(0);
2168 EVT VecTy = Op0->getValueType(0);
2170 if (!VecTy.is128BitVector())
2173 if (ResTy.isInteger()) {
2174 SDValue Op1 = Op->getOperand(1);
2175 EVT EltTy = VecTy.getVectorElementType();
2176 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2177 DAG.getValueType(EltTy));
2183 static bool isConstantOrUndef(const SDValue Op) {
2184 if (Op->getOpcode() == ISD::UNDEF)
2186 if (dyn_cast<ConstantSDNode>(Op))
2188 if (dyn_cast<ConstantFPSDNode>(Op))
2193 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2194 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2195 if (isConstantOrUndef(Op->getOperand(i)))
2200 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2203 // Lowers according to the following rules:
2204 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2205 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2207 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2208 // is a power of 2 less than or equal to 64 and the value does not fit into a
2209 // signed 10-bit immediate
2210 // - Non-constant splats are legal as-is.
2211 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2212 // - All others are illegal and must be expanded.
2213 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2214 SelectionDAG &DAG) const {
2215 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2216 EVT ResTy = Op->getValueType(0);
2218 APInt SplatValue, SplatUndef;
2219 unsigned SplatBitSize;
2222 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2225 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2227 !Subtarget->isLittle()) && SplatBitSize <= 64) {
2228 // We can only cope with 8, 16, 32, or 64-bit elements
2229 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2233 // If the value fits into a simm10 then we can use ldi.[bhwd]
2234 // However, if it isn't an integer type we will have to bitcast from an
2235 // integer type first. Also, if there are any undefs, we must lower them
2236 // to defined values first.
2237 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2242 switch (SplatBitSize) {
2246 ViaVecTy = MVT::v16i8;
2249 ViaVecTy = MVT::v8i16;
2252 ViaVecTy = MVT::v4i32;
2255 // There's no fill.d to fall back on for 64-bit values
2259 // SelectionDAG::getConstant will promote SplatValue appropriately.
2260 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2262 // Bitcast to the type we originally wanted
2263 if (ViaVecTy != ResTy)
2264 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2267 } else if (isSplatVector(Node))
2269 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2270 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2271 // The resulting code is the same length as the expansion, but it doesn't
2272 // use memory operations
2273 EVT ResTy = Node->getValueType(0);
2275 assert(ResTy.isVector());
2277 unsigned NumElts = ResTy.getVectorNumElements();
2278 SDValue Vector = DAG.getUNDEF(ResTy);
2279 for (unsigned i = 0; i < NumElts; ++i) {
2280 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2281 Node->getOperand(i),
2282 DAG.getConstant(i, MVT::i32));
2290 // Lower VECTOR_SHUFFLE into SHF (if possible).
2292 // SHF splits the vector into blocks of four elements, then shuffles these
2293 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2295 // It is therefore possible to lower into SHF when the mask takes the form:
2296 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2297 // When undef's appear they are treated as if they were whatever value is
2298 // necessary in order to fit the above form.
2301 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2302 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2303 // i32 7, i32 6, i32 5, i32 4>
2305 // (SHF_H $w0, $w1, 27)
2306 // where the 27 comes from:
2307 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2308 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2309 SmallVector<int, 16> Indices,
2310 SelectionDAG &DAG) {
2311 int SHFIndices[4] = { -1, -1, -1, -1 };
2313 if (Indices.size() < 4)
2316 for (unsigned i = 0; i < 4; ++i) {
2317 for (unsigned j = i; j < Indices.size(); j += 4) {
2318 int Idx = Indices[j];
2320 // Convert from vector index to 4-element subvector index
2321 // If an index refers to an element outside of the subvector then give up
2324 if (Idx < 0 || Idx >= 4)
2328 // If the mask has an undef, replace it with the current index.
2329 // Note that it might still be undef if the current index is also undef
2330 if (SHFIndices[i] == -1)
2331 SHFIndices[i] = Idx;
2333 // Check that non-undef values are the same as in the mask. If they
2334 // aren't then give up
2335 if (!(Idx == -1 || Idx == SHFIndices[i]))
2340 // Calculate the immediate. Replace any remaining undefs with zero
2342 for (int i = 3; i >= 0; --i) {
2343 int Idx = SHFIndices[i];
2352 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2353 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2356 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2358 // ILVEV interleaves the even elements from each vector.
2360 // It is possible to lower into ILVEV when the mask takes the form:
2361 // <0, n, 2, n+2, 4, n+4, ...>
2362 // where n is the number of elements in the vector.
2364 // When undef's appear in the mask they are treated as if they were whatever
2365 // value is necessary in order to fit the above form.
2366 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2367 SmallVector<int, 16> Indices,
2368 SelectionDAG &DAG) {
2369 assert ((Indices.size() % 2) == 0);
2371 int WtIdx = ResTy.getVectorNumElements();
2373 for (unsigned i = 0; i < Indices.size(); i += 2) {
2374 if (Indices[i] != -1 && Indices[i] != WsIdx)
2376 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2382 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2386 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2388 // ILVOD interleaves the odd elements from each vector.
2390 // It is possible to lower into ILVOD when the mask takes the form:
2391 // <1, n+1, 3, n+3, 5, n+5, ...>
2392 // where n is the number of elements in the vector.
2394 // When undef's appear in the mask they are treated as if they were whatever
2395 // value is necessary in order to fit the above form.
2396 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2397 SmallVector<int, 16> Indices,
2398 SelectionDAG &DAG) {
2399 assert ((Indices.size() % 2) == 0);
2401 int WtIdx = ResTy.getVectorNumElements() + 1;
2403 for (unsigned i = 0; i < Indices.size(); i += 2) {
2404 if (Indices[i] != -1 && Indices[i] != WsIdx)
2406 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2412 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2416 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2418 // ILVL interleaves consecutive elements from the left half of each vector.
2420 // It is possible to lower into ILVL when the mask takes the form:
2421 // <0, n, 1, n+1, 2, n+2, ...>
2422 // where n is the number of elements in the vector.
2424 // When undef's appear in the mask they are treated as if they were whatever
2425 // value is necessary in order to fit the above form.
2426 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2427 SmallVector<int, 16> Indices,
2428 SelectionDAG &DAG) {
2429 assert ((Indices.size() % 2) == 0);
2431 int WtIdx = ResTy.getVectorNumElements();
2433 for (unsigned i = 0; i < Indices.size(); i += 2) {
2434 if (Indices[i] != -1 && Indices[i] != WsIdx)
2436 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2442 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2446 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2448 // ILVR interleaves consecutive elements from the right half of each vector.
2450 // It is possible to lower into ILVR when the mask takes the form:
2451 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2452 // where n is the number of elements in the vector and x is half n.
2454 // When undef's appear in the mask they are treated as if they were whatever
2455 // value is necessary in order to fit the above form.
2456 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2457 SmallVector<int, 16> Indices,
2458 SelectionDAG &DAG) {
2459 assert ((Indices.size() % 2) == 0);
2460 unsigned NumElts = ResTy.getVectorNumElements();
2461 int WsIdx = NumElts / 2;
2462 int WtIdx = NumElts + NumElts / 2;
2464 for (unsigned i = 0; i < Indices.size(); i += 2) {
2465 if (Indices[i] != -1 && Indices[i] != WsIdx)
2467 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2473 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2477 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2479 // PCKEV copies the even elements of each vector into the result vector.
2481 // It is possible to lower into PCKEV when the mask takes the form:
2482 // <0, 2, 4, ..., n, n+2, n+4, ...>
2483 // where n is the number of elements in the vector.
2485 // When undef's appear in the mask they are treated as if they were whatever
2486 // value is necessary in order to fit the above form.
2487 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2488 SmallVector<int, 16> Indices,
2489 SelectionDAG &DAG) {
2490 assert ((Indices.size() % 2) == 0);
2493 for (unsigned i = 0; i < Indices.size(); ++i) {
2494 if (Indices[i] != -1 && Indices[i] != Idx)
2499 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2503 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2505 // PCKOD copies the odd elements of each vector into the result vector.
2507 // It is possible to lower into PCKOD when the mask takes the form:
2508 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2509 // where n is the number of elements in the vector.
2511 // When undef's appear in the mask they are treated as if they were whatever
2512 // value is necessary in order to fit the above form.
2513 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2514 SmallVector<int, 16> Indices,
2515 SelectionDAG &DAG) {
2516 assert ((Indices.size() % 2) == 0);
2519 for (unsigned i = 0; i < Indices.size(); ++i) {
2520 if (Indices[i] != -1 && Indices[i] != Idx)
2525 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2529 // Lower VECTOR_SHUFFLE into VSHF.
2531 // This mostly consists of converting the shuffle indices in Indices into a
2532 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2533 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2534 // if the type is v8i16 and all the indices are less than 8 then the second
2535 // operand is unused and can be replaced with anything. We choose to replace it
2536 // with the used operand since this reduces the number of instructions overall.
2537 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2538 SmallVector<int, 16> Indices,
2539 SelectionDAG &DAG) {
2540 SmallVector<SDValue, 16> Ops;
2543 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2544 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2545 bool Using1stVec = false;
2546 bool Using2ndVec = false;
2548 int ResTyNumElts = ResTy.getVectorNumElements();
2550 for (int i = 0; i < ResTyNumElts; ++i) {
2551 // Idx == -1 means UNDEF
2552 int Idx = Indices[i];
2554 if (0 <= Idx && Idx < ResTyNumElts)
2556 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2560 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2562 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2564 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
2566 if (Using1stVec && Using2ndVec) {
2567 Op0 = Op->getOperand(0);
2568 Op1 = Op->getOperand(1);
2569 } else if (Using1stVec)
2570 Op0 = Op1 = Op->getOperand(0);
2571 else if (Using2ndVec)
2572 Op0 = Op1 = Op->getOperand(1);
2574 llvm_unreachable("shuffle vector mask references neither vector operand?");
2576 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2577 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2578 // VSHF concatenates the vectors in a bitwise fashion:
2579 // <0b00, 0b01> + <0b10, 0b11> ->
2580 // 0b0100 + 0b1110 -> 0b01001110
2581 // <0b10, 0b11, 0b00, 0b01>
2582 // We must therefore swap the operands to get the correct result.
2583 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2586 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2587 // indices in the shuffle.
2588 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2589 SelectionDAG &DAG) const {
2590 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2591 EVT ResTy = Op->getValueType(0);
2593 if (!ResTy.is128BitVector())
2596 int ResTyNumElts = ResTy.getVectorNumElements();
2597 SmallVector<int, 16> Indices;
2599 for (int i = 0; i < ResTyNumElts; ++i)
2600 Indices.push_back(Node->getMaskElt(i));
2602 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2603 if (Result.getNode())
2605 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2606 if (Result.getNode())
2608 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2609 if (Result.getNode())
2611 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2612 if (Result.getNode())
2614 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2615 if (Result.getNode())
2617 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2618 if (Result.getNode())
2620 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2621 if (Result.getNode())
2623 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2626 MachineBasicBlock * MipsSETargetLowering::
2627 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2629 // bposge32_pseudo $vr0
2639 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2641 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2642 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2643 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2644 DebugLoc DL = MI->getDebugLoc();
2645 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2646 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2647 MachineFunction *F = BB->getParent();
2648 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2649 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2650 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2653 F->insert(It, Sink);
2655 // Transfer the remainder of BB and its successor edges to Sink.
2656 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2658 Sink->transferSuccessorsAndUpdatePHIs(BB);
2661 BB->addSuccessor(FBB);
2662 BB->addSuccessor(TBB);
2663 FBB->addSuccessor(Sink);
2664 TBB->addSuccessor(Sink);
2666 // Insert the real bposge32 instruction to $BB.
2667 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2670 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2671 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2672 .addReg(Mips::ZERO).addImm(0);
2673 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2676 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2677 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2678 .addReg(Mips::ZERO).addImm(1);
2680 // Insert phi function to $Sink.
2681 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2682 MI->getOperand(0).getReg())
2683 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2685 MI->eraseFromParent(); // The pseudo instruction is gone now.
2689 MachineBasicBlock * MipsSETargetLowering::
2690 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2691 unsigned BranchOp) const{
2693 // vany_nonzero $rd, $ws
2704 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2706 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2707 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2708 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2709 DebugLoc DL = MI->getDebugLoc();
2710 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2711 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2712 MachineFunction *F = BB->getParent();
2713 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2714 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2715 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2718 F->insert(It, Sink);
2720 // Transfer the remainder of BB and its successor edges to Sink.
2721 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2723 Sink->transferSuccessorsAndUpdatePHIs(BB);
2726 BB->addSuccessor(FBB);
2727 BB->addSuccessor(TBB);
2728 FBB->addSuccessor(Sink);
2729 TBB->addSuccessor(Sink);
2731 // Insert the real bnz.b instruction to $BB.
2732 BuildMI(BB, DL, TII->get(BranchOp))
2733 .addReg(MI->getOperand(1).getReg())
2737 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2738 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2739 .addReg(Mips::ZERO).addImm(0);
2740 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2743 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2744 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2745 .addReg(Mips::ZERO).addImm(1);
2747 // Insert phi function to $Sink.
2748 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2749 MI->getOperand(0).getReg())
2750 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2752 MI->eraseFromParent(); // The pseudo instruction is gone now.
2756 // Emit the COPY_FW pseudo instruction.
2758 // copy_fw_pseudo $fd, $ws, n
2760 // copy_u_w $rt, $ws, $n
2763 // When n is zero, the equivalent operation can be performed with (potentially)
2764 // zero instructions due to register overlaps. This optimization is never valid
2765 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2766 MachineBasicBlock * MipsSETargetLowering::
2767 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2768 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2769 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2770 DebugLoc DL = MI->getDebugLoc();
2771 unsigned Fd = MI->getOperand(0).getReg();
2772 unsigned Ws = MI->getOperand(1).getReg();
2773 unsigned Lane = MI->getOperand(2).getImm();
2776 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2778 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2780 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
2781 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2784 MI->eraseFromParent(); // The pseudo instruction is gone now.
2788 // Emit the COPY_FD pseudo instruction.
2790 // copy_fd_pseudo $fd, $ws, n
2792 // splati.d $wt, $ws, $n
2793 // copy $fd, $wt:sub_64
2795 // When n is zero, the equivalent operation can be performed with (potentially)
2796 // zero instructions due to register overlaps. This optimization is always
2797 // valid because FR=1 mode which is the only supported mode in MSA.
2798 MachineBasicBlock * MipsSETargetLowering::
2799 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2800 assert(Subtarget->isFP64bit());
2802 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2803 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2804 unsigned Fd = MI->getOperand(0).getReg();
2805 unsigned Ws = MI->getOperand(1).getReg();
2806 unsigned Lane = MI->getOperand(2).getImm() * 2;
2807 DebugLoc DL = MI->getDebugLoc();
2810 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2812 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2814 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2815 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2818 MI->eraseFromParent(); // The pseudo instruction is gone now.
2822 // Emit the INSERT_FW pseudo instruction.
2824 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2826 // subreg_to_reg $wt:sub_lo, $fs
2827 // insve_w $wd[$n], $wd_in, $wt[0]
2829 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2830 MachineBasicBlock *BB) const {
2831 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2832 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2833 DebugLoc DL = MI->getDebugLoc();
2834 unsigned Wd = MI->getOperand(0).getReg();
2835 unsigned Wd_in = MI->getOperand(1).getReg();
2836 unsigned Lane = MI->getOperand(2).getImm();
2837 unsigned Fs = MI->getOperand(3).getReg();
2838 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2840 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2843 .addImm(Mips::sub_lo);
2844 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2850 MI->eraseFromParent(); // The pseudo instruction is gone now.
2854 // Emit the INSERT_FD pseudo instruction.
2856 // insert_fd_pseudo $wd, $fs, n
2858 // subreg_to_reg $wt:sub_64, $fs
2859 // insve_d $wd[$n], $wd_in, $wt[0]
2861 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2862 MachineBasicBlock *BB) const {
2863 assert(Subtarget->isFP64bit());
2865 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2866 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2867 DebugLoc DL = MI->getDebugLoc();
2868 unsigned Wd = MI->getOperand(0).getReg();
2869 unsigned Wd_in = MI->getOperand(1).getReg();
2870 unsigned Lane = MI->getOperand(2).getImm();
2871 unsigned Fs = MI->getOperand(3).getReg();
2872 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2874 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2877 .addImm(Mips::sub_64);
2878 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2884 MI->eraseFromParent(); // The pseudo instruction is gone now.
2888 // Emit the FILL_FW pseudo instruction.
2890 // fill_fw_pseudo $wd, $fs
2892 // implicit_def $wt1
2893 // insert_subreg $wt2:subreg_lo, $wt1, $fs
2894 // splati.w $wd, $wt2[0]
2896 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2897 MachineBasicBlock *BB) const {
2898 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2899 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2900 DebugLoc DL = MI->getDebugLoc();
2901 unsigned Wd = MI->getOperand(0).getReg();
2902 unsigned Fs = MI->getOperand(1).getReg();
2903 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2904 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2906 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2907 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2910 .addImm(Mips::sub_lo);
2911 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2913 MI->eraseFromParent(); // The pseudo instruction is gone now.
2917 // Emit the FILL_FD pseudo instruction.
2919 // fill_fd_pseudo $wd, $fs
2921 // implicit_def $wt1
2922 // insert_subreg $wt2:subreg_64, $wt1, $fs
2923 // splati.d $wd, $wt2[0]
2925 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2926 MachineBasicBlock *BB) const {
2927 assert(Subtarget->isFP64bit());
2929 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2930 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2931 DebugLoc DL = MI->getDebugLoc();
2932 unsigned Wd = MI->getOperand(0).getReg();
2933 unsigned Fs = MI->getOperand(1).getReg();
2934 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2935 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2937 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2938 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2941 .addImm(Mips::sub_64);
2942 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2944 MI->eraseFromParent(); // The pseudo instruction is gone now.
2948 // Emit the FEXP2_W_1 pseudo instructions.
2950 // fexp2_w_1_pseudo $wd, $wt
2953 // fexp2.w $wd, $ws, $wt
2955 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2956 MachineBasicBlock *BB) const {
2957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2958 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2959 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2960 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2961 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2962 DebugLoc DL = MI->getDebugLoc();
2964 // Splat 1.0 into a vector
2965 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2966 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2968 // Emit 1.0 * fexp2(Wt)
2969 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2971 .addReg(MI->getOperand(1).getReg());
2973 MI->eraseFromParent(); // The pseudo instruction is gone now.
2977 // Emit the FEXP2_D_1 pseudo instructions.
2979 // fexp2_d_1_pseudo $wd, $wt
2982 // fexp2.d $wd, $ws, $wt
2984 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2985 MachineBasicBlock *BB) const {
2986 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2987 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2988 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2989 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2990 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2991 DebugLoc DL = MI->getDebugLoc();
2993 // Splat 1.0 into a vector
2994 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2995 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2997 // Emit 1.0 * fexp2(Wt)
2998 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
3000 .addReg(MI->getOperand(1).getReg());
3002 MI->eraseFromParent(); // The pseudo instruction is gone now.