1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41 if (Subtarget->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(1).getImm();
50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
74 llvm_unreachable("Could not map int to register");
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87 const MachineInstr& MI) {
88 unsigned DstReg = 0, ZeroReg = 0;
90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
93 (MI.getOperand(2).getImm() == 0)) {
94 DstReg = MI.getOperand(0).getReg();
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98 (MI.getOperand(2).getImm() == 0)) {
99 DstReg = MI.getOperand(0).getReg();
100 ZeroReg = Mips::ZERO_64;
106 // Replace uses with ZeroReg.
107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108 E = MRI->use_end(); U != E;) {
109 MachineOperand &MO = *U;
110 unsigned OpNo = U.getOperandNo();
111 MachineInstr *MI = MO.getParent();
114 // Do not replace if it is a phi's operand or is tied to def operand.
115 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
127 if (!MipsFI->globalBaseRegSet())
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator I = MBB.begin();
132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
133 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136 const TargetRegisterClass *RC;
137 const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
138 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
140 V0 = RegInfo.createVirtualRegister(RC);
141 V1 = RegInfo.createVirtualRegister(RC);
144 MF.getRegInfo().addLiveIn(Mips::T9_64);
145 MBB.addLiveIn(Mips::T9_64);
147 // lui $v0, %hi(%neg(%gp_rel(fname)))
148 // daddu $v1, $v0, $t9
149 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150 const GlobalValue *FName = MF.getFunction();
151 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
153 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
154 .addReg(Mips::T9_64);
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
160 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
161 // Set global register to __gnu_local_gp.
163 // lui $v0, %hi(__gnu_local_gp)
164 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
166 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
168 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
172 MF.getRegInfo().addLiveIn(Mips::T9);
173 MBB.addLiveIn(Mips::T9);
176 // lui $v0, %hi(%neg(%gp_rel(fname)))
177 // addu $v1, $v0, $t9
178 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
179 const GlobalValue *FName = MF.getFunction();
180 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
181 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
182 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
184 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
190 // For O32 ABI, the following instruction sequence is emitted to initialize
191 // the global base register:
193 // 0. lui $2, %hi(_gp_disp)
194 // 1. addiu $2, $2, %lo(_gp_disp)
195 // 2. addu $globalbasereg, $2, $t9
197 // We emit only the last instruction here.
199 // GNU linker requires that the first two instructions appear at the beginning
200 // of a function and no instructions be inserted before or between them.
201 // The two instructions are emitted during lowering to MC layer in order to
202 // avoid any reordering.
204 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
205 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
207 MF.getRegInfo().addLiveIn(Mips::V0);
208 MBB.addLiveIn(Mips::V0);
209 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
210 .addReg(Mips::V0).addReg(Mips::T9);
213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
214 initGlobalBaseReg(MF);
216 MachineRegisterInfo *MRI = &MF.getRegInfo();
218 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
220 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
221 if (I->getOpcode() == Mips::RDDSP)
222 addDSPCtrlRegOperands(false, *I, MF);
223 else if (I->getOpcode() == Mips::WRDSP)
224 addDSPCtrlRegOperands(true, *I, MF);
226 replaceUsesWithZeroReg(MRI, *I);
230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
231 SDValue CmpLHS, SDLoc DL,
232 SDNode *Node) const {
233 unsigned Opc = InFlag.getOpcode(); (void)Opc;
235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
240 if (Subtarget->isGP64bit()) {
241 SLTuOp = Mips::SLTu64;
242 ADDuOp = Mips::DADDu;
245 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
246 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
247 EVT VT = LHS.getValueType();
249 SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
251 if (Subtarget->isGP64bit()) {
252 // On 64-bit targets, sltu produces an i64 but our backend currently says
253 // that SLTu64 produces an i32. We need to fix this in the long run but for
254 // now, just make the DAG type-correct by asserting the upper bits are zero.
255 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
256 CurDAG->getTargetConstant(0, VT),
258 CurDAG->getTargetConstant(Mips::sub_32, VT));
261 SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,
262 SDValue(Carry, 0), RHS);
264 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
265 SDValue(AddCarry, 0));
269 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
270 SDValue &Offset) const {
271 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
272 EVT ValTy = Addr.getValueType();
274 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
275 Offset = CurDAG->getTargetConstant(0, ValTy);
281 /// Match frameindex+offset and frameindex|offset
282 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
284 unsigned OffsetBits) const {
285 if (CurDAG->isBaseWithConstantOffset(Addr)) {
286 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
287 if (isIntN(OffsetBits, CN->getSExtValue())) {
288 EVT ValTy = Addr.getValueType();
290 // If the first operand is a FI, get the TargetFI Node
291 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
292 (Addr.getOperand(0)))
293 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
295 Base = Addr.getOperand(0);
297 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
304 /// ComplexPattern used on MipsInstrInfo
305 /// Used on Mips Load/Store instructions
306 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
307 SDValue &Offset) const {
308 // if Address is FI, get the TargetFrameIndex.
309 if (selectAddrFrameIndex(Addr, Base, Offset))
312 // on PIC code Load GA
313 if (Addr.getOpcode() == MipsISD::Wrapper) {
314 Base = Addr.getOperand(0);
315 Offset = Addr.getOperand(1);
319 if (TM.getRelocationModel() != Reloc::PIC_) {
320 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
321 Addr.getOpcode() == ISD::TargetGlobalAddress))
325 // Addresses of the form FI+const or FI|const
326 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
329 // Operand is a result from an ADD.
330 if (Addr.getOpcode() == ISD::ADD) {
331 // When loading from constant pools, load the lower address part in
332 // the instruction itself. Example, instead of:
333 // lui $2, %hi($CPI1_0)
334 // addiu $2, $2, %lo($CPI1_0)
337 // lui $2, %hi($CPI1_0)
338 // lwc1 $f0, %lo($CPI1_0)($2)
339 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
340 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
341 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
342 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
343 isa<JumpTableSDNode>(Opnd0)) {
344 Base = Addr.getOperand(0);
354 /// ComplexPattern used on MipsInstrInfo
355 /// Used on Mips Load/Store instructions
356 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
357 SDValue &Offset) const {
358 // Operand is a result from an ADD.
359 if (Addr.getOpcode() == ISD::ADD) {
360 Base = Addr.getOperand(0);
361 Offset = Addr.getOperand(1);
368 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
369 SDValue &Offset) const {
371 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
375 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
376 SDValue &Offset) const {
377 return selectAddrRegImm(Addr, Base, Offset) ||
378 selectAddrDefault(Addr, Base, Offset);
381 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
382 SDValue &Offset) const {
383 if (selectAddrFrameIndex(Addr, Base, Offset))
386 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
392 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
393 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
394 SDValue &Offset) const {
395 if (selectAddrFrameIndex(Addr, Base, Offset))
398 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
404 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
405 SDValue &Offset) const {
406 return selectAddrRegImm12(Addr, Base, Offset) ||
407 selectAddrDefault(Addr, Base, Offset);
410 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
411 SDValue &Offset) const {
412 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
413 if (isa<FrameIndexSDNode>(Base))
416 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
417 unsigned CnstOff = CN->getZExtValue();
418 return (CnstOff == (CnstOff & 0x3c));
424 // For all other cases where "lw" would be selected, don't select "lw16"
425 // because it would result in additional instructions to prepare operands.
426 if (selectAddrRegImm(Addr, Base, Offset))
429 return selectAddrDefault(Addr, Base, Offset);
432 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
433 SDValue &Offset) const {
434 if (selectAddrRegImm10(Addr, Base, Offset))
437 if (selectAddrDefault(Addr, Base, Offset))
443 // Select constant vector splats.
445 // Returns true and sets Imm if:
447 // * N is a ISD::BUILD_VECTOR representing a constant splat
448 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
449 if (!Subtarget->hasMSA())
452 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
457 APInt SplatValue, SplatUndef;
458 unsigned SplatBitSize;
461 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
463 !Subtarget->isLittle()))
471 // Select constant vector splats.
473 // In addition to the requirements of selectVSplat(), this function returns
474 // true and sets Imm if:
475 // * The splat value is the same width as the elements of the vector
476 // * The splat value fits in an integer with the specified signed-ness and
479 // This function looks through ISD::BITCAST nodes.
480 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
481 // sometimes a shuffle in big-endian mode.
483 // It's worth noting that this function is not used as part of the selection
484 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
485 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
486 // MipsSEDAGToDAGISel::selectNode.
487 bool MipsSEDAGToDAGISel::
488 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
489 unsigned ImmBitSize) const {
491 EVT EltTy = N->getValueType(0).getVectorElementType();
493 if (N->getOpcode() == ISD::BITCAST)
494 N = N->getOperand(0);
496 if (selectVSplat (N.getNode(), ImmValue) &&
497 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
498 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
499 (!Signed && ImmValue.isIntN(ImmBitSize))) {
500 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
508 // Select constant vector splats.
509 bool MipsSEDAGToDAGISel::
510 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
511 return selectVSplatCommon(N, Imm, false, 1);
514 bool MipsSEDAGToDAGISel::
515 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
516 return selectVSplatCommon(N, Imm, false, 2);
519 bool MipsSEDAGToDAGISel::
520 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
521 return selectVSplatCommon(N, Imm, false, 3);
524 // Select constant vector splats.
525 bool MipsSEDAGToDAGISel::
526 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
527 return selectVSplatCommon(N, Imm, false, 4);
530 // Select constant vector splats.
531 bool MipsSEDAGToDAGISel::
532 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
533 return selectVSplatCommon(N, Imm, false, 5);
536 // Select constant vector splats.
537 bool MipsSEDAGToDAGISel::
538 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
539 return selectVSplatCommon(N, Imm, false, 6);
542 // Select constant vector splats.
543 bool MipsSEDAGToDAGISel::
544 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
545 return selectVSplatCommon(N, Imm, false, 8);
548 // Select constant vector splats.
549 bool MipsSEDAGToDAGISel::
550 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
551 return selectVSplatCommon(N, Imm, true, 5);
554 // Select constant vector splats whose value is a power of 2.
556 // In addition to the requirements of selectVSplat(), this function returns
557 // true and sets Imm if:
558 // * The splat value is the same width as the elements of the vector
559 // * The splat value is a power of two.
561 // This function looks through ISD::BITCAST nodes.
562 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
563 // sometimes a shuffle in big-endian mode.
564 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
566 EVT EltTy = N->getValueType(0).getVectorElementType();
568 if (N->getOpcode() == ISD::BITCAST)
569 N = N->getOperand(0);
571 if (selectVSplat (N.getNode(), ImmValue) &&
572 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
573 int32_t Log2 = ImmValue.exactLogBase2();
576 Imm = CurDAG->getTargetConstant(Log2, EltTy);
584 // Select constant vector splats whose value only has a consecutive sequence
585 // of left-most bits set (e.g. 0b11...1100...00).
587 // In addition to the requirements of selectVSplat(), this function returns
588 // true and sets Imm if:
589 // * The splat value is the same width as the elements of the vector
590 // * The splat value is a consecutive sequence of left-most bits.
592 // This function looks through ISD::BITCAST nodes.
593 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
594 // sometimes a shuffle in big-endian mode.
595 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
597 EVT EltTy = N->getValueType(0).getVectorElementType();
599 if (N->getOpcode() == ISD::BITCAST)
600 N = N->getOperand(0);
602 if (selectVSplat(N.getNode(), ImmValue) &&
603 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
604 // Extract the run of set bits starting with bit zero from the bitwise
605 // inverse of ImmValue, and test that the inverse of this is the same
606 // as the original value.
607 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
609 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
617 // Select constant vector splats whose value only has a consecutive sequence
618 // of right-most bits set (e.g. 0b00...0011...11).
620 // In addition to the requirements of selectVSplat(), this function returns
621 // true and sets Imm if:
622 // * The splat value is the same width as the elements of the vector
623 // * The splat value is a consecutive sequence of right-most bits.
625 // This function looks through ISD::BITCAST nodes.
626 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
627 // sometimes a shuffle in big-endian mode.
628 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
630 EVT EltTy = N->getValueType(0).getVectorElementType();
632 if (N->getOpcode() == ISD::BITCAST)
633 N = N->getOperand(0);
635 if (selectVSplat(N.getNode(), ImmValue) &&
636 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
637 // Extract the run of set bits starting with bit zero, and test that the
638 // result is the same as the original value
639 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
640 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
648 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
649 SDValue &Imm) const {
651 EVT EltTy = N->getValueType(0).getVectorElementType();
653 if (N->getOpcode() == ISD::BITCAST)
654 N = N->getOperand(0);
656 if (selectVSplat(N.getNode(), ImmValue) &&
657 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
658 int32_t Log2 = (~ImmValue).exactLogBase2();
661 Imm = CurDAG->getTargetConstant(Log2, EltTy);
669 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
670 unsigned Opcode = Node->getOpcode();
674 // Instruction Selection not handled by the auto-generated
675 // tablegen selection should be handled here.
683 SDValue InFlag = Node->getOperand(2);
684 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
685 Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
686 return std::make_pair(true, Result);
690 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
692 SDValue InFlag = Node->getOperand(2);
693 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
694 Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
695 return std::make_pair(true, Result);
698 case ISD::ConstantFP: {
699 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
700 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
701 if (Subtarget->isGP64bit()) {
702 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
703 Mips::ZERO_64, MVT::i64);
704 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
705 } else if (Subtarget->isFP64bit()) {
706 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
707 Mips::ZERO, MVT::i32);
708 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
711 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
712 Mips::ZERO, MVT::i32);
713 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
717 return std::make_pair(true, Result);
722 case ISD::Constant: {
723 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
724 unsigned Size = CN->getValueSizeInBits(0);
729 MipsAnalyzeImmediate AnalyzeImm;
730 int64_t Imm = CN->getSExtValue();
732 const MipsAnalyzeImmediate::InstSeq &Seq =
733 AnalyzeImm.Analyze(Imm, Size, false);
735 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
738 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
741 // The first instruction can be a LUi which is different from other
742 // instructions (ADDiu, ORI and SLL) in that it does not have a register
744 if (Inst->Opc == Mips::LUi64)
745 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
748 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
749 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
752 // The remaining instructions in the sequence are handled here.
753 for (++Inst; Inst != Seq.end(); ++Inst) {
754 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
756 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
757 SDValue(RegOpnd, 0), ImmOpnd);
760 return std::make_pair(true, RegOpnd);
763 case ISD::INTRINSIC_W_CHAIN: {
764 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
768 case Intrinsic::mips_cfcmsa: {
769 SDValue ChainIn = Node->getOperand(0);
770 SDValue RegIdx = Node->getOperand(2);
771 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
772 getMSACtrlReg(RegIdx), MVT::i32);
773 return std::make_pair(true, Reg.getNode());
779 case ISD::INTRINSIC_WO_CHAIN: {
780 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
784 case Intrinsic::mips_move_v:
785 // Like an assignment but will always produce a move.v even if
787 return std::make_pair(true,
788 CurDAG->getMachineNode(Mips::MOVE_V, DL,
789 Node->getValueType(0),
790 Node->getOperand(1)));
795 case ISD::INTRINSIC_VOID: {
796 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
800 case Intrinsic::mips_ctcmsa: {
801 SDValue ChainIn = Node->getOperand(0);
802 SDValue RegIdx = Node->getOperand(2);
803 SDValue Value = Node->getOperand(3);
804 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
805 getMSACtrlReg(RegIdx), Value);
806 return std::make_pair(true, ChainOut.getNode());
812 case MipsISD::ThreadPointer: {
813 EVT PtrVT = getTargetLowering()->getPointerTy();
814 unsigned RdhwrOpc, DestReg;
816 if (PtrVT == MVT::i32) {
817 RdhwrOpc = Mips::RDHWR;
820 RdhwrOpc = Mips::RDHWR64;
821 DestReg = Mips::V1_64;
825 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
826 Node->getValueType(0),
827 CurDAG->getRegister(Mips::HWR29, MVT::i32));
828 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
830 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
831 ReplaceUses(SDValue(Node, 0), ResNode);
832 return std::make_pair(true, ResNode.getNode());
835 case ISD::BUILD_VECTOR: {
836 // Select appropriate ldi.[bhwd] instructions for constant splats of
837 // 128-bit when MSA is enabled. Fixup any register class mismatches that
838 // occur as a result.
840 // This allows the compiler to use a wider range of immediates than would
841 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
842 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
843 // 0x01010101 } without using a constant pool. This would be sub-optimal
844 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
845 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
846 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
848 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
849 APInt SplatValue, SplatUndef;
850 unsigned SplatBitSize;
853 EVT ResVecTy = BVN->getValueType(0);
856 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
857 return std::make_pair(false, nullptr);
859 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
861 !Subtarget->isLittle()))
862 return std::make_pair(false, nullptr);
864 switch (SplatBitSize) {
866 return std::make_pair(false, nullptr);
869 ViaVecTy = MVT::v16i8;
873 ViaVecTy = MVT::v8i16;
877 ViaVecTy = MVT::v4i32;
881 ViaVecTy = MVT::v2i64;
885 if (!SplatValue.isSignedIntN(10))
886 return std::make_pair(false, nullptr);
888 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
889 ViaVecTy.getVectorElementType());
891 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
893 if (ResVecTy != ViaVecTy) {
894 // If LdiOp is writing to a different register class to ResVecTy, then
895 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
896 // since the source and destination register sets contain the same
898 const TargetLowering *TLI = getTargetLowering();
899 MVT ResVecTySimple = ResVecTy.getSimpleVT();
900 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
901 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
902 ResVecTy, SDValue(Res, 0),
903 CurDAG->getTargetConstant(RC->getID(),
907 return std::make_pair(true, Res);
912 return std::make_pair(false, nullptr);
915 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
916 return new MipsSEDAGToDAGISel(TM);