1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
86 void MipsRegisterInfo::
87 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
88 unsigned SrcReg, int FI,
89 const TargetRegisterClass *RC) const
91 if (RC == Mips::CPURegsRegisterClass)
92 BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, true)
93 .addImm(0).addFrameIndex(FI);
95 assert(0 && "Can't store this register to stack slot");
98 void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
99 SmallVectorImpl<MachineOperand> &Addr,
100 const TargetRegisterClass *RC,
101 SmallVectorImpl<MachineInstr*> &NewMIs) const {
102 if (RC != Mips::CPURegsRegisterClass)
103 assert(0 && "Can't store this register");
104 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
105 .addReg(SrcReg, false, false, true);
106 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
107 MachineOperand &MO = Addr[i];
109 MIB.addReg(MO.getReg());
110 else if (MO.isImmediate())
111 MIB.addImm(MO.getImmedValue());
113 MIB.addFrameIndex(MO.getFrameIndex());
115 NewMIs.push_back(MIB);
119 void MipsRegisterInfo::
120 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned DestReg, int FI,
122 const TargetRegisterClass *RC) const
124 if (RC == Mips::CPURegsRegisterClass)
125 BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
127 assert(0 && "Can't load this register from stack slot");
130 void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
131 SmallVectorImpl<MachineOperand> &Addr,
132 const TargetRegisterClass *RC,
133 SmallVectorImpl<MachineInstr*> &NewMIs) const {
134 if (RC != Mips::CPURegsRegisterClass)
135 assert(0 && "Can't load this register");
136 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
137 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
138 MachineOperand &MO = Addr[i];
140 MIB.addReg(MO.getReg());
141 else if (MO.isImmediate())
142 MIB.addImm(MO.getImmedValue());
144 MIB.addFrameIndex(MO.getFrameIndex());
146 NewMIs.push_back(MIB);
150 void MipsRegisterInfo::
151 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
152 unsigned DestReg, unsigned SrcReg,
153 const TargetRegisterClass *DestRC,
154 const TargetRegisterClass *SrcRC) const
156 if (DestRC != SrcRC) {
157 cerr << "Not yet supported!";
161 if (DestRC == Mips::CPURegsRegisterClass)
162 BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
165 assert (0 && "Can't copy this register");
168 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator I,
171 const MachineInstr *Orig) const
173 MachineInstr *MI = Orig->clone();
174 MI->getOperand(0).setReg(DestReg);
178 MachineInstr *MipsRegisterInfo::
179 foldMemoryOperand(MachineInstr* MI,
180 SmallVectorImpl<unsigned> &Ops, int FI) const
182 if (Ops.size() != 1) return NULL;
184 MachineInstr *NewMI = NULL;
186 switch (MI->getOpcode())
189 if ((MI->getOperand(0).isRegister()) &&
190 (MI->getOperand(1).isRegister()) &&
191 (MI->getOperand(1).getReg() == Mips::ZERO) &&
192 (MI->getOperand(2).isRegister()))
194 if (Ops[0] == 0) // COPY -> STORE
195 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
196 .addImm(0).addReg(MI->getOperand(2).getReg());
198 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
199 .getReg()).addImm(0).addFrameIndex(FI);
205 NewMI->copyKillDeadInfo(MI);
209 //===----------------------------------------------------------------------===//
211 // Callee Saved Registers methods
213 //===----------------------------------------------------------------------===//
215 /// Mips Callee Saved Registers
216 const unsigned* MipsRegisterInfo::
217 getCalleeSavedRegs(const MachineFunction *MF) const
219 // Mips calle-save register range is $16-$26(s0-s7)
220 static const unsigned CalleeSavedRegs[] = {
221 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
222 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
224 return CalleeSavedRegs;
227 /// Mips Callee Saved Register Classes
228 const TargetRegisterClass* const*
229 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
231 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
232 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
233 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
234 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
235 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
237 return CalleeSavedRegClasses;
240 BitVector MipsRegisterInfo::
241 getReservedRegs(const MachineFunction &MF) const
243 BitVector Reserved(getNumRegs());
244 Reserved.set(Mips::ZERO);
245 Reserved.set(Mips::AT);
246 Reserved.set(Mips::K0);
247 Reserved.set(Mips::K1);
248 Reserved.set(Mips::GP);
249 Reserved.set(Mips::SP);
250 Reserved.set(Mips::FP);
251 Reserved.set(Mips::RA);
255 //===----------------------------------------------------------------------===//
257 // Stack Frame Processing methods
258 // +----------------------------+
260 // The stack is allocated decrementing the stack pointer on
261 // the first instruction of a function prologue. Once decremented,
262 // all stack referencesare are done thought a positive offset
263 // from the stack/frame pointer, so the stack is considering
264 // to grow up! Otherwise terrible hacks would have to be made
265 // to get this stack ABI compliant :)
267 // The stack frame required by the ABI:
272 // . saved $GP (used in PIC - not supported yet)
274 // . saved "Callee Saved" Registers
277 // StackSize -----------
279 // Offset - offset from sp after stack allocation on function prologue
281 // The sp is the stack pointer subtracted/added from the stack size
282 // at the Prologue/Epilogue
284 // References to the previous stack (to obtain arguments) are done
285 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
288 // - reference to the actual stack frame
289 // for any local area var there is smt like : FI >= 0, StackOffset: 4
292 // - reference to previous stack frame
293 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
294 // The emitted instruction will be something like:
295 // lw REGX, 16+StackSize(SP)
297 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
298 // stack references (ObjectOffset) created to reference the function
299 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
300 // possible to detect those references and the offsets are adjusted to
301 // their real location.
305 //===----------------------------------------------------------------------===//
307 // hasFP - Return true if the specified function should have a dedicated frame
308 // pointer register. This is true if the function has variable sized allocas or
309 // if frame pointer elimination is disabled.
310 bool MipsRegisterInfo::
311 hasFP(const MachineFunction &MF) const {
312 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
315 // This function eliminate ADJCALLSTACKDOWN,
316 // ADJCALLSTACKUP pseudo instructions
317 void MipsRegisterInfo::
318 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
319 MachineBasicBlock::iterator I) const {
320 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
324 // FrameIndex represent objects inside a abstract stack.
325 // We must replace FrameIndex with an stack/frame pointer
327 void MipsRegisterInfo::
328 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
329 RegScavenger *RS) const
331 MachineInstr &MI = *II;
332 MachineFunction &MF = *MI.getParent()->getParent();
335 while (!MI.getOperand(i).isFrameIndex()) {
337 assert(i < MI.getNumOperands() &&
338 "Instr doesn't have FrameIndex operand!");
341 int FrameIndex = MI.getOperand(i).getFrameIndex();
342 int stackSize = MF.getFrameInfo()->getStackSize();
343 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
346 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
347 DOUT << "<--------->\n";
349 DOUT << "FrameIndex : " << FrameIndex << "\n";
350 DOUT << "spOffset : " << spOffset << "\n";
351 DOUT << "stackSize : " << stackSize << "\n";
354 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
355 // and adjust SPOffsets considering the final stack size.
356 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
357 Offset += MI.getOperand(i-1).getImm();
360 DOUT << "Offset : " << Offset << "\n";
361 DOUT << "<--------->\n";
364 MI.getOperand(i-1).ChangeToImmediate(Offset);
365 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
368 void MipsRegisterInfo::
369 emitPrologue(MachineFunction &MF) const
371 MachineBasicBlock &MBB = MF.front();
372 MachineFrameInfo *MFI = MF.getFrameInfo();
373 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
374 MachineBasicBlock::iterator MBBI = MBB.begin();
375 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
377 // Replace the dummy '0' SPOffset by the negative
378 // offsets, as explained on LowerFORMAL_ARGUMENTS
379 MipsFI->adjustLoadArgsFI(MFI);
380 MipsFI->adjustStoreVarArgsFI(MFI);
382 // Get the number of bytes to allocate from the FrameInfo.
383 int NumBytes = (int) MFI->getStackSize();
386 DOUT << "\n<--- EMIT PROLOGUE --->\n";
387 DOUT << "Actual Stack size :" << NumBytes << "\n";
390 // No need to allocate space on the stack.
391 if (NumBytes == 0) return;
393 int FPOffset, RAOffset;
395 // Allocate space for saved RA and FP when needed
396 if ((hasFP(MF)) && (MFI->hasCalls())) {
398 RAOffset = (NumBytes+4);
400 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
404 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
410 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
411 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
412 MipsFI->setFPStackOffset(FPOffset);
413 MipsFI->setRAStackOffset(RAOffset);
416 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
417 NumBytes = ((NumBytes+Align-1)/Align*Align);
420 DOUT << "FPOffset :" << FPOffset << "\n";
421 DOUT << "RAOffset :" << RAOffset << "\n";
422 DOUT << "New stack size :" << NumBytes << "\n\n";
426 MFI->setStackSize(NumBytes);
428 // PIC speficic function prologue
430 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
432 // Adjust stack : addi sp, sp, (-imm)
433 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
434 .addReg(Mips::SP).addImm(-NumBytes);
436 // Save the return address only if the function isnt a leaf one.
437 // sw $ra, stack_loc($sp)
438 if (MFI->hasCalls()) {
439 BuildMI(MBB, MBBI, TII.get(Mips::SW))
440 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
443 // if framepointer enabled, save it and set it
444 // to point to the stack pointer
446 // sw $fp,stack_loc($sp)
447 BuildMI(MBB, MBBI, TII.get(Mips::SW))
448 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
451 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
452 .addReg(Mips::SP).addReg(Mips::ZERO);
455 // PIC speficic function prologue
456 if ((isPIC) && (MFI->hasCalls()))
457 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
458 .addImm(MipsFI->getGPStackOffset());
461 void MipsRegisterInfo::
462 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
464 MachineBasicBlock::iterator MBBI = prior(MBB.end());
465 MachineFrameInfo *MFI = MF.getFrameInfo();
466 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
468 // Get the number of bytes from FrameInfo
469 int NumBytes = (int) MFI->getStackSize();
471 // Get the FI's where RA and FP are saved.
472 int FPOffset = MipsFI->getFPStackOffset();
473 int RAOffset = MipsFI->getRAStackOffset();
475 // if framepointer enabled, restore it and restore the
479 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
480 .addReg(Mips::FP).addReg(Mips::ZERO);
482 // lw $fp,stack_loc($sp)
483 BuildMI(MBB, MBBI, TII.get(Mips::LW))
484 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
487 // Restore the return address only if the function isnt a leaf one.
488 // lw $ra, stack_loc($sp)
489 if (MFI->hasCalls()) {
490 BuildMI(MBB, MBBI, TII.get(Mips::LW))
491 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
494 // adjust stack : insert addi sp, sp, (imm)
496 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
497 .addReg(Mips::SP).addImm(NumBytes);
501 void MipsRegisterInfo::
502 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
503 // Set the SPOffset on the FI where GP must be saved/loaded.
504 MachineFrameInfo *MFI = MF.getFrameInfo();
505 if (MFI->hasCalls()) {
506 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
508 DOUT << "processFunctionBeforeFrameFinalized\n";
509 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
510 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
512 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
516 unsigned MipsRegisterInfo::
517 getRARegister() const {
521 unsigned MipsRegisterInfo::
522 getFrameRegister(MachineFunction &MF) const {
523 return hasFP(MF) ? Mips::FP : Mips::SP;
526 unsigned MipsRegisterInfo::
527 getEHExceptionRegister() const {
528 assert(0 && "What is the exception register");
532 unsigned MipsRegisterInfo::
533 getEHHandlerRegister() const {
534 assert(0 && "What is the exception handler register");
538 int MipsRegisterInfo::
539 getDwarfRegNum(unsigned RegNum, bool isEH) const {
540 assert(0 && "What is the dwarf register number");
544 #include "MipsGenRegisterInfo.inc"