1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/Target/TargetFrameInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 //#include "MipsSubtarget.h"
38 // TODO: add subtarget support
39 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
40 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
43 void MipsRegisterInfo::
44 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
45 unsigned SrcReg, int FI,
46 const TargetRegisterClass *RC) const
48 if (RC == Mips::CPURegsRegisterClass)
49 BuildMI(MBB, I, TII.get(Mips::SW)).addFrameIndex(FI)
50 .addImm(0).addReg(SrcReg, false, false, true);
52 assert(0 && "Can't store this register to stack slot");
55 void MipsRegisterInfo::
56 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
57 unsigned DestReg, int FI,
58 const TargetRegisterClass *RC) const
60 if (RC == Mips::CPURegsRegisterClass)
61 BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
63 assert(0 && "Can't load this register from stack slot");
66 void MipsRegisterInfo::
67 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
68 unsigned DestReg, unsigned SrcReg,
69 const TargetRegisterClass *RC) const
71 if (RC == Mips::CPURegsRegisterClass)
72 BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
75 assert (0 && "Can't copy this register");
78 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator I,
81 const MachineInstr *Orig) const
83 MachineInstr *MI = Orig->clone();
84 MI->getOperand(0).setReg(DestReg);
88 MachineInstr *MipsRegisterInfo::
89 foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
91 MachineInstr *NewMI = NULL;
93 switch (MI->getOpcode())
96 if ((MI->getOperand(0).isRegister()) &&
97 (MI->getOperand(1).isRegister()) &&
98 (MI->getOperand(1).getReg() == Mips::ZERO) &&
99 (MI->getOperand(2).isRegister()))
101 if (OpNum == 0) // COPY -> STORE
102 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
103 .addImm(0).addReg(MI->getOperand(2).getReg());
105 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
106 .getReg()).addImm(0).addFrameIndex(FI);
112 NewMI->copyKillDeadInfo(MI);
116 /// Mips Callee Saved Registers
117 const unsigned* MipsRegisterInfo::
118 getCalleeSavedRegs() const
120 // Mips calle-save register range is $16-$26(s0-s7)
121 static const unsigned CalleeSavedRegs[] = {
122 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
123 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
125 return CalleeSavedRegs;
128 /// Mips Callee Saved Register Classes
129 const TargetRegisterClass* const*
130 MipsRegisterInfo::getCalleeSavedRegClasses() const
132 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
133 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
136 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
138 return CalleeSavedRegClasses;
141 BitVector MipsRegisterInfo::
142 getReservedRegs(const MachineFunction &MF) const
144 BitVector Reserved(getNumRegs());
145 Reserved.set(Mips::ZERO);
146 Reserved.set(Mips::AT);
147 Reserved.set(Mips::K0);
148 Reserved.set(Mips::K1);
149 Reserved.set(Mips::GP);
150 Reserved.set(Mips::SP);
151 Reserved.set(Mips::FP);
152 Reserved.set(Mips::RA);
156 //===----------------------------------------------------------------------===//
157 // Stack Frame Processing methods
158 //===----------------------------------------------------------------------===//
160 // True if target has frame pointer
161 bool MipsRegisterInfo::
162 hasFP(const MachineFunction &MF) const {
166 // This function eliminate ADJCALLSTACKDOWN,
167 // ADJCALLSTACKUP pseudo instructions
168 void MipsRegisterInfo::
169 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator I) const {
171 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
175 // FrameIndex represent objects inside a abstract stack.
176 // We must replace FrameIndex with an stack/frame pointer
178 void MipsRegisterInfo::
179 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
180 RegScavenger *RS) const
183 MachineInstr &MI = *II;
184 MachineFunction &MF = *MI.getParent()->getParent();
186 while (!MI.getOperand(i).isFrameIndex()) {
188 assert(i < MI.getNumOperands() &&
189 "Instr doesn't have FrameIndex operand!");
192 // FrameInfo addressable stack objects are accessed
193 // using neg. offsets, so we must add with the stack
194 // size to obtain $sp relative address.
195 int FrameIndex = MI.getOperand(i).getFrameIndex();
196 int stackSize = MF.getFrameInfo()->getStackSize();
197 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
200 DOUT << "\n<--------->\n";
202 DOUT << "FrameIndex : " << FrameIndex << "\n";
203 DOUT << "spOffset : " << spOffset << "\n";
204 DOUT << "stackSize : " << stackSize << "\n";
207 // If the FrameIndex points to a positive SPOffset this
208 // means we are inside the callee and getting the arguments
209 // from the caller stack
210 int Offset = (-(stackSize)) + spOffset;
213 DOUT << "Offset : " << Offset << "\n";
214 DOUT << "<--------->\n";
217 MI.getOperand(i-1).ChangeToImmediate(Offset);
218 MI.getOperand(i).ChangeToRegister(Mips::SP,false);
221 void MipsRegisterInfo::
222 emitPrologue(MachineFunction &MF) const
224 MachineBasicBlock &MBB = MF.front();
225 MachineFrameInfo *MFI = MF.getFrameInfo();
227 // Get the number of bytes to allocate from the FrameInfo
228 int NumBytes = (int) MFI->getStackSize();
230 // Do we need to allocate space on the stack?
231 if (NumBytes == 0) return;
233 // FIXME: is Stack Align needed here ?? (maybe it's done before...)
234 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
235 NumBytes = -((NumBytes+Align-1)/Align*Align);
237 // Update frame info to pretend that this is part of the stack...
238 MFI->setStackSize(NumBytes);
240 // adjust stack : addi sp, sp, (-imm)
241 BuildMI(MBB, MBB.begin(), TII.get(Mips::ADDi), Mips::SP)
242 .addReg(Mips::SP).addImm(NumBytes);
245 void MipsRegisterInfo::
246 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
248 MachineBasicBlock::iterator MBBI = prior(MBB.end());
249 MachineFrameInfo *MFI = MF.getFrameInfo();
251 // Get the number of bytes from FrameInfo
252 int NumBytes = (int) MFI->getStackSize();
254 // adjust stack : insert addi sp, sp, (imm)
256 BuildMI(MBB, MBBI, TII.get(Mips::ADDi), Mips::SP)
257 .addReg(Mips::SP).addImm(-NumBytes);
261 void MipsRegisterInfo::
262 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
264 unsigned MipsRegisterInfo::
265 getRARegister() const {
269 unsigned MipsRegisterInfo::
270 getFrameRegister(MachineFunction &MF) const {
271 assert(0 && "What is the frame register");
275 unsigned MipsRegisterInfo::
276 getEHExceptionRegister() const {
277 assert(0 && "What is the exception register");
281 unsigned MipsRegisterInfo::
282 getEHHandlerRegister() const {
283 assert(0 && "What is the exception handler register");
287 #include "MipsGenRegisterInfo.inc"