1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/STLExtras.h"
39 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
40 const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42 Subtarget(ST), TII(tii) {}
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : case Mips::F0 : return 0;
51 case Mips::AT : case Mips::F1 : return 1;
52 case Mips::V0 : case Mips::F2 : return 2;
53 case Mips::V1 : case Mips::F3 : return 3;
54 case Mips::A0 : case Mips::F4 : return 4;
55 case Mips::A1 : case Mips::F5 : return 5;
56 case Mips::A2 : case Mips::F6 : return 6;
57 case Mips::A3 : case Mips::F7 : return 7;
58 case Mips::T0 : case Mips::F8 : return 8;
59 case Mips::T1 : case Mips::F9 : return 9;
60 case Mips::T2 : case Mips::F10: return 10;
61 case Mips::T3 : case Mips::F11: return 11;
62 case Mips::T4 : case Mips::F12: return 12;
63 case Mips::T5 : case Mips::F13: return 13;
64 case Mips::T6 : case Mips::F14: return 14;
65 case Mips::T7 : case Mips::F15: return 15;
66 case Mips::T8 : case Mips::F16: return 16;
67 case Mips::T9 : case Mips::F17: return 17;
68 case Mips::S0 : case Mips::F18: return 18;
69 case Mips::S1 : case Mips::F19: return 19;
70 case Mips::S2 : case Mips::F20: return 20;
71 case Mips::S3 : case Mips::F21: return 21;
72 case Mips::S4 : case Mips::F22: return 22;
73 case Mips::S5 : case Mips::F23: return 23;
74 case Mips::S6 : case Mips::F24: return 24;
75 case Mips::S7 : case Mips::F25: return 25;
76 case Mips::K0 : case Mips::F26: return 26;
77 case Mips::K1 : case Mips::F27: return 27;
78 case Mips::GP : case Mips::F28: return 28;
79 case Mips::SP : case Mips::F29: return 29;
80 case Mips::FP : case Mips::F30: return 30;
81 case Mips::RA : case Mips::F31: return 31;
82 default: assert(0 && "Unknown register number!");
84 return 0; // Not reached
87 unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; }
89 //===----------------------------------------------------------------------===//
90 // Callee Saved Registers methods
91 //===----------------------------------------------------------------------===//
93 /// Mips Callee Saved Registers
94 const unsigned* MipsRegisterInfo::
95 getCalleeSavedRegs(const MachineFunction *MF) const
97 // Mips callee-save register range is $16-$23(s0-s7)
98 static const unsigned CalleeSavedRegs[] = {
99 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
100 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
103 return CalleeSavedRegs;
106 /// Mips Callee Saved Register Classes
107 const TargetRegisterClass* const*
108 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
110 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
111 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
112 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
113 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
114 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
116 return CalleeSavedRegClasses;
119 BitVector MipsRegisterInfo::
120 getReservedRegs(const MachineFunction &MF) const
122 BitVector Reserved(getNumRegs());
123 Reserved.set(Mips::ZERO);
124 Reserved.set(Mips::AT);
125 Reserved.set(Mips::K0);
126 Reserved.set(Mips::K1);
127 Reserved.set(Mips::GP);
128 Reserved.set(Mips::SP);
129 Reserved.set(Mips::FP);
130 Reserved.set(Mips::RA);
134 //===----------------------------------------------------------------------===//
136 // Stack Frame Processing methods
137 // +----------------------------+
139 // The stack is allocated decrementing the stack pointer on
140 // the first instruction of a function prologue. Once decremented,
141 // all stack referencesare are done thought a positive offset
142 // from the stack/frame pointer, so the stack is considering
143 // to grow up! Otherwise terrible hacks would have to be made
144 // to get this stack ABI compliant :)
146 // The stack frame required by the ABI:
151 // . saved $GP (used in PIC)
153 // . saved "Callee Saved" Registers
156 // StackSize -----------
158 // Offset - offset from sp after stack allocation on function prologue
160 // The sp is the stack pointer subtracted/added from the stack size
161 // at the Prologue/Epilogue
163 // References to the previous stack (to obtain arguments) are done
164 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
167 // - reference to the actual stack frame
168 // for any local area var there is smt like : FI >= 0, StackOffset: 4
171 // - reference to previous stack frame
172 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
173 // The emitted instruction will be something like:
174 // lw REGX, 16+StackSize(SP)
176 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
177 // stack references (ObjectOffset) created to reference the function
178 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
179 // possible to detect those references and the offsets are adjusted to
180 // their real location.
184 //===----------------------------------------------------------------------===//
186 // hasFP - Return true if the specified function should have a dedicated frame
187 // pointer register. This is true if the function has variable sized allocas or
188 // if frame pointer elimination is disabled.
189 bool MipsRegisterInfo::
190 hasFP(const MachineFunction &MF) const {
191 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
194 // This function eliminate ADJCALLSTACKDOWN,
195 // ADJCALLSTACKUP pseudo instructions
196 void MipsRegisterInfo::
197 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator I) const {
199 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
203 // FrameIndex represent objects inside a abstract stack.
204 // We must replace FrameIndex with an stack/frame pointer
206 void MipsRegisterInfo::
207 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
208 RegScavenger *RS) const
210 MachineInstr &MI = *II;
211 MachineFunction &MF = *MI.getParent()->getParent();
214 while (!MI.getOperand(i).isFrameIndex()) {
216 assert(i < MI.getNumOperands() &&
217 "Instr doesn't have FrameIndex operand!");
220 int FrameIndex = MI.getOperand(i).getIndex();
221 int stackSize = MF.getFrameInfo()->getStackSize();
222 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
225 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
226 DOUT << "<--------->\n";
228 DOUT << "FrameIndex : " << FrameIndex << "\n";
229 DOUT << "spOffset : " << spOffset << "\n";
230 DOUT << "stackSize : " << stackSize << "\n";
233 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
234 // and adjust SPOffsets considering the final stack size.
235 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
236 Offset += MI.getOperand(i-1).getImm();
239 DOUT << "Offset : " << Offset << "\n";
240 DOUT << "<--------->\n";
243 MI.getOperand(i-1).ChangeToImmediate(Offset);
244 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
247 void MipsRegisterInfo::
248 emitPrologue(MachineFunction &MF) const
250 MachineBasicBlock &MBB = MF.front();
251 MachineFrameInfo *MFI = MF.getFrameInfo();
252 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
253 MachineBasicBlock::iterator MBBI = MBB.begin();
254 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
256 // Replace the dummy '0' SPOffset by the negative
257 // offsets, as explained on LowerFORMAL_ARGUMENTS
258 MipsFI->adjustLoadArgsFI(MFI);
259 MipsFI->adjustStoreVarArgsFI(MFI);
261 // Get the number of bytes to allocate from the FrameInfo.
262 int NumBytes = (int) MFI->getStackSize();
265 DOUT << "\n<--- EMIT PROLOGUE --->\n";
266 DOUT << "Actual Stack size :" << NumBytes << "\n";
269 // No need to allocate space on the stack.
270 if (NumBytes == 0) return;
272 int FPOffset, RAOffset;
274 // Allocate space for saved RA and FP when needed
275 // FIXME: within 64-bit registers, change hardcoded
276 // sizes for RA and FP offsets.
277 if ((hasFP(MF)) && (MFI->hasCalls())) {
279 RAOffset = (NumBytes+4);
281 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
285 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
289 } else { // No calls and no fp.
290 RAOffset = FPOffset = 0;
293 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
294 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
295 MipsFI->setFPStackOffset(FPOffset);
296 MipsFI->setRAStackOffset(RAOffset);
299 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
300 NumBytes = ((NumBytes+Align-1)/Align*Align);
303 DOUT << "FPOffset :" << FPOffset << "\n";
304 DOUT << "RAOffset :" << RAOffset << "\n";
305 DOUT << "New stack size :" << NumBytes << "\n\n";
309 MFI->setStackSize(NumBytes);
311 BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER));
313 // TODO: check need from GP here.
314 if (isPIC && Subtarget.isABI_O32())
315 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
316 BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO));
318 // Adjust stack : addi sp, sp, (-imm)
319 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
320 .addReg(Mips::SP).addImm(-NumBytes);
322 // Save the return address only if the function isnt a leaf one.
323 // sw $ra, stack_loc($sp)
324 if (MFI->hasCalls()) {
325 BuildMI(MBB, MBBI, TII.get(Mips::SW))
326 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
329 // if framepointer enabled, save it and set it
330 // to point to the stack pointer
332 // sw $fp,stack_loc($sp)
333 BuildMI(MBB, MBBI, TII.get(Mips::SW))
334 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
337 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
338 .addReg(Mips::SP).addReg(Mips::ZERO);
341 // PIC speficic function prologue
342 if ((isPIC) && (MFI->hasCalls())) {
343 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
344 .addImm(MipsFI->getGPStackOffset());
348 void MipsRegisterInfo::
349 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
351 MachineBasicBlock::iterator MBBI = prior(MBB.end());
352 MachineFrameInfo *MFI = MF.getFrameInfo();
353 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
355 // Get the number of bytes from FrameInfo
356 int NumBytes = (int) MFI->getStackSize();
358 // Get the FI's where RA and FP are saved.
359 int FPOffset = MipsFI->getFPStackOffset();
360 int RAOffset = MipsFI->getRAStackOffset();
362 // if framepointer enabled, restore it and restore the
366 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
367 .addReg(Mips::FP).addReg(Mips::ZERO);
369 // lw $fp,stack_loc($sp)
370 BuildMI(MBB, MBBI, TII.get(Mips::LW))
371 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
374 // Restore the return address only if the function isnt a leaf one.
375 // lw $ra, stack_loc($sp)
376 if (MFI->hasCalls()) {
377 BuildMI(MBB, MBBI, TII.get(Mips::LW))
378 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
381 // adjust stack : insert addi sp, sp, (imm)
383 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
384 .addReg(Mips::SP).addImm(NumBytes);
388 void MipsRegisterInfo::
389 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
390 // Set the SPOffset on the FI where GP must be saved/loaded.
391 MachineFrameInfo *MFI = MF.getFrameInfo();
392 if (MFI->hasCalls()) {
393 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
395 DOUT << "processFunctionBeforeFrameFinalized\n";
396 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
397 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
399 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
403 unsigned MipsRegisterInfo::
404 getRARegister() const {
408 unsigned MipsRegisterInfo::
409 getFrameRegister(MachineFunction &MF) const {
410 return hasFP(MF) ? Mips::FP : Mips::SP;
413 unsigned MipsRegisterInfo::
414 getEHExceptionRegister() const {
415 assert(0 && "What is the exception register");
419 unsigned MipsRegisterInfo::
420 getEHHandlerRegister() const {
421 assert(0 && "What is the exception handler register");
425 int MipsRegisterInfo::
426 getDwarfRegNum(unsigned RegNum, bool isEH) const {
427 assert(0 && "What is the dwarf register number");
431 #include "MipsGenRegisterInfo.inc"