1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsMachineFunction.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/Function.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Analysis/DebugInfo.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "MipsGenRegisterInfo.inc"
46 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
47 const TargetInstrInfo &tii)
48 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
50 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
52 //===----------------------------------------------------------------------===//
53 // Callee Saved Registers methods
54 //===----------------------------------------------------------------------===//
56 /// Mips Callee Saved Registers
57 const uint16_t* MipsRegisterInfo::
58 getCalleeSavedRegs(const MachineFunction *MF) const {
59 if (Subtarget.isSingleFloat())
60 return CSR_SingleFloatOnly_SaveList;
61 else if (!Subtarget.hasMips64())
62 return CSR_O32_SaveList;
63 else if (Subtarget.isABI_N32())
64 return CSR_N32_SaveList;
66 assert(Subtarget.isABI_N64());
67 return CSR_N64_SaveList;
71 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
72 if (Subtarget.isSingleFloat())
73 return CSR_SingleFloatOnly_RegMask;
74 else if (!Subtarget.hasMips64())
75 return CSR_O32_RegMask;
76 else if (Subtarget.isABI_N32())
77 return CSR_N32_RegMask;
79 assert(Subtarget.isABI_N64());
80 return CSR_N64_RegMask;
83 BitVector MipsRegisterInfo::
84 getReservedRegs(const MachineFunction &MF) const {
85 static const uint16_t ReservedCPURegs[] = {
86 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
90 static const uint16_t ReservedCPU64Regs[] = {
91 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
92 Mips::SP_64, Mips::RA_64
95 BitVector Reserved(getNumRegs());
96 typedef TargetRegisterClass::const_iterator RegIter;
98 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
99 Reserved.set(ReservedCPURegs[I]);
101 if (Subtarget.hasMips64()) {
102 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
103 Reserved.set(ReservedCPU64Regs[I]);
105 // Reserve all registers in AFGR64.
106 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
107 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
110 // Reserve all registers in CPU64Regs & FGR64.
111 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
112 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
115 for (RegIter Reg = Mips::FGR64RegClass.begin(),
116 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
120 // Reserve FP if this function should have a dedicated frame pointer register.
121 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
122 Reserved.set(Mips::FP);
123 Reserved.set(Mips::FP_64);
126 // Reserve hardware registers.
127 Reserved.set(Mips::HWR29);
128 Reserved.set(Mips::HWR29_64);
134 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
139 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
143 // This function eliminate ADJCALLSTACKDOWN,
144 // ADJCALLSTACKUP pseudo instructions
145 void MipsRegisterInfo::
146 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I) const {
148 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
152 // FrameIndex represent objects inside a abstract stack.
153 // We must replace FrameIndex with an stack/frame pointer
155 void MipsRegisterInfo::
156 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
157 RegScavenger *RS) const {
158 MachineInstr &MI = *II;
159 MachineFunction &MF = *MI.getParent()->getParent();
160 MachineFrameInfo *MFI = MF.getFrameInfo();
161 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
164 while (!MI.getOperand(i).isFI()) {
166 assert(i < MI.getNumOperands() &&
167 "Instr doesn't have FrameIndex operand!");
170 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
171 errs() << "<--------->\n" << MI);
173 int FrameIndex = MI.getOperand(i).getIndex();
174 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
175 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
177 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
178 << "spOffset : " << spOffset << "\n"
179 << "stackSize : " << stackSize << "\n");
181 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
186 MinCSFI = CSI[0].getFrameIdx();
187 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
190 // The following stack frame objects are always referenced relative to $sp:
191 // 1. Outgoing arguments.
192 // 2. Pointer to dynamically allocated stack space.
193 // 3. Locations for callee-saved registers.
194 // Everything else is referenced relative to whatever register
195 // getFrameRegister() returns.
198 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
199 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
200 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
202 FrameReg = getFrameRegister(MF);
204 // Calculate final offset.
205 // - There is no need to change the offset if the frame object is one of the
206 // following: an outgoing argument, pointer to a dynamically allocated
207 // stack space or a $gp restore location,
208 // - If the frame object is any of the following, its offset must be adjusted
209 // by adding the size of the stack:
210 // incoming argument, callee-saved register location or local variable.
213 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
214 MipsFI->isGlobalRegFI(FrameIndex))
217 Offset = spOffset + (int64_t)stackSize;
219 Offset += MI.getOperand(i+1).getImm();
221 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
223 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
225 if (!MI.isDebugValue() && !isInt<16>(Offset)) {
226 MachineBasicBlock &MBB = *MI.getParent();
227 DebugLoc DL = II->getDebugLoc();
228 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
229 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
230 MipsAnalyzeImmediate::Inst LastInst(0, 0);
232 MipsFI->setEmitNOAT();
233 Mips::loadImmediate(Offset, Subtarget.isABI_N64(), TII, MBB, II, DL, true,
235 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
238 Offset = SignExtend64<16>(LastInst.ImmOpnd);
241 MI.getOperand(i).ChangeToRegister(FrameReg, false);
242 MI.getOperand(i+1).ChangeToImmediate(Offset);
245 unsigned MipsRegisterInfo::
246 getFrameRegister(const MachineFunction &MF) const {
247 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
248 bool IsN64 = Subtarget.isABI_N64();
250 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
251 (IsN64 ? Mips::SP_64 : Mips::SP);
254 unsigned MipsRegisterInfo::
255 getEHExceptionRegister() const {
256 llvm_unreachable("What is the exception register");
259 unsigned MipsRegisterInfo::
260 getEHHandlerRegister() const {
261 llvm_unreachable("What is the exception handler register");