1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
236 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
237 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
238 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
239 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
241 // The portions of MIPS-III that were also added to MIPS32
242 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
244 // The portions of MIPS-III that were also added to MIPS32
245 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
247 // The portions of MIPS-IV that were also added to MIPS32
248 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
250 // The portions of MIPS-IV that were also added to MIPS32R2
251 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
253 // The portions of MIPS-V that were also added to MIPS32R2
254 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
256 //===----------------------------------------------------------------------===//
258 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
259 let EncodingPredicates = [HasStdEnc];
262 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
263 InstAlias<Asm, Result, Emit>, PredicateControl;
266 bit isCommutable = 1;
283 bit isTerminator = 1;
286 bit hasExtraSrcRegAllocReq = 1;
287 bit isCodeGenOnly = 1;
290 class IsAsCheapAsAMove {
291 bit isAsCheapAsAMove = 1;
294 class NeverHasSideEffects {
295 bit neverHasSideEffects = 1;
298 //===----------------------------------------------------------------------===//
299 // Instruction format superclass
300 //===----------------------------------------------------------------------===//
302 include "MipsInstrFormats.td"
304 //===----------------------------------------------------------------------===//
305 // Mips Operand, Complex Patterns and Transformations Definitions.
306 //===----------------------------------------------------------------------===//
308 def MipsJumpTargetAsmOperand : AsmOperandClass {
309 let Name = "JumpTarget";
310 let ParserMethod = "ParseJumpTarget";
311 let PredicateMethod = "isImm";
312 let RenderMethod = "addImmOperands";
315 // Instruction operand types
316 def jmptarget : Operand<OtherVT> {
317 let EncoderMethod = "getJumpTargetOpValue";
318 let ParserMatchClass = MipsJumpTargetAsmOperand;
320 def brtarget : Operand<OtherVT> {
321 let EncoderMethod = "getBranchTargetOpValue";
322 let OperandType = "OPERAND_PCREL";
323 let DecoderMethod = "DecodeBranchTarget";
324 let ParserMatchClass = MipsJumpTargetAsmOperand;
326 def calltarget : Operand<iPTR> {
327 let EncoderMethod = "getJumpTargetOpValue";
328 let ParserMatchClass = MipsJumpTargetAsmOperand;
331 def simm10 : Operand<i32>;
333 def simm16 : Operand<i32> {
334 let DecoderMethod= "DecodeSimm16";
337 def simm19_lsl2 : Operand<i32> {
338 let EncoderMethod = "getSimm19Lsl2Encoding";
339 let DecoderMethod = "DecodeSimm19Lsl2";
342 def simm20 : Operand<i32> {
345 def uimm20 : Operand<i32> {
348 def uimm10 : Operand<i32> {
351 def simm16_64 : Operand<i64> {
352 let DecoderMethod = "DecodeSimm16";
356 def uimmz : Operand<i32> {
357 let PrintMethod = "printUnsignedImm";
361 def uimm2 : Operand<i32> {
362 let PrintMethod = "printUnsignedImm";
365 def uimm3 : Operand<i32> {
366 let PrintMethod = "printUnsignedImm";
369 def uimm5 : Operand<i32> {
370 let PrintMethod = "printUnsignedImm";
373 def uimm6 : Operand<i32> {
374 let PrintMethod = "printUnsignedImm";
377 def uimm16 : Operand<i32> {
378 let PrintMethod = "printUnsignedImm";
381 def pcrel16 : Operand<i32> {
384 def MipsMemAsmOperand : AsmOperandClass {
386 let ParserMethod = "parseMemOperand";
389 def MipsInvertedImmoperand : AsmOperandClass {
391 let RenderMethod = "addImmOperands";
392 let ParserMethod = "parseInvNum";
395 def InvertedImOperand : Operand<i32> {
396 let ParserMatchClass = MipsInvertedImmoperand;
399 def InvertedImOperand64 : Operand<i64> {
400 let ParserMatchClass = MipsInvertedImmoperand;
403 class mem_generic : Operand<iPTR> {
404 let PrintMethod = "printMemOperand";
405 let MIOperandInfo = (ops ptr_rc, simm16);
406 let EncoderMethod = "getMemEncoding";
407 let ParserMatchClass = MipsMemAsmOperand;
408 let OperandType = "OPERAND_MEMORY";
412 def mem : mem_generic;
414 // MSA specific address operand
415 def mem_msa : mem_generic {
416 let MIOperandInfo = (ops ptr_rc, simm10);
417 let EncoderMethod = "getMSAMemEncoding";
420 def mem_ea : Operand<iPTR> {
421 let PrintMethod = "printMemOperandEA";
422 let MIOperandInfo = (ops ptr_rc, simm16);
423 let EncoderMethod = "getMemEncoding";
424 let OperandType = "OPERAND_MEMORY";
427 def PtrRC : Operand<iPTR> {
428 let MIOperandInfo = (ops ptr_rc);
429 let DecoderMethod = "DecodePtrRegisterClass";
430 let ParserMatchClass = GPR32AsmOperand;
433 // size operand of ext instruction
434 def size_ext : Operand<i32> {
435 let EncoderMethod = "getSizeExtEncoding";
436 let DecoderMethod = "DecodeExtSize";
439 // size operand of ins instruction
440 def size_ins : Operand<i32> {
441 let EncoderMethod = "getSizeInsEncoding";
442 let DecoderMethod = "DecodeInsSize";
445 // Transformation Function - get the lower 16 bits.
446 def LO16 : SDNodeXForm<imm, [{
447 return getImm(N, N->getZExtValue() & 0xFFFF);
450 // Transformation Function - get the higher 16 bits.
451 def HI16 : SDNodeXForm<imm, [{
452 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
456 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
458 // Node immediate is zero (e.g. insve.d)
459 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
461 // Node immediate fits as 16-bit sign extended on target immediate.
463 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
465 // Node immediate fits as 16-bit sign extended on target immediate.
467 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
469 // Node immediate fits as 15-bit sign extended on target immediate.
471 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
473 // Node immediate fits as 16-bit zero extended on target immediate.
474 // The LO16 param means that only the lower 16 bits of the node
475 // immediate are caught.
477 def immZExt16 : PatLeaf<(imm), [{
478 if (N->getValueType(0) == MVT::i32)
479 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
481 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
484 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
485 def immLow16Zero : PatLeaf<(imm), [{
486 int64_t Val = N->getSExtValue();
487 return isInt<32>(Val) && !(Val & 0xffff);
490 // shamt field must fit in 5 bits.
491 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
493 // True if (N + 1) fits in 16-bit field.
494 def immSExt16Plus1 : PatLeaf<(imm), [{
495 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
498 // Mips Address Mode! SDNode frameindex could possibily be a match
499 // since load and store instructions from stack used it.
501 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
504 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
507 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
510 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
512 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
514 //===----------------------------------------------------------------------===//
515 // Instructions specific format
516 //===----------------------------------------------------------------------===//
518 // Arithmetic and logical instructions with 3 register operands.
519 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
520 InstrItinClass Itin = NoItinerary,
521 SDPatternOperator OpNode = null_frag>:
522 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
523 !strconcat(opstr, "\t$rd, $rs, $rt"),
524 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
525 let isCommutable = isComm;
526 let isReMaterializable = 1;
527 let TwoOperandAliasConstraint = "$rd = $rs";
530 // Arithmetic and logical instructions with 2 register operands.
531 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
532 InstrItinClass Itin = NoItinerary,
533 SDPatternOperator imm_type = null_frag,
534 SDPatternOperator OpNode = null_frag> :
535 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
536 !strconcat(opstr, "\t$rt, $rs, $imm16"),
537 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
539 let isReMaterializable = 1;
540 let TwoOperandAliasConstraint = "$rs = $rt";
543 // Arithmetic Multiply ADD/SUB
544 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
545 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
546 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
547 let Defs = [HI0, LO0];
548 let Uses = [HI0, LO0];
549 let isCommutable = isComm;
553 class LogicNOR<string opstr, RegisterOperand RO>:
554 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
555 !strconcat(opstr, "\t$rd, $rs, $rt"),
556 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
557 let isCommutable = 1;
561 class shift_rotate_imm<string opstr, Operand ImmOpnd,
562 RegisterOperand RO, InstrItinClass itin,
563 SDPatternOperator OpNode = null_frag,
564 SDPatternOperator PF = null_frag> :
565 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
566 !strconcat(opstr, "\t$rd, $rt, $shamt"),
567 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
568 let TwoOperandAliasConstraint = "$rt = $rd";
571 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
572 SDPatternOperator OpNode = null_frag>:
573 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
574 !strconcat(opstr, "\t$rd, $rt, $rs"),
575 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
578 // Load Upper Imediate
579 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
580 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
581 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
582 let neverHasSideEffects = 1;
583 let isReMaterializable = 1;
587 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
588 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
589 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
590 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
591 let DecoderMethod = "DecodeMem";
592 let canFoldAsLoad = 1;
596 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
597 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
598 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
599 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
600 let DecoderMethod = "DecodeMem";
604 // Load/Store Left/Right
605 let canFoldAsLoad = 1 in
606 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
607 InstrItinClass Itin> :
608 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
609 !strconcat(opstr, "\t$rt, $addr"),
610 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
611 let DecoderMethod = "DecodeMem";
612 string Constraints = "$src = $rt";
615 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
616 InstrItinClass Itin> :
617 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
618 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
619 let DecoderMethod = "DecodeMem";
622 // Conditional Branch
623 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
624 RegisterOperand RO> :
625 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
626 !strconcat(opstr, "\t$rs, $rt, $offset"),
627 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
630 let isTerminator = 1;
631 let hasDelaySlot = 1;
635 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
636 RegisterOperand RO> :
637 InstSE<(outs), (ins RO:$rs, opnd:$offset),
638 !strconcat(opstr, "\t$rs, $offset"),
639 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
642 let isTerminator = 1;
643 let hasDelaySlot = 1;
648 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
649 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
650 !strconcat(opstr, "\t$rd, $rs, $rt"),
651 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
652 II_SLT_SLTU, FrmR, opstr>;
654 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
656 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
657 !strconcat(opstr, "\t$rt, $rs, $imm16"),
658 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
659 II_SLTI_SLTIU, FrmI, opstr>;
662 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
663 SDPatternOperator targetoperator, string bopstr> :
664 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
665 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
668 let hasDelaySlot = 1;
669 let DecoderMethod = "DecodeJumpTarget";
673 // Unconditional branch
674 class UncondBranch<Instruction BEQInst> :
675 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
676 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
678 let isTerminator = 1;
680 let hasDelaySlot = 1;
681 let AdditionalPredicates = [RelocPIC];
685 // Base class for indirect branch and return instruction classes.
686 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
687 class JumpFR<string opstr, RegisterOperand RO,
688 SDPatternOperator operator = null_frag>:
689 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
693 class IndirectBranch<string opstr, RegisterOperand RO> :
694 JumpFR<opstr, RO, brind> {
696 let isIndirectBranch = 1;
699 // Return instruction
700 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
702 let isCodeGenOnly = 1;
704 let hasExtraSrcRegAllocReq = 1;
707 // Jump and Link (Call)
708 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
709 class JumpLink<string opstr, DAGOperand opnd> :
710 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
711 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
712 let DecoderMethod = "DecodeJumpTarget";
715 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
716 Register RetReg, RegisterOperand ResRO = RO>:
717 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
718 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
720 class JumpLinkReg<string opstr, RegisterOperand RO>:
721 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
724 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
725 InstSE<(outs), (ins RO:$rs, opnd:$offset),
726 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
730 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
731 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
732 class TailCall<Instruction JumpInst> :
733 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
734 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
736 class TailCallReg<RegisterOperand RO, Instruction JRInst,
737 RegisterOperand ResRO = RO> :
738 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
739 PseudoInstExpansion<(JRInst ResRO:$rs)>;
742 class BAL_BR_Pseudo<Instruction RealInst> :
743 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
744 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
746 let isTerminator = 1;
748 let hasDelaySlot = 1;
753 class SYS_FT<string opstr> :
754 InstSE<(outs), (ins uimm20:$code_),
755 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
757 class BRK_FT<string opstr> :
758 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
759 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
763 class ER_FT<string opstr> :
764 InstSE<(outs), (ins),
765 opstr, [], NoItinerary, FrmOther, opstr>;
768 class DEI_FT<string opstr, RegisterOperand RO> :
769 InstSE<(outs RO:$rt), (ins),
770 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
773 class WAIT_FT<string opstr> :
774 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
777 let hasSideEffects = 1 in
778 class SYNC_FT<string opstr> :
779 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
780 NoItinerary, FrmOther, opstr>;
782 let hasSideEffects = 1 in
783 class TEQ_FT<string opstr, RegisterOperand RO> :
784 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
785 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
788 class TEQI_FT<string opstr, RegisterOperand RO> :
789 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
790 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
792 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
793 list<Register> DefRegs> :
794 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
796 let isCommutable = 1;
798 let neverHasSideEffects = 1;
801 // Pseudo multiply/divide instruction with explicit accumulator register
803 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
804 SDPatternOperator OpNode, InstrItinClass Itin,
805 bit IsComm = 1, bit HasSideEffects = 0,
806 bit UsesCustomInserter = 0> :
807 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
808 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
809 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
810 let isCommutable = IsComm;
811 let hasSideEffects = HasSideEffects;
812 let usesCustomInserter = UsesCustomInserter;
815 // Pseudo multiply add/sub instruction with explicit accumulator register
817 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
819 : PseudoSE<(outs ACC64:$ac),
820 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
822 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
824 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
825 string Constraints = "$acin = $ac";
828 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
829 list<Register> DefRegs> :
830 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
831 [], itin, FrmR, opstr> {
836 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
837 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
838 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
840 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
841 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
844 let neverHasSideEffects = 1;
847 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
848 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
849 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
852 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
853 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
856 let neverHasSideEffects = 1;
859 class EffectiveAddress<string opstr, RegisterOperand RO> :
860 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
861 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
862 !strconcat(opstr, "_lea")> {
863 let isCodeGenOnly = 1;
864 let DecoderMethod = "DecodeMem";
867 // Count Leading Ones/Zeros in Word
868 class CountLeading0<string opstr, RegisterOperand RO>:
869 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
870 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
872 class CountLeading1<string opstr, RegisterOperand RO>:
873 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
874 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
876 // Sign Extend in Register.
877 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
878 InstrItinClass itin> :
879 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
880 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
883 class SubwordSwap<string opstr, RegisterOperand RO>:
884 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
885 NoItinerary, FrmR, opstr> {
886 let neverHasSideEffects = 1;
890 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
891 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
895 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
896 SDPatternOperator Op = null_frag>:
897 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
898 !strconcat(opstr, " $rt, $rs, $pos, $size"),
899 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
900 FrmR, opstr>, ISA_MIPS32R2;
902 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
903 SDPatternOperator Op = null_frag>:
904 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
905 !strconcat(opstr, " $rt, $rs, $pos, $size"),
906 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
907 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
908 let Constraints = "$src = $rt";
911 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
912 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
913 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
914 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
916 // Atomic Compare & Swap.
917 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
918 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
919 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
921 class LLBase<string opstr, RegisterOperand RO> :
922 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
923 [], NoItinerary, FrmI> {
924 let DecoderMethod = "DecodeMem";
928 class SCBase<string opstr, RegisterOperand RO> :
929 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
930 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
931 let DecoderMethod = "DecodeMem";
933 let Constraints = "$rt = $dst";
936 class MFC3OP<string asmstr, RegisterOperand RO> :
937 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
938 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
940 class TrapBase<Instruction RealInst>
941 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
942 PseudoInstExpansion<(RealInst 0, 0)> {
944 let isTerminator = 1;
945 let isCodeGenOnly = 1;
948 //===----------------------------------------------------------------------===//
949 // Pseudo instructions
950 //===----------------------------------------------------------------------===//
953 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
954 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
956 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
957 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
958 [(callseq_start timm:$amt)]>;
959 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
960 [(callseq_end timm:$amt1, timm:$amt2)]>;
963 let usesCustomInserter = 1 in {
964 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
965 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
966 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
967 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
968 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
969 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
970 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
971 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
972 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
973 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
974 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
975 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
976 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
977 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
978 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
979 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
980 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
981 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
983 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
984 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
985 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
987 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
988 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
989 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
992 /// Pseudo instructions for loading and storing accumulator registers.
993 let isPseudo = 1, isCodeGenOnly = 1 in {
994 def LOAD_ACC64 : Load<"", ACC64>;
995 def STORE_ACC64 : Store<"", ACC64>;
998 // We need these two pseudo instructions to avoid offset calculation for long
999 // branches. See the comment in file MipsLongBranch.cpp for detailed
1002 // Expands to: lui $dst, %hi($tgt - $baltgt)
1003 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1004 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1006 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1007 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1008 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1010 //===----------------------------------------------------------------------===//
1011 // Instruction definition
1012 //===----------------------------------------------------------------------===//
1013 //===----------------------------------------------------------------------===//
1014 // MipsI Instructions
1015 //===----------------------------------------------------------------------===//
1017 /// Arithmetic Instructions (ALU Immediate)
1018 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1020 ADDI_FM<0x9>, IsAsCheapAsAMove;
1021 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1022 ISA_MIPS1_NOT_32R6_64R6;
1023 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1025 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1027 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1030 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1033 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1036 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1038 /// Arithmetic Instructions (3-Operand, R-Type)
1039 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1041 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1043 let Defs = [HI0, LO0] in
1044 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1045 ADD_FM<0x1c, 2>, ISA_MIPS32;
1046 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1047 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1048 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1049 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1050 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1052 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1054 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1056 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1058 /// Shift Instructions
1059 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1060 immZExt5>, SRA_FM<0, 0>;
1061 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1062 immZExt5>, SRA_FM<2, 0>;
1063 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1064 immZExt5>, SRA_FM<3, 0>;
1065 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1067 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1069 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1072 // Rotate Instructions
1073 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1075 SRA_FM<2, 1>, ISA_MIPS32R2;
1076 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1077 SRLV_FM<6, 1>, ISA_MIPS32R2;
1079 /// Load and Store Instructions
1081 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1082 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1084 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1086 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1087 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1089 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1090 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1091 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1093 /// load/store left/right
1094 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1095 AdditionalPredicates = [NotInMicroMips] in {
1096 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1097 ISA_MIPS1_NOT_32R6_64R6;
1098 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1099 ISA_MIPS1_NOT_32R6_64R6;
1100 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1101 ISA_MIPS1_NOT_32R6_64R6;
1102 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1103 ISA_MIPS1_NOT_32R6_64R6;
1106 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1107 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1108 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1109 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1110 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1111 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1112 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1114 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1115 ISA_MIPS2_NOT_32R6_64R6;
1116 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1117 ISA_MIPS2_NOT_32R6_64R6;
1118 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1119 ISA_MIPS2_NOT_32R6_64R6;
1120 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1121 ISA_MIPS2_NOT_32R6_64R6;
1122 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1123 ISA_MIPS2_NOT_32R6_64R6;
1124 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1125 ISA_MIPS2_NOT_32R6_64R6;
1127 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1128 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1129 def TRAP : TrapBase<BREAK>;
1131 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1132 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1134 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1135 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1137 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1138 AdditionalPredicates = [NotInMicroMips] in {
1139 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1141 /// Load-linked, Store-conditional
1142 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1143 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1146 /// Jump and Branch Instructions
1147 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1148 AdditionalRequires<[RelocStatic]>, IsBranch;
1149 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1150 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1151 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1152 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1154 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1156 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1158 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1160 def B : UncondBranch<BEQ>;
1162 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1163 let AdditionalPredicates = [NotInMicroMips] in {
1164 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1165 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1167 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1168 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1169 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1170 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1171 def TAILCALL : TailCall<J>;
1172 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1174 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1176 // Exception handling related node and instructions.
1177 // The conversion sequence is:
1178 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1179 // MIPSeh_return -> (stack change + indirect branch)
1181 // MIPSeh_return takes the place of regular return instruction
1182 // but takes two arguments (V1, V0) which are used for storing
1183 // the offset and return address respectively.
1184 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1186 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1189 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1190 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1191 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1192 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1194 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1197 /// Multiply and Divide Instructions.
1198 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1200 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1202 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1204 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1207 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1208 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1209 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1210 AdditionalPredicates = [NotInMicroMips] in {
1211 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1212 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1215 /// Sign Ext In Register Instructions.
1216 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1217 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1218 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1219 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1222 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1223 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1225 /// Word Swap Bytes Within Halfwords
1226 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1229 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1231 // FrameIndexes are legalized when they are operands from load/store
1232 // instructions. The same not happens for stack address copies, so an
1233 // add op with mem ComplexPattern is used and the stack address copy
1234 // can be matched. It's similar to Sparc LEA_ADDRi
1235 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1238 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
1239 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
1240 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
1241 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
1243 let AdditionalPredicates = [NotDSP] in {
1244 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1245 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1246 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1247 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1248 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1249 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1250 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1251 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1252 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1255 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1257 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1260 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1262 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1263 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1265 /// Move Control Registers From/To CPU Registers
1266 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1267 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1268 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1269 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1271 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1273 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1274 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1275 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1277 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1279 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1280 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1281 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1282 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1284 //===----------------------------------------------------------------------===//
1285 // Instruction aliases
1286 //===----------------------------------------------------------------------===//
1287 def : MipsInstAlias<"move $dst, $src",
1288 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1290 let AdditionalPredicates = [NotInMicroMips];
1292 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1293 def : MipsInstAlias<"addu $rs, $rt, $imm",
1294 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1295 def : MipsInstAlias<"add $rs, $rt, $imm",
1296 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1297 def : MipsInstAlias<"and $rs, $rt, $imm",
1298 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1299 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1300 let Predicates = [NotInMicroMips] in {
1301 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1303 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1304 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1305 def : MipsInstAlias<"not $rt, $rs",
1306 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1307 def : MipsInstAlias<"neg $rt, $rs",
1308 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1309 def : MipsInstAlias<"negu $rt",
1310 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1311 def : MipsInstAlias<"negu $rt, $rs",
1312 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1313 def : MipsInstAlias<"slt $rs, $rt, $imm",
1314 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1315 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1316 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1317 def : MipsInstAlias<"xor $rs, $rt, $imm",
1318 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1319 def : MipsInstAlias<"or $rs, $rt, $imm",
1320 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1321 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1322 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1323 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1324 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1325 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1326 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1327 def : MipsInstAlias<"bnez $rs,$offset",
1328 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1329 def : MipsInstAlias<"beqz $rs,$offset",
1330 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1331 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1333 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1334 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1335 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1336 def : MipsInstAlias<"di", (DI ZERO), 1>;
1338 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1339 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1340 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1342 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1343 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1345 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1346 def : MipsInstAlias<"sll $rd, $rt, $rs",
1347 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1348 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1349 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1350 InvertedImOperand:$imm), 0>;
1351 def : MipsInstAlias<"sub $rs, $imm",
1352 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1354 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1355 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1356 InvertedImOperand:$imm), 0>;
1357 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1358 InvertedImOperand:$imm), 0>;
1359 def : MipsInstAlias<"sra $rd, $rt, $rs",
1360 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1361 def : MipsInstAlias<"srl $rd, $rt, $rs",
1362 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1363 //===----------------------------------------------------------------------===//
1364 // Assembler Pseudo Instructions
1365 //===----------------------------------------------------------------------===//
1367 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1368 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1369 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1370 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1372 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1373 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1374 !strconcat(instr_asm, "\t$rt, $addr")> ;
1375 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1377 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1378 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1379 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1380 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1382 //===----------------------------------------------------------------------===//
1383 // Arbitrary patterns that map to one or more instructions
1384 //===----------------------------------------------------------------------===//
1386 // Load/store pattern templates.
1387 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1388 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1390 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1391 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1394 def : MipsPat<(i32 immSExt16:$in),
1395 (ADDiu ZERO, imm:$in)>;
1396 def : MipsPat<(i32 immZExt16:$in),
1397 (ORi ZERO, imm:$in)>;
1398 def : MipsPat<(i32 immLow16Zero:$in),
1399 (LUi (HI16 imm:$in))>;
1401 // Arbitrary immediates
1402 def : MipsPat<(i32 imm:$imm),
1403 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1405 // Carry MipsPatterns
1406 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1407 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1408 let AdditionalPredicates = [NotDSP] in {
1409 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1410 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1411 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1412 (ADDiu GPR32:$src, imm:$imm)>;
1416 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1417 (JAL tglobaladdr:$dst)>;
1418 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1419 (JAL texternalsym:$dst)>;
1420 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1421 // (JALR GPR32:$dst)>;
1424 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1425 (TAILCALL tglobaladdr:$dst)>;
1426 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1427 (TAILCALL texternalsym:$dst)>;
1429 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1430 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1431 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1432 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1433 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1434 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1436 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1437 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1438 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1439 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1440 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1441 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1443 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1444 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1445 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1446 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1447 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1448 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1449 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1450 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1451 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1452 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1455 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1456 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1457 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1458 (ADDiu GPR32:$gp, tconstpool:$in)>;
1461 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1462 MipsPat<(MipsWrapper RC:$gp, node:$in),
1463 (ADDiuOp RC:$gp, node:$in)>;
1465 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1466 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1467 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1468 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1469 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1470 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1472 // Mips does not have "not", so we expand our way
1473 def : MipsPat<(not GPR32:$in),
1474 (NOR GPR32Opnd:$in, ZERO)>;
1477 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1478 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1479 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1482 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1485 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1486 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1487 Instruction SLTiuOp, Register ZEROReg> {
1488 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1489 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1490 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1491 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1493 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1494 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1495 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1496 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1497 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1498 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1499 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1500 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1501 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1502 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1503 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1504 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1506 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1507 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1508 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1509 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1511 def : MipsPat<(brcond RC:$cond, bb:$dst),
1512 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1515 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1517 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1518 (BLEZ i32:$lhs, bb:$dst)>;
1519 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1520 (BGEZ i32:$lhs, bb:$dst)>;
1523 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1524 Instruction SLTuOp, Register ZEROReg> {
1525 def : MipsPat<(seteq RC:$lhs, 0),
1526 (SLTiuOp RC:$lhs, 1)>;
1527 def : MipsPat<(setne RC:$lhs, 0),
1528 (SLTuOp ZEROReg, RC:$lhs)>;
1529 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1530 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1531 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1532 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1535 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1536 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1537 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1538 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1539 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1542 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1543 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1544 (SLTOp RC:$rhs, RC:$lhs)>;
1545 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1546 (SLTuOp RC:$rhs, RC:$lhs)>;
1549 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1550 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1551 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1552 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1553 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1556 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1557 Instruction SLTiuOp> {
1558 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1559 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1560 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1561 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1564 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1565 defm : SetlePats<GPR32, SLT, SLTu>;
1566 defm : SetgtPats<GPR32, SLT, SLTu>;
1567 defm : SetgePats<GPR32, SLT, SLTu>;
1568 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1571 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1573 // Load halfword/word patterns.
1574 let AddedComplexity = 40 in {
1575 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1576 def : LoadRegImmPat<LH, i32, sextloadi16>;
1577 def : LoadRegImmPat<LW, i32, load>;
1580 //===----------------------------------------------------------------------===//
1581 // Floating Point Support
1582 //===----------------------------------------------------------------------===//
1584 include "MipsInstrFPU.td"
1585 include "Mips64InstrInfo.td"
1586 include "MipsCondMov.td"
1588 include "Mips32r6InstrInfo.td"
1589 include "Mips64r6InstrInfo.td"
1594 include "Mips16InstrFormats.td"
1595 include "Mips16InstrInfo.td"
1598 include "MipsDSPInstrFormats.td"
1599 include "MipsDSPInstrInfo.td"
1602 include "MipsMSAInstrFormats.td"
1603 include "MipsMSAInstrInfo.td"
1606 include "MicroMipsInstrFormats.td"
1607 include "MicroMipsInstrInfo.td"
1608 include "MicroMipsInstrFPU.td"