1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def pcrel16 : Operand<i32> {
284 def MipsMemAsmOperand : AsmOperandClass {
286 let ParserMethod = "parseMemOperand";
289 def MipsInvertedImmoperand : AsmOperandClass {
291 let RenderMethod = "addImmOperands";
292 let ParserMethod = "parseInvNum";
295 def PtrRegAsmOperand : AsmOperandClass {
297 let ParserMethod = "parsePtrReg";
301 def InvertedImOperand : Operand<i32> {
302 let ParserMatchClass = MipsInvertedImmoperand;
305 class mem_generic : Operand<iPTR> {
306 let PrintMethod = "printMemOperand";
307 let MIOperandInfo = (ops ptr_rc, simm16);
308 let EncoderMethod = "getMemEncoding";
309 let ParserMatchClass = MipsMemAsmOperand;
310 let OperandType = "OPERAND_MEMORY";
314 def mem : mem_generic;
316 // MSA specific address operand
317 def mem_msa : mem_generic {
318 let EncoderMethod = "getMSAMemEncoding";
321 def mem_ea : Operand<iPTR> {
322 let PrintMethod = "printMemOperandEA";
323 let MIOperandInfo = (ops ptr_rc, simm16);
324 let EncoderMethod = "getMemEncoding";
325 let OperandType = "OPERAND_MEMORY";
328 def PtrRC : Operand<iPTR> {
329 let MIOperandInfo = (ops ptr_rc);
330 let DecoderMethod = "DecodePtrRegisterClass";
331 let ParserMatchClass = PtrRegAsmOperand;
334 // size operand of ext instruction
335 def size_ext : Operand<i32> {
336 let EncoderMethod = "getSizeExtEncoding";
337 let DecoderMethod = "DecodeExtSize";
340 // size operand of ins instruction
341 def size_ins : Operand<i32> {
342 let EncoderMethod = "getSizeInsEncoding";
343 let DecoderMethod = "DecodeInsSize";
346 // Transformation Function - get the lower 16 bits.
347 def LO16 : SDNodeXForm<imm, [{
348 return getImm(N, N->getZExtValue() & 0xFFFF);
351 // Transformation Function - get the higher 16 bits.
352 def HI16 : SDNodeXForm<imm, [{
353 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
357 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
359 // Node immediate fits as 16-bit sign extended on target immediate.
361 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
363 // Node immediate fits as 16-bit sign extended on target immediate.
365 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
367 // Node immediate fits as 15-bit sign extended on target immediate.
369 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
371 // Node immediate fits as 16-bit zero extended on target immediate.
372 // The LO16 param means that only the lower 16 bits of the node
373 // immediate are caught.
375 def immZExt16 : PatLeaf<(imm), [{
376 if (N->getValueType(0) == MVT::i32)
377 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
379 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
382 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
383 def immLow16Zero : PatLeaf<(imm), [{
384 int64_t Val = N->getSExtValue();
385 return isInt<32>(Val) && !(Val & 0xffff);
388 // shamt field must fit in 5 bits.
389 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
391 // True if (N + 1) fits in 16-bit field.
392 def immSExt16Plus1 : PatLeaf<(imm), [{
393 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
396 // Mips Address Mode! SDNode frameindex could possibily be a match
397 // since load and store instructions from stack used it.
399 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
402 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
405 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
408 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
410 //===----------------------------------------------------------------------===//
411 // Instructions specific format
412 //===----------------------------------------------------------------------===//
414 // Arithmetic and logical instructions with 3 register operands.
415 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
416 InstrItinClass Itin = NoItinerary,
417 SDPatternOperator OpNode = null_frag>:
418 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
419 !strconcat(opstr, "\t$rd, $rs, $rt"),
420 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
421 let isCommutable = isComm;
422 let isReMaterializable = 1;
425 // Arithmetic and logical instructions with 2 register operands.
426 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
427 InstrItinClass Itin = NoItinerary,
428 SDPatternOperator imm_type = null_frag,
429 SDPatternOperator OpNode = null_frag> :
430 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
431 !strconcat(opstr, "\t$rt, $rs, $imm16"),
432 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
434 let isReMaterializable = 1;
435 let TwoOperandAliasConstraint = "$rs = $rt";
438 // Arithmetic Multiply ADD/SUB
439 class MArithR<string opstr, bit isComm = 0> :
440 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
441 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
442 let Defs = [HI0, LO0];
443 let Uses = [HI0, LO0];
444 let isCommutable = isComm;
448 class LogicNOR<string opstr, RegisterOperand RO>:
449 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
450 !strconcat(opstr, "\t$rd, $rs, $rt"),
451 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
452 let isCommutable = 1;
456 class shift_rotate_imm<string opstr, Operand ImmOpnd,
457 RegisterOperand RO, InstrItinClass itin,
458 SDPatternOperator OpNode = null_frag,
459 SDPatternOperator PF = null_frag> :
460 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
461 !strconcat(opstr, "\t$rd, $rt, $shamt"),
462 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
464 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
465 SDPatternOperator OpNode = null_frag>:
466 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
467 !strconcat(opstr, "\t$rd, $rt, $rs"),
468 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
471 // Load Upper Imediate
472 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
473 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
474 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
475 let neverHasSideEffects = 1;
476 let isReMaterializable = 1;
480 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
481 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
482 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
483 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
484 let DecoderMethod = "DecodeMem";
485 let canFoldAsLoad = 1;
489 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
490 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
491 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
492 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
493 let DecoderMethod = "DecodeMem";
497 // Load/Store Left/Right
498 let canFoldAsLoad = 1 in
499 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
500 InstrItinClass Itin> :
501 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
502 !strconcat(opstr, "\t$rt, $addr"),
503 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
504 let DecoderMethod = "DecodeMem";
505 string Constraints = "$src = $rt";
508 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
509 InstrItinClass Itin> :
510 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
511 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
512 let DecoderMethod = "DecodeMem";
515 // Conditional Branch
516 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
517 RegisterOperand RO> :
518 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
519 !strconcat(opstr, "\t$rs, $rt, $offset"),
520 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
523 let isTerminator = 1;
524 let hasDelaySlot = 1;
528 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
529 RegisterOperand RO> :
530 InstSE<(outs), (ins RO:$rs, opnd:$offset),
531 !strconcat(opstr, "\t$rs, $offset"),
532 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
535 let isTerminator = 1;
536 let hasDelaySlot = 1;
541 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
542 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
543 !strconcat(opstr, "\t$rd, $rs, $rt"),
544 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
547 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
549 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
550 !strconcat(opstr, "\t$rt, $rs, $imm16"),
551 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
555 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
556 SDPatternOperator targetoperator, string bopstr> :
557 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
558 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
561 let hasDelaySlot = 1;
562 let DecoderMethod = "DecodeJumpTarget";
566 // Unconditional branch
567 class UncondBranch<Instruction BEQInst> :
568 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
569 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
571 let isTerminator = 1;
573 let hasDelaySlot = 1;
574 let Predicates = [RelocPIC, HasStdEnc];
578 // Base class for indirect branch and return instruction classes.
579 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
580 class JumpFR<string opstr, RegisterOperand RO,
581 SDPatternOperator operator = null_frag>:
582 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
586 class IndirectBranch<string opstr, RegisterOperand RO> :
587 JumpFR<opstr, RO, brind> {
589 let isIndirectBranch = 1;
592 // Return instruction
593 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
595 let isCodeGenOnly = 1;
597 let hasExtraSrcRegAllocReq = 1;
600 // Jump and Link (Call)
601 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
602 class JumpLink<string opstr, DAGOperand opnd> :
603 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
604 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
605 let DecoderMethod = "DecodeJumpTarget";
608 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
609 Register RetReg, RegisterOperand ResRO = RO>:
610 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
611 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
613 class JumpLinkReg<string opstr, RegisterOperand RO>:
614 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
615 [], IIBranch, FrmR, opstr>;
617 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
618 InstSE<(outs), (ins RO:$rs, opnd:$offset),
619 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
623 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
624 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
625 class TailCall<Instruction JumpInst> :
626 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
627 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
629 class TailCallReg<RegisterOperand RO, Instruction JRInst,
630 RegisterOperand ResRO = RO> :
631 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
632 PseudoInstExpansion<(JRInst ResRO:$rs)>;
635 class BAL_BR_Pseudo<Instruction RealInst> :
636 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
637 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
639 let isTerminator = 1;
641 let hasDelaySlot = 1;
646 class SYS_FT<string opstr> :
647 InstSE<(outs), (ins uimm20:$code_),
648 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
650 class BRK_FT<string opstr> :
651 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
652 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
656 class ER_FT<string opstr> :
657 InstSE<(outs), (ins),
658 opstr, [], NoItinerary, FrmOther, opstr>;
661 class DEI_FT<string opstr, RegisterOperand RO> :
662 InstSE<(outs RO:$rt), (ins),
663 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
666 class WAIT_FT<string opstr> :
667 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
670 let hasSideEffects = 1 in
671 class SYNC_FT<string opstr> :
672 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
673 NoItinerary, FrmOther, opstr>;
675 let hasSideEffects = 1 in
676 class TEQ_FT<string opstr, RegisterOperand RO> :
677 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
678 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
681 class TEQI_FT<string opstr, RegisterOperand RO> :
682 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
683 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
685 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
686 list<Register> DefRegs> :
687 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
689 let isCommutable = 1;
691 let neverHasSideEffects = 1;
694 // Pseudo multiply/divide instruction with explicit accumulator register
696 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
697 SDPatternOperator OpNode, InstrItinClass Itin,
698 bit IsComm = 1, bit HasSideEffects = 0,
699 bit UsesCustomInserter = 0> :
700 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
701 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
702 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
703 let isCommutable = IsComm;
704 let hasSideEffects = HasSideEffects;
705 let usesCustomInserter = UsesCustomInserter;
708 // Pseudo multiply add/sub instruction with explicit accumulator register
710 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
711 : PseudoSE<(outs ACC64:$ac),
712 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
714 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
716 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
717 string Constraints = "$acin = $ac";
720 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
721 list<Register> DefRegs> :
722 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
723 [], itin, FrmR, opstr> {
728 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
729 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
730 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
732 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
733 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
736 let neverHasSideEffects = 1;
739 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
740 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
741 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
744 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
745 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
748 let neverHasSideEffects = 1;
751 class EffectiveAddress<string opstr, RegisterOperand RO> :
752 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
753 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
754 !strconcat(opstr, "_lea")> {
755 let isCodeGenOnly = 1;
756 let DecoderMethod = "DecodeMem";
759 // Count Leading Ones/Zeros in Word
760 class CountLeading0<string opstr, RegisterOperand RO>:
761 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
762 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
763 Requires<[HasBitCount, HasStdEnc]>;
765 class CountLeading1<string opstr, RegisterOperand RO>:
766 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
767 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
768 Requires<[HasBitCount, HasStdEnc]>;
771 // Sign Extend in Register.
772 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
773 InstrItinClass itin> :
774 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
775 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
776 let Predicates = [HasSEInReg, HasStdEnc];
780 class SubwordSwap<string opstr, RegisterOperand RO>:
781 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
782 NoItinerary, FrmR, opstr> {
783 let Predicates = [HasSwap, HasStdEnc];
784 let neverHasSideEffects = 1;
788 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
789 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
793 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
794 SDPatternOperator Op = null_frag>:
795 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
796 !strconcat(opstr, " $rt, $rs, $pos, $size"),
797 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
799 let Predicates = [HasMips32r2, HasStdEnc];
802 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
803 SDPatternOperator Op = null_frag>:
804 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
805 !strconcat(opstr, " $rt, $rs, $pos, $size"),
806 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
807 NoItinerary, FrmR, opstr> {
808 let Predicates = [HasMips32r2, HasStdEnc];
809 let Constraints = "$src = $rt";
812 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
813 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
814 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
815 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
817 // Atomic Compare & Swap.
818 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
819 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
820 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
822 class LLBase<string opstr, RegisterOperand RO> :
823 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
824 [], NoItinerary, FrmI> {
825 let DecoderMethod = "DecodeMem";
829 class SCBase<string opstr, RegisterOperand RO> :
830 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
831 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
832 let DecoderMethod = "DecodeMem";
834 let Constraints = "$rt = $dst";
837 class MFC3OP<string asmstr, RegisterOperand RO> :
838 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
839 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
841 class TrapBase<Instruction RealInst>
842 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
843 PseudoInstExpansion<(RealInst 0, 0)> {
845 let isTerminator = 1;
846 let isCodeGenOnly = 1;
849 //===----------------------------------------------------------------------===//
850 // Pseudo instructions
851 //===----------------------------------------------------------------------===//
854 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
855 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
857 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
858 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
859 [(callseq_start timm:$amt)]>;
860 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
861 [(callseq_end timm:$amt1, timm:$amt2)]>;
864 let usesCustomInserter = 1 in {
865 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
866 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
867 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
868 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
869 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
870 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
871 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
872 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
873 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
874 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
875 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
876 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
877 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
878 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
879 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
880 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
881 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
882 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
884 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
885 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
886 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
888 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
889 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
890 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
893 /// Pseudo instructions for loading and storing accumulator registers.
894 let isPseudo = 1, isCodeGenOnly = 1 in {
895 def LOAD_ACC64 : Load<"", ACC64>;
896 def STORE_ACC64 : Store<"", ACC64>;
899 //===----------------------------------------------------------------------===//
900 // Instruction definition
901 //===----------------------------------------------------------------------===//
902 //===----------------------------------------------------------------------===//
903 // MipsI Instructions
904 //===----------------------------------------------------------------------===//
906 /// Arithmetic Instructions (ALU Immediate)
907 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
909 ADDI_FM<0x9>, IsAsCheapAsAMove;
910 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
911 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
913 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
915 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
918 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
921 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
924 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
926 /// Arithmetic Instructions (3-Operand, R-Type)
927 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
929 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
931 let Defs = [HI0, LO0] in
932 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
934 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
935 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
936 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
937 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
938 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
940 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
942 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
944 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
946 /// Shift Instructions
947 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
948 immZExt5>, SRA_FM<0, 0>;
949 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
950 immZExt5>, SRA_FM<2, 0>;
951 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
952 immZExt5>, SRA_FM<3, 0>;
953 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
955 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
957 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
960 // Rotate Instructions
961 let Predicates = [HasMips32r2, HasStdEnc] in {
962 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
963 immZExt5>, SRA_FM<2, 1>;
964 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
968 /// Load and Store Instructions
970 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
971 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
973 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
975 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
976 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
978 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
979 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
980 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
982 /// load/store left/right
983 let Predicates = [NotInMicroMips] in {
984 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
985 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
986 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
987 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
990 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
991 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
992 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
993 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
994 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
995 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
996 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
998 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
999 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1000 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1001 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1002 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1003 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1005 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1006 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1007 def TRAP : TrapBase<BREAK>;
1009 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1010 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1012 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1013 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1015 def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM;
1017 /// Load-linked, Store-conditional
1018 let Predicates = [NotInMicroMips] in {
1019 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1020 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1023 /// Jump and Branch Instructions
1024 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1025 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1026 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1027 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1028 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1029 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1031 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1033 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1035 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1037 def B : UncondBranch<BEQ>;
1039 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1040 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1041 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1042 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1043 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1044 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1045 def TAILCALL : TailCall<J>;
1046 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1048 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1050 // Exception handling related node and instructions.
1051 // The conversion sequence is:
1052 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1053 // MIPSeh_return -> (stack change + indirect branch)
1055 // MIPSeh_return takes the place of regular return instruction
1056 // but takes two arguments (V1, V0) which are used for storing
1057 // the offset and return address respectively.
1058 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1060 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1061 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1063 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1064 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1065 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1066 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1068 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1071 /// Multiply and Divide Instructions.
1072 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1074 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1076 def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1078 def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1081 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1082 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1083 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1084 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1086 /// Sign Ext In Register Instructions.
1087 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1088 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1091 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1092 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1094 /// Word Swap Bytes Within Halfwords
1095 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1098 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1100 // FrameIndexes are legalized when they are operands from load/store
1101 // instructions. The same not happens for stack address copies, so an
1102 // add op with mem ComplexPattern is used and the stack address copy
1103 // can be matched. It's similar to Sparc LEA_ADDRi
1104 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1107 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1108 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1109 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1110 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1112 let Predicates = [HasStdEnc, NotDSP] in {
1113 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1114 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1115 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1116 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1117 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1118 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1119 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1120 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1121 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1124 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1126 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1129 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1131 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1132 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1134 /// Move Control Registers From/To CPU Registers
1135 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1136 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1137 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1138 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1140 //===----------------------------------------------------------------------===//
1141 // Instruction aliases
1142 //===----------------------------------------------------------------------===//
1143 def : InstAlias<"move $dst, $src",
1144 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1145 Requires<[NotMips64]>;
1146 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1147 def : InstAlias<"addu $rs, $rt, $imm",
1148 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1149 def : InstAlias<"add $rs, $rt, $imm",
1150 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1151 def : InstAlias<"and $rs, $rt, $imm",
1152 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1153 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1154 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1155 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1156 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1157 def : InstAlias<"not $rt, $rs",
1158 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1159 def : InstAlias<"neg $rt, $rs",
1160 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1161 def : InstAlias<"negu $rt, $rs",
1162 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1163 def : InstAlias<"slt $rs, $rt, $imm",
1164 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1165 def : InstAlias<"xor $rs, $rt, $imm",
1166 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1167 def : InstAlias<"or $rs, $rt, $imm",
1168 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1169 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1170 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1171 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1172 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1173 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1174 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1175 def : InstAlias<"bnez $rs,$offset",
1176 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1177 def : InstAlias<"beqz $rs,$offset",
1178 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1179 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1181 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1182 def : InstAlias<"break", (BREAK 0, 0), 1>;
1183 def : InstAlias<"ei", (EI ZERO), 1>;
1184 def : InstAlias<"di", (DI ZERO), 1>;
1186 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1187 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1188 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1189 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1190 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1191 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1192 def : InstAlias<"sub, $rd, $rs, $imm",
1193 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1194 def : InstAlias<"subu, $rd, $rs, $imm",
1195 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1197 //===----------------------------------------------------------------------===//
1198 // Assembler Pseudo Instructions
1199 //===----------------------------------------------------------------------===//
1201 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1202 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1203 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1204 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1206 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1207 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1208 !strconcat(instr_asm, "\t$rt, $addr")> ;
1209 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1211 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1212 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1213 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1214 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1216 //===----------------------------------------------------------------------===//
1217 // Arbitrary patterns that map to one or more instructions
1218 //===----------------------------------------------------------------------===//
1220 // Load/store pattern templates.
1221 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1222 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1224 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1225 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1228 def : MipsPat<(i32 immSExt16:$in),
1229 (ADDiu ZERO, imm:$in)>;
1230 def : MipsPat<(i32 immZExt16:$in),
1231 (ORi ZERO, imm:$in)>;
1232 def : MipsPat<(i32 immLow16Zero:$in),
1233 (LUi (HI16 imm:$in))>;
1235 // Arbitrary immediates
1236 def : MipsPat<(i32 imm:$imm),
1237 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1239 // Carry MipsPatterns
1240 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1241 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1242 let Predicates = [HasStdEnc, NotDSP] in {
1243 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1244 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1245 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1246 (ADDiu GPR32:$src, imm:$imm)>;
1250 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1251 (JAL tglobaladdr:$dst)>;
1252 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1253 (JAL texternalsym:$dst)>;
1254 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1255 // (JALR GPR32:$dst)>;
1258 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1259 (TAILCALL tglobaladdr:$dst)>;
1260 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1261 (TAILCALL texternalsym:$dst)>;
1263 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1264 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1265 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1266 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1267 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1268 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1270 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1271 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1272 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1273 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1274 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1275 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1277 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1278 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1279 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1280 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1281 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1282 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1283 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1284 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1285 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1286 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1289 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1290 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1291 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1292 (ADDiu GPR32:$gp, tconstpool:$in)>;
1295 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1296 MipsPat<(MipsWrapper RC:$gp, node:$in),
1297 (ADDiuOp RC:$gp, node:$in)>;
1299 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1300 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1301 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1302 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1303 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1304 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1306 // Mips does not have "not", so we expand our way
1307 def : MipsPat<(not GPR32:$in),
1308 (NOR GPR32Opnd:$in, ZERO)>;
1311 let Predicates = [HasStdEnc] in {
1312 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1313 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1314 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1318 let Predicates = [HasStdEnc] in
1319 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1322 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1323 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1324 Instruction SLTiuOp, Register ZEROReg> {
1325 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1326 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1327 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1328 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1330 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1331 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1332 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1333 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1334 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1335 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1336 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1337 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1338 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1339 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1340 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1341 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1343 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1344 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1345 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1346 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1348 def : MipsPat<(brcond RC:$cond, bb:$dst),
1349 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1352 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1354 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1355 (BLEZ i32:$lhs, bb:$dst)>;
1356 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1357 (BGEZ i32:$lhs, bb:$dst)>;
1360 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1361 Instruction SLTuOp, Register ZEROReg> {
1362 def : MipsPat<(seteq RC:$lhs, 0),
1363 (SLTiuOp RC:$lhs, 1)>;
1364 def : MipsPat<(setne RC:$lhs, 0),
1365 (SLTuOp ZEROReg, RC:$lhs)>;
1366 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1367 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1368 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1369 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1372 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1373 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1374 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1375 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1376 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1379 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1380 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1381 (SLTOp RC:$rhs, RC:$lhs)>;
1382 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1383 (SLTuOp RC:$rhs, RC:$lhs)>;
1386 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1387 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1388 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1389 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1390 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1393 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1394 Instruction SLTiuOp> {
1395 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1396 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1397 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1398 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1401 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1402 defm : SetlePats<GPR32, SLT, SLTu>;
1403 defm : SetgtPats<GPR32, SLT, SLTu>;
1404 defm : SetgePats<GPR32, SLT, SLTu>;
1405 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1408 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1410 // Load halfword/word patterns.
1411 let AddedComplexity = 40 in {
1412 let Predicates = [HasStdEnc] in {
1413 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1414 def : LoadRegImmPat<LH, i32, sextloadi16>;
1415 def : LoadRegImmPat<LW, i32, load>;
1419 //===----------------------------------------------------------------------===//
1420 // Floating Point Support
1421 //===----------------------------------------------------------------------===//
1423 include "MipsInstrFPU.td"
1424 include "Mips64InstrInfo.td"
1425 include "MipsCondMov.td"
1430 include "Mips16InstrFormats.td"
1431 include "Mips16InstrInfo.td"
1434 include "MipsDSPInstrFormats.td"
1435 include "MipsDSPInstrInfo.td"
1438 include "MipsMSAInstrFormats.td"
1439 include "MipsMSAInstrInfo.td"
1442 include "MicroMipsInstrFormats.td"
1443 include "MicroMipsInstrInfo.td"
1444 include "MicroMipsInstrFPU.td"