1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
164 AssemblerPredicate<"FeatureGP64Bit">;
165 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
166 AssemblerPredicate<"!FeatureGP64Bit">;
167 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
168 AssemblerPredicate<"FeatureMips64">;
169 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def IsGP64 : Predicate<"Subtarget.isGP64()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
174 AssemblerPredicate<"FeatureMips64r2">;
175 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
176 AssemblerPredicate<"FeatureN64">;
177 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
178 AssemblerPredicate<"FeatureMips16">;
179 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
180 AssemblerPredicate<"FeatureCnMips">;
181 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
182 AssemblerPredicate<"FeatureMips32">;
183 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
184 AssemblerPredicate<"FeatureMips32">;
185 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
186 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
187 AssemblerPredicate<"!FeatureMips16">;
188 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
189 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
190 AssemblerPredicate<"FeatureMicroMips">;
191 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
192 AssemblerPredicate<"!FeatureMicroMips">;
193 def IsLE : Predicate<"Subtarget.isLittle()">;
194 def IsBE : Predicate<"!Subtarget.isLittle()">;
195 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
197 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
198 let Predicates = [HasStdEnc];
202 bit isCommutable = 1;
219 bit isTerminator = 1;
222 bit hasExtraSrcRegAllocReq = 1;
223 bit isCodeGenOnly = 1;
226 class IsAsCheapAsAMove {
227 bit isAsCheapAsAMove = 1;
230 class NeverHasSideEffects {
231 bit neverHasSideEffects = 1;
234 //===----------------------------------------------------------------------===//
235 // Instruction format superclass
236 //===----------------------------------------------------------------------===//
238 include "MipsInstrFormats.td"
240 //===----------------------------------------------------------------------===//
241 // Mips Operand, Complex Patterns and Transformations Definitions.
242 //===----------------------------------------------------------------------===//
244 def MipsJumpTargetAsmOperand : AsmOperandClass {
245 let Name = "JumpTarget";
246 let ParserMethod = "ParseJumpTarget";
247 let PredicateMethod = "isImm";
248 let RenderMethod = "addImmOperands";
251 // Instruction operand types
252 def jmptarget : Operand<OtherVT> {
253 let EncoderMethod = "getJumpTargetOpValue";
254 let ParserMatchClass = MipsJumpTargetAsmOperand;
256 def brtarget : Operand<OtherVT> {
257 let EncoderMethod = "getBranchTargetOpValue";
258 let OperandType = "OPERAND_PCREL";
259 let DecoderMethod = "DecodeBranchTarget";
260 let ParserMatchClass = MipsJumpTargetAsmOperand;
262 def calltarget : Operand<iPTR> {
263 let EncoderMethod = "getJumpTargetOpValue";
264 let ParserMatchClass = MipsJumpTargetAsmOperand;
267 def simm10 : Operand<i32>;
269 def simm16 : Operand<i32> {
270 let DecoderMethod= "DecodeSimm16";
273 def simm20 : Operand<i32> {
276 def uimm20 : Operand<i32> {
279 def uimm10 : Operand<i32> {
282 def simm16_64 : Operand<i64> {
283 let DecoderMethod = "DecodeSimm16";
287 def uimmz : Operand<i32> {
288 let PrintMethod = "printUnsignedImm";
292 def uimm5 : Operand<i32> {
293 let PrintMethod = "printUnsignedImm";
296 def uimm6 : Operand<i32> {
297 let PrintMethod = "printUnsignedImm";
300 def uimm16 : Operand<i32> {
301 let PrintMethod = "printUnsignedImm";
304 def pcrel16 : Operand<i32> {
307 def MipsMemAsmOperand : AsmOperandClass {
309 let ParserMethod = "parseMemOperand";
312 def MipsInvertedImmoperand : AsmOperandClass {
314 let RenderMethod = "addImmOperands";
315 let ParserMethod = "parseInvNum";
318 def InvertedImOperand : Operand<i32> {
319 let ParserMatchClass = MipsInvertedImmoperand;
322 def InvertedImOperand64 : Operand<i64> {
323 let ParserMatchClass = MipsInvertedImmoperand;
326 class mem_generic : Operand<iPTR> {
327 let PrintMethod = "printMemOperand";
328 let MIOperandInfo = (ops ptr_rc, simm16);
329 let EncoderMethod = "getMemEncoding";
330 let ParserMatchClass = MipsMemAsmOperand;
331 let OperandType = "OPERAND_MEMORY";
335 def mem : mem_generic;
337 // MSA specific address operand
338 def mem_msa : mem_generic {
339 let MIOperandInfo = (ops ptr_rc, simm10);
340 let EncoderMethod = "getMSAMemEncoding";
343 def mem_ea : Operand<iPTR> {
344 let PrintMethod = "printMemOperandEA";
345 let MIOperandInfo = (ops ptr_rc, simm16);
346 let EncoderMethod = "getMemEncoding";
347 let OperandType = "OPERAND_MEMORY";
350 def PtrRC : Operand<iPTR> {
351 let MIOperandInfo = (ops ptr_rc);
352 let DecoderMethod = "DecodePtrRegisterClass";
353 let ParserMatchClass = GPR32AsmOperand;
356 // size operand of ext instruction
357 def size_ext : Operand<i32> {
358 let EncoderMethod = "getSizeExtEncoding";
359 let DecoderMethod = "DecodeExtSize";
362 // size operand of ins instruction
363 def size_ins : Operand<i32> {
364 let EncoderMethod = "getSizeInsEncoding";
365 let DecoderMethod = "DecodeInsSize";
368 // Transformation Function - get the lower 16 bits.
369 def LO16 : SDNodeXForm<imm, [{
370 return getImm(N, N->getZExtValue() & 0xFFFF);
373 // Transformation Function - get the higher 16 bits.
374 def HI16 : SDNodeXForm<imm, [{
375 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
379 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
381 // Node immediate is zero (e.g. insve.d)
382 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
384 // Node immediate fits as 16-bit sign extended on target immediate.
386 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
388 // Node immediate fits as 16-bit sign extended on target immediate.
390 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
392 // Node immediate fits as 15-bit sign extended on target immediate.
394 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
396 // Node immediate fits as 16-bit zero extended on target immediate.
397 // The LO16 param means that only the lower 16 bits of the node
398 // immediate are caught.
400 def immZExt16 : PatLeaf<(imm), [{
401 if (N->getValueType(0) == MVT::i32)
402 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
404 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
407 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
408 def immLow16Zero : PatLeaf<(imm), [{
409 int64_t Val = N->getSExtValue();
410 return isInt<32>(Val) && !(Val & 0xffff);
413 // shamt field must fit in 5 bits.
414 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
416 // True if (N + 1) fits in 16-bit field.
417 def immSExt16Plus1 : PatLeaf<(imm), [{
418 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
421 // Mips Address Mode! SDNode frameindex could possibily be a match
422 // since load and store instructions from stack used it.
424 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
427 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
430 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
433 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
435 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
437 //===----------------------------------------------------------------------===//
438 // Instructions specific format
439 //===----------------------------------------------------------------------===//
441 // Arithmetic and logical instructions with 3 register operands.
442 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
443 InstrItinClass Itin = NoItinerary,
444 SDPatternOperator OpNode = null_frag>:
445 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
446 !strconcat(opstr, "\t$rd, $rs, $rt"),
447 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
448 let isCommutable = isComm;
449 let isReMaterializable = 1;
450 let TwoOperandAliasConstraint = "$rd = $rs";
453 // Arithmetic and logical instructions with 2 register operands.
454 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
455 InstrItinClass Itin = NoItinerary,
456 SDPatternOperator imm_type = null_frag,
457 SDPatternOperator OpNode = null_frag> :
458 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
459 !strconcat(opstr, "\t$rt, $rs, $imm16"),
460 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
462 let isReMaterializable = 1;
463 let TwoOperandAliasConstraint = "$rs = $rt";
466 // Arithmetic Multiply ADD/SUB
467 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
468 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
469 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
470 let Defs = [HI0, LO0];
471 let Uses = [HI0, LO0];
472 let isCommutable = isComm;
476 class LogicNOR<string opstr, RegisterOperand RO>:
477 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
478 !strconcat(opstr, "\t$rd, $rs, $rt"),
479 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
480 let isCommutable = 1;
484 class shift_rotate_imm<string opstr, Operand ImmOpnd,
485 RegisterOperand RO, InstrItinClass itin,
486 SDPatternOperator OpNode = null_frag,
487 SDPatternOperator PF = null_frag> :
488 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
489 !strconcat(opstr, "\t$rd, $rt, $shamt"),
490 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
491 let TwoOperandAliasConstraint = "$rt = $rd";
494 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
495 SDPatternOperator OpNode = null_frag>:
496 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
497 !strconcat(opstr, "\t$rd, $rt, $rs"),
498 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
500 let TwoOperandAliasConstraint = "$rt = $rd";
503 // Load Upper Imediate
504 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
505 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
506 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
507 let neverHasSideEffects = 1;
508 let isReMaterializable = 1;
512 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
513 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
514 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
515 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
516 let DecoderMethod = "DecodeMem";
517 let canFoldAsLoad = 1;
521 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
522 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
523 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
524 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
525 let DecoderMethod = "DecodeMem";
529 // Load/Store Left/Right
530 let canFoldAsLoad = 1 in
531 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
532 InstrItinClass Itin> :
533 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
534 !strconcat(opstr, "\t$rt, $addr"),
535 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
536 let DecoderMethod = "DecodeMem";
537 string Constraints = "$src = $rt";
540 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
541 InstrItinClass Itin> :
542 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
543 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
544 let DecoderMethod = "DecodeMem";
547 // Conditional Branch
548 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
549 RegisterOperand RO> :
550 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
551 !strconcat(opstr, "\t$rs, $rt, $offset"),
552 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
555 let isTerminator = 1;
556 let hasDelaySlot = 1;
560 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
561 RegisterOperand RO> :
562 InstSE<(outs), (ins RO:$rs, opnd:$offset),
563 !strconcat(opstr, "\t$rs, $offset"),
564 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
567 let isTerminator = 1;
568 let hasDelaySlot = 1;
573 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
574 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
575 !strconcat(opstr, "\t$rd, $rs, $rt"),
576 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
577 II_SLT_SLTU, FrmR, opstr>;
579 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
581 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
582 !strconcat(opstr, "\t$rt, $rs, $imm16"),
583 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
584 II_SLTI_SLTIU, FrmI, opstr>;
587 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
588 SDPatternOperator targetoperator, string bopstr> :
589 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
590 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
593 let hasDelaySlot = 1;
594 let DecoderMethod = "DecodeJumpTarget";
598 // Unconditional branch
599 class UncondBranch<Instruction BEQInst> :
600 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
601 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
603 let isTerminator = 1;
605 let hasDelaySlot = 1;
606 let Predicates = [RelocPIC, HasStdEnc];
610 // Base class for indirect branch and return instruction classes.
611 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
612 class JumpFR<string opstr, RegisterOperand RO,
613 SDPatternOperator operator = null_frag>:
614 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
618 class IndirectBranch<string opstr, RegisterOperand RO> :
619 JumpFR<opstr, RO, brind> {
621 let isIndirectBranch = 1;
624 // Return instruction
625 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
627 let isCodeGenOnly = 1;
629 let hasExtraSrcRegAllocReq = 1;
632 // Jump and Link (Call)
633 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
634 class JumpLink<string opstr, DAGOperand opnd> :
635 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
636 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
637 let DecoderMethod = "DecodeJumpTarget";
640 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
641 Register RetReg, RegisterOperand ResRO = RO>:
642 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
643 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
645 class JumpLinkReg<string opstr, RegisterOperand RO>:
646 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
649 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
650 InstSE<(outs), (ins RO:$rs, opnd:$offset),
651 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
655 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
656 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
657 class TailCall<Instruction JumpInst> :
658 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
659 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
661 class TailCallReg<RegisterOperand RO, Instruction JRInst,
662 RegisterOperand ResRO = RO> :
663 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
664 PseudoInstExpansion<(JRInst ResRO:$rs)>;
667 class BAL_BR_Pseudo<Instruction RealInst> :
668 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
669 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
671 let isTerminator = 1;
673 let hasDelaySlot = 1;
678 class SYS_FT<string opstr> :
679 InstSE<(outs), (ins uimm20:$code_),
680 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
682 class BRK_FT<string opstr> :
683 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
684 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
688 class ER_FT<string opstr> :
689 InstSE<(outs), (ins),
690 opstr, [], NoItinerary, FrmOther, opstr>;
693 class DEI_FT<string opstr, RegisterOperand RO> :
694 InstSE<(outs RO:$rt), (ins),
695 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
698 class WAIT_FT<string opstr> :
699 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
702 let hasSideEffects = 1 in
703 class SYNC_FT<string opstr> :
704 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
705 NoItinerary, FrmOther, opstr>;
707 let hasSideEffects = 1 in
708 class TEQ_FT<string opstr, RegisterOperand RO> :
709 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
710 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
713 class TEQI_FT<string opstr, RegisterOperand RO> :
714 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
715 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
717 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
718 list<Register> DefRegs> :
719 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
721 let isCommutable = 1;
723 let neverHasSideEffects = 1;
726 // Pseudo multiply/divide instruction with explicit accumulator register
728 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
729 SDPatternOperator OpNode, InstrItinClass Itin,
730 bit IsComm = 1, bit HasSideEffects = 0,
731 bit UsesCustomInserter = 0> :
732 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
733 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
734 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
735 let isCommutable = IsComm;
736 let hasSideEffects = HasSideEffects;
737 let usesCustomInserter = UsesCustomInserter;
740 // Pseudo multiply add/sub instruction with explicit accumulator register
742 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
744 : PseudoSE<(outs ACC64:$ac),
745 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
747 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
749 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
750 string Constraints = "$acin = $ac";
753 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
754 list<Register> DefRegs> :
755 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
756 [], itin, FrmR, opstr> {
761 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
762 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
763 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
765 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
766 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
769 let neverHasSideEffects = 1;
772 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
773 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
774 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
777 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
778 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
781 let neverHasSideEffects = 1;
784 class EffectiveAddress<string opstr, RegisterOperand RO> :
785 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
786 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
787 !strconcat(opstr, "_lea")> {
788 let isCodeGenOnly = 1;
789 let DecoderMethod = "DecodeMem";
792 // Count Leading Ones/Zeros in Word
793 class CountLeading0<string opstr, RegisterOperand RO>:
794 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
795 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
796 Requires<[HasBitCount, HasStdEnc]>;
798 class CountLeading1<string opstr, RegisterOperand RO>:
799 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
800 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
801 Requires<[HasBitCount, HasStdEnc]>;
803 // Sign Extend in Register.
804 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
805 InstrItinClass itin> :
806 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
807 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
808 let Predicates = [HasSEInReg, HasStdEnc];
812 class SubwordSwap<string opstr, RegisterOperand RO>:
813 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
814 NoItinerary, FrmR, opstr> {
815 let Predicates = [HasSwap, HasStdEnc];
816 let neverHasSideEffects = 1;
820 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
821 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
825 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
826 SDPatternOperator Op = null_frag>:
827 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
828 !strconcat(opstr, " $rt, $rs, $pos, $size"),
829 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
831 let Predicates = [HasMips32r2, HasStdEnc];
834 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
835 SDPatternOperator Op = null_frag>:
836 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
837 !strconcat(opstr, " $rt, $rs, $pos, $size"),
838 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
839 NoItinerary, FrmR, opstr> {
840 let Predicates = [HasMips32r2, HasStdEnc];
841 let Constraints = "$src = $rt";
844 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
845 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
846 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
847 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
849 // Atomic Compare & Swap.
850 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
851 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
852 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
854 class LLBase<string opstr, RegisterOperand RO> :
855 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
856 [], NoItinerary, FrmI> {
857 let DecoderMethod = "DecodeMem";
861 class SCBase<string opstr, RegisterOperand RO> :
862 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
863 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
864 let DecoderMethod = "DecodeMem";
866 let Constraints = "$rt = $dst";
869 class MFC3OP<string asmstr, RegisterOperand RO> :
870 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
871 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
873 class TrapBase<Instruction RealInst>
874 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
875 PseudoInstExpansion<(RealInst 0, 0)> {
877 let isTerminator = 1;
878 let isCodeGenOnly = 1;
881 //===----------------------------------------------------------------------===//
882 // Pseudo instructions
883 //===----------------------------------------------------------------------===//
886 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
887 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
889 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
890 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
891 [(callseq_start timm:$amt)]>;
892 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
893 [(callseq_end timm:$amt1, timm:$amt2)]>;
896 let usesCustomInserter = 1 in {
897 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
898 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
899 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
900 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
901 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
902 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
903 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
904 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
905 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
906 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
907 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
908 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
909 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
910 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
911 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
912 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
913 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
914 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
916 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
917 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
918 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
920 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
921 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
922 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
925 /// Pseudo instructions for loading and storing accumulator registers.
926 let isPseudo = 1, isCodeGenOnly = 1 in {
927 def LOAD_ACC64 : Load<"", ACC64>;
928 def STORE_ACC64 : Store<"", ACC64>;
931 // We need these two pseudo instructions to avoid offset calculation for long
932 // branches. See the comment in file MipsLongBranch.cpp for detailed
935 // Expands to: lui $dst, %hi($tgt - $baltgt)
936 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
937 (ins brtarget:$tgt, brtarget:$baltgt), []>;
939 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
940 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
941 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
943 //===----------------------------------------------------------------------===//
944 // Instruction definition
945 //===----------------------------------------------------------------------===//
946 //===----------------------------------------------------------------------===//
947 // MipsI Instructions
948 //===----------------------------------------------------------------------===//
950 /// Arithmetic Instructions (ALU Immediate)
951 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
953 ADDI_FM<0x9>, IsAsCheapAsAMove;
954 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
955 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
957 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
959 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
962 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
965 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
968 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
970 /// Arithmetic Instructions (3-Operand, R-Type)
971 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
973 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
975 let Defs = [HI0, LO0] in
976 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
978 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
979 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
980 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
981 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
982 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
984 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
986 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
988 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
990 /// Shift Instructions
991 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
992 immZExt5>, SRA_FM<0, 0>;
993 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
994 immZExt5>, SRA_FM<2, 0>;
995 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
996 immZExt5>, SRA_FM<3, 0>;
997 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
999 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1001 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1004 // Rotate Instructions
1005 let Predicates = [HasMips32r2, HasStdEnc] in {
1006 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1007 immZExt5>, SRA_FM<2, 1>;
1008 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1012 /// Load and Store Instructions
1014 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1015 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1017 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1019 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1020 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1022 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1023 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1024 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1026 /// load/store left/right
1027 let Predicates = [NotInMicroMips] in {
1028 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1029 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1030 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1031 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1034 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1035 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1036 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1037 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1038 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1039 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1040 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1042 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1043 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1044 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1045 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1046 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1047 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1049 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1050 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1051 def TRAP : TrapBase<BREAK>;
1053 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1054 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1056 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1057 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1059 let Predicates = [NotInMicroMips] in {
1060 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1062 /// Load-linked, Store-conditional
1063 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1064 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1067 /// Jump and Branch Instructions
1068 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1069 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1070 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1071 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1072 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1073 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1075 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1077 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1079 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1081 def B : UncondBranch<BEQ>;
1083 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1084 let Predicates = [NotInMicroMips, HasStdEnc] in {
1085 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1086 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1088 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1089 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1090 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1091 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1092 def TAILCALL : TailCall<J>;
1093 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1095 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1097 // Exception handling related node and instructions.
1098 // The conversion sequence is:
1099 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1100 // MIPSeh_return -> (stack change + indirect branch)
1102 // MIPSeh_return takes the place of regular return instruction
1103 // but takes two arguments (V1, V0) which are used for storing
1104 // the offset and return address respectively.
1105 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1107 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1108 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1110 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1111 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1112 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1113 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1115 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1118 /// Multiply and Divide Instructions.
1119 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1121 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1123 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1125 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1128 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1129 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1130 let Predicates = [NotInMicroMips] in {
1131 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1132 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1135 /// Sign Ext In Register Instructions.
1136 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1137 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1140 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1141 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1143 /// Word Swap Bytes Within Halfwords
1144 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1147 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1149 // FrameIndexes are legalized when they are operands from load/store
1150 // instructions. The same not happens for stack address copies, so an
1151 // add op with mem ComplexPattern is used and the stack address copy
1152 // can be matched. It's similar to Sparc LEA_ADDRi
1153 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1156 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1157 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1158 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1159 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1161 let Predicates = [HasStdEnc, NotDSP] in {
1162 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1163 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1164 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1165 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1166 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1167 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1168 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1169 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1170 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1173 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1175 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1178 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1180 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1181 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1183 /// Move Control Registers From/To CPU Registers
1184 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1185 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1186 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1187 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1189 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1191 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1192 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1193 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>;
1195 //===----------------------------------------------------------------------===//
1196 // Instruction aliases
1197 //===----------------------------------------------------------------------===//
1198 def : InstAlias<"move $dst, $src",
1199 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1200 Requires<[IsGP32, NotInMicroMips]>;
1201 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1202 def : InstAlias<"addu $rs, $rt, $imm",
1203 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1204 def : InstAlias<"add $rs, $rt, $imm",
1205 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1206 def : InstAlias<"and $rs, $rt, $imm",
1207 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1208 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1209 let Predicates = [NotInMicroMips] in {
1210 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1212 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1213 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1214 def : InstAlias<"not $rt, $rs",
1215 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1216 def : InstAlias<"neg $rt, $rs",
1217 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1218 def : InstAlias<"negu $rt, $rs",
1219 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1220 def : InstAlias<"slt $rs, $rt, $imm",
1221 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1222 def : InstAlias<"xor $rs, $rt, $imm",
1223 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1224 def : InstAlias<"or $rs, $rt, $imm",
1225 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1226 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1227 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1228 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1229 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1230 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1231 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1232 def : InstAlias<"bnez $rs,$offset",
1233 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1234 def : InstAlias<"beqz $rs,$offset",
1235 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1236 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1238 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1239 def : InstAlias<"break", (BREAK 0, 0), 1>;
1240 def : InstAlias<"ei", (EI ZERO), 1>;
1241 def : InstAlias<"di", (DI ZERO), 1>;
1243 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1244 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1245 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1246 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1247 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1248 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1249 def : InstAlias<"sll $rd, $rt, $rs",
1250 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1251 def : InstAlias<"sub, $rd, $rs, $imm",
1252 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1253 def : InstAlias<"sub $rs, $imm",
1254 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1256 def : InstAlias<"subu, $rd, $rs, $imm",
1257 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1258 def : InstAlias<"subu $rs, $imm",
1259 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1261 def : InstAlias<"srl $rd, $rt, $rs",
1262 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1263 //===----------------------------------------------------------------------===//
1264 // Assembler Pseudo Instructions
1265 //===----------------------------------------------------------------------===//
1267 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1268 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1269 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1270 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1272 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1273 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1274 !strconcat(instr_asm, "\t$rt, $addr")> ;
1275 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1277 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1278 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1279 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1280 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1282 //===----------------------------------------------------------------------===//
1283 // Arbitrary patterns that map to one or more instructions
1284 //===----------------------------------------------------------------------===//
1286 // Load/store pattern templates.
1287 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1288 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1290 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1291 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1294 def : MipsPat<(i32 immSExt16:$in),
1295 (ADDiu ZERO, imm:$in)>;
1296 def : MipsPat<(i32 immZExt16:$in),
1297 (ORi ZERO, imm:$in)>;
1298 def : MipsPat<(i32 immLow16Zero:$in),
1299 (LUi (HI16 imm:$in))>;
1301 // Arbitrary immediates
1302 def : MipsPat<(i32 imm:$imm),
1303 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1305 // Carry MipsPatterns
1306 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1307 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1308 let Predicates = [HasStdEnc, NotDSP] in {
1309 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1310 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1311 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1312 (ADDiu GPR32:$src, imm:$imm)>;
1316 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1317 (JAL tglobaladdr:$dst)>;
1318 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1319 (JAL texternalsym:$dst)>;
1320 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1321 // (JALR GPR32:$dst)>;
1324 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1325 (TAILCALL tglobaladdr:$dst)>;
1326 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1327 (TAILCALL texternalsym:$dst)>;
1329 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1330 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1331 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1332 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1333 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1334 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1336 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1337 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1338 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1339 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1340 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1341 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1343 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1344 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1345 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1346 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1347 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1348 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1349 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1350 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1351 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1352 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1355 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1356 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1357 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1358 (ADDiu GPR32:$gp, tconstpool:$in)>;
1361 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1362 MipsPat<(MipsWrapper RC:$gp, node:$in),
1363 (ADDiuOp RC:$gp, node:$in)>;
1365 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1366 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1367 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1368 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1369 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1370 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1372 // Mips does not have "not", so we expand our way
1373 def : MipsPat<(not GPR32:$in),
1374 (NOR GPR32Opnd:$in, ZERO)>;
1377 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1378 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1379 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1382 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1385 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1386 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1387 Instruction SLTiuOp, Register ZEROReg> {
1388 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1389 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1390 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1391 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1393 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1394 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1395 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1396 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1397 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1398 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1399 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1400 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1401 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1402 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1403 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1404 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1406 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1407 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1408 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1409 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1411 def : MipsPat<(brcond RC:$cond, bb:$dst),
1412 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1415 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1417 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1418 (BLEZ i32:$lhs, bb:$dst)>;
1419 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1420 (BGEZ i32:$lhs, bb:$dst)>;
1423 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1424 Instruction SLTuOp, Register ZEROReg> {
1425 def : MipsPat<(seteq RC:$lhs, 0),
1426 (SLTiuOp RC:$lhs, 1)>;
1427 def : MipsPat<(setne RC:$lhs, 0),
1428 (SLTuOp ZEROReg, RC:$lhs)>;
1429 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1430 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1431 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1432 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1435 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1436 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1437 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1438 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1439 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1442 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1443 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1444 (SLTOp RC:$rhs, RC:$lhs)>;
1445 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1446 (SLTuOp RC:$rhs, RC:$lhs)>;
1449 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1450 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1451 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1452 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1453 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1456 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1457 Instruction SLTiuOp> {
1458 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1459 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1460 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1461 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1464 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1465 defm : SetlePats<GPR32, SLT, SLTu>;
1466 defm : SetgtPats<GPR32, SLT, SLTu>;
1467 defm : SetgePats<GPR32, SLT, SLTu>;
1468 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1471 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1473 // Load halfword/word patterns.
1474 let AddedComplexity = 40 in {
1475 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1476 def : LoadRegImmPat<LH, i32, sextloadi16>;
1477 def : LoadRegImmPat<LW, i32, load>;
1480 //===----------------------------------------------------------------------===//
1481 // Floating Point Support
1482 //===----------------------------------------------------------------------===//
1484 include "MipsInstrFPU.td"
1485 include "Mips64InstrInfo.td"
1486 include "MipsCondMov.td"
1491 include "Mips16InstrFormats.td"
1492 include "Mips16InstrInfo.td"
1495 include "MipsDSPInstrFormats.td"
1496 include "MipsDSPInstrInfo.td"
1499 include "MipsMSAInstrFormats.td"
1500 include "MipsMSAInstrInfo.td"
1503 include "MicroMipsInstrFormats.td"
1504 include "MicroMipsInstrInfo.td"
1505 include "MicroMipsInstrFPU.td"