1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget->isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64_NOT_64R6 {
244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
246 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
247 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
248 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
253 // The portions of MIPS-III that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS3_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-III that were also added to MIPS32
260 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
262 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
263 // MIPS32r6 and MIPS64r6.
264 class INSN_MIPS4_32_NOT_32R6_64R6 {
265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
268 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
280 //===----------------------------------------------------------------------===//
282 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
283 let EncodingPredicates = [HasStdEnc];
286 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
287 InstAlias<Asm, Result, Emit>, PredicateControl;
290 bit isCommutable = 1;
307 bit isTerminator = 1;
310 bit hasExtraSrcRegAllocReq = 1;
311 bit isCodeGenOnly = 1;
314 class IsAsCheapAsAMove {
315 bit isAsCheapAsAMove = 1;
318 class NeverHasSideEffects {
319 bit neverHasSideEffects = 1;
322 //===----------------------------------------------------------------------===//
323 // Instruction format superclass
324 //===----------------------------------------------------------------------===//
326 include "MipsInstrFormats.td"
328 //===----------------------------------------------------------------------===//
329 // Mips Operand, Complex Patterns and Transformations Definitions.
330 //===----------------------------------------------------------------------===//
332 def MipsJumpTargetAsmOperand : AsmOperandClass {
333 let Name = "JumpTarget";
334 let ParserMethod = "parseJumpTarget";
335 let PredicateMethod = "isImm";
336 let RenderMethod = "addImmOperands";
339 // Instruction operand types
340 def jmptarget : Operand<OtherVT> {
341 let EncoderMethod = "getJumpTargetOpValue";
342 let ParserMatchClass = MipsJumpTargetAsmOperand;
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBranchTarget";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def calltarget : Operand<iPTR> {
351 let EncoderMethod = "getJumpTargetOpValue";
352 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def simm9 : Operand<i32>;
356 def simm10 : Operand<i32>;
357 def simm11 : Operand<i32>;
359 def simm16 : Operand<i32> {
360 let DecoderMethod= "DecodeSimm16";
363 def simm19_lsl2 : Operand<i32> {
364 let EncoderMethod = "getSimm19Lsl2Encoding";
365 let DecoderMethod = "DecodeSimm19Lsl2";
366 let ParserMatchClass = MipsJumpTargetAsmOperand;
369 def simm18_lsl3 : Operand<i32> {
370 let EncoderMethod = "getSimm18Lsl3Encoding";
371 let DecoderMethod = "DecodeSimm18Lsl3";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm20 : Operand<i32> {
378 def uimm20 : Operand<i32> {
381 def uimm10 : Operand<i32> {
384 def simm16_64 : Operand<i64> {
385 let DecoderMethod = "DecodeSimm16";
389 def uimmz : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
394 def uimm2 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm3 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm5 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm6 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def uimm16 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def pcrel16 : Operand<i32> {
417 def MipsMemAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseMemOperand";
422 def MipsMemSimm11AsmOperand : AsmOperandClass {
423 let Name = "MemOffsetSimm11";
424 let SuperClasses = [MipsMemAsmOperand];
425 let RenderMethod = "addMemOperands";
426 let ParserMethod = "parseMemOperand";
427 let PredicateMethod = "isMemWithSimmOffset<11>";
428 //let DiagnosticType = "Simm11";
431 def MipsInvertedImmoperand : AsmOperandClass {
433 let RenderMethod = "addImmOperands";
434 let ParserMethod = "parseInvNum";
437 def InvertedImOperand : Operand<i32> {
438 let ParserMatchClass = MipsInvertedImmoperand;
441 def InvertedImOperand64 : Operand<i64> {
442 let ParserMatchClass = MipsInvertedImmoperand;
445 class mem_generic : Operand<iPTR> {
446 let PrintMethod = "printMemOperand";
447 let MIOperandInfo = (ops ptr_rc, simm16);
448 let EncoderMethod = "getMemEncoding";
449 let ParserMatchClass = MipsMemAsmOperand;
450 let OperandType = "OPERAND_MEMORY";
454 def mem : mem_generic;
456 // MSA specific address operand
457 def mem_msa : mem_generic {
458 let MIOperandInfo = (ops ptr_rc, simm10);
459 let EncoderMethod = "getMSAMemEncoding";
462 def mem_simm9 : mem_generic {
463 let MIOperandInfo = (ops ptr_rc, simm9);
464 let EncoderMethod = "getMemEncoding";
467 def mem_simm11 : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm11);
469 let EncoderMethod = "getMemEncoding";
470 let ParserMatchClass = MipsMemSimm11AsmOperand;
473 def mem_ea : Operand<iPTR> {
474 let PrintMethod = "printMemOperandEA";
475 let MIOperandInfo = (ops ptr_rc, simm16);
476 let EncoderMethod = "getMemEncoding";
477 let OperandType = "OPERAND_MEMORY";
480 def PtrRC : Operand<iPTR> {
481 let MIOperandInfo = (ops ptr_rc);
482 let DecoderMethod = "DecodePtrRegisterClass";
483 let ParserMatchClass = GPR32AsmOperand;
486 // size operand of ext instruction
487 def size_ext : Operand<i32> {
488 let EncoderMethod = "getSizeExtEncoding";
489 let DecoderMethod = "DecodeExtSize";
492 // size operand of ins instruction
493 def size_ins : Operand<i32> {
494 let EncoderMethod = "getSizeInsEncoding";
495 let DecoderMethod = "DecodeInsSize";
498 // Transformation Function - get the lower 16 bits.
499 def LO16 : SDNodeXForm<imm, [{
500 return getImm(N, N->getZExtValue() & 0xFFFF);
503 // Transformation Function - get the higher 16 bits.
504 def HI16 : SDNodeXForm<imm, [{
505 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
509 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
511 // Node immediate is zero (e.g. insve.d)
512 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
514 // Node immediate fits as 16-bit sign extended on target immediate.
516 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
518 // Node immediate fits as 16-bit sign extended on target immediate.
520 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
522 // Node immediate fits as 15-bit sign extended on target immediate.
524 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
526 // Node immediate fits as 16-bit zero extended on target immediate.
527 // The LO16 param means that only the lower 16 bits of the node
528 // immediate are caught.
530 def immZExt16 : PatLeaf<(imm), [{
531 if (N->getValueType(0) == MVT::i32)
532 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
534 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
537 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
538 def immLow16Zero : PatLeaf<(imm), [{
539 int64_t Val = N->getSExtValue();
540 return isInt<32>(Val) && !(Val & 0xffff);
543 // shamt field must fit in 5 bits.
544 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
546 // True if (N + 1) fits in 16-bit field.
547 def immSExt16Plus1 : PatLeaf<(imm), [{
548 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
551 // Mips Address Mode! SDNode frameindex could possibily be a match
552 // since load and store instructions from stack used it.
554 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
557 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
560 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
563 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
565 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
567 //===----------------------------------------------------------------------===//
568 // Instructions specific format
569 //===----------------------------------------------------------------------===//
571 // Arithmetic and logical instructions with 3 register operands.
572 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
573 InstrItinClass Itin = NoItinerary,
574 SDPatternOperator OpNode = null_frag>:
575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
576 !strconcat(opstr, "\t$rd, $rs, $rt"),
577 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
578 let isCommutable = isComm;
579 let isReMaterializable = 1;
580 let TwoOperandAliasConstraint = "$rd = $rs";
583 // Arithmetic and logical instructions with 2 register operands.
584 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
585 InstrItinClass Itin = NoItinerary,
586 SDPatternOperator imm_type = null_frag,
587 SDPatternOperator OpNode = null_frag> :
588 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
589 !strconcat(opstr, "\t$rt, $rs, $imm16"),
590 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
592 let isReMaterializable = 1;
593 let TwoOperandAliasConstraint = "$rs = $rt";
596 // Arithmetic Multiply ADD/SUB
597 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
598 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
599 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
600 let Defs = [HI0, LO0];
601 let Uses = [HI0, LO0];
602 let isCommutable = isComm;
606 class LogicNOR<string opstr, RegisterOperand RO>:
607 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
608 !strconcat(opstr, "\t$rd, $rs, $rt"),
609 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
610 let isCommutable = 1;
614 class shift_rotate_imm<string opstr, Operand ImmOpnd,
615 RegisterOperand RO, InstrItinClass itin,
616 SDPatternOperator OpNode = null_frag,
617 SDPatternOperator PF = null_frag> :
618 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
619 !strconcat(opstr, "\t$rd, $rt, $shamt"),
620 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
621 let TwoOperandAliasConstraint = "$rt = $rd";
624 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
625 SDPatternOperator OpNode = null_frag>:
626 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
627 !strconcat(opstr, "\t$rd, $rt, $rs"),
628 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
631 // Load Upper Imediate
632 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
633 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
634 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
635 let neverHasSideEffects = 1;
636 let isReMaterializable = 1;
640 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
641 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
642 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
643 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
644 let DecoderMethod = "DecodeMem";
645 let canFoldAsLoad = 1;
649 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
650 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
652 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
653 let DecoderMethod = "DecodeMem";
657 // Load/Store Left/Right
658 let canFoldAsLoad = 1 in
659 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
660 InstrItinClass Itin> :
661 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
662 !strconcat(opstr, "\t$rt, $addr"),
663 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
664 let DecoderMethod = "DecodeMem";
665 string Constraints = "$src = $rt";
668 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
669 InstrItinClass Itin> :
670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
671 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
672 let DecoderMethod = "DecodeMem";
675 // Conditional Branch
676 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
677 RegisterOperand RO, bit DelaySlot = 1> :
678 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
679 !strconcat(opstr, "\t$rs, $rt, $offset"),
680 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
683 let isTerminator = 1;
684 let hasDelaySlot = DelaySlot;
688 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
689 RegisterOperand RO, bit DelaySlot = 1> :
690 InstSE<(outs), (ins RO:$rs, opnd:$offset),
691 !strconcat(opstr, "\t$rs, $offset"),
692 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
695 let isTerminator = 1;
696 let hasDelaySlot = DelaySlot;
701 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
702 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
703 !strconcat(opstr, "\t$rd, $rs, $rt"),
704 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
705 II_SLT_SLTU, FrmR, opstr>;
707 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
709 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
710 !strconcat(opstr, "\t$rt, $rs, $imm16"),
711 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
712 II_SLTI_SLTIU, FrmI, opstr>;
715 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
716 SDPatternOperator targetoperator, string bopstr> :
717 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
718 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
721 let hasDelaySlot = 1;
722 let DecoderMethod = "DecodeJumpTarget";
726 // Unconditional branch
727 class UncondBranch<Instruction BEQInst> :
728 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
729 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
731 let isTerminator = 1;
733 let hasDelaySlot = 1;
734 let AdditionalPredicates = [RelocPIC];
738 // Base class for indirect branch and return instruction classes.
739 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
740 class JumpFR<string opstr, RegisterOperand RO,
741 SDPatternOperator operator = null_frag>:
742 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
746 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
748 let isIndirectBranch = 1;
751 // Jump and Link (Call)
752 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
753 class JumpLink<string opstr, DAGOperand opnd> :
754 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
755 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
756 let DecoderMethod = "DecodeJumpTarget";
759 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
760 Register RetReg, RegisterOperand ResRO = RO>:
761 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
762 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
764 class JumpLinkReg<string opstr, RegisterOperand RO>:
765 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
768 class BGEZAL_FT<string opstr, DAGOperand opnd,
769 RegisterOperand RO, bit DelaySlot = 1> :
770 InstSE<(outs), (ins RO:$rs, opnd:$offset),
771 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
772 let hasDelaySlot = DelaySlot;
777 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
778 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
779 class TailCall<Instruction JumpInst> :
780 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
781 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
783 class TailCallReg<RegisterOperand RO, Instruction JRInst,
784 RegisterOperand ResRO = RO> :
785 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
786 PseudoInstExpansion<(JRInst ResRO:$rs)>;
789 class BAL_BR_Pseudo<Instruction RealInst> :
790 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
791 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
793 let isTerminator = 1;
795 let hasDelaySlot = 1;
800 class SYS_FT<string opstr> :
801 InstSE<(outs), (ins uimm20:$code_),
802 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
804 class BRK_FT<string opstr> :
805 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
806 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
810 class ER_FT<string opstr> :
811 InstSE<(outs), (ins),
812 opstr, [], NoItinerary, FrmOther, opstr>;
815 class DEI_FT<string opstr, RegisterOperand RO> :
816 InstSE<(outs RO:$rt), (ins),
817 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
820 class WAIT_FT<string opstr> :
821 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
824 let hasSideEffects = 1 in
825 class SYNC_FT<string opstr> :
826 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
827 NoItinerary, FrmOther, opstr>;
829 let hasSideEffects = 1 in
830 class TEQ_FT<string opstr, RegisterOperand RO> :
831 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
832 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
835 class TEQI_FT<string opstr, RegisterOperand RO> :
836 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
837 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
839 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
840 list<Register> DefRegs> :
841 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
843 let isCommutable = 1;
845 let neverHasSideEffects = 1;
848 // Pseudo multiply/divide instruction with explicit accumulator register
850 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
851 SDPatternOperator OpNode, InstrItinClass Itin,
852 bit IsComm = 1, bit HasSideEffects = 0,
853 bit UsesCustomInserter = 0> :
854 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
855 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
856 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
857 let isCommutable = IsComm;
858 let hasSideEffects = HasSideEffects;
859 let usesCustomInserter = UsesCustomInserter;
862 // Pseudo multiply add/sub instruction with explicit accumulator register
864 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
866 : PseudoSE<(outs ACC64:$ac),
867 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
869 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
871 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
872 string Constraints = "$acin = $ac";
875 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
876 list<Register> DefRegs> :
877 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
878 [], itin, FrmR, opstr> {
883 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
884 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
885 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
887 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
888 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
891 let neverHasSideEffects = 1;
894 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
895 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
896 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
899 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
900 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
903 let neverHasSideEffects = 1;
906 class EffectiveAddress<string opstr, RegisterOperand RO> :
907 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
908 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
909 !strconcat(opstr, "_lea")> {
910 let isCodeGenOnly = 1;
911 let DecoderMethod = "DecodeMem";
914 // Count Leading Ones/Zeros in Word
915 class CountLeading0<string opstr, RegisterOperand RO>:
916 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
917 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
919 class CountLeading1<string opstr, RegisterOperand RO>:
920 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
921 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
923 // Sign Extend in Register.
924 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
925 InstrItinClass itin> :
926 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
927 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
930 class SubwordSwap<string opstr, RegisterOperand RO>:
931 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
932 NoItinerary, FrmR, opstr> {
933 let neverHasSideEffects = 1;
937 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
938 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
942 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
943 SDPatternOperator Op = null_frag>:
944 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
945 !strconcat(opstr, " $rt, $rs, $pos, $size"),
946 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
947 FrmR, opstr>, ISA_MIPS32R2;
949 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
950 SDPatternOperator Op = null_frag>:
951 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
952 !strconcat(opstr, " $rt, $rs, $pos, $size"),
953 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
954 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
955 let Constraints = "$src = $rt";
958 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
959 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
960 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
961 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
963 // Atomic Compare & Swap.
964 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
965 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
966 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
968 class LLBase<string opstr, RegisterOperand RO> :
969 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
970 [], NoItinerary, FrmI> {
971 let DecoderMethod = "DecodeMem";
975 class SCBase<string opstr, RegisterOperand RO> :
976 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
977 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
978 let DecoderMethod = "DecodeMem";
980 let Constraints = "$rt = $dst";
983 class MFC3OP<string asmstr, RegisterOperand RO> :
984 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
985 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
987 class TrapBase<Instruction RealInst>
988 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
989 PseudoInstExpansion<(RealInst 0, 0)> {
991 let isTerminator = 1;
992 let isCodeGenOnly = 1;
995 //===----------------------------------------------------------------------===//
996 // Pseudo instructions
997 //===----------------------------------------------------------------------===//
1000 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1001 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1003 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1004 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1005 [(callseq_start timm:$amt)]>;
1006 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1007 [(callseq_end timm:$amt1, timm:$amt2)]>;
1010 let usesCustomInserter = 1 in {
1011 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1012 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1013 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1014 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1015 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1016 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1017 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1018 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1019 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1020 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1021 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1022 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1023 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1024 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1025 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1026 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1027 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1028 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1030 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1031 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1032 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1034 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1035 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1036 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1039 /// Pseudo instructions for loading and storing accumulator registers.
1040 let isPseudo = 1, isCodeGenOnly = 1 in {
1041 def LOAD_ACC64 : Load<"", ACC64>;
1042 def STORE_ACC64 : Store<"", ACC64>;
1045 // We need these two pseudo instructions to avoid offset calculation for long
1046 // branches. See the comment in file MipsLongBranch.cpp for detailed
1049 // Expands to: lui $dst, %hi($tgt - $baltgt)
1050 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1051 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1053 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1054 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1055 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1057 //===----------------------------------------------------------------------===//
1058 // Instruction definition
1059 //===----------------------------------------------------------------------===//
1060 //===----------------------------------------------------------------------===//
1061 // MipsI Instructions
1062 //===----------------------------------------------------------------------===//
1064 /// Arithmetic Instructions (ALU Immediate)
1065 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1067 ADDI_FM<0x9>, IsAsCheapAsAMove;
1068 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1069 ISA_MIPS1_NOT_32R6_64R6;
1070 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1072 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1074 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1077 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1080 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1083 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1085 /// Arithmetic Instructions (3-Operand, R-Type)
1086 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1088 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1090 let Defs = [HI0, LO0] in
1091 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1092 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1093 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1094 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1095 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1096 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1097 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1099 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1101 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1103 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1105 /// Shift Instructions
1106 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1107 immZExt5>, SRA_FM<0, 0>;
1108 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1109 immZExt5>, SRA_FM<2, 0>;
1110 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1111 immZExt5>, SRA_FM<3, 0>;
1112 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1114 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1116 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1119 // Rotate Instructions
1120 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1122 SRA_FM<2, 1>, ISA_MIPS32R2;
1123 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1124 SRLV_FM<6, 1>, ISA_MIPS32R2;
1126 /// Load and Store Instructions
1128 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1129 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1131 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1133 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1134 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1136 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1137 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1138 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1140 /// load/store left/right
1141 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1142 AdditionalPredicates = [NotInMicroMips] in {
1143 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1144 ISA_MIPS1_NOT_32R6_64R6;
1145 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1146 ISA_MIPS1_NOT_32R6_64R6;
1147 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1148 ISA_MIPS1_NOT_32R6_64R6;
1149 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1150 ISA_MIPS1_NOT_32R6_64R6;
1153 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1155 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1156 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1157 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1158 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1159 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1160 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1162 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1163 ISA_MIPS2_NOT_32R6_64R6;
1164 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1165 ISA_MIPS2_NOT_32R6_64R6;
1166 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1167 ISA_MIPS2_NOT_32R6_64R6;
1168 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1169 ISA_MIPS2_NOT_32R6_64R6;
1170 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1171 ISA_MIPS2_NOT_32R6_64R6;
1172 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1173 ISA_MIPS2_NOT_32R6_64R6;
1175 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1176 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1177 def TRAP : TrapBase<BREAK>;
1178 def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1180 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1181 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1183 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1184 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1186 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1187 AdditionalPredicates = [NotInMicroMips] in {
1188 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1190 /// Load-linked, Store-conditional
1191 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1192 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1195 /// Jump and Branch Instructions
1196 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1197 AdditionalRequires<[RelocStatic]>, IsBranch;
1198 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1199 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1200 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1201 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1202 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1203 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1204 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1205 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1207 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1208 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1209 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1211 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1212 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1213 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1215 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1216 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1217 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1219 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1220 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1221 def B : UncondBranch<BEQ>;
1223 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1224 let AdditionalPredicates = [NotInMicroMips] in {
1225 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1226 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1229 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1230 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1231 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1232 ISA_MIPS1_NOT_32R6_64R6;
1233 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1234 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1235 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1236 ISA_MIPS1_NOT_32R6_64R6;
1237 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1238 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1239 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1240 def TAILCALL : TailCall<J>;
1241 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1243 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1244 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1245 class PseudoIndirectBranchBase<RegisterOperand RO> :
1246 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1249 let hasDelaySlot = 1;
1251 let isIndirectBranch = 1;
1254 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1256 // Return instructions are matched as a RetRA instruction, then ar expanded
1257 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1258 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1260 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1262 let isTerminator = 1;
1264 let hasDelaySlot = 1;
1266 let isCodeGenOnly = 1;
1268 let hasExtraSrcRegAllocReq = 1;
1271 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1273 // Exception handling related node and instructions.
1274 // The conversion sequence is:
1275 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1276 // MIPSeh_return -> (stack change + indirect branch)
1278 // MIPSeh_return takes the place of regular return instruction
1279 // but takes two arguments (V1, V0) which are used for storing
1280 // the offset and return address respectively.
1281 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1283 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1284 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1286 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1287 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1288 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1289 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1291 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1294 /// Multiply and Divide Instructions.
1295 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1296 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1297 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1298 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1299 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1300 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1301 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1302 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1304 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1305 ISA_MIPS1_NOT_32R6_64R6;
1306 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1307 ISA_MIPS1_NOT_32R6_64R6;
1308 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1309 AdditionalPredicates = [NotInMicroMips] in {
1310 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1311 ISA_MIPS1_NOT_32R6_64R6;
1312 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1313 ISA_MIPS1_NOT_32R6_64R6;
1316 /// Sign Ext In Register Instructions.
1317 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1318 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1319 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1320 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1323 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1324 ISA_MIPS32_NOT_32R6_64R6;
1325 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1326 ISA_MIPS32_NOT_32R6_64R6;
1328 /// Word Swap Bytes Within Halfwords
1329 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1332 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1334 // FrameIndexes are legalized when they are operands from load/store
1335 // instructions. The same not happens for stack address copies, so an
1336 // add op with mem ComplexPattern is used and the stack address copy
1337 // can be matched. It's similar to Sparc LEA_ADDRi
1338 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1341 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1342 ISA_MIPS32_NOT_32R6_64R6;
1343 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1344 ISA_MIPS32_NOT_32R6_64R6;
1345 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1346 ISA_MIPS32_NOT_32R6_64R6;
1347 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1348 ISA_MIPS32_NOT_32R6_64R6;
1350 let AdditionalPredicates = [NotDSP] in {
1351 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1352 ISA_MIPS1_NOT_32R6_64R6;
1353 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1354 ISA_MIPS1_NOT_32R6_64R6;
1355 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1356 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1357 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1358 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1359 ISA_MIPS32_NOT_32R6_64R6;
1360 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1361 ISA_MIPS32_NOT_32R6_64R6;
1362 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1363 ISA_MIPS32_NOT_32R6_64R6;
1364 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1365 ISA_MIPS32_NOT_32R6_64R6;
1368 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1369 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1370 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1371 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1373 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1375 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1376 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1378 /// Move Control Registers From/To CPU Registers
1379 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1380 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1381 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1382 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1384 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1386 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1387 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1388 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1390 // JR_HB and JALR_HB are defined here using the new style naming
1391 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1392 // and because of that it doesn't follow the naming convention of the
1393 // rest of the file. To avoid a mixture of old vs new style, the new
1394 // style was chosen.
1395 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1396 dag OutOperandList = (outs);
1397 dag InOperandList = (ins GPROpnd:$rs);
1398 string AsmString = !strconcat(instr_asm, "\t$rs");
1399 list<dag> Pattern = [];
1402 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1403 dag OutOperandList = (outs GPROpnd:$rd);
1404 dag InOperandList = (ins GPROpnd:$rs);
1405 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1406 list<dag> Pattern = [];
1409 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1410 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1412 let isIndirectBranch=1;
1418 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1419 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1420 let isIndirectBranch=1;
1424 class JR_HB_ENC : JR_HB_FM<8>;
1425 class JALR_HB_ENC : JALR_HB_FM<9>;
1427 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1428 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1430 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1432 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1433 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1434 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1435 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1437 class CacheOp<string instr_asm, Operand MemOpnd> :
1438 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1439 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> {
1440 let DecoderMethod = "DecodeCacheOp";
1443 def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1444 INSN_MIPS3_32_NOT_32R6_64R6;
1445 def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1446 INSN_MIPS3_32_NOT_32R6_64R6;
1448 //===----------------------------------------------------------------------===//
1449 // Instruction aliases
1450 //===----------------------------------------------------------------------===//
1451 def : MipsInstAlias<"move $dst, $src",
1452 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1454 let AdditionalPredicates = [NotInMicroMips];
1456 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1457 ISA_MIPS1_NOT_32R6_64R6;
1458 def : MipsInstAlias<"addu $rs, $rt, $imm",
1459 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1460 def : MipsInstAlias<"addu $rs, $imm",
1461 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1462 def : MipsInstAlias<"add $rs, $rt, $imm",
1463 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1464 ISA_MIPS1_NOT_32R6_64R6;
1465 def : MipsInstAlias<"add $rs, $imm",
1466 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1467 ISA_MIPS1_NOT_32R6_64R6;
1468 def : MipsInstAlias<"and $rs, $rt, $imm",
1469 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1470 def : MipsInstAlias<"and $rs, $imm",
1471 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1472 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1473 let Predicates = [NotInMicroMips] in {
1474 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1476 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1477 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1478 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1479 def : MipsInstAlias<"not $rt, $rs",
1480 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1481 def : MipsInstAlias<"neg $rt, $rs",
1482 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1483 def : MipsInstAlias<"negu $rt",
1484 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1485 def : MipsInstAlias<"negu $rt, $rs",
1486 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1487 def : MipsInstAlias<"slt $rs, $rt, $imm",
1488 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1489 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1490 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1491 def : MipsInstAlias<"xor $rs, $rt, $imm",
1492 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1493 def : MipsInstAlias<"or $rs, $rt, $imm",
1494 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1495 def : MipsInstAlias<"or $rs, $imm",
1496 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1497 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1498 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1499 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1500 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1501 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1502 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1503 def : MipsInstAlias<"bnez $rs,$offset",
1504 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1505 def : MipsInstAlias<"beqz $rs,$offset",
1506 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1507 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1509 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1510 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1511 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1512 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1514 def : MipsInstAlias<"teq $rs, $rt",
1515 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1516 def : MipsInstAlias<"tge $rs, $rt",
1517 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1518 def : MipsInstAlias<"tgeu $rs, $rt",
1519 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1520 def : MipsInstAlias<"tlt $rs, $rt",
1521 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1522 def : MipsInstAlias<"tltu $rs, $rt",
1523 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1524 def : MipsInstAlias<"tne $rs, $rt",
1525 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1527 def : MipsInstAlias<"sll $rd, $rt, $rs",
1528 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1529 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1530 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1531 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1532 def : MipsInstAlias<"sub $rs, $imm",
1533 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1534 0>, ISA_MIPS1_NOT_32R6_64R6;
1535 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1536 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1537 InvertedImOperand:$imm), 0>;
1538 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1539 InvertedImOperand:$imm), 0>;
1540 def : MipsInstAlias<"sra $rd, $rt, $rs",
1541 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1542 def : MipsInstAlias<"srl $rd, $rt, $rs",
1543 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1544 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1545 def : MipsInstAlias<"sync",
1546 (SYNC 0), 1>, ISA_MIPS2;
1547 //===----------------------------------------------------------------------===//
1548 // Assembler Pseudo Instructions
1549 //===----------------------------------------------------------------------===//
1551 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1552 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1553 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1554 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1556 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1557 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1558 !strconcat(instr_asm, "\t$rt, $addr")> ;
1559 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1561 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1562 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1563 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1564 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1566 //===----------------------------------------------------------------------===//
1567 // Arbitrary patterns that map to one or more instructions
1568 //===----------------------------------------------------------------------===//
1570 // Load/store pattern templates.
1571 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1572 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1574 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1575 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1578 def : MipsPat<(i32 immSExt16:$in),
1579 (ADDiu ZERO, imm:$in)>;
1580 def : MipsPat<(i32 immZExt16:$in),
1581 (ORi ZERO, imm:$in)>;
1582 def : MipsPat<(i32 immLow16Zero:$in),
1583 (LUi (HI16 imm:$in))>;
1585 // Arbitrary immediates
1586 def : MipsPat<(i32 imm:$imm),
1587 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1589 // Carry MipsPatterns
1590 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1591 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1592 let AdditionalPredicates = [NotDSP] in {
1593 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1594 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1595 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1596 (ADDiu GPR32:$src, imm:$imm)>;
1600 def : MipsPat<(MipsSync (i32 immz)),
1601 (SYNC 0)>, ISA_MIPS2;
1604 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1605 (JAL tglobaladdr:$dst)>;
1606 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1607 (JAL texternalsym:$dst)>;
1608 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1609 // (JALR GPR32:$dst)>;
1612 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1613 (TAILCALL tglobaladdr:$dst)>;
1614 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1615 (TAILCALL texternalsym:$dst)>;
1617 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1618 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1619 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1620 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1621 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1622 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1624 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1625 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1626 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1627 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1628 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1629 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1631 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1632 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1633 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1634 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1635 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1636 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1637 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1638 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1639 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1640 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1643 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1644 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1645 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1646 (ADDiu GPR32:$gp, tconstpool:$in)>;
1649 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1650 MipsPat<(MipsWrapper RC:$gp, node:$in),
1651 (ADDiuOp RC:$gp, node:$in)>;
1653 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1654 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1655 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1656 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1657 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1658 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1660 // Mips does not have "not", so we expand our way
1661 def : MipsPat<(not GPR32:$in),
1662 (NOR GPR32Opnd:$in, ZERO)>;
1665 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1666 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1667 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1670 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1673 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1674 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1675 Instruction SLTiuOp, Register ZEROReg> {
1676 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1677 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1678 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1679 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1681 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1682 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1683 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1684 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1685 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1686 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1687 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1688 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1689 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1690 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1691 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1692 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1694 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1695 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1696 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1697 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1699 def : MipsPat<(brcond RC:$cond, bb:$dst),
1700 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1703 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1705 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1706 (BLEZ i32:$lhs, bb:$dst)>;
1707 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1708 (BGEZ i32:$lhs, bb:$dst)>;
1711 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1712 Instruction SLTuOp, Register ZEROReg> {
1713 def : MipsPat<(seteq RC:$lhs, 0),
1714 (SLTiuOp RC:$lhs, 1)>;
1715 def : MipsPat<(setne RC:$lhs, 0),
1716 (SLTuOp ZEROReg, RC:$lhs)>;
1717 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1718 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1719 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1720 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1723 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1724 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1725 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1726 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1727 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1730 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1731 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1732 (SLTOp RC:$rhs, RC:$lhs)>;
1733 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1734 (SLTuOp RC:$rhs, RC:$lhs)>;
1737 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1738 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1739 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1740 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1741 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1744 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1745 Instruction SLTiuOp> {
1746 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1747 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1748 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1749 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1752 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1753 defm : SetlePats<GPR32, SLT, SLTu>;
1754 defm : SetgtPats<GPR32, SLT, SLTu>;
1755 defm : SetgePats<GPR32, SLT, SLTu>;
1756 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1759 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1761 // Load halfword/word patterns.
1762 let AddedComplexity = 40 in {
1763 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1764 def : LoadRegImmPat<LH, i32, sextloadi16>;
1765 def : LoadRegImmPat<LW, i32, load>;
1768 //===----------------------------------------------------------------------===//
1769 // Floating Point Support
1770 //===----------------------------------------------------------------------===//
1772 include "MipsInstrFPU.td"
1773 include "Mips64InstrInfo.td"
1774 include "MipsCondMov.td"
1776 include "Mips32r6InstrInfo.td"
1777 include "Mips64r6InstrInfo.td"
1782 include "Mips16InstrFormats.td"
1783 include "Mips16InstrInfo.td"
1786 include "MipsDSPInstrFormats.td"
1787 include "MipsDSPInstrInfo.td"
1790 include "MipsMSAInstrFormats.td"
1791 include "MipsMSAInstrInfo.td"
1794 include "MicroMipsInstrFormats.td"
1795 include "MicroMipsInstrInfo.td"
1796 include "MicroMipsInstrFPU.td"