1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "MipsRegisterInfo.h"
25 // All CC branch operations on Mips I are turned
26 // into BEQ and BNE CC branches instructions.
37 // Turn condition code into conditional branch opcode.
38 unsigned GetCondBranchFromCond(CondCode CC);
40 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
41 /// e.g. turning COND_E to COND_NE.
42 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
46 class MipsInstrInfo : public TargetInstrInfo
48 MipsTargetMachine &TM;
49 const MipsRegisterInfo RI;
51 MipsInstrInfo(MipsTargetMachine &TM);
53 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
54 /// such, whenever a client has an instance of instruction info, it should
55 /// always be able to get register info as well (through this method).
57 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
59 /// Return true if the instruction is a register to register move and
60 /// leave the source and dest operands in the passed parameters.
62 virtual bool isMoveInstr(const MachineInstr &MI,
63 unsigned &SrcReg, unsigned &DstReg) const;
65 /// isLoadFromStackSlot - If the specified machine instruction is a direct
66 /// load from a stack slot, return the virtual or physical register number of
67 /// the destination along with the FrameIndex of the loaded stack slot. If
68 /// not, return 0. This predicate must return 0 if the instruction has
69 /// any side effects other than loading from the stack slot.
70 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
72 /// isStoreToStackSlot - If the specified machine instruction is a direct
73 /// store to a stack slot, return the virtual or physical register number of
74 /// the source reg along with the FrameIndex of the loaded stack slot. If
75 /// not, return 0. This predicate must return 0 if the instruction has
76 /// any side effects other than storing to the stack slot.
77 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
80 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
81 MachineBasicBlock *&FBB,
82 std::vector<MachineOperand> &Cond) const;
83 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
84 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
85 MachineBasicBlock *FBB,
86 const std::vector<MachineOperand> &Cond) const;
87 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
88 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
90 /// Insert nop instruction when hazard condition is found
91 virtual void insertNoop(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI) const;