1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
72 // Node used to extract integer from accumulator.
76 // Node used to insert integers to accumulator.
107 // EXTR.W instrinsic nodes.
117 // DPA.W intrinsic nodes.
153 // DSP setcc and select_cc nodes.
157 // Vector comparisons.
158 // These take a vector and return a boolean.
164 // These take a vector and return a vector bitmask.
171 // Element-wise vector max/min.
177 // Vector Shuffle with mask as an operand
178 VSHF, // Generic shuffle
179 SHF, // 4-element set shuffle.
180 ILVEV, // Interleave even elements
181 ILVOD, // Interleave odd elements
182 ILVL, // Interleave left elements
183 ILVR, // Interleave right elements
184 PCKEV, // Pack even elements
185 PCKOD, // Pack odd elements
188 INSVE, // Copy element from one vector to another
190 // Combined (XOR (OR $a, $b), -1)
193 // Extended vector element extraction
197 // Load/Store Left/Right nodes.
198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
209 //===--------------------------------------------------------------------===//
210 // TargetLowering Implementation
211 //===--------------------------------------------------------------------===//
212 class MipsFunctionInfo;
214 class MipsTargetLowering : public TargetLowering {
217 explicit MipsTargetLowering(MipsTargetMachine &TM);
219 static const MipsTargetLowering *create(MipsTargetMachine &TM);
221 /// createFastISel - This method returns a target specific FastISel object,
222 /// or null if the target does not support "fast" ISel.
223 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
224 const TargetLibraryInfo *libInfo) const override;
226 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
228 virtual void LowerOperationWrapper(SDNode *N,
229 SmallVectorImpl<SDValue> &Results,
230 SelectionDAG &DAG) const;
232 /// LowerOperation - Provide custom lowering hooks for some operations.
233 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
235 /// ReplaceNodeResults - Replace the results of node with an illegal result
236 /// type with new values built out of custom code.
238 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
239 SelectionDAG &DAG) const;
241 /// getTargetNodeName - This method returns the name of a target specific
243 virtual const char *getTargetNodeName(unsigned Opcode) const;
245 /// getSetCCResultType - get the ISD::SETCC result ValueType
246 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
248 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
250 virtual MachineBasicBlock *
251 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
254 bool operator()(const char *S1, const char *S2) const {
255 return strcmp(S1, S2) < 0;
260 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
262 // This method creates the following nodes, which are necessary for
263 // computing a local symbol's address:
265 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
266 template <class NodeTy>
267 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
268 bool IsN32OrN64) const {
270 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
271 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
272 getTargetNode(N, Ty, DAG, GOTFlag));
273 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
274 MachinePointerInfo::getGOT(), false, false,
276 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
277 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
278 getTargetNode(N, Ty, DAG, LoFlag));
279 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
282 // This method creates the following nodes, which are necessary for
283 // computing a global symbol's address:
285 // (load (wrapper $gp, %got(sym)))
286 template<class NodeTy>
287 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
288 unsigned Flag, SDValue Chain,
289 const MachinePointerInfo &PtrInfo) const {
291 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
292 getTargetNode(N, Ty, DAG, Flag));
293 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
296 // This method creates the following nodes, which are necessary for
297 // computing a global symbol's address in large-GOT mode:
299 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
300 template<class NodeTy>
301 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
302 unsigned HiFlag, unsigned LoFlag,
304 const MachinePointerInfo &PtrInfo) const {
306 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
307 getTargetNode(N, Ty, DAG, HiFlag));
308 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
309 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
310 getTargetNode(N, Ty, DAG, LoFlag));
311 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
315 // This method creates the following nodes, which are necessary for
316 // computing a symbol's address in non-PIC mode:
318 // (add %hi(sym), %lo(sym))
319 template<class NodeTy>
320 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
322 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
323 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
324 return DAG.getNode(ISD::ADD, DL, Ty,
325 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
326 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
329 /// This function fills Ops, which is the list of operands that will later
330 /// be used when a function call node is created. It also generates
331 /// copyToReg nodes to set up argument registers.
333 getOpndList(SmallVectorImpl<SDValue> &Ops,
334 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
335 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
336 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
338 /// ByValArgInfo - Byval argument information.
339 struct ByValArgInfo {
340 unsigned FirstIdx; // Index of the first register used.
341 unsigned NumRegs; // Number of registers used for this argument.
342 unsigned Address; // Offset of the stack area used to pass this argument.
344 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
347 /// MipsCC - This class provides methods used to analyze formal and call
348 /// arguments and inquire about calling convention information.
351 enum SpecialCallingConvType {
352 Mips16RetHelperConv, NoSpecialCallingConv
355 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
356 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
359 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
360 bool IsVarArg, bool IsSoftFloat,
361 const SDNode *CallNode,
362 std::vector<ArgListEntry> &FuncArgs);
363 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
365 Function::const_arg_iterator FuncArg);
367 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
368 bool IsSoftFloat, const SDNode *CallNode,
369 const Type *RetTy) const;
371 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
372 bool IsSoftFloat, const Type *RetTy) const;
374 const CCState &getCCInfo() const { return CCInfo; }
376 /// hasByValArg - Returns true if function has byval arguments.
377 bool hasByValArg() const { return !ByValArgs.empty(); }
379 /// regSize - Size (in number of bits) of integer registers.
380 unsigned regSize() const { return IsO32 ? 4 : 8; }
382 /// numIntArgRegs - Number of integer registers available for calls.
383 unsigned numIntArgRegs() const;
385 /// reservedArgArea - The size of the area the caller reserves for
386 /// register arguments. This is 16-byte if ABI is O32.
387 unsigned reservedArgArea() const;
389 /// Return pointer to array of integer argument registers.
390 const MCPhysReg *intArgRegs() const;
392 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
393 byval_iterator byval_begin() const { return ByValArgs.begin(); }
394 byval_iterator byval_end() const { return ByValArgs.end(); }
397 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
398 CCValAssign::LocInfo LocInfo,
399 ISD::ArgFlagsTy ArgFlags);
401 /// useRegsForByval - Returns true if the calling convention allows the
402 /// use of registers to pass byval arguments.
403 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
405 /// Return the function that analyzes fixed argument list functions.
406 llvm::CCAssignFn *fixedArgFn() const;
408 /// Return the function that analyzes variable argument list functions.
409 llvm::CCAssignFn *varArgFn() const;
411 const MCPhysReg *shadowRegs() const;
413 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
416 /// Return the type of the register which is used to pass an argument or
417 /// return a value. This function returns f64 if the argument is an i64
418 /// value which has been generated as a result of softening an f128 value.
419 /// Otherwise, it just returns VT.
420 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
421 bool IsSoftFloat) const;
423 template<typename Ty>
424 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
425 const SDNode *CallNode, const Type *RetTy) const;
428 CallingConv::ID CallConv;
430 SpecialCallingConvType SpecialCallingConv;
431 SmallVector<ByValArgInfo, 2> ByValArgs;
434 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
435 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
438 const MipsSubtarget *Subtarget;
440 bool hasMips64() const { return Subtarget->hasMips64(); }
441 bool isGP64bit() const { return Subtarget->isGP64bit(); }
442 bool isO32() const { return Subtarget->isABI_O32(); }
443 bool isN32() const { return Subtarget->isABI_N32(); }
444 bool isN64() const { return Subtarget->isABI_N64(); }
447 // Create a TargetGlobalAddress node.
448 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
449 unsigned Flag) const;
451 // Create a TargetExternalSymbol node.
452 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
453 unsigned Flag) const;
455 // Create a TargetBlockAddress node.
456 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
457 unsigned Flag) const;
459 // Create a TargetJumpTable node.
460 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
461 unsigned Flag) const;
463 // Create a TargetConstantPool node.
464 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
465 unsigned Flag) const;
467 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
468 // Lower Operand helpers
469 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
470 CallingConv::ID CallConv, bool isVarArg,
471 const SmallVectorImpl<ISD::InputArg> &Ins,
472 SDLoc dl, SelectionDAG &DAG,
473 SmallVectorImpl<SDValue> &InVals,
474 const SDNode *CallNode, const Type *RetTy) const;
476 // Lower Operand specifics
477 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
482 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
483 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
484 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
486 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
487 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
488 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
489 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
490 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
491 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
492 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
493 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
494 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
495 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
497 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
498 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
500 /// isEligibleForTailCallOptimization - Check whether the call is eligible
501 /// for tail call optimization.
503 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
504 unsigned NextStackOffset,
505 const MipsFunctionInfo& FI) const = 0;
507 /// copyByValArg - Copy argument registers which were used to pass a byval
508 /// argument to the stack. Create a stack frame object for the byval
510 void copyByValRegs(SDValue Chain, SDLoc DL,
511 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
512 const ISD::ArgFlagsTy &Flags,
513 SmallVectorImpl<SDValue> &InVals,
514 const Argument *FuncArg,
515 const MipsCC &CC, const ByValArgInfo &ByVal) const;
517 /// passByValArg - Pass a byval argument in registers or on stack.
518 void passByValArg(SDValue Chain, SDLoc DL,
519 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
520 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
521 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
522 const MipsCC &CC, const ByValArgInfo &ByVal,
523 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
525 /// writeVarArgRegs - Write variable function arguments passed in registers
526 /// to the stack. Also create a stack frame object for the first variable
528 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
529 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
532 LowerFormalArguments(SDValue Chain,
533 CallingConv::ID CallConv, bool isVarArg,
534 const SmallVectorImpl<ISD::InputArg> &Ins,
535 SDLoc dl, SelectionDAG &DAG,
536 SmallVectorImpl<SDValue> &InVals) const;
538 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
539 SDValue Arg, SDLoc DL, bool IsTailCall,
540 SelectionDAG &DAG) const;
543 LowerCall(TargetLowering::CallLoweringInfo &CLI,
544 SmallVectorImpl<SDValue> &InVals) const;
547 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
549 const SmallVectorImpl<ISD::OutputArg> &Outs,
550 LLVMContext &Context) const;
553 LowerReturn(SDValue Chain,
554 CallingConv::ID CallConv, bool isVarArg,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 SDLoc dl, SelectionDAG &DAG) const;
559 // Inline asm support
560 ConstraintType getConstraintType(const std::string &Constraint) const;
562 /// Examine constraint string and operand type and determine a weight value.
563 /// The operand object must already have been set up with the operand type.
564 ConstraintWeight getSingleConstraintMatchWeight(
565 AsmOperandInfo &info, const char *constraint) const;
567 /// This function parses registers that appear in inline-asm constraints.
568 /// It returns pair (0, 0) on failure.
569 std::pair<unsigned, const TargetRegisterClass *>
570 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
572 std::pair<unsigned, const TargetRegisterClass*>
573 getRegForInlineAsmConstraint(const std::string &Constraint,
576 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
577 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
578 /// true it means one of the asm constraint of the inline asm instruction
579 /// being processed is 'm'.
580 virtual void LowerAsmOperandForConstraint(SDValue Op,
581 std::string &Constraint,
582 std::vector<SDValue> &Ops,
583 SelectionDAG &DAG) const;
585 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
587 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
589 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
591 bool IsMemset, bool ZeroMemset,
593 MachineFunction &MF) const;
595 /// isFPImmLegal - Returns true if the target can instruction select the
596 /// specified FP immediate natively. If false, the legalizer will
597 /// materialize the FP immediate as a load from a constant pool.
598 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
600 virtual unsigned getJumpTableEncoding() const;
602 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
603 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
604 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
605 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
606 bool Nand = false) const;
607 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
608 MachineBasicBlock *BB, unsigned Size) const;
609 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
610 MachineBasicBlock *BB, unsigned Size) const;
613 /// Create MipsTargetLowering objects.
614 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
615 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
618 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
619 const TargetLibraryInfo *libInfo);
623 #endif // MipsISELLOWERING_H