1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Floating Point Branch Conditional
49 // Floating Point Compare
52 // Floating Point Conditional Moves
56 // Floating Point Rounding
84 // Load/Store Left/Right nodes.
85 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
96 //===--------------------------------------------------------------------===//
97 // TargetLowering Implementation
98 //===--------------------------------------------------------------------===//
100 class MipsTargetLowering : public TargetLowering {
102 explicit MipsTargetLowering(MipsTargetMachine &TM);
104 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
106 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
108 /// LowerOperation - Provide custom lowering hooks for some operations.
109 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
111 /// getTargetNodeName - This method returns the name of a target specific
113 virtual const char *getTargetNodeName(unsigned Opcode) const;
115 /// getSetCCResultType - get the ISD::SETCC result ValueType
116 EVT getSetCCResultType(EVT VT) const;
118 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
121 const MipsSubtarget *Subtarget;
123 bool HasMips64, IsN64, IsO32;
125 // Lower Operand helpers
126 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
127 CallingConv::ID CallConv, bool isVarArg,
128 const SmallVectorImpl<ISD::InputArg> &Ins,
129 DebugLoc dl, SelectionDAG &DAG,
130 SmallVectorImpl<SDValue> &InVals) const;
132 // Lower Operand specifics
133 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
147 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
148 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
149 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, bool IsSRA) const;
150 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
154 LowerFormalArguments(SDValue Chain,
155 CallingConv::ID CallConv, bool isVarArg,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
157 DebugLoc dl, SelectionDAG &DAG,
158 SmallVectorImpl<SDValue> &InVals) const;
161 LowerCall(TargetLowering::CallLoweringInfo &CLI,
162 SmallVectorImpl<SDValue> &InVals) const;
165 LowerReturn(SDValue Chain,
166 CallingConv::ID CallConv, bool isVarArg,
167 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<SDValue> &OutVals,
169 DebugLoc dl, SelectionDAG &DAG) const;
171 virtual MachineBasicBlock *
172 EmitInstrWithCustomInserter(MachineInstr *MI,
173 MachineBasicBlock *MBB) const;
175 // Inline asm support
176 ConstraintType getConstraintType(const std::string &Constraint) const;
178 /// Examine constraint string and operand type and determine a weight value.
179 /// The operand object must already have been set up with the operand type.
180 ConstraintWeight getSingleConstraintMatchWeight(
181 AsmOperandInfo &info, const char *constraint) const;
183 std::pair<unsigned, const TargetRegisterClass*>
184 getRegForInlineAsmConstraint(const std::string &Constraint,
187 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
188 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
189 /// true it means one of the asm constraint of the inline asm instruction
190 /// being processed is 'm'.
191 virtual void LowerAsmOperandForConstraint(SDValue Op,
192 std::string &Constraint,
193 std::vector<SDValue> &Ops,
194 SelectionDAG &DAG) const;
196 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
198 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
199 unsigned SrcAlign, bool IsZeroVal,
201 MachineFunction &MF) const;
203 /// isFPImmLegal - Returns true if the target can instruction select the
204 /// specified FP immediate natively. If false, the legalizer will
205 /// materialize the FP immediate as a load from a constant pool.
206 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
208 virtual unsigned getJumpTableEncoding() const;
210 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
211 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
212 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
213 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
214 bool Nand = false) const;
215 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
216 MachineBasicBlock *BB, unsigned Size) const;
217 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
218 MachineBasicBlock *BB, unsigned Size) const;
222 #endif // MipsISELLOWERING_H