1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
29 // Start the numbering from where ISD NodeType finishes.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 // Jump and link (call)
38 // Get the Higher 16 bits from a 32-bit immediate
39 // No relation with Mips Hi register
42 // Get the Lower 16 bits from a 32-bit immediate
43 // No relation with Mips Lo register
46 // Handle gp_rel (small data/bss sections) relocation.
52 // Floating Point Branch Conditional
55 // Floating Point Compare
58 // Floating Point Conditional Moves
62 // Floating Point Rounding
90 // EXTR.W instrinsic nodes.
100 // DPA.W intrinsic nodes.
131 // Load/Store Left/Right nodes.
132 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
143 //===--------------------------------------------------------------------===//
144 // TargetLowering Implementation
145 //===--------------------------------------------------------------------===//
146 class MipsFunctionInfo;
148 class MipsTargetLowering : public TargetLowering {
150 explicit MipsTargetLowering(MipsTargetMachine &TM);
152 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
154 virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const;
156 virtual void LowerOperationWrapper(SDNode *N,
157 SmallVectorImpl<SDValue> &Results,
158 SelectionDAG &DAG) const;
160 /// LowerOperation - Provide custom lowering hooks for some operations.
161 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
163 /// ReplaceNodeResults - Replace the results of node with an illegal result
164 /// type with new values built out of custom code.
166 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
167 SelectionDAG &DAG) const;
169 /// getTargetNodeName - This method returns the name of a target specific
171 virtual const char *getTargetNodeName(unsigned Opcode) const;
173 /// getSetCCResultType - get the ISD::SETCC result ValueType
174 EVT getSetCCResultType(EVT VT) const;
176 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
179 void SetMips16LibcallName(RTLIB::Libcall, const char *Name);
181 void setMips16HardFloatLibCalls();
184 getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
186 const char *getMips16HelperFunction
187 (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
189 /// ByValArgInfo - Byval argument information.
190 struct ByValArgInfo {
191 unsigned FirstIdx; // Index of the first register used.
192 unsigned NumRegs; // Number of registers used for this argument.
193 unsigned Address; // Offset of the stack area used to pass this argument.
195 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
198 /// MipsCC - This class provides methods used to analyze formal and call
199 /// arguments and inquire about calling convention information.
202 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
205 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
206 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
207 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
208 CCValAssign::LocInfo LocInfo,
209 ISD::ArgFlagsTy ArgFlags);
211 const CCState &getCCInfo() const { return CCInfo; }
213 /// hasByValArg - Returns true if function has byval arguments.
214 bool hasByValArg() const { return !ByValArgs.empty(); }
216 /// useRegsForByval - Returns true if the calling convention allows the
217 /// use of registers to pass byval arguments.
218 bool useRegsForByval() const { return UseRegsForByval; }
220 /// regSize - Size (in number of bits) of integer registers.
221 unsigned regSize() const { return RegSize; }
223 /// numIntArgRegs - Number of integer registers available for calls.
224 unsigned numIntArgRegs() const { return NumIntArgRegs; }
226 /// reservedArgArea - The size of the area the caller reserves for
227 /// register arguments. This is 16-byte if ABI is O32.
228 unsigned reservedArgArea() const { return ReservedArgArea; }
230 /// intArgRegs - Pointer to array of integer registers.
231 const uint16_t *intArgRegs() const { return IntArgRegs; }
233 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
234 byval_iterator byval_begin() const { return ByValArgs.begin(); }
235 byval_iterator byval_end() const { return ByValArgs.end(); }
238 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
242 bool UseRegsForByval;
244 unsigned NumIntArgRegs;
245 unsigned ReservedArgArea;
246 const uint16_t *IntArgRegs, *ShadowRegs;
247 SmallVector<ByValArgInfo, 2> ByValArgs;
248 llvm::CCAssignFn *FixedFn, *VarFn;
252 const MipsSubtarget *Subtarget;
254 bool HasMips64, IsN64, IsO32;
256 // Lower Operand helpers
257 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
258 CallingConv::ID CallConv, bool isVarArg,
259 const SmallVectorImpl<ISD::InputArg> &Ins,
260 DebugLoc dl, SelectionDAG &DAG,
261 SmallVectorImpl<SDValue> &InVals) const;
263 // Lower Operand specifics
264 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
265 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
266 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
267 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
268 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
269 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
270 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
271 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
272 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
273 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
274 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
275 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
276 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
277 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
278 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
279 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
280 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
281 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
283 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
284 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
285 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
286 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
287 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
289 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
290 /// for tail call optimization.
291 bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
292 unsigned NextStackOffset,
293 const MipsFunctionInfo& FI) const;
295 /// copyByValArg - Copy argument registers which were used to pass a byval
296 /// argument to the stack. Create a stack frame object for the byval
298 void copyByValRegs(SDValue Chain, DebugLoc DL,
299 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
300 const ISD::ArgFlagsTy &Flags,
301 SmallVectorImpl<SDValue> &InVals,
302 const Argument *FuncArg,
303 const MipsCC &CC, const ByValArgInfo &ByVal) const;
305 /// passByValArg - Pass a byval argument in registers or on stack.
306 void passByValArg(SDValue Chain, DebugLoc DL,
307 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
308 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
309 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
310 const MipsCC &CC, const ByValArgInfo &ByVal,
311 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
313 /// writeVarArgRegs - Write variable function arguments passed in registers
314 /// to the stack. Also create a stack frame object for the first variable
316 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
317 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
320 LowerFormalArguments(SDValue Chain,
321 CallingConv::ID CallConv, bool isVarArg,
322 const SmallVectorImpl<ISD::InputArg> &Ins,
323 DebugLoc dl, SelectionDAG &DAG,
324 SmallVectorImpl<SDValue> &InVals) const;
326 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
327 SDValue Arg, DebugLoc DL, bool IsTailCall,
328 SelectionDAG &DAG) const;
331 LowerCall(TargetLowering::CallLoweringInfo &CLI,
332 SmallVectorImpl<SDValue> &InVals) const;
335 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
337 const SmallVectorImpl<ISD::OutputArg> &Outs,
338 LLVMContext &Context) const;
341 LowerReturn(SDValue Chain,
342 CallingConv::ID CallConv, bool isVarArg,
343 const SmallVectorImpl<ISD::OutputArg> &Outs,
344 const SmallVectorImpl<SDValue> &OutVals,
345 DebugLoc dl, SelectionDAG &DAG) const;
347 virtual MachineBasicBlock *
348 EmitInstrWithCustomInserter(MachineInstr *MI,
349 MachineBasicBlock *MBB) const;
351 // Inline asm support
352 ConstraintType getConstraintType(const std::string &Constraint) const;
354 /// Examine constraint string and operand type and determine a weight value.
355 /// The operand object must already have been set up with the operand type.
356 ConstraintWeight getSingleConstraintMatchWeight(
357 AsmOperandInfo &info, const char *constraint) const;
359 std::pair<unsigned, const TargetRegisterClass*>
360 getRegForInlineAsmConstraint(const std::string &Constraint,
363 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
364 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
365 /// true it means one of the asm constraint of the inline asm instruction
366 /// being processed is 'm'.
367 virtual void LowerAsmOperandForConstraint(SDValue Op,
368 std::string &Constraint,
369 std::vector<SDValue> &Ops,
370 SelectionDAG &DAG) const;
372 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
374 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
376 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
378 bool IsMemset, bool ZeroMemset,
380 MachineFunction &MF) const;
382 /// isFPImmLegal - Returns true if the target can instruction select the
383 /// specified FP immediate natively. If false, the legalizer will
384 /// materialize the FP immediate as a load from a constant pool.
385 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
387 virtual unsigned getJumpTableEncoding() const;
389 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
390 MachineBasicBlock *BB) const;
391 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
392 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
393 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
394 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
395 bool Nand = false) const;
396 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
397 MachineBasicBlock *BB, unsigned Size) const;
398 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
399 MachineBasicBlock *BB, unsigned Size) const;
403 #endif // MipsISELLOWERING_H