1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
70 // Interrupt, exception, error trap Return
73 // Software Exception Return.
76 // Node used to extract integer from accumulator.
80 // Node used to insert integers to accumulator.
111 // EXTR.W instrinsic nodes.
121 // DPA.W intrinsic nodes.
157 // DSP setcc and select_cc nodes.
161 // Vector comparisons.
162 // These take a vector and return a boolean.
168 // These take a vector and return a vector bitmask.
175 // Element-wise vector max/min.
181 // Vector Shuffle with mask as an operand
182 VSHF, // Generic shuffle
183 SHF, // 4-element set shuffle.
184 ILVEV, // Interleave even elements
185 ILVOD, // Interleave odd elements
186 ILVL, // Interleave left elements
187 ILVR, // Interleave right elements
188 PCKEV, // Pack even elements
189 PCKOD, // Pack odd elements
192 INSVE, // Copy element from one vector to another
194 // Combined (XOR (OR $a, $b), -1)
197 // Extended vector element extraction
201 // Load/Store Left/Right nodes.
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
213 //===--------------------------------------------------------------------===//
214 // TargetLowering Implementation
215 //===--------------------------------------------------------------------===//
216 class MipsFunctionInfo;
220 class MipsTargetLowering : public TargetLowering {
223 explicit MipsTargetLowering(const MipsTargetMachine &TM,
224 const MipsSubtarget &STI);
226 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
227 const MipsSubtarget &STI);
229 /// createFastISel - This method returns a target specific FastISel object,
230 /// or null if the target does not support "fast" ISel.
231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
232 const TargetLibraryInfo *libInfo) const override;
234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
238 void LowerOperationWrapper(SDNode *N,
239 SmallVectorImpl<SDValue> &Results,
240 SelectionDAG &DAG) const override;
242 /// LowerOperation - Provide custom lowering hooks for some operations.
243 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
245 /// ReplaceNodeResults - Replace the results of node with an illegal result
246 /// type with new values built out of custom code.
248 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
249 SelectionDAG &DAG) const override;
251 /// getTargetNodeName - This method returns the name of a target specific
253 const char *getTargetNodeName(unsigned Opcode) const override;
255 /// getSetCCResultType - get the ISD::SETCC result ValueType
256 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
257 EVT VT) const override;
259 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
262 EmitInstrWithCustomInserter(MachineInstr *MI,
263 MachineBasicBlock *MBB) const override;
265 void HandleByVal(CCState *, unsigned &, unsigned) const override;
267 unsigned getRegisterByName(const char* RegName, EVT VT,
268 SelectionDAG &DAG) const override;
270 /// Returns true if a cast between SrcAS and DestAS is a noop.
271 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
272 // Mips doesn't have any special address spaces so we just reserve
273 // the first 256 for software use (e.g. OpenCL) and treat casts
274 // between them as noops.
275 return SrcAS < 256 && DestAS < 256;
279 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
281 // This method creates the following nodes, which are necessary for
282 // computing a local symbol's address:
284 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
285 template <class NodeTy>
286 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
287 bool IsN32OrN64) const {
288 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
289 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
290 getTargetNode(N, Ty, DAG, GOTFlag));
292 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
293 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
294 false, false, false, 0);
295 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
296 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
297 getTargetNode(N, Ty, DAG, LoFlag));
298 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
301 // This method creates the following nodes, which are necessary for
302 // computing a global symbol's address:
304 // (load (wrapper $gp, %got(sym)))
305 template <class NodeTy>
306 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
307 unsigned Flag, SDValue Chain,
308 const MachinePointerInfo &PtrInfo) const {
309 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
310 getTargetNode(N, Ty, DAG, Flag));
311 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
314 // This method creates the following nodes, which are necessary for
315 // computing a global symbol's address in large-GOT mode:
317 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
318 template <class NodeTy>
319 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
320 SelectionDAG &DAG, unsigned HiFlag,
321 unsigned LoFlag, SDValue Chain,
322 const MachinePointerInfo &PtrInfo) const {
324 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
325 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
326 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
327 getTargetNode(N, Ty, DAG, LoFlag));
328 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
332 // This method creates the following nodes, which are necessary for
333 // computing a symbol's address in non-PIC mode:
335 // (add %hi(sym), %lo(sym))
336 template <class NodeTy>
337 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
338 SelectionDAG &DAG) const {
339 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
340 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
341 return DAG.getNode(ISD::ADD, DL, Ty,
342 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
343 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
346 // This method creates the following nodes, which are necessary for
347 // computing a symbol's address using gp-relative addressing:
349 // (add $gp, %gp_rel(sym))
350 template <class NodeTy>
351 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
352 assert(Ty == MVT::i32);
353 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
354 return DAG.getNode(ISD::ADD, DL, Ty,
355 DAG.getRegister(Mips::GP, Ty),
356 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
360 /// This function fills Ops, which is the list of operands that will later
361 /// be used when a function call node is created. It also generates
362 /// copyToReg nodes to set up argument registers.
364 getOpndList(SmallVectorImpl<SDValue> &Ops,
365 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
366 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
367 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
368 SDValue Chain) const;
371 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
372 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
375 const MipsSubtarget &Subtarget;
376 // Cache the ABI from the TargetMachine, we use it everywhere.
377 const MipsABIInfo &ABI;
380 // Create a TargetGlobalAddress node.
381 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
382 unsigned Flag) const;
384 // Create a TargetExternalSymbol node.
385 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
386 unsigned Flag) const;
388 // Create a TargetBlockAddress node.
389 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
390 unsigned Flag) const;
392 // Create a TargetJumpTable node.
393 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
394 unsigned Flag) const;
396 // Create a TargetConstantPool node.
397 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
398 unsigned Flag) const;
400 // Lower Operand helpers
401 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
402 CallingConv::ID CallConv, bool isVarArg,
403 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
404 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
405 TargetLowering::CallLoweringInfo &CLI) const;
407 // Lower Operand specifics
408 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
417 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
421 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
422 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
423 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
424 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
425 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
426 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
427 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
429 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
430 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
432 /// isEligibleForTailCallOptimization - Check whether the call is eligible
433 /// for tail call optimization.
435 isEligibleForTailCallOptimization(const CCState &CCInfo,
436 unsigned NextStackOffset,
437 const MipsFunctionInfo &FI) const = 0;
439 /// copyByValArg - Copy argument registers which were used to pass a byval
440 /// argument to the stack. Create a stack frame object for the byval
442 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
443 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
444 SmallVectorImpl<SDValue> &InVals,
445 const Argument *FuncArg, unsigned FirstReg,
446 unsigned LastReg, const CCValAssign &VA,
447 MipsCCState &State) const;
449 /// passByValArg - Pass a byval argument in registers or on stack.
450 void passByValArg(SDValue Chain, SDLoc DL,
451 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
452 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
453 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
454 unsigned FirstReg, unsigned LastReg,
455 const ISD::ArgFlagsTy &Flags, bool isLittle,
456 const CCValAssign &VA) const;
458 /// writeVarArgRegs - Write variable function arguments passed in registers
459 /// to the stack. Also create a stack frame object for the first variable
461 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
462 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
465 LowerFormalArguments(SDValue Chain,
466 CallingConv::ID CallConv, bool isVarArg,
467 const SmallVectorImpl<ISD::InputArg> &Ins,
468 SDLoc dl, SelectionDAG &DAG,
469 SmallVectorImpl<SDValue> &InVals) const override;
471 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
472 SDValue Arg, SDLoc DL, bool IsTailCall,
473 SelectionDAG &DAG) const;
475 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
476 SmallVectorImpl<SDValue> &InVals) const override;
478 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
480 const SmallVectorImpl<ISD::OutputArg> &Outs,
481 LLVMContext &Context) const override;
483 SDValue LowerReturn(SDValue Chain,
484 CallingConv::ID CallConv, bool isVarArg,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 const SmallVectorImpl<SDValue> &OutVals,
487 SDLoc dl, SelectionDAG &DAG) const override;
489 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL,
490 SelectionDAG &DAG) const;
492 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
494 // Inline asm support
495 ConstraintType getConstraintType(StringRef Constraint) const override;
497 /// Examine constraint string and operand type and determine a weight value.
498 /// The operand object must already have been set up with the operand type.
499 ConstraintWeight getSingleConstraintMatchWeight(
500 AsmOperandInfo &info, const char *constraint) const override;
502 /// This function parses registers that appear in inline-asm constraints.
503 /// It returns pair (0, 0) on failure.
504 std::pair<unsigned, const TargetRegisterClass *>
505 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
507 std::pair<unsigned, const TargetRegisterClass *>
508 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
509 StringRef Constraint, MVT VT) const override;
511 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
512 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
513 /// true it means one of the asm constraint of the inline asm instruction
514 /// being processed is 'm'.
515 void LowerAsmOperandForConstraint(SDValue Op,
516 std::string &Constraint,
517 std::vector<SDValue> &Ops,
518 SelectionDAG &DAG) const override;
521 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
522 if (ConstraintCode == "R")
523 return InlineAsm::Constraint_R;
524 else if (ConstraintCode == "ZC")
525 return InlineAsm::Constraint_ZC;
526 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
529 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
530 Type *Ty, unsigned AS) const override;
532 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
534 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
536 bool IsMemset, bool ZeroMemset,
538 MachineFunction &MF) const override;
540 /// isFPImmLegal - Returns true if the target can instruction select the
541 /// specified FP immediate natively. If false, the legalizer will
542 /// materialize the FP immediate as a load from a constant pool.
543 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
545 unsigned getJumpTableEncoding() const override;
546 bool useSoftFloat() const override;
548 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
549 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
550 MachineBasicBlock *BB,
551 unsigned Size, unsigned DstReg,
552 unsigned SrcRec) const;
554 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
555 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
556 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
557 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
558 bool Nand = false) const;
559 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
560 MachineBasicBlock *BB, unsigned Size) const;
561 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
562 MachineBasicBlock *BB, unsigned Size) const;
563 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
564 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
565 MachineBasicBlock *BB, bool isFPCmp,
569 /// Create MipsTargetLowering objects.
570 const MipsTargetLowering *
571 createMips16TargetLowering(const MipsTargetMachine &TM,
572 const MipsSubtarget &STI);
573 const MipsTargetLowering *
574 createMipsSETargetLowering(const MipsTargetMachine &TM,
575 const MipsSubtarget &STI);
578 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
579 const TargetLibraryInfo *libInfo);