1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
156 // These take a vector and return a boolean.
162 // These take a vector and return a vector bitmask.
169 // Element-wise vector max/min.
175 // Special case of BUILD_VECTOR where all elements are the same.
177 // Special case of VSPLAT where the result is v2i64, the operand is
178 // constant, and the operand fits in a signed 10-bits value.
181 // Combined (XOR (OR $a, $b), -1)
184 // Extended vector element extraction
188 // Load/Store Left/Right nodes.
189 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
200 //===--------------------------------------------------------------------===//
201 // TargetLowering Implementation
202 //===--------------------------------------------------------------------===//
203 class MipsFunctionInfo;
205 class MipsTargetLowering : public TargetLowering {
207 explicit MipsTargetLowering(MipsTargetMachine &TM);
209 static const MipsTargetLowering *create(MipsTargetMachine &TM);
211 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
213 virtual void LowerOperationWrapper(SDNode *N,
214 SmallVectorImpl<SDValue> &Results,
215 SelectionDAG &DAG) const;
217 /// LowerOperation - Provide custom lowering hooks for some operations.
218 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
220 /// ReplaceNodeResults - Replace the results of node with an illegal result
221 /// type with new values built out of custom code.
223 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
224 SelectionDAG &DAG) const;
226 /// getTargetNodeName - This method returns the name of a target specific
228 virtual const char *getTargetNodeName(unsigned Opcode) const;
230 /// getSetCCResultType - get the ISD::SETCC result ValueType
231 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
233 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
235 virtual MachineBasicBlock *
236 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
239 bool operator()(const char *S1, const char *S2) const {
240 return strcmp(S1, S2) < 0;
245 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
247 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
249 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
251 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
252 unsigned HiFlag, unsigned LoFlag) const;
254 /// This function fills Ops, which is the list of operands that will later
255 /// be used when a function call node is created. It also generates
256 /// copyToReg nodes to set up argument registers.
258 getOpndList(SmallVectorImpl<SDValue> &Ops,
259 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
260 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
261 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
263 /// ByValArgInfo - Byval argument information.
264 struct ByValArgInfo {
265 unsigned FirstIdx; // Index of the first register used.
266 unsigned NumRegs; // Number of registers used for this argument.
267 unsigned Address; // Offset of the stack area used to pass this argument.
269 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
272 /// MipsCC - This class provides methods used to analyze formal and call
273 /// arguments and inquire about calling convention information.
276 enum SpecialCallingConvType {
277 Mips16RetHelperConv, NoSpecialCallingConv
280 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
281 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
284 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
285 bool IsVarArg, bool IsSoftFloat,
286 const SDNode *CallNode,
287 std::vector<ArgListEntry> &FuncArgs);
288 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
290 Function::const_arg_iterator FuncArg);
292 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
293 bool IsSoftFloat, const SDNode *CallNode,
294 const Type *RetTy) const;
296 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
297 bool IsSoftFloat, const Type *RetTy) const;
299 const CCState &getCCInfo() const { return CCInfo; }
301 /// hasByValArg - Returns true if function has byval arguments.
302 bool hasByValArg() const { return !ByValArgs.empty(); }
304 /// regSize - Size (in number of bits) of integer registers.
305 unsigned regSize() const { return IsO32 ? 4 : 8; }
307 /// numIntArgRegs - Number of integer registers available for calls.
308 unsigned numIntArgRegs() const;
310 /// reservedArgArea - The size of the area the caller reserves for
311 /// register arguments. This is 16-byte if ABI is O32.
312 unsigned reservedArgArea() const;
314 /// Return pointer to array of integer argument registers.
315 const uint16_t *intArgRegs() const;
317 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
318 byval_iterator byval_begin() const { return ByValArgs.begin(); }
319 byval_iterator byval_end() const { return ByValArgs.end(); }
322 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
323 CCValAssign::LocInfo LocInfo,
324 ISD::ArgFlagsTy ArgFlags);
326 /// useRegsForByval - Returns true if the calling convention allows the
327 /// use of registers to pass byval arguments.
328 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
330 /// Return the function that analyzes fixed argument list functions.
331 llvm::CCAssignFn *fixedArgFn() const;
333 /// Return the function that analyzes variable argument list functions.
334 llvm::CCAssignFn *varArgFn() const;
336 const uint16_t *shadowRegs() const;
338 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
341 /// Return the type of the register which is used to pass an argument or
342 /// return a value. This function returns f64 if the argument is an i64
343 /// value which has been generated as a result of softening an f128 value.
344 /// Otherwise, it just returns VT.
345 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
346 bool IsSoftFloat) const;
348 template<typename Ty>
349 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
350 const SDNode *CallNode, const Type *RetTy) const;
353 CallingConv::ID CallConv;
355 SpecialCallingConvType SpecialCallingConv;
356 SmallVector<ByValArgInfo, 2> ByValArgs;
359 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
360 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
363 const MipsSubtarget *Subtarget;
365 bool HasMips64, IsN64, IsO32;
369 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
370 // Lower Operand helpers
371 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
372 CallingConv::ID CallConv, bool isVarArg,
373 const SmallVectorImpl<ISD::InputArg> &Ins,
374 SDLoc dl, SelectionDAG &DAG,
375 SmallVectorImpl<SDValue> &InVals,
376 const SDNode *CallNode, const Type *RetTy) const;
378 // Lower Operand specifics
379 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
381 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
388 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
392 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
393 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
394 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
395 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
396 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
397 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
399 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
402 /// isEligibleForTailCallOptimization - Check whether the call is eligible
403 /// for tail call optimization.
405 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
406 unsigned NextStackOffset,
407 const MipsFunctionInfo& FI) const = 0;
409 /// copyByValArg - Copy argument registers which were used to pass a byval
410 /// argument to the stack. Create a stack frame object for the byval
412 void copyByValRegs(SDValue Chain, SDLoc DL,
413 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
414 const ISD::ArgFlagsTy &Flags,
415 SmallVectorImpl<SDValue> &InVals,
416 const Argument *FuncArg,
417 const MipsCC &CC, const ByValArgInfo &ByVal) const;
419 /// passByValArg - Pass a byval argument in registers or on stack.
420 void passByValArg(SDValue Chain, SDLoc DL,
421 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
422 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
423 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
424 const MipsCC &CC, const ByValArgInfo &ByVal,
425 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
427 /// writeVarArgRegs - Write variable function arguments passed in registers
428 /// to the stack. Also create a stack frame object for the first variable
430 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
431 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
434 LowerFormalArguments(SDValue Chain,
435 CallingConv::ID CallConv, bool isVarArg,
436 const SmallVectorImpl<ISD::InputArg> &Ins,
437 SDLoc dl, SelectionDAG &DAG,
438 SmallVectorImpl<SDValue> &InVals) const;
440 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
441 SDValue Arg, SDLoc DL, bool IsTailCall,
442 SelectionDAG &DAG) const;
445 LowerCall(TargetLowering::CallLoweringInfo &CLI,
446 SmallVectorImpl<SDValue> &InVals) const;
449 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
452 LLVMContext &Context) const;
455 LowerReturn(SDValue Chain,
456 CallingConv::ID CallConv, bool isVarArg,
457 const SmallVectorImpl<ISD::OutputArg> &Outs,
458 const SmallVectorImpl<SDValue> &OutVals,
459 SDLoc dl, SelectionDAG &DAG) const;
461 // Inline asm support
462 ConstraintType getConstraintType(const std::string &Constraint) const;
464 /// Examine constraint string and operand type and determine a weight value.
465 /// The operand object must already have been set up with the operand type.
466 ConstraintWeight getSingleConstraintMatchWeight(
467 AsmOperandInfo &info, const char *constraint) const;
469 /// This function parses registers that appear in inline-asm constraints.
470 /// It returns pair (0, 0) on failure.
471 std::pair<unsigned, const TargetRegisterClass *>
472 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
474 std::pair<unsigned, const TargetRegisterClass*>
475 getRegForInlineAsmConstraint(const std::string &Constraint,
478 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
479 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
480 /// true it means one of the asm constraint of the inline asm instruction
481 /// being processed is 'm'.
482 virtual void LowerAsmOperandForConstraint(SDValue Op,
483 std::string &Constraint,
484 std::vector<SDValue> &Ops,
485 SelectionDAG &DAG) const;
487 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
489 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
491 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
493 bool IsMemset, bool ZeroMemset,
495 MachineFunction &MF) const;
497 /// isFPImmLegal - Returns true if the target can instruction select the
498 /// specified FP immediate natively. If false, the legalizer will
499 /// materialize the FP immediate as a load from a constant pool.
500 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
502 virtual unsigned getJumpTableEncoding() const;
504 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
505 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
506 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
507 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
508 bool Nand = false) const;
509 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
510 MachineBasicBlock *BB, unsigned Size) const;
511 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
512 MachineBasicBlock *BB, unsigned Size) const;
515 /// Create MipsTargetLowering objects.
516 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
517 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
520 #endif // MipsISELLOWERING_H